Signal elimination method, signal elimination circuit and interface circuit

Abstract

The invention discloses a signal elimination method, a signal elimination circuit and an interface circuit for a full-duplex transmitting and receiving circuit. The full duplex transmit receive circuit includes a transmitter for providing a first channel signal to a communication link according to an input signal and a receiver for receiving a second channel signal over the communication link. The signal elimination method comprises the following steps: providing a plurality of reverse suppression signals with different amplitudes to an input end of a receiver according to a plurality of bias currents through a signal suppression unit; obtaining a residual value between the reverse suppression signal and the first channel signal under each bias current; comparing the plurality of residual values, and taking the bias current corresponding to the minimum residual as a target bias current; and calibrating a current source of the signal suppression unit according to the target bias current. The communication quality can be improved by calibrating the current source of the signal suppression unit through the minimum residual error.

Description

Technical Field

[0001] This invention relates to the field of electronic and electrical technology, and in particular to a signal cancellation method, a signal cancellation circuit, and an interface circuit. Background Technology

[0002] A full-duplex transmit / receive circuit is a circuit capable of simultaneously transmitting and receiving signals. Specifically, a full-duplex transmit / receive circuit typically includes a first interface circuit and a second interface circuit connected via a communication link.

[0003] Figure 1 Taking a full-duplex transmit / receive circuit of differential communication as an example, a schematic structural diagram of any interface circuit 10 in the prior art is shown. Figure 1 As shown, the first / second interface circuit has a transmitter 11 and a receiver 12. The transmitter 11 is used to provide a first channel signal to the communication link 13 according to the input signals TX-IN and TX-IP, and the receiver 12 is used to receive a second channel signal through the communication link 13. The signal transmission directions of the first channel and the second channel are opposite, thus enabling bidirectional communication.

[0004] Since both transmitter 11 and receiver 12 are connected to communication link 13, the first channel signal transmitted by transmitter 11 will cause self-interference to the second channel signal received by receiver 12. In the prior art, interface circuit 10 also has signal cancellation circuit 14 to eliminate this self-interference.

[0005] like Figure 1 As shown, the signal cancellation circuit 14 includes a pair of resistors R1 and R2, a pair of differential transistors M1 and M2, and a current source I1. The signal cancellation circuit 14 generates a reverse rejection signal based on the input signals TX-IN and TX-IP. The signal cancellation circuit 14 is connected to the input terminal of the receiver 12 and cancels the first channel signal in the signal received by the receiver 12 through the reverse rejection signal.

[0006] However, due to factors such as device mismatch, temperature drift, and process deviation, the reverse suppression signal is difficult to completely match the actual interference of the first channel signal on the second channel signal, which greatly affects the communication quality. Summary of the Invention

[0007] In view of the above problems, the purpose of this application is to provide a signal cancellation method, a signal cancellation circuit and an interface circuit, which can improve communication quality.

[0008] According to one aspect of the present invention, a signal cancellation method for a full-duplex transmit-receive circuit is provided. The full-duplex transmit-receive circuit includes a transmitter and a receiver. The transmitter is used to provide a first channel signal to a communication link according to an input signal, and the receiver is used to receive a second channel signal through the communication link. The signal cancellation method includes: providing a plurality of reverse suppression signals with different amplitudes to the input terminal of the receiver according to a plurality of bias currents through a signal suppression unit; obtaining a residual value between the reverse suppression signal and the first channel signal under each bias current; comparing the plurality of residual values ​​and taking the bias current corresponding to the smallest residual as a target bias current; and calibrating the current source of the signal suppression unit according to the target bias current.

[0009] Optionally, the step of obtaining the minimum residual includes: setting a first number of bias currents; traversing the first number of bias currents to obtain a first number of residual values; and comparing the first number of residual values ​​to obtain the minimum residual.

[0010] Optionally, the step of obtaining the minimum residual includes: setting a second number of bias currents; providing at least a portion of the second number of bias currents in a set order and obtaining the corresponding residual value; and detecting the inflection point of the residual value to obtain the minimum residual.

[0011] Optionally, the step of obtaining the minimum residual further includes: after detecting the inflection point of the residual value, continuing to obtain a third number of the residual values, wherein the third number of the residual values ​​are used to verify the inflection point.

[0012] Optionally, the setting order is monotonically increasing or monotonically decreasing.

[0013] Optionally, the step of obtaining the residual value includes: transmitting a sample signal through the current interface circuit; transmitting a common-mode signal through the opposing interface circuit; and using the input signal of the receiver in the current interface circuit as the residual value.

[0014] Optionally, the sample signal includes: clock samples, pseudo-random bit sequence samples, and custom samples.

[0015] According to another aspect of the present invention, a signal cancellation circuit for a full-duplex transmit-receive circuit is provided. The full-duplex transmit-receive circuit includes a transmitter and a receiver. The transmitter is used to provide a first channel signal to a communication link according to an input signal, and the receiver is used to receive a second channel signal through the communication link. The signal cancellation circuit includes: a signal suppression unit, used to provide multiple reverse suppression signals with different amplitudes to the input terminal of the receiver according to multiple bias currents during a calibration phase; and a residual calibration unit, used to obtain a residual value between the reverse suppression signal and the first channel signal under each bias current, and adjust the current source of the signal suppression unit according to the bias current corresponding to the minimum residual.

[0016] Optionally, the residual calibration unit includes: a storage module for storing the residual value between the reverse suppression signal and the first channel signal under each bias current; a comparison module for comparing the stored residual values ​​to obtain the minimum residual, so as to obtain a target bias current according to the bias current corresponding to the minimum residual; and an adjustment module for adjusting the current source according to the target bias current.

[0017] Optionally, the signal suppression unit includes: a differential pair transistor, comprising a first transistor and a second transistor, wherein a first terminal of the first transistor is connected to one input terminal of the receiver, and a control terminal is connected to one of the input signals; a first terminal of the second transistor is connected to the other input terminal of the receiver, and a control terminal is connected to the other of the input signals; the second terminals of the first transistor and the second transistor are connected together and connected to the current source; a first resistor, wherein the first terminal of the first transistor is connected to one output terminal of the transmitter via the first resistor; and a second resistor, wherein the first terminal of the second transistor is connected to the other output terminal of the transmitter via the second resistor.

[0018] According to another aspect of the present invention, an interface circuit for a full-duplex transmit-receive circuit is provided, comprising: a transmitter for providing a first channel signal to a communication link according to an input signal; a receiver for receiving a second channel signal through the communication link; and the aforementioned signal cancellation circuit, connected between the communication link and the receiver, for providing the reverse suppression signal to the input terminal of the receiver, the reverse suppression signal being used to cancel the first channel signal mixed in the second channel signal, wherein the first channel is a forward channel and the second channel is a reverse channel.

[0019] According to another aspect of the present invention, an interface circuit for a full-duplex transmit-receive circuit is provided, comprising: a transmitter for providing a first channel signal to a communication link according to an input signal; a receiver for receiving a second channel signal through the communication link; and the aforementioned signal cancellation circuit, connected between the communication link and the receiver, for providing the reverse suppression signal to the input terminal of the receiver, the reverse suppression signal being used to cancel the first channel signal mixed in the second channel signal, wherein the first channel is a reverse channel and the second signal is a forward channel.

[0020] According to the signal cancellation method, signal cancellation circuit, and interface circuit provided in this application, the amplitude of the reverse suppression signal can be adjusted by regulating the current source in the signal suppression unit based on the minimum residual adjustment, thereby improving the accuracy and reliability of signal cancellation and enhancing communication quality. In particular, it can reduce the impact of environmental factors such as temperature changes on communication quality. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic structural diagram of an interface circuit in the prior art is shown;

[0023] Figure 2 A schematic structural diagram of the full-duplex transmit and receive circuit for differential communication according to this application is shown.

[0024] Figure 3 A schematic structural diagram of the signal cancellation circuit of this application is shown;

[0025] Figure 4 A schematic circuit diagram of the signal cancellation circuit of this application is shown;

[0026] Figure 5 A schematic structural diagram of the full-duplex transmit and receive circuit for single-ended communication according to this application is shown.

[0027] Figure 6 A schematic flowchart of the signal cancellation method of this application is shown. Detailed Implementation

[0028] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0029] Furthermore, certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0030] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0031] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should also be noted that in the various methods and processes of this application, the order of the steps does not imply the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of this application.

[0033] Figure 2 A schematic structural diagram of the full-duplex transmit and receive circuit for differential communication according to this application is shown. (Reference) Figure 2 The full-duplex transmit and receive circuit of differential communication includes a first interface circuit 20, a second interface circuit 30, and a communication link 40 between them. The first interface circuit 20 is used to provide a forward signal and receive a reverse signal, and the second interface circuit 30 is used to provide a reverse signal and receive a forward signal. The first interface circuit 20 and the second interface circuit 30 are communicatively connected via the communication link 40.

[0034] Each interface circuit includes a transmitter and a receiver. In each interface circuit, the transmitter provides a first channel signal to the communication link based on the differential input signal, which is the transmit signal of the interface circuit. The receiver receives a second channel signal through the communication link, which is the receive signal of the interface circuit.

[0035] Specifically, in Figure 2 In the first interface circuit 20, a transmitter 21 and a receiver 22 are included. The second interface circuit 30 includes a receiver 31 and a transmitter 32. It should be understood that for the first interface circuit 20, the first channel is a forward channel, and the first channel signal is the aforementioned forward signal; the second channel is a reverse channel, and the second channel signal is the aforementioned reverse signal. For the second interface circuit 30, the first channel is a reverse channel, and the first channel signal is the aforementioned reverse signal; the second channel is a forward channel, and the second channel signal is the aforementioned forward signal.

[0036] The transmitter 21 in the first interface circuit 20 provides forward transmission signals TX-OP and TX-ON based on a pair of differential input signals TX-IP and TX-IN. These forward transmission signals TX-OP and TX-ON are transmitted via the communication link 40 to the receiver 31 of the second interface circuit 30, thereby obtaining the forward signals RX-OP and RX-ON received by the second interface circuit 30.

[0037] Similarly, the transmitter 32 in the second interface circuit 30 provides reverse transmission signals BCTX-OP and BCTX-ON based on a pair of differential input signals BCTX-IP and BCTX-IN. These reverse transmission signals are transmitted via communication link 40 to the receiver 22 of the first interface circuit 20 to obtain the reverse signals BCRX-OP and BCRX-ON received by the first interface circuit 20.

[0038] In some embodiments, the transmission rate of the forward signal is greater than the transmission rate of the reverse signal. In still other embodiments, the forward signal includes high-speed data and low-speed data, and the reverse signal includes low-speed data. In yet other embodiments, the full-duplex transmit / receive circuit described above can be applied to an in-vehicle system. For example, the high-speed data in the forward signal is video data and / or audio data captured by an in-vehicle camera, and the low-speed data in both the forward and reverse signals is control data between the in-vehicle camera and the processor. Furthermore, the full-duplex transmit / receive circuit provided in this application can also be applied to other fields, such as communications and consumer electronics.

[0039] In the full-duplex transmit / receive circuit of differential communication, the communication link 40 includes a first signal line 41 and a second signal line 42. The first signal terminal of the first interface circuit 20 is connected to the first signal terminal of the second interface circuit 30 via the first signal line 41, and the second signal terminal of the first interface circuit 20 is connected to the second signal terminal of the second interface circuit 30 via the second signal line 42. The first signal line 41 and the second signal line 42 can be implemented, for example, using shielded twisted pair (STP) cable. It should be understood that DC blocking capacitors are also connected between the communication link 40 and the signal terminals of each interface circuit. Figure 2 The components are labeled C1, C2, C1', and C2'. By using DC blocking capacitors, the DC components mixed in with the first and second channel signals can be filtered out, reducing common-mode noise interference with the signal.

[0040] For each interface circuit, its transmitted signal can cause self-interference with the received signal, especially at high frequencies. Therefore, in the embodiments of this application, the interface circuit further includes a signal cancellation circuit to eliminate the first channel signal mixed in the received signal, thereby improving communication quality.

[0041] Specifically, such as Figure 2 As shown, the first interface circuit 20 also includes a signal cancellation circuit 23, which is connected between the communication link 40 and the receiver 22. The second interface circuit 30 also includes a signal cancellation circuit 33, which is connected between the communication link 40 and the receiver 31.

[0042] It should be understood that signal cancellation circuits 23 and 33 operate on the same principle. Therefore, in Figure 3 and Figure 4 The diagram below shows a schematic structural diagram and circuit diagram of the signal cancellation circuit according to an embodiment of this application, using signal cancellation circuit 23 as an example. The following section, in conjunction with... Figures 2 to 4 The signal cancellation circuit of the embodiments of this application will be described in detail.

[0043] refer to Figure 3 The signal cancellation circuit 23 is connected to the communication link 40. Specifically, the signal cancellation circuit 23 is connected between the transmitter 21 and the receiver 22, and the common node of the signal cancellation circuit 23 and the transmitter 21 is connected to the communication link 40 through corresponding DC blocking capacitors C1 and C2. The signal cancellation circuit 23 includes a signal suppression unit 200. The signal suppression unit 200 is connected to the input terminal of the receiver 22 and is used to provide a reverse suppression signal to the input terminal of the receiver 22 according to the input signals TX-IN and TX-IP.

[0044] Combination Figure 3 and Figure 4For ease of understanding, the transmitter 21 includes a pair of resistors Rfa and Rfb, a pair of transistors Ma and Mb, and a current source Ia as an example. Resistor Rfa is coupled between the power supply voltage VDD and the first terminal of transistor Ma, resistor Rfb is coupled between the power supply voltage VDD and the first terminal of transistor Mb, and the second terminals of transistors Ma and Mb are connected and grounded via the current source Ia. One of the input signals TX-IN and TX-IP (e.g., TX-IN) is applied to the control terminal of transistor Ma, and the other (e.g., TX-IP) is applied to the control terminal of transistor Mb. The first signal terminal 24 of the first interface circuit 20 is connected to the first terminal of transistor Ma to extract one of the forward signals, for example, TX-OP, which is connected to the communication link 40 via a DC blocking capacitor C1; the second signal terminal 25 is connected to the first terminal of transistor Mb to extract the other of the forward signals, for example, TX-ON, which is connected to the communication link 40 via a DC blocking capacitor C2. However, it should be understood that the working principle of transmitter 21 is well known to those skilled in the art and can be implemented using any related technology.

[0045] The signal suppression unit 200 is connected between the first signal terminal 24, the second signal terminal 25 and the input terminal of the receiver 22, and includes a first resistor R1, a second resistor R2, a pair of transistors having a first transistor M1 and a second transistor M2, and a current source I1.

[0046] The first terminal of the first transistor M1 is connected to one input terminal of the receiver 22, and the control terminal is connected to one of the input signals, such as TX-IN; the first terminal of the second transistor M2 is connected to the other input terminal of the receiver 22, and the control terminal is connected to the other input signal, such as TX-IP; the second terminal of the first transistor M1 and the second terminal of the second transistor M2 are connected together and grounded through the current source I1.

[0047] The first terminal of the first transistor M1 is also connected to the second signal terminal 25 via the first resistor R1, which is one output terminal of the transmitter 21. The first terminal of the second transistor M2 is also connected to the first signal terminal 24 via the second resistor, which is the other output terminal of the transmitter 21.

[0048] Under the control of the input signals TX-IN and TX-IP, the signal cancellation circuit 23 can provide a reverse suppression signal to the input terminal of the receiver 22 to eliminate the forward signals TX-OP and TX-ON mixed in the reverse signals BCTX-OP and BCTX-ON.

[0049] exist Figure 4In the examples, transistors Ma, Mb, M1, and M2 are all N-type field-effect transistors (MOSFETs). It should be understood that a MOSFET consists of a first terminal, a second terminal, and a control terminal. When the MOSFET is turned on, current flows from the first terminal to the second terminal. For an N-type MOSFET, the first terminal is the drain, the second terminal is the source, and the control terminal is the gate. For a P-type MOSFET, the first terminal is the source, the second terminal is the drain, and the control terminal is the gate.

[0050] It should be pointed out that, in cases such as Figure 4 In the illustrated embodiment, the signal suppression unit 200 provides a reverse suppression signal through the first resistor R1, the second resistor R2, the first transistor M1, the second transistor M2, and the current source I1. However, this application is not limited thereto. In some other embodiments, the signal suppression unit 200 further includes a mirror structure. The mirror structure is used to mirror the received signal of the receiver 22 and / or the first channel signal, and to eliminate interference in the received signal of the receiver 22 through a differential circuit. Related mirror structures should also be well known to those skilled in the art, and will not be described in detail here.

[0051] In actual operation, the reverse suppression signal provided by the signal cancellation circuit can be deflected by factors such as device mismatch, temperature drift, and process deviation, and cannot completely cancel the transmitted signal. To solve this problem, the signal cancellation circuit 23 of this application also includes a residual calibration unit 100 for calibrating the current source I1.

[0052] Specifically, the current source I1 is calibrated before the full-duplex transmit / receive circuit operates normally, or when the operating environment of the full-duplex transmit / receive circuit changes. For example, the current source I1 is calibrated whenever the operating temperature changes. Therefore, this application is particularly applicable to avoiding the negative effects of environmental factors such as temperature on the signal cancellation circuit.

[0053] Specifically, the signal suppression unit 200 is further configured to provide multiple reverse suppression signals with different amplitudes to the input terminal of the receiver 22 according to multiple bias currents during the calibration phase described above. The residual calibration unit 100 is configured to obtain the residual value between the reverse suppression signal and the first channel signal under each bias current, and adjust the current source of the signal suppression unit according to the bias current corresponding to the minimum residual.

[0054] In a preferred embodiment, the transmitter 21 of the current interface circuit can transmit a sample signal during the calibration phase and receive a common-mode signal via a communication link. This allows the residual value to be directly obtained through signal sampling, which simplifies the circuit structure of the residual calibration unit. The sample signal can be a clock pattern, a pseudo-random bit sequence pattern, a custom pattern, or other types of data samples.

[0055] Combination Figure 3 and Figure 4 The residual calibration unit 100 includes a storage module 110, a comparison module 120, and an adjustment module 130. The storage module 110 stores the residual value between the reverse suppression signal and the first channel signal under each bias current during the calibration phase described above. The comparison module 120 compares the stored residual values ​​to obtain the minimum residual, and obtains the target bias current based on the bias current corresponding to the minimum residual. The adjustment module 130 provides an adjustment signal based on the target bias current to adjust the current source I1.

[0056] In some embodiments, the storage module 110 also stores a first set number of bias currents. That is, during the calibration phase described above, the adjustment module 130 provides corresponding adjustment signals based on these preset bias currents to obtain multiple residual values; after obtaining the minimum residual, the adjustment module 130 provides an adjustment signal based on the bias current (i.e., the target bias current) corresponding to the minimum residual and completes the calibration. This further enhances the automation level of the system.

[0057] In some embodiments, the storage module 110 may store a pre-set second number of bias currents. During the calibration phase described above, the adjustment module 130 provides at least a portion of the second number of bias currents according to a set order and obtains corresponding residual values. When the comparison module 120 detects an inflection point in the residual value, it takes that inflection point as the minimum residual, and the bias current corresponding to that inflection point is the target current. The set order specifically refers to a monotonically increasing or monotonically decreasing order of the bias currents. For example, taking 256 different bias currents as an example, when testing the first 130 bias currents from smallest to largest, the residual value decreases as the bias current increases; when testing the 131st bias current, its residual value is greater than the residual value corresponding to the 130th bias current. That is, the inflection point of the residual occurs at the 130th bias current. Therefore, the 130th bias current can be taken as the target current.

[0058] In some other embodiments, after obtaining the inflection point, the adjustment module 130 continues to adjust the bias current by a third number of times and obtains a corresponding third number of residual values. The comparison module 120 verifies whether the inflection point corresponds to the minimum residual based on these third number of residual values. For example, when the inflection point corresponding to the residual value of the 130th bias current is detected, the residual values ​​corresponding to the remaining 5 bias currents can be detected. If the residual values ​​corresponding to these 5 bias currents are all greater than the inflection point, then the inflection point is confirmed to be correct.

[0059] This application also provides an interface circuit that includes the elimination circuit provided in this application. The interface circuit is, for example, a... Figure 2 The first interface circuit 20 and / or the second interface circuit 30 in the full-duplex transmit and receive circuit shown.

[0060] It should be pointed out that, although in Figures 2 to 4 The examples all use full-duplex transmit and receive circuits for differential communication. However, as... Figure 5 As shown, the signal cancellation circuit provided in this application can also be used as a full-duplex transmit and receive circuit for single-ended communication.

[0061] refer to Figure 5 The single-ended full-duplex transmit and receive circuit includes a first link interface 20', a second link interface 30', and a single-ended communication link 40' between them. The first interface circuit 20' provides a forward signal and receives a reverse signal, while the second interface circuit 30' provides a reverse signal and receives a forward signal. The first interface circuit 20' and the second interface circuit 30' are communicatively connected via the communication link 40'.

[0062] Each interface circuit includes a transmitter and a receiver. The transmitter provides a first channel signal to the communication link based on the input signal, which is the transmit signal of the interface circuit. The receiver receives a second channel signal through the communication link, which is the receive signal of the interface circuit.

[0063] Specifically, in Figure 5 In the first interface circuit 20', a transmitter 21, a receiver 22, and a signal cancellation circuit 23 are included. The second interface circuit 30 includes a receiver 31, a transmitter 32, and a signal cancellation circuit 33. It should be understood that for the first interface circuit 20', the first channel is a forward channel, and the first channel signal is the aforementioned forward signal; the second channel is a reverse channel, and the second channel signal is the aforementioned reverse signal. For the second interface circuit 30', the first channel is a reverse channel, and the first channel signal is the aforementioned reverse signal; the second channel is a forward channel, and the second channel signal is the aforementioned forward signal.

[0064] The transmitter 21, receiver 22, and signal cancellation circuit 23 in the first interface circuit 20', and the receiver 31, transmitter 32, and signal cancellation circuit 33 in the second interface circuit 30' can be referred to Figures 2 to 4 The relevant explanations in the document will not be repeated here.

[0065] Unlike the full-duplex transmit / receive circuit of differential communication, the single-ended full-duplex transmit / receive circuit of single-ended communication includes only a single signal line 40'. This signal line connects the first signal terminal of the first interface circuit 20' and the first signal terminal of the second interface circuit 30'. The second signal terminal of the first interface circuit 20' is grounded to GND via resistor Rg1, and the second signal terminal of the second interface circuit 30' is grounded to GND via resistor Rg2. The single-ended communication link 40' can be implemented, for example, using a coaxial cable (COAX). It should be understood that each signal terminal of each interface circuit is connected to the communication link 40 via a corresponding DC blocking capacitor or grounded via a corresponding resistor. These DC blocking capacitors... Figure 5 These are also labeled C1, C2, C1', and C2'. The DC blocking capacitors can filter out the DC components mixed in with the first and second channel signals, reducing common-mode noise interference with the forward and reverse signals.

[0066] This application also provides a signal cancellation method for a full-duplex transmit and receive circuit. Figure 6 This diagram illustrates a schematic flowchart of a signal cancellation method according to an embodiment of this application. The full-duplex transmit / receive circuit is, for example, described above. Figures 2 to 5 The details are omitted here. The signal cancellation method provided in this application can be implemented, for example, using the signal cancellation circuit provided in this application. Figure 6 As shown, the signal cancellation method includes:

[0067] In step S11, the signal suppression unit provides multiple reverse suppression signals with different amplitudes to the input terminal of the receiver based on multiple bias currents.

[0068] For example, the signal suppression unit can be referred to Figure 3 and Figure 4 The signal suppression unit 200 is located in the signal suppression unit. In this step, the current magnitude of the current source in the signal suppression unit can be adjusted according to a plurality of pre-set bias currents, thereby providing a plurality of reverse suppression signals with different amplitudes.

[0069] In step S12, the residual value between the reverse suppression signal and the first channel signal under each bias current is obtained.

[0070] In a preferred embodiment, the transmitter of the current interface circuit can transmit a sample signal during the calibration phase and receive a common-mode signal via a communication link. This allows the residual value to be directly obtained through signal sampling, which simplifies the circuit structure of the residual calibration unit. The sample signal can be a clock pattern, a pseudo-random bit sequence pattern, a custom pattern, or other types of data samples.

[0071] In step S13, multiple residual values ​​are compared, and the bias current corresponding to the smallest residual is taken as the target bias current.

[0072] In some embodiments, the step of obtaining the minimum residual includes: setting a first number of bias currents; iterating through the first number of bias currents to obtain a first number of residual values; and comparing the first number of residual values ​​to obtain the minimum residual.

[0073] In some embodiments, the step of obtaining the minimum residual includes: setting a second number of bias currents; providing at least a portion of the second number of bias currents in a set order and obtaining corresponding residual values; and detecting the inflection point of the residual value to obtain the minimum residual. The set order specifically refers to a monotonically increasing or monotonically decreasing order of the bias currents. For example, taking 256 different bias currents as an example, when testing the first 130 bias currents from smallest to largest, the residual value decreases as the bias current increases; when testing the 131st bias current, its residual value is greater than the residual value corresponding to the 130th bias current. That is, the inflection point of the residual occurs at the 130th bias current. Therefore, the 130th bias current can be taken as the target current.

[0074] In some other embodiments, after obtaining the inflection point, the step of obtaining the minimum residual further includes: obtaining a third number of residual values, which are used to verify whether the inflection point corresponds to the minimum residual. For example, when the inflection point corresponding to the residual value of the 130th bias current is detected, the residual values ​​corresponding to 5 more bias currents can be detected. If the residual values ​​corresponding to these 5 bias currents are all greater than the inflection point, then the inflection point is confirmed to be correct.

[0075] In actual working conditions, any of the above methods can be selected to obtain the minimum residual, taking into account both cost and accuracy requirements.

[0076] In step S14, the current source of the signal suppression unit is calibrated according to the target bias current.

[0077] According to the signal cancellation method, signal cancellation circuit, and interface circuit provided in this application, by adjusting the current source in the signal suppression unit to adjust the amplitude of the reverse suppression signal, the accuracy and reliability of signal cancellation can be improved, thereby enhancing communication quality. In particular, it can reduce the impact of environmental factors such as temperature changes on communication quality.

[0078] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit this application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method of signal cancellation for a full-duplex transmit-receive circuit, the full-duplex transmit-receive circuit comprising a transmitter for providing a first channel signal to a communication link in dependence on an input signal, and a receiver for receiving a second channel signal over the communication link, wherein, The signal cancellation method comprises: providing a plurality of reverse suppression signals with different amplitudes to the input end of the receiver according to a plurality of bias currents by a signal suppression unit; obtaining a residual value between the reverse suppression signal and the first channel signal under each bias current; comparing a plurality of residual values, and taking the bias current corresponding to the minimum residual as a target bias current; and calibrating the current source of the signal suppression unit according to the target bias current.

2. The signal cancellation method of claim 1, wherein, The step of obtaining the minimum residual value comprises: setting a first number of bias currents; traversing the first number of bias currents to obtain the first number of residual values; and comparing the first number of residual values to obtain the minimum residual value.

3. The signal cancellation method of claim 1, wherein, The step of obtaining the minimum residual value comprises: setting a second number of bias currents; providing at least part of the second number of bias currents in a set order and obtaining the corresponding residual values; and detecting the inflection point of the residual values to obtain the minimum residual value.

4. The signal cancellation method of claim 3, wherein, The step of obtaining the minimum residual value further comprises: after detecting the inflection point of the residual values, continuing to obtain a third number of residual values, the third number of residual values are used to verify the inflection point.

5. The signal cancellation method of claim 3, wherein, The set order is monotonically increasing or monotonically decreasing.

6. The signal cancellation method according to any one of claims 1 to 5, wherein, The step of obtaining the residual value comprises: transmitting a sample signal through a current interface circuit; transmitting a common mode signal through a counter interface circuit; and taking the input signal of the receiver in the current interface circuit as the residual value.

7. The signal cancellation method of claim 6, wherein, The sample signal comprises: a clock sample, a pseudo-random bit sequence sample, and a self-defined sample.

8. A signal cancellation circuit for a full-duplex transmit-receive circuit, the full-duplex transmit-receive circuit comprising a transmitter for providing a first channel signal to a communication link in dependence on an input signal, and a receiver for receiving a second channel signal over the communication link, wherein, The signal cancellation circuit comprises: a signal suppression unit for providing a plurality of reverse suppression signals with different amplitudes to the input end of the receiver according to a plurality of bias currents in a calibration phase; and a residual calibration unit for obtaining a residual value between the reverse suppression signal and the first channel signal under each bias current, and adjusting the current source of the signal suppression unit according to the bias current corresponding to the minimum residual value.

9. The signal cancellation circuit of claim 8, wherein, The residual calibration unit comprises: a storage module for storing the residual value between the reverse suppression signal and the first channel signal under each bias current; a comparison module for comparing the stored residual values to obtain the minimum residual value, and obtaining a target bias current according to the bias current corresponding to the minimum residual value; and an adjustment module for adjusting the current source according to the target bias current.

10. The signal cancellation circuit of claim 8 or 9, wherein, The signal suppression unit comprises: a differential pair transistor comprising a first transistor and a second transistor, a first end of the first transistor is connected to one input end of the receiver, a control end is connected to one of the input signals; a first end of the second transistor is connected to the other input end of the receiver, a control end is connected to the other input signal, a second end of the first transistor and a second end of the second transistor are connected and connected to the current source; a first resistor, the first end of the first transistor is connected to one output end of the transmitter through the first resistor; and a second resistor, the first terminal of the second transistor being connected to the other output terminal of the transmitter via the second resistor.

11. An interface circuit for a full duplex transmit receive circuit, wherein, comprising: a transmitter for providing a first channel signal to a communication link in dependence on an input signal; a receiver for receiving a second channel signal via the communication link; and a signal cancellation circuit as claimed in any of claims 8-10, connected between the communication link and the receiver for providing the reverse suppression signal to an input of the receiver, the reverse suppression signal being arranged to cancel the first channel signal mixed in the second channel signal, wherein the first channel is a forward channel and the second channel is a reverse channel.

12. An interface circuit for a full-duplex transmit-receive circuit, wherein, comprising: a transmitter for providing a first channel signal to a communication link in dependence on an input signal; a receiver for receiving a second channel signal via the communication link; and a signal cancellation circuit as claimed in any of claims 8-10, connected between the communication link and the receiver for providing the reverse suppression signal to an input of the receiver, the reverse suppression signal being arranged to cancel the first channel signal mixed in the second channel signal, wherein the first channel is a reverse channel and the second channel is a forward channel.

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