A method and system for synchronous simulation injection of images from a binocular camera

Abstract

This invention provides a method and system for simulating image synchronization injection from a binocular camera, belonging to the field of image simulation and testing technology. It relies on a general-purpose computer and an FPGA board with a PCIe interface to work together to simulate injecting two channels of infrared or visible light image data with time synchronization characteristics into an image processing module. The method includes: host software reading two image frames from the hard drive and writing them to the PCIe device memory; a notification signal triggering the FPGA to read and write the frames to the ping-pong loop buffers of dual DDR memory; and the FPGA's image transmission timing control module, based on its internal clock, generating frame start and column start signals, and synchronously outputting the two image data channels in column units via the DDR→FIFO→image transmission module link, transmitting them to the image processing module. The FPGA can control the difference between the two data outputs to within one clock cycle, achieving a synchronization accuracy of 10ns.

Description

Technical Field

[0001] This invention relates to the field of image simulation and testing technology, specifically to an FPGA-based method and system for synchronous simulation injection of binocular camera images. Background Technology

[0002] With the rapid development of computer vision and artificial intelligence technologies, perception systems based on multi-channel imaging sensors are increasingly widely used in fields such as industrial automation, autonomous driving, security monitoring, precision measurement, and aerospace reconnaissance. The algorithmic complexity of image processing modules is constantly increasing, placing higher demands on the quality and consistency of image input sources. In practical applications, dual-channel or multi-channel imaging devices often need to work collaboratively, achieving higher-precision target recognition and tracking through methods such as fusion processing, differential processing, or time-synchronized feature extraction.

[0003] Binocular vision systems are an important research area in computer vision. Their core principle involves using two cameras to simultaneously acquire images of a target from different angles, and then calculating the target's depth information using a stereo matching algorithm. This technology places extremely stringent requirements on the time synchronization of the two image data streams; any time deviation can lead to errors in depth calculation, thereby affecting the accuracy of subsequent processing such as 3D reconstruction, motion detection, and target tracking.

[0004] During the algorithm development and system integration verification phase, due to factors such as the high cost of real infrared or visible light camera equipment, the difficulty in strictly controlling environmental conditions, and the difficulty in reproducing faults, there is an urgent need for an image injection device that can simulate the output of a real camera and generate image data stably and controllably.

[0005] Relevant patent documents retrieved:

[0006] This document, published in China (CN 120029915 A) on May 23, 2025, discloses a high-speed simulation image injection system with dynamically configurable transmission timing and its operation method. It includes image transmission timing generation and system control software, an ARM-based transmission timing management module, and an FPGA-based simulation image transmission module. The ARM-based transmission timing management module enables start / stop operation and task mode selection, allowing simultaneous transmission of multiple fiber optic images with a timing control error of less than 1 microsecond.

[0007] The prior art represented by the aforementioned documents has at least the following unresolved technical problems or defects:

[0008] Insufficient synchronization accuracy: Although the existing technology CN 120029915 A mentions that the timing of multiple images can be controlled, the timing control error can only reach the microsecond level (less than 1 microsecond), which cannot meet the verification requirements of algorithms such as stereo matching and inter-frame difference that have strict requirements for time consistency. The relevant evidence is that paragraph

[0021] of the specification states that "the timing control error is less than 1 microsecond", while the stereo matching algorithm in the binocular vision system usually requires the synchronization error of the two images to be controlled at the nanosecond level to avoid disparity calculation errors caused by time deviation.

[0009] The synchronization implementation scheme is unclear: Existing technology CN 120029915 A does not describe in detail the specific technical solution for how to achieve timing synchronization between multiple images, and lacks reproducibility. Relevant evidence is that this document only briefly mentions "the timing within each image and between each image" in the claims and specification, but does not disclose the specific hardware architecture and data flow control mechanism.

[0010] Lack of fault injection capability: Existing technologies CN 120029915 A and CN 120370741 A do not have the function of actively injecting faults into image data streams, and therefore cannot be used for system robustness testing and fault reproduction and localization. The relevant evidence is that none of the aforementioned documents address the design and implementation of a fault injection module.

[0011] Lack of independent dual-path caching mechanism: Existing technologies do not employ an independent ping-pong loop caching architecture for dual-path images, making it difficult to guarantee accurate synchronous output of the two-path image data.

[0012] In solving the above problems or overcoming the above defects, the present invention encountered the following difficulties and obstacles:

[0013] Achieving nanosecond-level precise synchronous output of two image data streams on an FPGA platform requires solving the collaborative optimization problem of multiple technical challenges, such as DDR read timing, FIFO buffer management, and clock signal synchronization.

[0014] How to design a ping-pong dual-buffering mechanism to ensure parallel processing of data writing and reading, avoid data conflicts, and ensure the accuracy of frame switching.

[0015] How to flexibly configure the fault injection module to simulate multiple fault modes while ensuring high-precision synchronization, without affecting the normal image transmission timing? Summary of the Invention

[0016] The purpose of this invention is to provide a binocular camera image synchronization simulation injection method and system to solve the technical problems or combinations thereof in existing image simulation systems, such as the inability to achieve high-precision time synchronization output of dual-channel image data, the lack of fault injection capability, and the inability to meet the algorithm verification requirements with stringent time consistency requirements.

[0017] Terminology Explanation

[0018] Unless otherwise defined, all technical terms in this document have the same meanings as commonly understood by one of ordinary skill in the art to which the subject matter of the claims pertains. Unless otherwise stated, all patents, patent inventions, and publications cited in this document are incorporated herein by reference in their entirety. If multiple definitions exist for terms in this document, the definitions in this chapter shall prevail.

[0019] It should be understood that the above brief description and the following detailed description are exemplary and for illustrative purposes only, and do not limit the subject matter of the invention in any way. In this invention, the singular is used in conjunction with the plural unless otherwise specified. It should also be noted that, unless otherwise specified, the use of “or” or “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms such as “including,” “containing,” and “contains” are not limiting.

[0020] The term "ping-pong caching" used in this article refers to a double-buffering technique that sets up two independent buffer areas (ping area and pong area). When data is written to one buffer area, data is read from the other buffer area, and the continuity and seamless connection of data transmission are achieved by switching between them.

[0021] The term "FIFO" used in this article refers to First In First Out, a data buffer structure that outputs data in the order it enters, and is often used for data rate matching and timing alignment.

[0022] The term "frame start signal" as used in this article refers to a synchronization signal used to identify the start of transmission of a frame of image data, which is generated by the FPGA's internal clock through counting in this invention.

[0023] The term "column start signal" as used in this article refers to a synchronization signal used to identify the start of transmission of a column of pixels in image data, which is used in this invention to control the synchronous reading of data by two FIFOs.

[0024] The term "synchronization accuracy" used in this article refers to the maximum time difference between the output of two image data streams. In this invention, it is measured in clock cycles, with a 100MHz clock corresponding to a synchronization accuracy of 10ns.

[0025] The term "fault injection" as used in this article refers to the artificial introduction of a specific type of anomaly or error into an image data stream to test the robustness and fault handling capabilities of the system.

[0026] To achieve the above objectives, the present invention provides the following technical solution:

[0027] In a first aspect, the present invention provides:

[0028] A method for synchronous simulation injection of images from a binocular camera, comprising the following technical features: A, B, C, D, E, F, G, H, I.

[0029] in:

[0030] Technical Feature A: The host software reads the two images stored on the hard disk and writes them into the host PCIe device memory;

[0031] Technical Feature B: After the host software is written, it sends a data ready signal to the FPGA;

[0032] Technical Feature C: The FPGA generates frame start signals and column start signals based on its internal clock;

[0033] Technical Feature D: The FPGA reads two images via PCIe and writes them into the ping-pong loop buffers of two DDR channels respectively;

[0034] Technical Feature E: The DDR output is connected to a FIFO, and the FIFO pre-reads one column of data at a time;

[0035] Technical Feature F: Simultaneously reads one column of data from two FIFOs under the action of the column start signal;

[0036] Technical feature G: Two data streams are sent to the image transmission module and then to the image processing module via the image data interface;

[0037] Technical Feature H: A fault injection module is configured between the image FIFO buffer and the image transmission module; the fault injection module can implement pixel error, column loss, and timing jitter fault modes; wherein, pixel error is implemented by replacing image data values ​​with abnormal values; column loss error is implemented by pausing image transmission; timing jitter fault is implemented by delaying transmission;

[0038] Technical Feature I: The internal clock is 100MHz or 200MHz, and the time difference between the two image outputs is less than one clock cycle;

[0039] Among them, technical feature C is selected from:

[0040] C1: Internal clock frequency is 100MHz;

[0041] C2: Internal clock frequency is 200MHz;

[0042] C3: Internal clock frequency is 50MHz;

[0043] C4: Internal clock frequency is 150MHz;

[0044] Among them, the preferred technical feature C is C1 or C2.

[0045] Among them, technical feature C is further preferably: C1.

[0046] Among them, the image data interface of technical feature G is selected from:

[0047] G1: Fiber optic interface;

[0048] G2: MIPI interface;

[0049] G3: Camera Link interface;

[0050] G4: LVDS interface;

[0051] G5: CoaXPress interface;

[0052] Among them, the preferred technical feature G is G1, G2, or G3.

[0053] Among them, the failure modes of technical feature H are selected from:

[0054] H1: Pixel error (replace image data value with an outlier);

[0055] H2: Column missing (image transmission paused, one or more columns missing);

[0056] H3: Timing jitter (delayed transmission);

[0057] H4: Frame loss (loss of the entire frame of image).

[0058] H5: Data Flip (Random Bit Flip);

[0059] Among them, the preferred technical feature H is H1, H2, or H3.

[0060] Based on further solutions to the technical problems of the present invention, or simultaneous solutions to multiple technical problems, the preferred solution in the technical solution provided in the first aspect of the present invention includes:

[0061] The first preferred solution: The image format includes 640×512×16bit, 1280×1080×16bit, or other images of the same size. The image data stored on the hard disk can be a standard test set, a custom scene, or recorded real data. This technical solution, based on solving the technical problem of "simultaneous output of dual-channel images," further solves the technical problem of "flexible configuration supporting multiple resolutions and multiple data sources."

[0062] The second preferred solution is to set up ping and pong buffers for the two image streams in DDR, and switch between the buffers using the frame start signal. This solution not only solves the technical problem of "synchronous output of dual images", but also further solves the technical problem of "ensuring parallel processing of data writing and reading, and achieving seamless switching between frames".

[0063] The third preferred solution: FIFO is used to buffer data column by column to achieve synchronous column-by-column reading of two images. This technical solution, while solving the technical problem of "synchronous output of dual images", further solves the technical problem of "achieving pixel-level precise synchronization".

[0064] The fourth preferred solution: When injecting image data of different formats, the host software sends image size parameters (including the number of rows, columns, frame rate, etc.) to the FPGA. This technical solution, in addition to solving the technical problem of "synchronous output of dual-channel images", further solves the technical problem of "supporting dynamic configuration of image parameters".

[0065] The fifth preferred solution: repeatedly read data from the FIFO and send it until a frame is read. After receiving the start signal of the next frame, the two DDR channels perform a ping-pong area switch and start sending the next frame. This technical solution, based on solving the technical problem of "synchronous output of dual-channel images", further solves the technical problem of "stable synchronous transmission of multiple consecutive frames of images".

[0066] Secondly, the present invention provides:

[0067] A binocular camera image synchronization simulation injection system includes: a general-purpose computer, an FPGA board with a PCIe interface, and dual-channel DDR memory located on the FPGA board.

[0068] The general-purpose computer runs host software to read two channels of image data from the hard drive and write them to the PCIe device memory, as well as control the fault injection module.

[0069] The FPGA board includes: an image transmission timing control module, a PCIe interface module, a DDR control module, a FIFO buffer module, a fault injection module, and an image transmission module.

[0070] Compared with the prior art, the present invention has the following advantages:

[0071] I. Compared with the prior art, the present invention has a significantly improved technical effect in terms of synchronization accuracy.

[0072] This invention reduces the time difference between dual-channel image output from microseconds (<1μs) to nanoseconds (<10ns) compared to existing technologies, improving synchronization accuracy by more than two orders of magnitude. With an internal clock of 100MHz, the time difference between the two data outputs is less than one clock cycle (10ns), meeting the stringent time consistency requirements of algorithms such as stereo matching, inter-frame differencing, and 3D positioning.

[0073] Second, compared with the prior art, the present invention provides controllable fault injection capability.

[0074] This invention configures a fault injection module between the image FIFO buffer and the image transmission module, which can proactively and accurately inject faults such as pixel errors, column loss, and timing jitter into the image data stream for system robustness testing and fault reproduction and localization, helping developers quickly identify and resolve potential problems. This is a function not available in existing technologies.

[0075] Third, compared with the prior art, the present invention adopts a clearly implementable dual-path independent ping-pong caching architecture.

[0076] This invention sets up independent DDR ping-pong buffers for each of the two image streams, and switches between buffers using a frame start signal to ensure parallel processing of data writing and reading, avoid data conflicts, and achieve seamless switching between frames. This technical solution has a clear implementation path and is reproducible.

[0077] Fourth, this invention has good flexibility and scalability.

[0078] The FPGA-based implementation provides the system with a high degree of flexibility. By reconfiguring the FPGA logic, it can easily adapt to different image resolutions (640×512, 1280×1080, etc.), frame rates, data interfaces (fiber optic, MIPI, CameraLink, LVDS, etc.), and simulate more than two camera systems, showing good prospects for industrial applications and room for technological evolution.

[0079] Fifth, this invention can significantly improve the efficiency of algorithm development and reduce the cost of research and development and testing.

[0080] This invention can replace expensive camera equipment, complex test scenarios, and large experimental platforms, reducing equipment procurement costs and avoiding uncontrollable testing problems caused by environmental factors. Users can freely load specified image sequences (including standard test sets, custom scenes, or recorded real data) to achieve complete consistency in test conditions, greatly facilitating comparative and regression testing of algorithms. Attached Figure Description

[0081] Figure 1 A hardware block diagram of a binocular camera image synchronization simulation injection method provided in an embodiment of the present invention;

[0082] Figure 2 This is a data flow diagram of a binocular camera image synchronization simulation injection method provided in an embodiment of the present invention. Detailed Implementation

[0083] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0084] The binocular camera image synchronization simulation injection method and system provided by this invention rely on a general-purpose computer and an FPGA board with a PCIe interface to work together to simulate the injection of two infrared or visible light image data with time synchronization characteristics into the image processing module. This method can simulate the image synchronization output process of a binocular camera with high precision in a laboratory environment and is suitable for application scenarios such as algorithm verification, system integration and fault reproduction.

[0085] like Figure 1 As shown, the hardware system of this invention mainly comprises three parts: a general-purpose computer, an FPGA board, and a dual-channel DDR memory. The general-purpose computer, acting as the host, runs host software and is responsible for reading two channels of image data from the hard disk and writing them to the device memory of the FPGA board via the PCIe interface. It also handles sending control signals to the FPGA and configuring the fault injection module. The FPGA board has a PCIe interface and integrates functional units such as an image transmission timing control module, a PCIe interface module, a DDR control module, a FIFO buffer module, a fault injection module, and an image transmission module. The dual-channel DDR memory is located on the FPGA board and is used to buffer the two channels of image data respectively. Each DDR channel has two independent buffer areas: a ping area and a pong area, forming a ping-pong circular buffer structure.

[0086] like Figure 2 As shown, the data flow of the present invention includes the following specific steps.

[0087] First, the host software reads the two image data streams stored on the hard drive and writes them into the host PCIe device memory. The image data stored on the hard drive can come from various sources, including standard test sets, user-defined simulation scenarios, or actual data recorded from real cameras. The two images should be in the same format, and the resolution can be configured according to actual needs. For example, 640×512×16bit is suitable for certain infrared imaging scenarios, and 1280×1080×16bit is suitable for high-definition visible light imaging scenarios. Other image formats with consistent dimensions are also acceptable. When different image data formats need to be injected, the host software needs to send the corresponding image size parameters to the FPGA. These parameters include the number of rows, columns, and frame rate of the image, so that the FPGA can correctly configure its internal timing control logic.

[0088] After the host software completes writing the image data, it sends a data ready signal to the FPGA, notifying the FPGA that it can begin reading the image data. This handshake mechanism ensures the reliability of data transmission between the host and the FPGA, preventing data errors caused by the FPGA starting to read before the data is fully written.

[0089] The image transmission timing control module on the FPGA operates based on an internal clock, generating frame start and column start signals via counters. The internal clock frequency can be configured to 100MHz or 200MHz; a higher clock frequency provides finer timing control. The frame start signal identifies the beginning of a frame and controls the switching of the DDR buffer; the column start signal identifies the beginning of each column of data in the image and controls the synchronous read operations of the two FIFOs. Because the timing control signals for both images are generated from the same clock source through the same counting logic, strict consistency in timing between the two data streams is guaranteed.

[0090] After receiving the data ready signal, the FPGA reads two channels of image data through the PCIe interface and buffers them into two DDR memories. Each DDR uses a ping-pong dual-buffer structure, meaning it has two independent buffer areas: a ping area and a pong area. While the system is reading data from one buffer and sending it to the image processing module, the other buffer can simultaneously receive a new frame of image data from the host, allowing the two operations to run in parallel without interference. This design effectively solves the conflict between data writing and reading, enabling seamless inter-frame switching during continuous multi-frame image transmission. Buffer switching is controlled by a frame start signal. After one frame of image data is sent and the next frame start signal is received, both DDRs simultaneously perform ping-pong area switching and begin sending the next frame of image data.

[0091] The output of the DDR memory is connected to a FIFO buffer module. The FIFO uses a first-in, first-out (FIFO) data structure to buffer image data column by column. Specifically, the FIFO pre-reads one column of image data at a time for buffering. Once the image transmission module has completely read that column of data, the FIFO automatically requests the DDR to read the next column. This column-by-column pre-reading mechanism ensures that image data can be output continuously and stably in columns, while also providing a buffer for the synchronous reading of data from both channels.

[0092] Under the influence of the column start signal, the system simultaneously reads one column of data from two FIFOs. Since the column start signal is generated by the same clock source and applies to both FIFOs simultaneously, the reading operations of the two data streams are strictly synchronized in time. With an internal clock configuration of 100MHz, the output time difference between the two image data streams is less than one clock cycle, i.e., less than 10ns, achieving nanosecond-level synchronization accuracy. This synchronization accuracy is more than two orders of magnitude higher than the microsecond-level accuracy of existing technologies, meeting the stringent time consistency requirements of algorithms such as stereo matching, inter-frame differencing, and 3D positioning.

[0093] Data read from the two FIFOs is sent to their respective image transmission modules, and then transmitted to the downstream image processing module via the image data interface. This invention supports multiple image data interface types, including fiber optic interfaces, MIPI interfaces, and Camera Link interfaces. Different image data interfaces have different physical characteristics and protocol specifications, suitable for different application scenarios. For example, fiber optic interfaces have the characteristics of long transmission distance and strong anti-interference capability, suitable for long-distance transmission or situations with complex electromagnetic environments; MIPI interfaces are widely used in mobile devices and embedded systems; Camera Link interfaces are the standard interface in the industrial camera field, with advantages of high bandwidth and low latency. Selecting different image data interfaces requires downloading different FPGA code; that is, corresponding FPGA logic programs are pre-written for different interface types, and the corresponding program is loaded according to actual needs during use.

[0094] A fault injection module is configured between the image FIFO buffer and the image transmission module. The control signals for the fault injection module are sent by the host software via the PCIe interface, allowing for flexible configuration of different fault modes according to testing requirements. This invention supports three fault modes: pixel error, column loss, and timing jitter. Pixel error faults are implemented by replacing pixel values ​​at specific locations in the image data with abnormal values. For example, a normal pixel value can be replaced with 0 to represent complete black, or with 16384 (a saturation value for 14-bit images) to represent overexposure, or other preset abnormal values. Column loss faults are implemented by pausing image transmission, simulating the loss of one or multiple consecutive columns of image data, used to test the image processing algorithm's tolerance to data loss. Timing jitter faults are implemented by introducing delays during data transmission, simulating timing instability that may occur in real-world systems. The fault injection function enables this invention not only to simulate the output of a stereo camera under normal operating conditions but also to accurately simulate various abnormal scenarios, providing a powerful tool for system robustness testing and fault reproduction and localization.

[0095] The system repeatedly reads data from the FIFO and sends it until all columns of data for one frame of image have been read. Then, upon receiving the start signal of the next frame, both DDR channels simultaneously switch ping-pong buffers, starting to read and send the next frame of image data from the other buffer. This process is repeated to achieve stable synchronous transmission of multiple consecutive frames of images.

[0096] This invention, through the aforementioned technical solution, uses the FPGA's internal clock as a unified timing reference to drive two image data streams to achieve synchronous sampling and transmission along the complete data path of "DDR→FIFO→image transmission module". Since all timing control signals originate from the same clock domain, the operation timing of the two data streams is completely consistent, thereby controlling the output time difference between the two image data streams to within one clock cycle. When using a 100MHz internal clock, the corresponding synchronization accuracy reaches 10ns; when using a 200MHz internal clock, the synchronization accuracy can be further improved to 5ns.

[0097] In practical applications, this invention can be flexibly configured according to different testing requirements. For testing infrared binocular vision systems, a 640×512×16bit resolution infrared image sequence can be loaded; for testing visible light stereo vision systems, a 1280×1080×16bit resolution high-definition image sequence can be loaded. Image data can come from standard test image sets to verify the basic functions of the algorithm, or from simulated images generated in specific scenarios to test the algorithm's performance in the target application environment, or from image data recorded by real cameras to reproduce actual working conditions. Through the fault injection module, testers can artificially introduce various faults into the normal image stream to evaluate the image processing system's ability to detect and handle abnormal situations, which is of great significance for improving system reliability.

[0098] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for synchronous simulation injection of images from a binocular camera, characterized in that, Includes the following steps: 1) The host software reads the two images stored on the hard disk and writes them into the host PCIe device memory; 2) After the host software is written, it sends a data ready signal to the FPGA; 3) The FPGA generates frame start signals and column start signals based on its internal clock; 4) The FPGA reads two images via PCIe and writes them into the ping-pong loop buffers of two DDR channels respectively; 5) The DDR output is connected to a FIFO. The FIFO pre-reads one column of data at a time, and automatically reads the next column after one column is read. 6) Simultaneously read one column of data from two FIFOs under the action of the column start signal; 7) The two data streams are sent to the image transmission module and then to the image processing module via the image data interface; 8) Repeat steps 6-7 until a frame is read; 9) After receiving the next frame start signal, the two DDR channels perform ping-pong area switching and start sending the next frame; In step 7, before the two data streams are sent to the image transmission module, a fault injection module is configured between the image FIFO buffer and the image transmission module. The host software controls the fault injection module via the PCIe interface. The fault injection module can implement pixel error, column loss, and timing jitter fault modes. Pixel error is achieved by replacing image data values ​​with abnormal values; column loss error is achieved by pausing image transmission; and timing jitter fault is achieved by delaying transmission. The internal clock is 100MHz or 200MHz, and the time difference between the two image outputs is less than one clock cycle.

2. The method according to claim 1, characterized in that: The image format includes 640×512×16bit, 1280×1080×16bit or other images of the same size, and the image data stored on the hard disk is a standard test set, a custom scene or recorded real data.

3. The method according to claim 1, characterized in that: The two image streams are configured with ping and pong buffers in DDR respectively, and the buffer switching is achieved through the frame start signal.

4. The method according to claim 1, characterized in that: The FIFO is used to cache data column by column to enable synchronous column-by-column reading of two images.

5. The method according to claim 1, characterized in that: When injecting image data of different formats, the host software sends image size parameters to the FPGA, which include the number of rows, the number of columns, and the frame rate.

6. The method according to claim 1, characterized in that: The image data interface includes fiber optic, MIPI, or Camera Link interfaces; different image data interfaces are selected by downloading different FPGA code.

7. A binocular camera image synchronization simulation injection system, using the binocular camera image synchronization simulation injection method as described in claim 1, characterized in that, include: A general-purpose computer, running host software, is used to read two channels of image data from the hard drive and write them to the PCIe device memory; The FPGA board has a PCIe interface and includes an image transmission timing control module, a DDR control module, a FIFO buffer module, a fault injection module, and an image transmission module. Dual-channel DDR memory, located on the FPGA board, is used to cache two channels of image data, with each DDR channel having a ping-pong cyclic buffer.

8. The system according to claim 7, characterized in that: The image transmission timing control module generates frame start signal and column start signal based on the FPGA internal clock to control the synchronous output of two image data channels, so that the time difference between the two image output channels is less than one clock cycle.

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