Micro-led chip and preparation method thereof
By setting a buffer layer of alternating SiO2 and HfO2 on the sidewall of the isolation trench of the Micro-LED chip, the problem of Bragg mirror breakage during laser lift-off was solved, improving the chip yield and brightness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGXI ZHAO CHI SEMICON CO LTD
- Filing Date
- 2026-02-10
- Publication Date
- 2026-04-28
AI Technical Summary
During the laser stripping process, the Bragg reflector on the sidewall of the isolation trench of the Micro-LED chip delaminates and breaks, resulting in a loss of light emission brightness. Existing solutions result in the loss of some side light emission, affecting chip yield and brightness.
A buffer layer and a DBR reflective layer are set on the sidewall of the isolation trench. The buffer layer is composed of alternating layers of SiO2 and HfO2, and its thermal expansion coefficient is between that of the N-type semiconductor layer and the DBR reflective layer. This adjusts the thermal mismatch and prevents crack formation.
This effectively prevents the DBR reflective layer from cracking during rapid temperature changes, improving chip manufacturing yield and brightness, and ensuring structural integrity.
Smart Images
Figure CN121692878B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a Micro-LED chip and its fabrication method. Background Technology
[0002] The fabrication of Micro-LED chips involves a laser lift-off process. During this process, the Bragg reflectors on the sidewall surface of the isolation trench of the Micro-LED chip decompose and crack from the sidewall. This is because the laser lift-off process involves a rapid increase and rapid cooling of heat, and the difference in thermal expansion coefficients between the sidewall of the isolation trench and the Bragg reflectors on the sidewall surface is significant. Therefore, after the laser lift-off is completed, the Bragg reflectors on the sidewall surface of the isolation trench will decompose and crack from the sidewall. The existing solution is not to fabricate the Bragg reflector layer on the slope of the isolation trench, but this will result in the loss of some side light emission from the Micro-LED chip, causing a loss of luminous brightness. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a Micro-LED chip with high yield and high brightness.
[0004] Accordingly, the present invention also provides a method for fabricating the above-mentioned Micro-LED chip.
[0005] To address the aforementioned technical problems, this invention provides a Micro-LED chip comprising an epitaxial layer, a current spreading layer, a P-type metal conductive layer, an N-type metal conductive layer, a DBR reflective layer, a P-type pad layer, and an N-type pad layer.
[0006] The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked sequentially. A light-emitting structure, an N-type conductive step, and an isolation trench are formed on the epitaxial layer. The N-type conductive step is disposed on one side of the light-emitting structure, and the isolation trench is disposed around the light-emitting structure. The sidewall of the isolation trench exposes the N-type semiconductor layer.
[0007] A buffer layer and a DBR reflective layer are sequentially stacked on the sidewall of the isolation trench; the buffer layer includes alternating layers of a first SiO2 layer and an HfO2 layer, and the thermal expansion coefficient of the buffer layer is greater than that of the N-type semiconductor layer and less than that of the DBR reflective layer.
[0008] As an improvement to the above technical solution, the number of cycles of the buffer layer is 2 to 4;
[0009] The thickness of a single first SiO2 layer is 50 Å to 150 Å, and the thickness of a single HfO2 layer is 200 Å to 400 Å.
[0010] As an improvement to the above technical solution, along the growth direction of the buffer layer, the thickness of the HfO2 layer in the later cycle is greater than the thickness of the HfO2 layer in the previous cycle, and the thickness of the first SiO2 layer in the later cycle is less than the thickness of the first SiO2 layer in the previous cycle.
[0011] As an improvement to the above technical solution, in the buffer layer of the first cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 1:1 to 1:2.
[0012] In the buffer layer of the last cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 1:5 to 1:6.5.
[0013] As an improvement to the above technical solution, the number of cycles of the buffer layer is 3, and along the growth direction of the buffer layer, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer in each cycle is 1:1.1~1:1.5, 1:2~1:2.5 and 1:5.5~1:6.5, respectively.
[0014] As an improvement to the above technical solution, the DBR reflective layer includes alternating layers of second SiO2 and TiO2, with a period number of 10 to 25.
[0015] The thickness of a single second SiO2 layer is 500 Å to 1200 Å, and the thickness of a single TiO2 layer is 400 Å to 1000 Å.
[0016] As an improvement to the above technical solution, both the P-type metal conductive layer and the N-type metal conductive layer include a Cr layer, a first Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer, a first Au layer, a third Pt layer, and a third Ti layer stacked sequentially, with thicknesses of 30Å~50Å, 1200Å~2000Å, 1000Å~2000Å, 500Å~1000Å, 1000Å~2000Å, 500Å~1000Å, 8000Å~10000Å, 2000Å~3000Å, and 30Å~50Å, respectively.
[0017] As an improvement to the above technical solution, both the P-type pad layer and the N-type pad layer include a second Al layer, a fourth Ti layer, a fourth Pt layer, a fifth Ti layer, a Ni layer, and a second Au layer stacked sequentially, with thicknesses of 10000Å~15000Å, 1000Å~2000Å, 500Å~1000Å, 1000Å~2000Å, 6000Å~10000Å, and 300Å~500Å, respectively.
[0018] Accordingly, the present invention also discloses a method for fabricating a Micro-LED chip, which includes:
[0019] (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate;
[0020] (2) A current spreading layer is formed on the epitaxial layer;
[0021] (3) Etch the epitaxial layer and the current spreading layer to form an N-type conductive step that exposes the N-type semiconductor layer, an isolation trench that exposes the substrate, and a light-emitting structure;
[0022] (4) A P-type metal conductive layer is formed on the current spreading layer, and an N-type metal conductive layer is formed on the N-type conductive step;
[0023] (5) A buffer layer is formed on the side wall of the isolation groove to obtain a first intermediate; wherein the buffer layer includes alternating layers of a first SiO2 layer and a HfO2 layer;
[0024] (6) A DBR reflective layer is formed on the first intermediate, and a first via is formed to expose the P-type metal conductive layer and a second via is formed to expose the N-type metal conductive layer;
[0025] (7) A P-type pad layer and an N-type pad layer are formed on the DBR reflective layer to obtain a second intermediate; wherein the P-type pad layer is in contact with the P-type metal conductive layer through a first through-hole, and the N-type pad layer is in contact with the N-type metal conductive layer through a second through-hole.
[0026] (8) The substrate is peeled off from the second intermediate and the epitaxial layer is divided along the isolation trench to obtain multiple Micro-LED chips.
[0027] As an improvement to the above technical solution, in step (5), the first SiO2 layer and HfO2 layer are alternately formed by electron beam evaporation until a buffer layer is obtained;
[0028] In step (6), the second SiO2 layer and TiO2 layer are alternately formed by electron beam evaporation until the DBR reflective layer is obtained.
[0029] Implementing this invention has the following beneficial effects:
[0030] In one embodiment of the present invention, a buffer layer and a DBR reflective layer are disposed on the sidewall of the isolation trench in the Micro-LED chip. The coefficient of thermal expansion of the buffer layer is greater than that of the N-type semiconductor layer and less than that of the DBR reflective layer. Based on this, the thermal mismatch between the N-type semiconductor layer and the DBR reflective layer can be effectively adjusted, avoiding cracks or ruptures in the DBR reflective layer during rapid heating / cooling, thereby ensuring the structural integrity of the Micro-LED chip before and after laser lift-off and improving the manufacturing yield. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of the structure of a Micro-LED chip in one embodiment of the present invention;
[0032] Figure 2 This is a schematic diagram of the structure of the buffer layer in one embodiment of the present invention;
[0033] Figure 3 This is a schematic diagram of the structure of the first intermediate after step (6) in one embodiment of the present invention;
[0034] In the figure, 110 is the N-type semiconductor layer, 120 is the light-emitting layer, 130 is the P-type semiconductor layer, 140 is the N-type conductive step, 150 is the isolation trench, 160 is the light-emitting structure, 200 is the current spreading layer, 310 is the P-type metal conductive layer, 320 is the N-type metal conductive layer, 400 is the DBR reflective layer, 410 is the first via, 420 is the second via, 510 is the P-type pad layer, 520 is the N-type pad layer, 600 is the buffer layer, 610 is the first SiO2 layer, 620 is the HfO2 layer, and 700 is the substrate. Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this document are based solely on the accompanying drawings and are not intended to specifically limit the invention.
[0036] Please see Figure 1 , Figure 2 An embodiment of the present invention provides a Micro-LED chip, which includes an epitaxial layer, a current spreading layer 200, a P-type metal conductive layer 310, an N-type metal conductive layer 320, a DBR reflective layer 400, a P-type pad layer 510, an N-type pad layer 520, and a buffer layer 600.
[0037] In the vertical direction, the epitaxial layer includes an N-type semiconductor layer 110, a light-emitting layer 120, and a P-type semiconductor layer 130 stacked sequentially. A light-emitting structure 160, an isolation trench 150, and an N-type conductive step 140 are formed on the epitaxial layer. The isolation trench 150 is used to divide the epitaxial layer to form multiple Micro-LED chips, which are arranged around the light-emitting structure 160. The N-type conductive step 140 is located on one side of the light-emitting structure 160, exposing the N-type semiconductor layer 110, and is used to form electrical connections with the N-type metal conductive layer 320 and the N-type pad layer 520. The light-emitting structure 160 emits light, and its top is a P-type semiconductor layer 130, which is used to form electrical connections with the P-type metal conductive layer 310 and the P-type pad layer 510.
[0038] Specifically, the N-type semiconductor layer 110 can be an N-type GaAs layer, an N-type GaN layer, or an N-type AlGaN layer, but is not limited to these. The light-emitting layer 120 can be an InGaN-GaN type multiple quantum well layer, an InGaN-AlGaN type multiple quantum well layer, an AlGaN-AlGaN type multiple quantum well layer, or an AlGaInP-AlGaInP type multiple quantum well layer, but is not limited to these. The P-type semiconductor layer 130 can be a P-type GaN layer, a P-type AlGaInP layer, or a P-type AlGaN layer, but is not limited to these. Preferably, in some embodiments, the N-type semiconductor layer 110 is an N-type GaN layer, the light-emitting layer 120 is an InGaN-GaN type multiple quantum well layer, and the P-type semiconductor layer 130 is a P-type GaN layer.
[0039] Specifically, the sidewall of the isolation trench 150 exposes the N-type semiconductor layer 110, and a buffer layer 600 and a DBR reflective layer 400 are sequentially stacked on the sidewall of the isolation trench 150. The buffer layer 600 includes alternating layers of a first SiO2 layer 610 and an HfO2 layer 620. The coefficient of thermal expansion of the buffer layer 600 is greater than that of the N-type semiconductor layer 110 and less than that of the DBR reflective layer 400. Based on this, the thermal mismatch between the N-type semiconductor layer 110 and the DBR reflective layer 400 can be effectively adjusted, preventing cracks or breakage of the DBR reflective layer 400 during rapid heating / cooling, thereby ensuring the structural integrity of the Micro-LED chip before and after laser lift-off and improving manufacturing yield. Specifically, taking the common SiO2 / TiO2 type DBR reflective layer 400 as an example, the coefficient of thermal expansion of a single layer of SiO2 is 0.5~0.55×10⁻⁶. -6 K -1 The coefficient of thermal expansion of a single layer of TiO2 is approximately 8.6~10×10⁻⁶. -6 K -1 This makes the overall thermal expansion coefficient of the DBR reflective layer similar to that of the N-type semiconductor layer (typically GaN, with a thermal expansion coefficient of approximately 2.9~5.5×10⁻⁶). -6 K -1The thermal expansion coefficients of the two layers are significantly different, resulting in a large thermal mismatch between the DBR reflective layer 400 and the N-type semiconductor layer 110 during rapid heating and cooling, which can easily lead to cracking of the DBR reflective layer 400. The buffer layer 600 introduced in this application is formed by alternating layers of a first SiO2 layer 610 and an HfO2 layer 620, with the HfO2 layer 620 having a thermal expansion coefficient of 5.0~5.5×10⁻⁶. -6 K -1 Therefore, the coefficient of thermal expansion of the buffer layer 600 is generally between that of the N-type semiconductor layer 110 and the DBR reflective layer 400, which plays a good role in thermal buffering, reducing the cracking of the DBR reflective layer 400 and improving the manufacturing yield. Furthermore, it should be noted that during the fabrication and transfer of Micro-LED chips, not only is laser used for substrate lift-off, but also for wafer-to-chip dicing. This generates a lot of heat, resulting in significant stress changes due to thermal variations.
[0040] Specifically, the buffer layer 600 can be made of one or more of HfO2, Ta2O5, and SiO2, but is not limited to these. The thickness of the buffer layer 600 is 500Å to 3000Å. If its thickness is too small, it will be difficult to effectively buffer thermal stress; if its thickness is too large, it may lead to stress accumulation and cause cracking risk, which will also reduce reliability.
[0041] Specifically, the current spreading layer 200 is disposed on the P-type semiconductor layer 130 on top of the light-emitting structure 160, and it is an ITO layer, an IZO layer, or an AZO layer, but is not limited to these. The current spreading layer 200 can enhance current diffusion and avoid current congestion.
[0042] Specifically, the P-type metal conductive layer 310 is disposed on the current spreading layer 200, and the N-type metal conductive layer 320 is disposed on the N-type conductive step 140. Both the P-type metal conductive layer 310 and the N-type metal conductive layer 320 are common single-layer or multilayer metal structures in the art, and for example, they can be made of one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag, but are not limited thereto. Preferably, in some embodiments, both the P-type metal conductive layer 310 and the N-type metal conductive layer 320 include a Cr layer, a first Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer, a first Au layer, a third Pt layer, and a third Ti layer stacked sequentially, with thicknesses of 30 Å~50 Å, 1200 Å~2000 Å, 1000 Å~2000 Å, 500 Å~1000 Å, 1000 Å~2000 Å, 500 Å~1000 Å, 8000 Å~10000 Å, 2000 Å~3000 Å, and 30 Å~50 Å, respectively.
[0043] Specifically, see Figure 1 , Figure 3The DBR reflective layer 400 covers the isolation groove 150, the N-type conductive step 140, the N-type metal conductive layer 320, the light-emitting structure 160, and the P-type metal conductive layer 310. A first through-hole 410 exposing the P-type metal conductive layer 310 and a second through-hole 420 exposing the N-type metal conductive layer 320 are formed on the DBR reflective layer 400. The DBR reflective layer 400 not only reflects the light emitted from the light-emitting layer 120 but also passivates the sidewalls of the light-emitting structure 160 and the etching defects of the N-type conductive step 140, thereby improving luminous efficiency.
[0044] Specifically, the DBR reflective layer 400 can be a SiO2-TiO2 type DBR layer, a SiO2-Ti2O5 type DBR layer, or a SiO2-MgF2 type DBR layer, but is not limited to these. Preferably, in some embodiments, the DBR reflective layer 400 includes alternating layers of second SiO2 layers and TiO2 layers, with a period number of 10 to 25; the thickness of a single second SiO2 layer is 500 Å to 1200 Å. The thickness of a single TiO2 layer is 400 Å to 1000 Å.
[0045] Specifically, both the P-type pad layer 510 and the N-type pad layer 520 are disposed above the DBR reflective layer 400. The P-type pad layer 510 contacts the P-type metal conductive layer 310 through a first via 410, and the N-type pad layer 520 contacts the N-type metal conductive layer 320 through a second via 420. One side of the N-type pad layer 520 extends onto the DBR reflective layer 400 located above the light-emitting structure 160. Based on this, the P-type pad layer 510 and the N-type pad layer 520 can be made to be at approximately the same height, improving the yield of subsequent transfer processes.
[0046] Specifically, the P-type pad layer 510 and the N-type pad layer 520 are common metal pad structures in the art, such as a stacked structure composed of one or more of Ti, Sn, Ni, and Au, but are not limited thereto. Preferably, both the P-type pad layer 510 and the N-type pad layer 520 include a second Al layer, a fourth Ti layer, a fourth Pt layer, a fifth Ti layer, a Ni layer, and a second Au layer stacked sequentially, with thicknesses of 10000Å~15000Å, 1000Å~2000Å, 500Å~1000Å, 1000Å~2000Å, 6000Å~10000Å, and 300Å~500Å, respectively.
[0047] Preferably, please refer to Figure 2In some embodiments, the buffer layer 600 includes alternating layers of a first SiO2 layer 610 and an HfO2 layer 620, with a cycle number of 2 to 4. This buffer layer 600 not only effectively alleviates thermal stress but also significantly improves the interfacial bonding strength between the buffer layer 600 and the N-type semiconductor layer 110 and the DBR reflective layer 400, thereby enhancing the reliability of the Micro-LED chip. Specifically, the thickness of the first SiO2 layer 610 is 50 Å to 150 Å, exemplarily 65 Å, 80 Å, 95 Å, 110 Å, 125 Å, or 140 Å, but is not limited thereto. Preferably, it is 60 Å to 150 Å. The thickness of the HfO2 layer 620 is 200 Å to 400 Å, exemplarily 240 Å, 280 Å, 320 Å, or 360 Å, but is not limited thereto. Preferably, it is 200 Å to 350 Å.
[0048] Preferably, in some embodiments, along the growth direction of the buffer layer 600, the thickness of the HfO2 layer 620 in the later cycle is greater than the thickness of the HfO2 layer 620 in the previous cycle, and the thickness of the first SiO2 layer 610 in the later cycle is less than the thickness of the first SiO2 layer 610 in the previous cycle. This gradient thickness design can further optimize the distribution of thermal stress, reduce the interface stress concentration caused by the difference in the interlayer thermal expansion coefficient, effectively avoid crack initiation and propagation, and effectively improve manufacturing yield.
[0049] More specifically, in the first cycle of the buffer layer 600, the thickness ratio of the first SiO2 layer 610 to the thickness of the HfO2 layer 620 is 1:1 to 1:2; in the last cycle of the buffer layer 600, the thickness ratio of the first SiO2 layer 610 to the thickness of the HfO2 layer 620 is 1:5 to 1:6.5. In the intermediate cycles, the thickness ratio of the two layers varies with a gradient, which can be linear or nonlinear, but is not limited to this. More preferably, the number of cycles of the buffer layer 600 is 3, and along the growth direction of the buffer layer 600, the thickness ratio of the first SiO2 layer 610 to the thickness of the HfO2 layer 620 in each cycle is 1:1.1 to 1:1.5, 1:2 to 1:2.5, and 1:5.5 to 1:6.5, respectively.
[0050] Accordingly, the present invention also discloses a method for fabricating a Micro-LED chip, which specifically includes the following steps:
[0051] (1) Forming an epitaxial layer on a substrate;
[0052] Specifically, the substrate 700 may be a sapphire substrate or a silicon substrate, but is not limited to these. The substrate 700 will be removed during subsequent fabrication processes.
[0053] Specifically, an N-type semiconductor layer 110, a light-emitting layer 120, and a P-type semiconductor layer 130 are sequentially formed on a substrate 700 using methods such as MOCVD, MBE, and PVD, thus obtaining an epitaxial layer.
[0054] (2) A current spreading layer is formed on the epitaxial layer;
[0055] Specifically, the current spreading layer 200 can be formed by electron beam evaporation or PVD, but is not limited to these methods.
[0056] (3) Etch the epitaxial layer and current spreading layer to form an N-type conductive step that exposes the N-type semiconductor layer, an isolation trench that exposes the substrate, and a light-emitting structure;
[0057] Specifically, the current spreading layer 200 can be etched first to expose the epitaxial layer; then the epitaxial layer can be etched to form an N-type conductive step 140; and then the N-type semiconductor layer 110 can be etched to form an isolation trench 150 that exposes the substrate 700, but this is not the only option.
[0058] Preferably, in some embodiments, a photoresist layer is first formed on the current spreading layer 200, and the photoresist layer in a predetermined area is removed by exposure and development. Then, the current spreading layer 200 is removed using an etchant to expose the P-type semiconductor layer 130. Next, the exposed P-type semiconductor layer 130, the light-emitting layer 120, and the N-type semiconductor layer 110 of a predetermined thickness are removed by inductively coupled plasma etching to form an N-type conductive step 140. Then, the photoresist layer is removed. A new photoresist layer is then formed, and the photoresist layer in a predetermined area is removed by exposure and development to expose the N-type conductive step 140. Then, a portion of the exposed N-type conductive step 140 is removed using inductively coupled plasma etching, and finally, the photoresist layer is removed to form an isolation trench 150.
[0059] (4) A P-type metal conductive layer is formed on the current spreading layer, and an N-type metal conductive layer is formed on the N-type conductive step;
[0060] Specifically, metal stacks can be formed through electron beam evaporation or PVD processes to obtain a P-type metal conductive layer 310 and an N-type metal conductive layer 320, but are not limited to these methods.
[0061] Preferably, in some embodiments, a photoresist layer is first formed on the light-emitting structure 160, the N-type conductive step 140, and the isolation trench 150. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type metal conductive layer 310 and an N-type metal conductive layer 320. Then, the metal on the photoresist layer is removed by blue film stripping. Finally, the photoresist layer is removed.
[0062] (5) A buffer layer is formed on the side wall of the isolation tank to obtain the first intermediate;
[0063] Specifically, the buffer layer 600 can be formed by electron beam evaporation, PECVD, MOCVD or PVD, but is not limited to these methods.
[0064] Preferably, in some embodiments, a photoresist layer is first formed using negative photoresist, and then the photoresist layer on the sidewall of the isolation tank 150 is removed by exposure and development. Then, the first SiO2 layer 610 and the HfO2 layer 620 are alternately deposited using an electron beam evaporation process until a buffer layer 600 is obtained. Then, the buffer layer 600 located on the photoresist layer is removed using a blue film stripping process, and finally the photoresist layer is removed.
[0065] (6) A DBR reflective layer is formed on the first intermediate, and a first via is formed to expose the P-type metal conductive layer and a second via is formed to expose the N-type metal conductive layer 320;
[0066] Specifically, the DBR reflective layer 400 can be formed by electron beam evaporation, PECVD or other processes, and then photolithography can be used to form the first via 410 and the second via 420, but it is not limited to this.
[0067] Preferably, in some embodiments, a second SiO2 layer and a TiO2 layer are alternately deposited using an electron beam evaporation process until a DBR reflective layer 400 is obtained. Then, a photoresist layer is formed on the DBR reflective layer 400, and the photoresist layer in a predetermined area is removed by exposure and development. Finally, the exposed DBR reflective layer 400 is removed using an inductively coupled plasma etching process, forming a first via 410 exposing a P-type conductive metal layer 310 and a second via 420 exposing an N-type conductive metal layer 320.
[0068] (7) A P-type pad layer and an N-type pad layer are formed on the DBR reflective layer to obtain the second intermediate;
[0069] Specifically, metal layers can be formed through electron beam evaporation or PVD processes to obtain P-type pad layer 510 and N-type pad layer 520, but are not limited to these.
[0070] Preferably, in some embodiments, a photoresist layer is first formed on the DBR reflective layer 400, inside the first via 410 and inside the second via 420. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type pad layer 510 and an N-type pad layer 520. Then, the metal on the photoresist layer is removed by blue film stripping. Finally, the photoresist layer is removed.
[0071] (8) The substrate is peeled off from the second intermediate and the epitaxial layer is divided along the isolation trench to obtain multiple Micro-LED chips.
[0072] Specifically, a laser lift-off process is used to peel the substrate 700 from the second intermediate, but this is not the only method used. After peeling, the resulting wafer can be directly diced to form individual dies, thus creating a Micro-LED chip.
[0073] The present invention will be further described below with reference to specific embodiments:
[0074] Example 1
[0075] This embodiment provides a Micro-LED chip, which includes an epitaxial layer, a current spreading layer, a P-type metal conductive layer, an N-type metal conductive layer, a DBR reflective layer, a P-type pad layer, and an N-type pad layer.
[0076] The epitaxial layer comprises sequentially stacked N-type GaN layers, InGaN-GaN type multiple quantum well layers, and P-type GaN layers. A light-emitting structure, an isolation trench, and an N-type conductive step are formed on the epitaxial layer. The N-type conductive step is located on one side of the light-emitting structure and exposes the N-type GaN layer. The isolation trench surrounds the light-emitting structure, with its sidewalls exposing the N-type GaN layer. A buffer layer and a DBR reflective layer are sequentially stacked on the sidewalls of the isolation trench. The buffer layer comprises alternating stacked first SiO2 layers and HfO2 layers, with a period of 2. In the first period of the buffer layer, the thickness of the first SiO2 layer is 150 Å, and the thickness of the HfO2 layer is 200 Å; in the second period of the buffer layer, the thickness of the first SiO2 layer is 60 Å, and the thickness of the HfO2 layer is 350 Å.
[0077] The P-type GaN layer has a current spreading layer, which is an ITO layer with a thickness of 800 Å.
[0078] The P-type conductive metal layer is disposed on the current spreading layer, and the N-type conductive metal layer is disposed on the N-type conductive step. Both the P-type and N-type conductive metal layers consist of a Cr layer, a first Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer, a first Au layer, a third Pt layer, and a third Ti layer stacked sequentially, with thicknesses of 40 Å, 1500 Å, 1400 Å, 800 Å, 1500 Å, 600 Å, 9000 Å, 2400 Å, and 50 Å, respectively.
[0079] The DBR reflective layer includes an isolation trench, an N-type conductive step, an N-type metal conductive layer, a light-emitting structure, and a P-type metal conductive layer. A first via exposing the P-type metal conductive layer and a second via exposing the N-type metal conductive layer are formed on the DBR reflective layer. The DBR reflective layer comprises alternating layers of second SiO2 and TiO2 layers, with a period of 20.
[0080] Specifically, both the P-type and N-type pad layers are located above the DBR reflective layer. The P-type pad layer contacts the P-type conductive metal layer through a first via, and the N-type pad layer contacts the N-type conductive metal layer through a second via. Both the P-type and N-type pad layers comprise a second Al layer, a fourth Ti layer, a fourth Pt layer, a fifth Ti layer, a Ni layer, and a second Au layer, stacked sequentially. The thicknesses of each layer are 14000 Å, 1600 Å, 800 Å, 1400 Å, 8000 Å, and 450 Å, respectively.
[0081] The fabrication method of the Micro-LED chip in this embodiment is as follows:
[0082] (1) Forming an epitaxial layer on a substrate;
[0083] Specifically, the substrate can be a sapphire substrate. An N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer are sequentially formed on the substrate using MOCVD to obtain the epitaxial layer.
[0084] (2) A current spreading layer is formed on the epitaxial layer;
[0085] Specifically, the current spreading layer is formed by electron beam evaporation.
[0086] (3) Etch the epitaxial layer and current spreading layer to form an N-type conductive step that exposes the N-type semiconductor layer, an isolation trench that exposes the substrate, and a light-emitting structure;
[0087] Specifically, a photoresist layer is first formed on the current spreading layer. Exposure and development are used to remove the photoresist layer in a predetermined area. Then, an etchant is used to remove the current spreading layer, exposing the P-type semiconductor layer. Next, inductively coupled plasma etching (ICP-CPE) is used to remove the exposed P-type semiconductor layer, the light-emitting layer, and an N-type semiconductor layer of a predetermined thickness, forming N-type conductive steps. The photoresist layer is then removed. A new photoresist layer is formed, and exposure and development are used to remove the photoresist layer in a predetermined area, exposing the N-type conductive steps. ICP-CPE is then used to remove some of the exposed N-type conductive steps, and finally, the photoresist layer is removed, forming an isolation trench.
[0088] (4) A P-type metal conductive layer is formed on the current spreading layer, and an N-type metal conductive layer is formed on the N-type conductive step;
[0089] Specifically, a photoresist layer is first formed on the light-emitting structure, the N-type conductive step, and the isolation trench. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type metal conductive layer and an N-type metal conductive layer. Then, the metal on the photoresist layer is removed by blue film stripping. Finally, the photoresist layer is removed.
[0090] (5) A buffer layer is formed on the side wall of the isolation tank to obtain the first intermediate;
[0091] Specifically, a photoresist layer is first formed using negative photoresist, then the photoresist layer on the sidewall of the isolation tank is removed by exposure and development, then the first SiO2 layer and HfO2 layer are alternately deposited using electron beam evaporation until a buffer layer is obtained, then the buffer layer located on the photoresist layer is removed using blue film stripping process, and finally the photoresist layer is removed.
[0092] (6) A DBR reflective layer is formed on the first intermediate, and a first via and a second via are formed to expose the P-type metal conductive layer and the N-type metal conductive layer.
[0093] Specifically, a second SiO2 layer and a TiO2 layer are alternately deposited using an electron beam evaporation process until a DBR reflective layer is obtained. Then, a photoresist layer is formed on the DBR reflective layer, and the photoresist layer in a predetermined area is removed by exposure and development. Finally, the exposed DBR reflective layer is removed using an inductively coupled plasma etching process to form a first via exposing a P-type metal conductive layer and a second via exposing an N-type metal conductive layer.
[0094] (7) A P-type pad layer and an N-type pad layer are formed on the DBR reflective layer to obtain the second intermediate;
[0095] Specifically, a photoresist layer is first formed on the DBR reflective layer, inside the first via, and inside the second via. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type pad layer and an N-type pad layer. Then, the metal on the photoresist layer is removed by blue film stripping. Finally, the photoresist layer is removed.
[0096] (8) The substrate is peeled off from the second intermediate and the epitaxial layer is divided along the isolation trench to obtain multiple Micro-LED chips.
[0097] Specifically, a laser lift-off process is used to peel the substrate from the second intermediate, after which it is cut and transferred in large quantities to the substrate.
[0098] Example 2
[0099] This embodiment provides a Micro-LED chip, whose basic structure is the same as that of Embodiment 1. The difference between it and Embodiment 1 is:
[0100] The buffer layer has 3 cycles. In the first cycle, the thickness of the first SiO2 layer is 150 Å and the thickness of the HfO2 layer is 200 Å. In the second cycle, the thickness of the first SiO2 layer is 105 Å and the thickness of the HfO2 layer is 225 Å. In the third cycle, the thickness of the first SiO2 layer is 60 Å and the thickness of the HfO2 layer is 350 Å.
[0101] Example 3
[0102] This embodiment provides a Micro-LED chip, whose basic structure is the same as that of Embodiment 1. The difference between it and Embodiment 1 is:
[0103] The buffer layer has four periods. In the first period, the thickness of the first SiO2 layer is 150 Å and the thickness of the HfO2 layer is 200 Å. In the second period, the thickness of the first SiO2 layer is 125 Å and the thickness of the HfO2 layer is 250 Å. In the third period, the thickness of the first SiO2 layer is 90 Å and the thickness of the HfO2 layer is 300 Å. In the fourth period, the thickness of the first SiO2 layer is 60 Å and the thickness of the HfO2 layer is 350 Å.
[0104] Comparative Example 1
[0105] This comparative example provides a Micro-LED chip with the same basic structure as Example 1. The difference between it and Example 1 is:
[0106] No buffer layer is provided on the sidewall of the isolation trench. In addition, it should be noted that during the fabrication process of the Micro-LED chip in this comparative example, a DBR reflective layer was formed on the top, sidewall, and bottom wall of the isolation trench.
[0107] After substrate removal, cutting, and transfer, the Micro-LED chips from Examples 1-3 and Comparative Example 1 were inspected using AOI equipment to check for cracks in the DBR reflective layer and to perform yield statistics. Specific test data are as follows:
[0108]
[0109] As can be seen from the table above, when a buffer layer is not provided on the sidewall of the isolation tank (Comparative Example 1), the DBR reflective layer has more cracks, and the yield is much lower than that of Example 1, which has a buffer layer on the sidewall of the isolation tank. Furthermore, a comparison of Examples 1 and 2 shows that by controlling the number of cycles in the buffer layer and the thickness of the first SiO2 layer and HfO2 layer in each cycle, the yield can be further improved to 100%. A comparison of Examples 2 and 3 shows that further increasing the number of cycles in the buffer layer does not further improve the yield, and the manufacturing cost is higher. Therefore, the technical solution of Example 2 is better.
[0110] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.
Claims
1. A Micro-LED chip, characterized in that, It includes an epitaxial layer, a current spreading layer, a P-type conductive metal layer, an N-type conductive metal layer, a DBR reflective layer, a P-type pad layer, and an N-type pad layer; The epitaxial layer includes an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked sequentially. A light-emitting structure, an N-type conductive step, and an isolation trench are formed on the epitaxial layer. The N-type conductive step is disposed on one side of the light-emitting structure, and the isolation trench is disposed around the light-emitting structure. The sidewall of the isolation trench exposes the N-type semiconductor layer. A buffer layer and a DBR reflective layer are stacked sequentially on the sidewall of the isolation trench; the buffer layer includes alternating layers of first SiO2 layer and HfO2 layer, and the number of cycles of the buffer layer is 2 to 4; the thickness of a single first SiO2 layer is 50 Å to 150 Å, and the thickness of a single HfO2 layer is 200 Å to 400 Å. The coefficient of thermal expansion of the buffer layer is greater than that of the N-type semiconductor layer and less than that of the DBR reflective layer.
2. The Micro-LED chip as described in claim 1, characterized in that, Along the growth direction of the buffer layer, the thickness of the HfO2 layer in the later cycle is greater than the thickness of the HfO2 layer in the previous cycle, and the thickness of the first SiO2 layer in the later cycle is less than the thickness of the first SiO2 layer in the previous cycle.
3. The Micro-LED chip as described in claim 2, characterized in that, In the buffer layer of the first cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 1:1 to 1:
2. In the buffer layer of the last cycle, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer is 1:5 to 1:6.
5.
4. The Micro-LED chip as described in claim 2, characterized in that, The buffer layer has 3 cycles. Along the growth direction of the buffer layer, the ratio of the thickness of the first SiO2 layer to the thickness of the HfO2 layer in each cycle is 1:1.1~1:1.5, 1:2~1:2.5 and 1:5.5~1:6.5, respectively.
5. The Micro-LED chip according to any one of claims 1 to 4, characterized in that, The DBR reflective layer comprises alternating layers of second SiO2 and TiO2, with a period number of 10 to 25. The thickness of a single second SiO2 layer is 500 Å to 1200 Å, and the thickness of a single TiO2 layer is 400 Å to 1000 Å.
6. The Micro-LED chip as described in claim 1, characterized in that, Both the P-type and N-type metal conductive layers comprise sequentially stacked Cr, Al, Ti, Pt, Ti, Pt, Au, Pt, and Ti layers, with thicknesses of 30 Å to 50 Å, 1200 Å to 2000 Å, 1000 Å to 2000 Å, 500 Å to 1000 Å, 1000 Å to 2000 Å, 500 Å to 1000 Å, 8000 Å to 10000 Å, 2000 Å to 3000 Å, and 30 Å to 50 Å.
7. The Micro-LED chip as described in claim 1, characterized in that, Both the P-type pad layer and the N-type pad layer comprise a second Al layer, a fourth Ti layer, a fourth Pt layer, a fifth Ti layer, a Ni layer, and a second Au layer, stacked sequentially, with thicknesses of 10000Å~15000Å, 1000Å~2000Å, 500Å~1000Å, 1000Å~2000Å, 6000Å~10000Å, and 300Å~500Å, respectively.
8. A method for fabricating a Micro-LED chip, used to fabricate the Micro-LED chip as described in any one of claims 1 to 7, characterized in that, include: (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially stacked on the substrate; (2) A current spreading layer is formed on the epitaxial layer; (3) Etch the epitaxial layer and the current spreading layer to form an N-type conductive step that exposes the N-type semiconductor layer, an isolation trench that exposes the substrate, and a light-emitting structure; (4) A P-type metal conductive layer is formed on the current spreading layer, and an N-type metal conductive layer is formed on the N-type conductive step; (5) A buffer layer is formed on the side wall of the isolation groove to obtain a first intermediate; wherein the buffer layer includes alternating layers of a first SiO2 layer and a HfO2 layer; (6) A DBR reflective layer is formed on the first intermediate, and a first via is formed to expose the P-type metal conductive layer and a second via is formed to expose the N-type metal conductive layer; (7) A P-type pad layer and an N-type pad layer are formed on the DBR reflective layer to obtain a second intermediate; wherein the P-type pad layer is in contact with the P-type metal conductive layer through a first through-hole, and the N-type pad layer is in contact with the N-type metal conductive layer through a second through-hole. (8) The substrate is peeled off from the second intermediate and the epitaxial layer is divided along the isolation trench to obtain multiple Micro-LED chips.
9. The method for fabricating a Micro-LED chip as described in claim 8, characterized in that, In step (5), the first SiO2 layer and the HfO2 layer are alternately formed by electron beam evaporation until a buffer layer is obtained; In step (6), the second SiO2 layer and TiO2 layer are alternately formed by electron beam evaporation until the DBR reflective layer is obtained.
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