Instruction execution method and device, electronic equipment and computer program product

Abstract

The invention provides an instruction execution method and device, electronic equipment and a computer program product, and is applied to a processor core, the processor core maintains a renaming mapping table, table items of the renaming mapping table are configured to store physical register numbers or immediate numerical values, and status bits are set for indicating types of table item storage contents. The method mainly comprises the following steps of: dynamically detecting whether the result of a first instruction is an immediate data conforming to a preset numerical range after execution is completed, and directly writing the immediate data into a renaming mapping table, so that a second instruction with data correlation can obtain the immediate data from the mapping table as a source operand at the earliest renaming stage. The fixed path that in a traditional scheme, a consumer instruction must wait for a producer instruction to write back a physical register file to obtain the operand is broken through, the operand ready time is advanced from execution to renaming, and the performance of a processor can be improved.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and in particular relates to an instruction execution method, apparatus, electronic device and computer program product. Background Technology

[0002] In modern high-performance processors, register renaming is a widely adopted technique used to eliminate data dependencies between instructions, thereby allowing out-of-order instruction execution to improve performance. In this mechanism, the processor typically maintains a renaming mapping table that records the mapping relationship between logical registers and physical registers.

[0003] In related technologies, processors that rely on the aforementioned renaming mapping table require subsequent instructions that need to consume data (consumer instructions) to wait for their producer instructions to complete before they can obtain the required source operands by accessing the physical register file or through the data forwarding network, thus limiting processor performance. Summary of the Invention

[0004] This application provides an instruction execution method, apparatus, electronic device, and computer program product that can improve processor performance.

[0005] A first aspect of this application provides an instruction execution method applied to a processor core. The processor core maintains a renaming mapping table, and the entries in the renaming mapping table are configured to store physical register numbers or immediate values, and are equipped with a status bit (S bit) to indicate the type of content stored in the entries. The method includes: executing a first instruction to obtain the result of the first instruction; when the execution of the first instruction is completed and the result of the first instruction is detected to be an immediate value within a preset value range, writing the immediate value into the entry in the renaming mapping table corresponding to the destination logical register number of the first instruction, and setting the status bit of the entry to indicate that the stored content is an immediate value; for a second instruction related to a read-after-write (RAW) operation of the first instruction, renaming the mapping table according to the source logical register number of the second instruction during the renaming stage to obtain the status bit and entry content corresponding to the second instruction; when it is determined from the status bit that the content stored in the entry corresponding to the source logical register number is an immediate value, fusing the second instruction with the immediate value obtained from the entry to obtain a fused instruction, wherein the fused instruction is configured to directly use the immediate value as the source operand during the execution stage.

[0006] In this application's technical solution, the main approach is to dynamically detect whether the result of the first instruction conforms to a preset numerical range after execution, and directly write it into the rename mapping table. This allows the second instruction with data dependencies to obtain the immediate value from the mapping table as its source operand at the earliest rename stage. This breaks the fixed path in traditional solutions where consumer instructions must wait for producer instructions to write back to the physical register file before obtaining operands, advancing the operand readiness time from after execution to during the rename process, thereby improving processor performance.

[0007] Optionally, in one possible implementation of the first aspect, writing the immediate value into the entry corresponding to the destination logical register number of the first instruction in the rename mapping table and setting the status bit of the entry to indicate that the stored content is an immediate value includes: determining whether the physical register number currently stored in the entry corresponding to the destination logical register number of the first instruction in the rename mapping table is the physical register number allocated by the first instruction; if the physical register number currently stored in the entry is the physical register number allocated by the first instruction, writing the immediate value into the entry, setting the status bit of the entry to indicate that the stored content is an immediate value, and reclaiming the physical register number to a temporary reclamation pool, setting the valid bit of the corresponding entry in the temporary reclamation pool. Thus, by checking whether the physical register number in the entry is allocated by the instruction before updating the rename mapping table after execution, erroneous overwriting of subsequently updated mapping relationships is avoided when Write After Write (WAW) relationships exist, ensuring data correctness; and by placing the confirmed reclaimable physical register numbers into the temporary reclamation pool, early reclamation and safe management of physical register resources are achieved.

[0008] Optionally, in another possible implementation of the first aspect, the method further includes: upon completion of the second instruction execution, determining whether the source operand of the second instruction was obtained from the general-purpose register file via the physical register number; and if the source operand of the second instruction was obtained from the general-purpose register file via the physical register number, clearing the valid bit of the entry corresponding to the physical register number in the temporary recycling pool. Thus, by determining whether the physical register in the temporary recycling pool was actually used upon completion of the second instruction execution, and only clearing its valid bit to complete the final release when it is confirmed that the physical register has no further dependencies, accurate and safe reclamation of physical register resources is achieved, avoiding the risk of premature release or long-term occupation of resources.

[0009] Optionally, in another possible implementation of the first aspect, the method further includes: writing the immediate value and the destination logical register number of the first instruction into the corresponding entry of the re-order buffer (ROB); in the event of an exception or interruption and it is determined that recovery to a checkpoint is required, reading the destination logical register number and the immediate value of the first instruction from the ROB; based on the read destination logical register number and immediate value, restoring the content and status bits of the corresponding entry in the rename mapping table, and restoring the information related to the physical register number reclamation status. Thus, by recording the immediate value and the corresponding logical register number information in the ROB, when an exception or interruption occurs and recovery to a checkpoint is required, the rename mapping table and related resource reclamation status can be accurately restored based on the information stored in the ROB, ensuring the correctness and recoverability of the scheme under speculative execution state.

[0010] Optionally, in another possible implementation of the first aspect, before executing the first instruction and obtaining its result, the method further includes: if the first instruction enters the renaming stage, determining whether all source operand values ​​have been obtained for the first instruction; if it is determined that all source operand values ​​have been obtained for the first instruction, calculating the result of the first instruction in the renaming stage; if the calculated result of the first instruction is an immediate value within a preset range, writing the immediate value into the renaming mapping table corresponding to the destination logic register number of the first instruction, setting the status bit of the entry to indicate that the stored content is an immediate value, and suppressing the execution of the first instruction. Thus, by obtaining all source operands and calculating the result in advance during the renaming stage, the renaming mapping table can be updated directly during the renaming stage when the result meets the conditions, and subsequent issuance and execution operations of the instruction can be suppressed, saving backend resources such as the issue queue, execution unit, and register ports.

[0011] Optionally, in another possible implementation of the first aspect, the above-described fusion of the second instruction with the immediate value obtained from the table entry to obtain a fused instruction includes: extending the source operand field of the second instruction to include an operand type identifier and an operand value field; writing the immediate value obtained from the table entry into the operand value field; and setting the operand type identifier to indicate that the source operand is an immediate value. Thus, by extending the source operand field of the second instruction to include a type identifier and an operand value field, hardware support is provided for directly embedding the immediate value obtained from the rename mapping table into the instruction, enabling the fused instruction to be directly recognized and used by the immediate value in the execution unit, eliminating the need to read the register file.

[0012] Optionally, in another possible implementation of the first aspect, the aforementioned preset numerical range is 0 to... ,or- arrive ,in The bit width for the physical register number.

[0013] A second aspect of this application provides an instruction execution apparatus applied to a processor core. The processor core maintains a rename mapping table, and entries in the rename mapping table are configured to store physical register numbers or immediate values, and are provided with status bits to indicate the type of content stored in the entries. The apparatus includes:

[0014] The instruction execution module is used to execute the first instruction and obtain the result of the first instruction.

[0015] The instruction processing module is used to write the immediate value into the rename mapping table corresponding to the destination logic register number of the first instruction when the first instruction is executed and the result of the first instruction is detected to be an immediate value that meets the preset value range, and to set the status bit of the table entry to indicate that the stored content is an immediate value.

[0016] The instruction index module is used to rename the mapping table based on the source logic register number of the second instruction during the renaming stage for second instructions that have data write-after-read relationships with the first instruction, so as to obtain the status bits and table entries corresponding to the second instruction.

[0017] The instruction fusion module is used to fuse the second instruction with the immediate value obtained from the table entry when the table entry corresponding to the source logic register number is determined to be an immediate value based on the status bit, so as to obtain a fused instruction. The fused instruction is configured to directly use the immediate value as the source operand during the execution phase.

[0018] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the instruction execution method of the first aspect described above.

[0019] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the instruction execution method of the first aspect described above.

[0020] The fifth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the instruction execution method of the first aspect described above.

[0021] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a register mapping table modification provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a temporary recycling pool provided in an embodiment of this application; Figure 3 This is a flowchart illustrating an instruction execution method provided in an embodiment of this application; Figure 4 This is a flowchart comparing two instruction execution methods provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0025] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0026] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0027] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0028] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0030] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0031] In related technologies, processors that rely on the aforementioned renaming mapping table require subsequent instructions that need to consume data (consumer instructions) to wait for their producer instructions to complete before they can obtain the required source operands by accessing the physical register file or through the data forwarding network, thus limiting processor performance.

[0032] In view of this, embodiments of this application provide an instruction execution method, apparatus, electronic device, and computer program product, applied to a processor core. The processor core maintains a renaming mapping table, and the entries in the renaming mapping table are configured to store physical register numbers or immediate values, and are equipped with status bits to indicate the type of content stored in the entries. The method includes: firstly, executing a first instruction to obtain the result of the first instruction; then, when the execution of the first instruction is completed and the result of the first instruction is detected to be an immediate value within a preset value range, writing the immediate value into the entry in the renaming mapping table corresponding to the destination logical register number of the first instruction, and setting the status bit of the entry to indicate that the stored content is an immediate value; next, for a second instruction related to a data write-after-read operation with the first instruction, renaming the mapping table according to the source logical register number of the second instruction during the renaming stage to obtain the status bit and entry content corresponding to the second instruction; finally, when it is determined from the status bit that the entry content corresponding to the source logical register number is an immediate value, fusing the second instruction with the immediate value obtained from the entry to obtain a fused instruction, wherein the fused instruction is configured to directly use the immediate value as the source operand during the execution stage. Therefore, by dynamically detecting whether the result of the first instruction is an immediate value within a preset range after execution and directly writing it into the rename mapping table, the second instruction with data dependencies can obtain the immediate value from the mapping table as its source operand at the earliest rename stage. This breaks the fixed path in traditional schemes where consumer instructions must wait for producer instructions to write back to the physical register file before obtaining operands, advancing the operand readiness time from after execution to during renaming, thus improving processor performance.

[0033] To illustrate the technical solution of this application, specific embodiments are described below.

[0034] The embodiments of this application aim to improve the performance and energy efficiency of processor cores (such as out-of-order superscalar processor cores). The core of this approach lies in structurally enhancing the renaming mapping table upon which the critical register renaming mechanism within the processor core relies, and designing corresponding dynamic management logic. This allows specific immediate values ​​generated by arithmetic instructions to be efficiently and directly passed to subsequent instructions that depend on those results, thereby reducing the need for access to the General-purpose Register File (GRF) and optimizing the use of physical register resources.

[0035] Figure 1 A schematic diagram illustrating a register mapping table modification provided in an embodiment of this application is shown. For example... Figure 1As shown, each entry in a traditional rename mapping table stores only one Physical Register Number (PRN), and its function is to dynamically map the Logical Register Number (LRN) in the instruction to the physical register space. To support specific embodiments of the instruction execution method described below, a key extension has been made to this register mapping table structure.

[0036] Specifically, a dedicated status bit has been added to each entry in the modified rename mapping table. This status bit, S, indicates the type of content stored in the current entry: when the status bit is a first predetermined value (e.g., logic '0'), it indicates that the entry stores a physical register number; when the status bit is a second predetermined value (e.g., logic '1'), it indicates that the entry stores an immediate value. Simultaneously, the data field, which was originally used only to store physical register numbers, has been expanded to a data carrier field that multiplexes both physical register numbers and immediate values. The actual bit width of this data carrier field can be designed according to the target instruction set architecture and microarchitecture implementation requirements. For example, for the RISC-V instruction set architecture, to accommodate the 12-bit immediate values ​​in its Type I instructions (such as ADDI rd, rs1, imm12), the mapping table data carrier field for integer registers can be designed to be no less than 12 bits. Through this modification, the rename mapping table has evolved from a simple "logic-physical" register mapping tool into a hybrid mapping structure capable of dynamically binding logical registers with specific immediate values, which is the hardware foundation for implementing subsequent instruction execution methods.

[0037] The processor core execution unit may be equipped with a value detection module. This module is used to determine, after instruction execution, whether the result of its operation is an immediate value that can be stored in the data carrying field of the aforementioned rename mapping table. This determination is based on a preset value range, which is related to the bit width of the physical register number. Closely related. For example, in a 64-bit processor, if configured to detect "unsigned smaller immediate values", the decision condition is: 0 ≤ result ≤ If configured to detect "signed smaller immediate values", the determination condition is: - ≤Result≤ The existence of the numerical detection module enables the embodiments of this application to dynamically capture those situations that produce small immediate value results from various integer arithmetic instructions (such as addition, subtraction, multiplication, logical operations, etc.), rather than being limited to identifying specific immediate value loading instructions, which greatly expands the optimized application scenarios.

[0038] To enable early reclamation and secure management of physical register resources, this application introduces a logical structure called a Temporary Recycle Pool. Figure 2 A schematic diagram of a temporary recycling pool provided in an embodiment of this application is shown. Figure 2 As shown, the temporary reclamation pool is used to temporarily store physical register numbers that have been reclaimed from the active physical register set because their corresponding logical register mapping entries have been updated to immediate values. Each entry in the pool contains a physical register number and a valid bit (V bit). When a physical register number is reclaimed into the pool, its corresponding valid bit is set (e.g., set to '1'), indicating that the physical register resource is in a "reclaimed but final release postponed" state, ensuring that any instruction that may still need to read the physical register data from the general register file can safely obtain operands. The temporary reclamation pool is the core management component for implementing dynamic resource optimization and avoiding resource conflicts in this embodiment of the application. It connects the updating of the rename mapping table with the lifecycle management of physical register resources.

[0039] Furthermore, to ensure proper recovery of the speculative execution state in the event of a processor core exception or interruption, this embodiment requires that relevant update information be recorded in the reordering buffer (ROB). The ROB entries need to record the destination logical register number of the instruction and, if applicable, the immediate value determined by the value detection module. This information, combined with a checkpoint mechanism, ensures that even if the speculative execution path is revoked, modifications made to the rename mapping table and temporary garbage collection pool by this embodiment can be correctly rolled back or rebuilt, thereby maintaining the consistency of the processor state.

[0040] To facilitate understanding, a simplified instruction sequence example is used to illustrate the basic working principle of the above structure. Assume the processor core recognizes an instruction `ADD x3, x1, x2` (this instruction acts as a producer instruction), whose function is to add the values ​​of registers x1 and x2, and write the result to register x3. In a conventional process, this instruction would allocate a free physical register (e.g., P10) for logical register x3 during the renaming phase, and write the result to the general-purpose register file location corresponding to P10 after execution. In the microarchitecture supported by this application embodiment, after the `ADD` instruction completes its calculation in the execution unit, the value detection module will judge its result. Assume the result is a small constant (i.e., a small immediate value), such as the value "5", and this value falls within a preset value range. At this point, the processor core does not simply write the result to physical register P10, but performs a series of additional operations: First, it checks the entry for logical register x3 in the current rename mapping table to confirm that the physical register number stored therein is indeed P10 allocated for this instruction (this step is used to avoid erroneous overwriting when processing subsequent write-after-write (WAW) related instructions). After confirmation, the processor core writes the immediate value "5" to the data field of the entry and sets the status bit of the entry to '1', indicating that logical register x3 is currently mapped to an immediate value. Simultaneously, physical register number P10 is reclaimed to the temporary reclamation pool, and the valid bit V of its corresponding entry is set to '1'. The effect of this series of operations is that the mapping target of logical register x3 is "switched" from physical register P10 to the immediate value "5", and P10 is safely marked for reclamation. For any subsequent instruction (consumer instruction) with x3 as its source operand, when querying the mapping table during the rename phase, the status S=1 and the immediate value "5" will be obtained directly, thus bypassing access to the general-purpose register file. If a consumer instruction enters the renaming phase before the producer instruction ADD completes, it will still obtain physical register number P10 and read data from the general-purpose register file normally, ensuring the correctness of program execution. The valid bits of P10 in the temporary reclamation pool will be cleared to zero after all consumer instructions that depend on it have finished executing, thus achieving the final release of this physical register resource.

[0041] Through the above introduction of basic structure and working principle, the embodiments of this application provide the necessary hardware and logic foundation for the complete instruction execution flow that will be described in detail later. The instruction execution method flow covering various scenarios will be explained step by step below with reference to the accompanying drawings.

[0042] In the above Figure 1 Based on the modified register mapping table shown, Figure 3The diagram illustrates a flowchart of an instruction execution method provided in an embodiment of this application. This method is applied to a processor core, which maintains a renaming mapping table. Entries in the renaming mapping table are configured to store physical register numbers or immediate values, and status bits are set to indicate the type of content stored in the entries.

[0043] The following is about Figure 3 The steps shown will be explained.

[0044] Step 301: Execute the first instruction and obtain the result of the first instruction.

[0045] In this embodiment, step 301 describes the complete front-end processing flow for the producer instruction (i.e., the first instruction). This flow begins at the decoding stage of the processor core, with the goal of preparing the instruction result for subsequent optimization decisions and operand passing.

[0046] During the decoding stage, the processor core parses the instructions, identifying their opcodes and operands. These instructions can be integer arithmetic instructions, such as addition (ADD), subtraction (SUB), multiplication (MUL), and logical AND, and are selected as potential first-order instructions (producer instructions). A common characteristic of these instructions is that their execution result is written to a destination logic register and may be consumed as a source operand by subsequent instructions.

[0047] After decoding, integer arithmetic instructions identified as the first instruction enter the renaming stage. The core of this stage is accessing the renaming map to resolve and allocate register resources, and in the process, determining the subsequent execution path of the instruction. The renaming logic first attempts to query the renaming map based on the source logical register number of the first instruction to obtain information about all its source operands. The goal here is to obtain the specific values ​​of the source operands, not just the numbers pointing to the physical register files. Whether this goal can be achieved directly determines which optimized path the first instruction will follow.

[0048] In one embodiment, when the first instruction enters the renaming stage, it is determined whether all source operand values ​​have been obtained for the first instruction. If it is determined that all source operand values ​​have been obtained for the first instruction, the result of the first instruction is calculated during the renaming stage. If the calculated result of the first instruction is an immediate value that meets the preset value range, the immediate value is written into the renaming mapping table corresponding to the destination logic register number of the first instruction, and the status bit of the table entry is set to indicate that the stored content is an immediate value, and the step of executing the first instruction is suppressed. Thus, by obtaining all source operands and calculating the result in advance during the renaming stage, the renaming mapping table can be updated directly during the renaming stage when the result meets the conditions, and the subsequent issuance and execution operations of the instruction are suppressed, saving backend resources such as the issue queue, execution unit, and register port.

[0049] It should be noted that if the specific values ​​of all source operands of the first instruction can be successfully obtained, the processor core will activate the first path, that is, complete the calculation during the renaming phase. This situation usually occurs when all source operands come from pre-prepared immediate values. For example, in the renaming map entries corresponding to the two source operands of an instruction, the status bits both indicate that the stored content is an immediate value. In this case, the fast calculation circuit inside the renaming station or adjacent to it will directly perform calculations based on the opcode of the first instruction and the obtained source operand values, thereby obtaining the calculation result of the first instruction during the renaming phase. Under this path, the functional execution of the first instruction is significantly advanced and completed at the front end of the pipeline, and the process of obtaining the calculation result of the first instruction does not require the use of back-end resources such as the issue queue, scheduler, and execution unit.

[0050] In another embodiment, if the specific values ​​of all source operands of the first instruction cannot be obtained during the renaming phase (this is a more common scenario, for example, when the source operands depend on an incomplete preceding instruction), the processor core will activate another path, namely the traditional back-end execution path. Under this path, the renaming logic will perform a standard register renaming operation: First, a free target physical register number is allocated to the destination logical register of the first instruction, and the new mapping from this logical register number to the physical register number is updated to the corresponding entry in the renaming mapping table (at this time, the status bit of the entry is set to indicate that the stored content is a physical register number). Subsequently, the first instruction, carrying its operation information (including the physical register number corresponding to the source operands, the target physical register number, the opcode, etc.), is sent to the issue queue. When all its source operands are ready in the general-purpose register file and execution resources are available, the instruction is issued to the corresponding execution unit. The execution unit performs the arithmetic or logical operation defined by the instruction and writes the result to the general-purpose register file storage location corresponding to its target physical register number. Under this path, the process of obtaining the calculation result of the first instruction is the classic process of the instruction being calculated by a complete functional unit in the processor back-end and written back to the register file.

[0051] It should be noted that regardless of which path the first instruction is executed through, its result (a specific integer value) will be generated and used as the core input for the subsequent process (step 302). This design ensures that the embodiments of this application can intelligently adapt to the dynamic context of instruction execution, achieving maximum front-end optimization when conditions permit, and seamlessly reverting to the efficient and reliable traditional execution mode when conditions are not met, thereby capturing a wide range of optimization opportunities without sacrificing versatility.

[0052] Step 302: After the first instruction is executed and the result of the first instruction is detected to be an immediate value that meets the preset value range, the immediate value is written into the table entry corresponding to the destination logic register number of the first instruction in the renaming mapping table, and the status bit of the table entry is set to indicate that the stored content is an immediate value.

[0053] In this embodiment, step 302 is the core operation for performance optimization and resource reclamation. The goal is to directly convert the qualified calculation results into source operands usable by subsequent instructions and trigger corresponding microarchitecture state changes.

[0054] Once the first instruction is executed and a result is generated, regardless of whether the result comes from pre-calculation during the renaming phase or traditional calculation by the execution unit, a crucial judgment process is required. This judgment can be performed by the numerical detection module. The function of the numerical detection module is to determine whether the integer operation result of the first instruction is a small immediate value, that is, whether the result falls within a preset numerical range.

[0055] In one embodiment, the preset numerical range is 0 to ,or- arrive ,in This refers to the bit width of the physical register number (PRN). Specifically, the defined preset value range is closely related to the specific implementation of the processor microarchitecture and primarily depends on the bit width of the PRN. The specific rules are configurable in the hardware: if configured to detect unsigned small immediate values, the decision condition is that the result N satisfies 0 ≤ N ≤ 0. If configured to detect small signed immediate values ​​(represented in two's complement form), the determination condition is - ≤N≤ The introduction of the numerical detection module allows optimization to move beyond specific instruction types and dynamically capture events where any integer arithmetic instruction produces a small immediate value, greatly expanding the scenarios in which optimization can be triggered.

[0056] In this embodiment, once the numerical detection module determines that the result of the first instruction is an immediate value within a preset numerical range, the processor core initiates a speculative update process for the rename mapping table. However, in an out-of-order execution environment, multiple write operations (WAW pseudo-related) to the same logical register may occur simultaneously. To ensure the correctness of the update, a check can be performed as follows: the processor core reads the entry in the rename mapping table corresponding to the target logical register number of the first instruction and checks whether the currently stored physical register number is exactly the target physical register number allocated by this first instruction during the renaming phase. The purpose of the above check is to confirm that since the current first instruction was renamed, no instruction later in the program sequence has renamed the same logical register. Only if the check matches is it safe to update the mapping entry and will not overwrite the new mapping relationship established by subsequent instructions. If the check does not match, the update is abandoned, and the original mapping relationship is maintained.

[0057] After the above verification, the processor core performs a substantive update operation. The processor core writes the immediate value calculated by the first instruction into the data field of the corresponding entry in the rename mapping table, and simultaneously changes the status bit of that entry from a state indicating "physical register number" (e.g., 0) to a state indicating "immediate value" (e.g., 1). This operation is microarchitecturally equivalent to dynamically and speculatively changing the mapping target of the corresponding logical register from an initially allocated physical storage location (physical register) to a specific constant (immediate value).

[0058] In one embodiment, the management of physical register resource reclamation is closely coupled with the update of the rename mapping table. First, it can be determined whether the physical register number currently stored in the entry of the rename mapping table corresponding to the destination logical register number of the first instruction is the same physical register number allocated by the first instruction. Then, if the currently stored physical register number is the same as the one allocated by the first instruction, an immediate value is written to the entry, the status bit of the entry is set to indicate that the stored content is an immediate value, and the physical register number is reclaimed to a temporary reclamation pool. The valid bit of the corresponding entry in the temporary reclamation pool is then set. Thus, by checking whether the physical register number in the entry is allocated by the instruction before updating the rename mapping table after execution, erroneous overwriting of subsequently updated mapping relationships is avoided when WAW-related issues exist, ensuring data correctness. Furthermore, by placing confirmed reclaimable physical register numbers into the temporary reclamation pool, early reclamation and safe management of physical register resources are achieved.

[0059] It should be noted that when an entry is updated to an immediate value, the old data (if any) or newly written data (in the traditional execution path) stored in the physical register number originally allocated to the logical register of the first instruction destination are theoretically no longer needed. To ensure resource reuse while absolutely avoiding data conflicts, this application introduces a temporary recycling pool management mechanism. Specifically, while updating the mapping table, the physical register number is recycled to the temporary recycling pool. During recycling, the processor core finds the corresponding entry in the temporary recycling pool, stores the physical register number there, and sets its valid bit to '1'. Setting the valid bit is a critical operation, marking that the physical register resource enters a "protected recycling" state. That is, although the physical register resource has been removed from the active register set, allowing the microarchitectural logic to reallocate it in the future, the contents of the corresponding physical register storage unit must be retained while the valid bit is '1', and cannot be overwritten by other instructions subsequently allocated to use that number. This is to ensure that second instructions (i.e., consumer instructions) that have passed the renaming phase before the first instruction has finished executing and whose source operands are still recorded as the physical register number can still safely read the correct operands from the general-purpose register file GRF during subsequent execution.

[0060] In one embodiment, to maintain the consistency of the processor's speculative execution state, the update operation in step 302 can include an exception and interrupt recovery mechanism. Specifically, firstly, the immediate value and the destination logical register number of the first instruction are written into the corresponding entries in the reorder buffer (ROB); then, if an exception or interrupt occurs and it is determined that recovery to a checkpoint is required, the destination logical register number and immediate value of the first instruction are read from the ROB; finally, based on the read destination logical register number and immediate value, the contents and status bits of the corresponding entries in the rename mapping table are restored, and information related to the physical register number reclamation status is restored. Thus, by recording the immediate value and the corresponding logical register number information in the ROB, when an exception or interrupt occurs and recovery to a checkpoint is required, the rename mapping table and related resource reclamation status can be accurately restored based on the information stored in the ROB, ensuring the correctness and recoverability of the scheme under speculative execution state.

[0061] It's important to note that after the processor core writes the immediate value to the rename mapping table, regardless of whether it's currently in an exception or interrupt handling process, it can write that immediate value, along with the destination logical register number of the first instruction, as a record in the corresponding entry for the first instruction in the ROB. The ROB is the core hardware structure that maintains in-order instruction submission and precise exception handling; storing this information is to support state rollback. Furthermore, the processor core will only actually apply the modifications to the rename mapping table and temporary garbage collection pool to the current speculative execution hardware state if it's confirmed that it's not currently in an exception or interrupt handling process, or if the current first instruction is earlier than any checkpoint to be recovered. Otherwise, these modifications are only recorded in the ROB and only take effect when it's determined that no rollback is needed. This design ensures that optimization operations are fully compatible with the processor's speculative execution and precise exception model.

[0062] In the above embodiments, the smaller immediate value generated by the first instruction is forwarded and fixed in the rename mapping table, the corresponding physical register resources are safely reclaimed, and all state changes are properly recorded to support possible recovery.

[0063] Step 303: For the second instruction that is related to the first instruction in terms of data write-after-read, in the renaming stage, the mapping table is renamed according to the source logic register number index of the second instruction to obtain the status bit and table entry content corresponding to the second instruction.

[0064] In this embodiment, step 303 describes the core step of how the second instruction resolves its source operand to prepare for execution. The second instruction is any instruction in the instruction sequence that uses the destination logic register of the first instruction as its source operand, and there is a data write-after-read dependency between the two. This dependency is identified and tracked by the processor's dependency detection logic during instruction scheduling.

[0065] It should be noted that the first instruction and the second instruction are not required to be adjacent in the program's address space, which means that a series of unrelated instructions may be located between them. The optimization mechanism of this application embodiment can transcend these instructions and capture data dependencies between non-adjacent instructions, thereby expanding the scope of optimization.

[0066] When the second instruction enters the renaming phase, its primary task is to parse its source operands. For each source operand, the renaming logic uses its corresponding source logic register number as an index to access the renaming mapping table. The purpose of this access is to obtain all information about the current mapping state of the logic register, specifically including two key pieces of information: first, the status bit of the mapping table entry, and second, the specific content stored in its data carrying field (i.e., the table entry content). This query operation is a standard step in the processor renaming mechanism, but under the novel renaming mapping table structure extended in this application embodiment, the meaning of its query result becomes richer.

[0067] In this embodiment of the application, the query result for the second instruction depends on the execution status of the first instruction and whether the update operation in step 302 has occurred. This results in the second instruction potentially facing two completely different scenarios, which will be described below.

[0068] In one embodiment, the first scenario is that the second instruction enters the renaming stage only after the first instruction has completed execution (and the update operation in step 302 has taken effect). This is the scenario where processor performance optimization is most significant. In this scenario, since the result of the first instruction (a small immediate value) has already been updated in the renaming map table, and the status bit of the corresponding entry has been set to indicate "immediate value," when the second instruction queries the entry, the read status bit will clearly indicate that the current stored content is an immediate value, and the specific value of the immediate value can be directly obtained from the data carrying field. This is equivalent to the second instruction obtaining the final value of its required operand at the very beginning of the pipeline (the renaming stage), creating conditions for completely eliminating subsequent register access operations.

[0069] In another embodiment, the second scenario is that the second instruction has already passed the renaming phase before the first instruction has completed execution. This is a common scenario in out-of-order execution processors, caused by inter-instruction latency and the processor's wide issue capability. In this scenario, when the second instruction performs a renaming query, the first instruction may not have been executed yet, or it may have been executed but the update in step 302 has not yet taken effect (e.g., the update logic has pipeline delays, or is subject to other microarchitectural conditions). At this time, the entry for the corresponding logical register in the renaming map table still indicates "physical register number" in its status bit, and the data carrying field still stores the target physical register number allocated by the first instruction during the renaming phase. Therefore, the query result of the second instruction will obtain a status bit indicating the physical register and a physical register number. This means that the second instruction still needs to read the operand from the general-purpose register file GRF using this physical register number in subsequent stages, as in the traditional process, or wait for the result to bypass the network's data forwarding.

[0070] In this embodiment, the application is applicable to efficiently handling multi-consumer dependency scenarios. Specifically, the processor core can execute the rename query operation in parallel on multiple second instructions within one cycle. This means that if multiple instructions simultaneously depend on the result of the first instruction, they can concurrently access the rename mapping table and independently obtain the status information of their source operands.

[0071] Step 304: If the table entry corresponding to the source logic register number is determined to be an immediate value based on the status bit, the second instruction is fused with the immediate value obtained from the table entry to obtain a fused instruction. The fused instruction is configured to directly use the immediate value as the source operand during the execution phase.

[0072] In this embodiment, step 304 is the final step in realizing the performance gain. Based mainly on the query result of step 303, the internal representation of the second instruction is modified in a key way, so that it can completely avoid access to the general-purpose register file GRF during the execution phase and directly use the obtained immediate value.

[0073] It should be noted that the triggering condition of step 304 depends on the status bit obtained in step 303. The renaming logic will only initiate the fusion operation for the second instruction when the status bit indicates that the content stored in the corresponding rename mapping table entry is an immediate value. Otherwise, if the status bit indicates a physical register number, the second instruction will follow the traditional processing flow, and its internal representation will not be changed. The source operand will need to be obtained by accessing the general-purpose register file or waiting for the bypass network.

[0074] In one embodiment, the core of the fusion operation lies in format expansion and content padding of the microarchitectural representation of the second instruction. To enable the immediate value to be directly carried within the instruction, the format of its source operand field can be uniformly modified. Specifically, the source operand field of the second instruction can be expanded to include an operand type identifier and an operand value field; the immediate value obtained from the table entry is written into the operand value field; and the operand type identifier is set to indicate that the source operand is an immediate value. Thus, by expanding the source operand field of the second instruction to include a type identifier and an operand value field, hardware support is provided for directly embedding the immediate value obtained from the rename mapping table into the instruction, enabling the fusion instruction to be directly recognized and used by the execution unit, eliminating the need to read the register file.

[0075] The modified source operand field contains at least two components: an operand type identifier, indicating whether the field currently carries a physical register number or an immediate value; and an operand value field, whose bit width is sufficient to accommodate the largest immediate value that may be obtained from the rename mapping table data carrying field. This format extension provides fused instructions with a physical container for carrying and identifying immediate operands.

[0076] In this embodiment, after determining to perform fusion, the renaming logic executes specific fusion actions: First, the immediate value obtained from the data-carrying field of the corresponding entry in the renaming mapping table is written into the operand value field of the corresponding source operand field of the second instruction. Next, the operand type identifier of the source operand field is set to a predefined value to explicitly indicate that this operand is an immediate value. For example, it can be agreed that an identifier of '1' represents an immediate value, and '0' represents a physical register number. After this operation, the second instruction is transformed into a fusion instruction. The essence of this fusion instruction is a special micro-operation that already contains one or more determined source operand values. Its significant characteristic is that these operands are already ready within the instruction itself, rather than pointing to an external register location to be read.

[0077] Furthermore, after generating the fused instruction, its behavior in the subsequent pipeline changes fundamentally. When the instruction passes through the register read station, its source operand carrying the immediate value will completely skip access to the read port of the general-purpose register file. The source operand of the fused instruction comes directly from its own internal operand value field. This directly eliminates the risk of pipeline stalls caused by structural conflicts that may be caused by accessing the register file (such as multiple instructions competing for limited read ports), and saves corresponding dynamic power consumption. Finally, during the execution phase, the execution unit directly extracts the immediate value from the fused instruction as the source operand for computation. For the second scenario described in step 303 (status bit indicating physical register) where the second instruction has not undergone fusion, its execution flow is no different from the traditional one, still requiring data to be read from the general-purpose register file or bypass data to be received at appropriate times.

[0078] It should be noted that the fusion mechanism in this application embodiment is not limited to a single consumer. If, after the first instruction, multiple instructions all use their results as source operands, and their status bits all indicate immediate values ​​when querying the mapping table during the renaming phase, then the renaming logic can execute the aforementioned fusion operation in parallel for all these instructions, generating multiple fused instructions. This achieves efficient and parallel forwarding of the result of a single producer instruction to multiple consumer instructions.

[0079] In one embodiment, the completion of the fusion operation is also associated with the final release of physical register resources. Specifically, upon completion of the second instruction execution, it is determined whether the source operand of the second instruction was obtained from the general-purpose register file via the physical register number; if the source operand of the second instruction was obtained from the general-purpose register file via the physical register number, the valid bit of the entry corresponding to the physical register number in the temporary recycling pool is cleared to zero. Thus, by determining whether the physical register in the temporary recycling pool was actually used upon completion of the second instruction execution, the valid bit is cleared to complete the final release only when it is confirmed that the physical register has no further dependencies, achieving precise and safe reclamation of physical register resources and avoiding the risk of premature release or long-term occupation of resources.

[0080] It should be noted that when the result of the first instruction is updated to an immediate value, its physical register is reclaimed to the temporary reclaim pool and its valid bit (V bit) is set to '1'. For any second instruction that needs to actually access the general-purpose register file because its source operand status bit indicates a physical register (i.e., unfused), the processor core recognizes that the last read dependency of that physical register has been satisfied after its execution. At this time, the processor core clears the valid bit of the entry corresponding to that physical register number in the temporary reclaim pool. Clearing the valid bit signifies that all protective dependencies of that physical register resource have been released, and its number can be safely placed back into the list of free physical registers for allocation by subsequent instructions, thus completing the full lifecycle management of that physical register resource. For fused second instructions, since they do not actually use the physical register, they do not directly trigger the clearing of the valid bit.

[0081] For example, consider the instruction sequence ADD x3, x1, x2 (first instruction) followed by MUL x5, x3, x4 (second instruction). Assume the ADD instruction executes to the value 5, and after step 302, the status bit of the entry corresponding to x3 in the renaming mapping table is '1', and the data field stores the immediate value 5. When the MUL instruction enters the renaming phase (step 303), it queries x3 to obtain the status bit '1' and the immediate value 5. Subsequently, in step 304, the corresponding source operand field of the MUL instruction is expanded and filled: its operand value field is written with 5, and the operand type identifier is set to '1'. During the execution phase of this merged MUL instruction, one of its source operands will directly use 5, while the other source operand x4 will be read from the register file according to the normal mapping.

[0082] The instruction execution method disclosed in the above embodiments of this application first executes a first instruction to obtain the result of the first instruction; then, when the execution of the first instruction is completed and the result of the first instruction is detected to be an immediate value within a preset numerical range, the immediate value is written into the renaming mapping table to the entry corresponding to the destination logical register number of the first instruction, and the status bit of the entry is set to indicate that the stored content is an immediate value; next, for a second instruction that is related to a data write-after-read instruction, the renaming mapping table is renamed according to the source logical register number index of the second instruction during the renaming stage to obtain the status bit and entry content corresponding to the second instruction; finally, when it is determined from the status bit that the entry content corresponding to the source logical register number is an immediate value, the second instruction is merged with the immediate value obtained from the entry to obtain a merged instruction, wherein the merged instruction is configured to directly use the immediate value as the source operand during the execution stage. Therefore, by dynamically detecting whether the result of the first instruction is an immediate value within a preset numerical range after execution and directly writing it into the renaming mapping table, the second instruction that is related to data can obtain the immediate value as the source operand from the mapping table in the earliest renaming stage. This breaks the fixed path in the traditional scheme where consumer instructions must wait for producer instructions to write back to the physical register file before they can obtain operands. By advancing the operand readiness time from after execution to during renaming, processor performance can be improved.

[0083] In this embodiment, through the complete execution of steps 301 to 304, this embodiment achieves the dynamic conversion of smaller immediate values ​​generated by general-purpose arithmetic instructions into immediate source operands for subsequent dependent instructions within an out-of-order superscalar processor core. This not only advances operand readiness time from after execution to during renaming, significantly compressing the latency of data dependency chains, but also improves resource utilization by implementing a corresponding temporary reclamation pool mechanism for the early and safe reclamation of physical register resources. Furthermore, all operations are designed to be fully compatible with the processor's speculative execution and exception recovery mechanisms, ensuring that optimization pursues high performance without sacrificing correctness.

[0084] In one possible implementation, after completing the speculative execution process in the above instruction execution method, when the first instruction, acting as the producer instruction, reaches its retirement point (i.e., the moment the instruction is committed and its operation result becomes finally visible to the processor architecture state), and no exceptions or interrupts requiring rollback are triggered during its execution, the Reorder Buffer (ROB) is responsible for the final architecture state synchronization. Specifically, the ROB can set the status bit of the entry to indicate that the stored content is an immediate value, based on the destination logical register number and corresponding immediate value recorded for the first instruction in its entry. Through the above operations, the optimization update of the rename mapping table previously completed during speculative execution is finally transformed into a stable and permanent architecture state for the processor.

[0085] In one possible implementation, to ensure that the processor can correctly roll back to a consistent speculative state in the event of an exception or interrupt (hereinafter collectively referred to as a Trap), recovery can be performed through the following steps. First, when the processor core performs a save checkpoint for speculative execution, it needs to save not only the speculative rename mapping table but also the temporary garbage collection pool in the speculative state. When a Trap occurs and it is determined that recovery to a certain checkpoint is required, the processor core will periodically read instruction information (e.g., whether the instruction produces a smaller immediate value and its value) sequentially from the reorder buffer (ROB) according to the program order, starting from that checkpoint. For these instructions, the processor core will re-execute update logic similar to step 302: if the instruction information indicates that it is a producer instruction and the result is a smaller immediate value, then the immediate value is used to update the recovered speculative rename mapping table, and the corresponding physical register number is synchronously garbage collected to the temporary garbage collection pool and the valid bit is set. This process continues until the instruction information recorded in the ROB has been processed, thereby accurately reconstructing all speculative states (including the rename mapping table and the temporary garbage collection pool) modified by the embodiments of this application before the Trap occurred, ensuring the correctness and recoverability of the optimization operation.

[0086] In one possible implementation, consider a typical loop sequence as an example: 1) Op0: mul x3, x2, x1; 2) Op1: add x6, x4, x3; 3) Op2: load x7, x6(imm); 4) Op3: addi x1, x1, 0x1; 5) Op4: blt x1, x8, Op0. This loop loads data from a base address offset by the loop variable x1. Assuming a dispatch width of 6, each loop iteration can dispatch the above 5 instructions. In a conventional scheme, assuming no other microarchitectural strategies are considered, this sequence requires reading the general-purpose register file GRF 8 times and writing 4 times per loop iteration. If the value of the loop variable x1 is a "small immediate value", then through the instruction execution method in the aforementioned embodiments of this application, the source operand x1 of Op0 (and the x1 updated by the subsequent Op3 result) can be directly written to the rename mapping table as an immediate value. This allows subsequent instructions that depend on x1 (such as Op0 and related instructions in subsequent iterations) to obtain the value directly from the mapping table during the renaming phase, thereby reducing the access requirements to the GRF per loop to 6 reads and 3 writes. This example specifically demonstrates how embodiments of this application reduce the risk of port conflicts by decreasing the number of accesses to the GRF, thereby improving loop performance and energy efficiency.

[0087] In one possible implementation, this application can leverage the unique characteristics of the decoded producer instructions to pre-determine whether the result of the renaming instruction is an immediate value that can be written into the renaming mapping table without actual computation during the renaming stage. For example: 1) If the instruction is in the form of addi rd, x0, imm12, the value of the immediate value imm12 can be directly checked at the decoding station to see if it conforms to a preset range. 2) If the instruction is in the form of addi rd, x1, imm12, and the value of imm12 can be checked to be 0, then the result of rd can be determined from the query result of x1 in the renaming mapping table to see if it is an immediate value. This method simplifies the judgment logic by utilizing the inherent characteristics of the instruction set, is applicable to specific instruction patterns, and reduces the latency and implementation complexity of the optimization path.

[0088] In one possible implementation, Figure 4 A flowchart comparing two instruction execution methods is shown. The instruction execution method in the foregoing embodiments of this application can be referred to... Figure 4 The flowchart in the upper part. As another implementation of resource management, it can be referenced. Figure 4 The lower half of the flowchart shows that the processor core can release physical register numbers in the temporary recycling pool without checking the execution status of consumer instructions (second instructions). Instead, the release condition is: the old physical register number corresponding to the logical register in the temporary recycling pool is released only when a new producer instruction allocates a new physical register number for the same logical register number. Although this approach may slightly increase the average occupancy time of physical register resources, its advantage is that it completely avoids the monitoring logic of consumer instruction execution status, simplifies hardware design, and is an optional implementation that balances resource utilization and design complexity.

[0089] In one possible implementation, physical register numbers in the temporary recycling pool can be released early if it can be determined that no consumer instructions need to use them, allowing them to be allocated to new producer instructions. The core of this strategy is to determine in advance whether a physical register resource is safe for reuse by monitoring relevant statuses (e.g., whether all relevant consumer instructions have passed the renaming phase and their source operands do not depend on the physical register) before the consumer instructions actually complete execution. Implementing this strategy can further shorten the average turnaround time of physical register resources and improve resource utilization without excessively increasing hardware complexity.

[0090] See Figure 5 The diagram shows a schematic of the structure of an instruction execution device provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0091] The instruction execution device may specifically include the following modules: The instruction execution module 501 is used to execute the first instruction and obtain the result of the first instruction.

[0092] The instruction processing module 502 is used to write the immediate value into the rename mapping table corresponding to the destination logic register number of the first instruction when the first instruction is executed and the result of the first instruction is detected to be an immediate value that meets the preset numerical range, and to set the status bit of the table entry to indicate that the stored content is an immediate value.

[0093] The instruction index module 503 is used to rename the mapping table based on the source logic register number index of the second instruction during the renaming stage for the second instruction that has a data write-after-read relationship with the first instruction, so as to obtain the status bit and table entry content corresponding to the second instruction.

[0094] The instruction fusion module 504 is used to fuse the second instruction with the immediate value obtained from the table entry when the table entry corresponding to the source logic register number is determined to be an immediate value based on the status bit, so as to obtain a fused instruction. The fused instruction is configured to directly use the immediate value as the source operand during the execution phase.

[0095] The instruction execution apparatus disclosed in the above embodiments of this application first executes a first instruction to obtain the result of the first instruction; then, after the execution of the first instruction is completed and it is detected that the result of the first instruction is an immediate value that conforms to a preset numerical range, the immediate value is written into the renaming mapping table to the entry corresponding to the destination logical register number of the first instruction, and the status bit of the entry is set to indicate that the stored content is an immediate value; next, for a second instruction that is related to a data write-after-read instruction, the renaming mapping table is renamed according to the source logical register number index of the second instruction during the renaming stage to obtain the status bit and entry content corresponding to the second instruction; finally, if it is determined from the status bit that the entry content corresponding to the source logical register number is an immediate value, the second instruction is merged with the immediate value obtained from the entry to obtain a merged instruction, wherein the merged instruction is configured to directly use the immediate value as the source operand during the execution stage. Thus, by dynamically detecting whether the result of the first instruction conforms to a preset numerical range after execution and directly writing it into the renaming mapping table, the second instruction that is related to data can obtain the immediate value as the source operand from the mapping table in the earliest renaming stage. This breaks the fixed path in the traditional scheme where consumer instructions must wait for producer instructions to write back to the physical register file before they can obtain operands. By advancing the operand readiness time from after execution to during renaming, processor performance can be improved.

[0096] Furthermore, in one possible implementation of this application embodiment, the instruction processing module 502 may specifically include the following units: The first determining unit is used to determine whether the physical register number currently stored in the entry of the renaming mapping table corresponding to the destination logical register number of the first instruction is the physical register number allocated by the first instruction.

[0097] The first processing unit is configured to, when the physical register number currently stored in the table entry is the physical register number allocated by the first instruction, write an immediate value into the table entry, set the status bit of the table entry to indicate that the stored content is an immediate value, reclaim the physical register number to a temporary reclamation pool, and set the valid bit of the corresponding entry in the temporary reclamation pool.

[0098] Therefore, by checking whether the physical register number in the table entry is assigned by the instruction before updating the rename mapping table after execution, the error of overwriting the subsequently updated mapping relationship is avoided when there is a write-after-write (WAW) relationship, thus ensuring data correctness; and by placing the confirmed reclaimable physical register numbers into the temporary recycling pool, the early reclamation and safe management of physical register resources are realized.

[0099] Furthermore, in another possible implementation of the embodiments of this application, the above-mentioned instruction execution device may further include the following modules: The first processing module is used to determine whether the source operand of the second instruction is obtained from the general-purpose register file through the physical register number when the second instruction has been executed; and to clear the valid bit of the entry corresponding to the physical register number in the temporary recycling pool if the source operand of the second instruction is obtained from the general-purpose register file through the physical register number.

[0100] Therefore, by determining whether the physical register in the temporary recycling pool was actually used when the second instruction is executed, the valid bits of the physical register are cleared to complete the final release only when it is confirmed that the physical register has no further dependencies. This achieves accurate and safe reclamation of physical register resources and avoids the risk of premature release or long-term occupation of resources.

[0101] Furthermore, in another possible implementation of this application embodiment, the above-mentioned instruction execution device may further include the following modules: The second processing module is used to write the immediate value and the destination logical register number of the first instruction into the corresponding entry of the reorder buffer ROB; in the event of an exception or interruption and it is determined that recovery to a checkpoint is required, the module reads the destination logical register number and the immediate value of the first instruction from the ROB; based on the read destination logical register number and immediate value, the module restores the contents and status bits of the corresponding entry in the rename mapping table, and restores the information related to the physical register number reclamation status.

[0102] Therefore, by recording immediate values ​​and their corresponding logical register numbers in the ROB, when an exception or interrupt occurs and it is necessary to recover to the checkpoint, the rename mapping table and related resource reclamation status can be accurately restored based on the information stored in the ROB, ensuring the correctness and recoverability of the scheme in the speculative execution state.

[0103] Furthermore, in another possible implementation of this application embodiment, the above-mentioned instruction execution device may further include the following modules: The third processing module is used to determine whether all source operand values ​​have been obtained for the first instruction when the first instruction enters the renaming stage; if it is determined that all source operand values ​​have been obtained for the first instruction, the module calculates the result of the first instruction in the renaming stage; if the calculated result of the first instruction is an immediate value that meets the preset value range, the module writes the immediate value into the table corresponding to the destination logic register number of the first instruction in the renaming mapping table, sets the status bit of the table entry to indicate that the stored content is an immediate value, and suppresses the step of executing the first instruction.

[0104] Therefore, by obtaining all source operands and calculating the results in advance during the renaming phase, the renaming mapping table can be updated directly during the renaming phase when the results meet the conditions, and the subsequent issuance and execution of the instruction can be suppressed, saving backend resources such as the issue queue, execution unit and register port.

[0105] Furthermore, in another possible implementation of this application embodiment, the instruction fusion module 504 may specifically include the following units: The second processing unit is used to expand the source operand field of the second instruction so that the source operand field of the second instruction includes an operand type identifier and an operand value field.

[0106] The third processing unit is used to write the immediate value obtained from the table entry into the operand value field.

[0107] The fourth processing unit is used to set the operand type identifier to indicate that the source operand is an immediate value.

[0108] Therefore, by extending the source operand field of the second instruction to include the type identifier and operand value field, hardware support is provided for directly embedding the immediate value obtained from the rename mapping table into the instruction, so that the fused instruction can be directly recognized and used by the immediate value in the execution unit, eliminating the need to read the register file.

[0109] Furthermore, in another possible implementation of this application embodiment, the aforementioned preset numerical range is 0 to... ,or- arrive ,in The bit width for the physical register number.

[0110] The instruction execution device provided in this application embodiment can be applied in the foregoing method embodiment. For details, please refer to the description of the above method embodiment, which will not be repeated here.

[0111] Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 6 As shown, the electronic device 600 of this embodiment includes: at least one processor 610 ( Figure 6 The diagram shows only one processor, a memory 620, and a computer program 621 stored in the memory 620 and executable on the at least one processor 610. When the processor 610 executes the computer program 621, it implements the steps in the above-described instruction execution method embodiments.

[0112] The electronic device 600 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. This electronic device may include, but is not limited to, a processor 610 and a memory 620. Those skilled in the art will understand that... Figure 6 This is merely an example of electronic device 600 and does not constitute a limitation on electronic device 600. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0113] The processor 610 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0114] In some embodiments, the memory 620 may be an internal storage unit of the electronic device 600, such as a hard disk or memory of the electronic device 600. In other embodiments, the memory 620 may be an external storage device of the electronic device 600, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 600. Furthermore, the memory 620 may include both internal and external storage units of the electronic device 600. The memory 620 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 620 can also be used to temporarily store data that has been output or will be output.

[0115] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0116] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0117] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0118] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0119] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0121] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0122] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the various method embodiments described above.

[0123] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An instruction execution method applied to a processor core, characterized in that, The processor core maintains a rename mapping table, wherein entries in the rename mapping table are configured to store physical register numbers or immediate values, and are equipped with status bits to indicate the type of content stored in the entries; the method includes: Execute the first instruction and obtain the result of the first instruction; When the first instruction is executed and the result of the first instruction is detected to be an immediate value that meets the preset value range, the immediate value is written into the table entry corresponding to the destination logical register number of the first instruction in the rename mapping table, and the status bit of the table entry is set to indicate that the stored content is an immediate value; For a second instruction that is related to a data write-after-read instruction, during the renaming phase, the renaming mapping table is indexed according to the source logic register number of the second instruction to obtain the status bit and table entry content corresponding to the second instruction; If the table entry corresponding to the source logic register number is determined to be an immediate value based on the status bit, the second instruction is fused with the immediate value obtained from the table entry to obtain a fused instruction, wherein the fused instruction is configured to directly use the immediate value as the source operand during the execution phase.

2. The method according to claim 1, characterized in that, The step of writing the immediate value into the entry in the rename mapping table corresponding to the destination logical register number of the first instruction, and setting the status bit of the entry to indicate that the stored content is an immediate value, includes: Determine whether the physical register number currently stored in the entry of the rename mapping table corresponding to the destination logical register number of the first instruction is the physical register number allocated by the first instruction. If the physical register number currently stored in the table entry is the physical register number allocated by the first instruction, the immediate value is written to the table entry, the status bit of the table entry is set to indicate that the stored content is an immediate value, the physical register number is recycled to a temporary recycling pool, and the valid bit of the corresponding entry in the temporary recycling pool is set.

3. The method according to claim 2, characterized in that, The method further includes: If the second instruction has been executed, determine whether the source operand of the second instruction was obtained from the general-purpose register file through the physical register number; If the source operand of the second instruction is obtained from the general register file via the physical register number, the valid bit of the entry corresponding to the physical register number in the temporary recycling pool is cleared.

4. The method according to claim 1, characterized in that, The method further includes: Write the immediate value and the destination logic register number of the first instruction into the corresponding entry of the reorder buffer ROB; In the event of an exception or interruption and it is determined that recovery to a checkpoint is required, the destination logic register number of the first instruction and the immediate value are read from the ROB. Based on the read destination logical register number and the immediate value, the contents and status bits of the corresponding entry in the renaming mapping table are restored, and the information related to the recycling status of the physical register number is restored.

5. The method according to claim 1, characterized in that, Before executing the first instruction and obtaining the result of the first instruction, the method further includes: If the first instruction enters the renaming stage, determine whether the first instruction has obtained all the source operation values; If it is determined that all source operation values ​​have been obtained for the first instruction, the result of the first instruction is calculated in the renaming phase; If the calculated result of the first instruction is an immediate value that conforms to the preset numerical range, the immediate value is written into the table entry corresponding to the destination logical register number of the first instruction in the renaming mapping table, and the status bit of the table entry is set to indicate that the stored content is an immediate value, and the step of executing the first instruction is suppressed.

6. The method according to claim 1, characterized in that, The step of fusing the second instruction with the immediate value obtained from the table entry to obtain a fused instruction includes: The source operand field of the second instruction is extended so that the source operand field of the second instruction includes an operand type identifier and an operand value field; The immediate value obtained from the table entry is written into the operand value field; Set the operand type identifier to indicate that the source operand is an immediate value.

7. The method according to claim 1, characterized in that, The preset numerical range is 0 to... ,or- arrive ,in The bit width for numbering the physical register.

8. An instruction execution device applied to a processor core, characterized in that, The processor core maintains a rename mapping table, wherein entries in the rename mapping table are configured to store physical register numbers or immediate values, and are equipped with status bits to indicate the type of content stored in the entries; the device includes: The instruction execution module is used to execute the first instruction and obtain the result of the first instruction. The instruction processing module is configured to, when the first instruction has been executed and the result of the first instruction is detected to be an immediate value that conforms to a preset numerical range, write the immediate value into the table entry corresponding to the destination logical register number of the first instruction in the renaming mapping table, and set the status bit of the table entry to indicate that the stored content is an immediate value; The instruction index module is used to index the renaming mapping table according to the source logic register number of the second instruction during the renaming stage for a second instruction that has a data write-after-read relationship with the first instruction, so as to obtain the status bit and table entry content corresponding to the second instruction. The instruction fusion module is used to fuse the second instruction with the immediate value obtained from the table entry when the table entry corresponding to the source logic register number is determined to be an immediate value based on the status bit, to obtain a fused instruction, wherein the fused instruction is configured to directly use the immediate value as the source operand during the execution phase.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1 to 7.

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