Streaming data processing method and device, electronic equipment, storage medium and program product
By sharing SRAM for multiple data transfer paths in the GPU and allocating dedicated storage space for each path, the problem of excessive cache area is solved, achieving a reduction in cache area and an improvement in storage space utilization without reducing performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-20
AI Technical Summary
In GPU data stream processing, the cache area of multiple data transmission paths increases proportionally with the number of channels, but performance optimization is not proportional, resulting in an excessively large cache area.
A shared static random access memory (SRAM) is used for multiple data transmission paths, and a dedicated storage space is allocated for each path. The target data transmission path and output data are determined by a preset streaming data transmission rule.
Significantly reduce cache size, improve storage space utilization, and shrink graphics processor area without compromising performance.
Smart Images
Figure CN121705058A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer chip architecture technology, specifically to the fields of graphics processors, data transmission paths, caches, etc., and particularly to a streaming data processing method, electronic device, computer-readable storage medium, and computer program product. Background Technology
[0002] In GPU (Graphics Processing Unit) data stream processing scenarios, there exists a situation where data from multiple data transmission paths converges at the same location, and then is processed uniformly by the convergence point module.
[0003] To ensure that data can flow smoothly through each data transmission path, a method has been proposed that each data transmission path be equipped with a separate cache to store data. However, when there are a large number of data transmission paths, the cache area will increase proportionally with the number of channels. In some scenarios, this increased area does not necessarily lead to a proportional performance optimization.
[0004] Therefore, how to reduce the cache size as much as possible without reducing performance is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] This disclosure provides a streaming data processing method, a data transmission path, and corresponding electronic devices, graphics processors, computer-readable storage media, and computer program products.
[0006] In a first aspect, embodiments of this disclosure propose a streaming data processing method applied to a graphics processor. The graphics processor includes multiple data transmission paths and a shared static random access memory (SRAM) disposed in the multiple data transmission paths. Each data transmission path has its own dedicated data storage space in the shared SRAM. The method includes: storing the stream data to be processed transmitted by the data transmission path that initiates the temporary storage request in the corresponding data storage space in the shared SRAM; determining, according to preset streaming data transmission rules, target stream data to be processed corresponding to the current clock cycle from the stream data to be processed stored in the shared SRAM; and outputting the target stream data to be processed to the first target data transmission path for transmission to a set location for convergence processing.
[0007] Secondly, embodiments of this disclosure propose a data transmission path applied to a graphics processor. The graphics processor includes multiple data transmission paths and a shared static random access memory (SRAM) disposed in the multiple data transmission paths. Each data transmission path has its own dedicated data storage space in the shared SRAM. The device includes: a pending stream data storage unit configured to store pending stream data transmitted by the data transmission path that initiates a temporary storage request in the corresponding data storage space in the shared SRAM; a target pending stream data determination unit configured to determine, according to preset stream data transmission rules, the target pending stream data of a first target data transmission path corresponding to the current clock cycle from the pending stream data stored in the shared SRAM; and an output unit configured to output the target pending stream data to the first target data transmission path for convergence processing at a set location.
[0008] Thirdly, embodiments of this disclosure provide an electronic device comprising: at least one graphics processor; and a memory communicatively connected to the at least one graphics processor; wherein the memory stores instructions executable by the at least one graphics processor, the instructions being executed by the at least one graphics processor to enable the at least one graphics processor to perform a streaming data processing method as described in the first aspect.
[0009] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that enable a computer including a graphics processor to implement the streaming data processing method as described in the first aspect when executed.
[0010] Fifthly, embodiments of this disclosure provide a computer program product including a computer program that, when executed by a processor, can implement the steps of the streaming data processing method as described in the first aspect.
[0011] The streaming data processing scheme provided in this disclosure uses a unique static random-access memory (SRAM) in multiple data transmission paths of the graphics processor as a shared memory for all data transmission paths. This eliminates the need to set up an independent cache for each data transmission path. Furthermore, the shared SRAM is logically divided into dedicated storage spaces for each data transmission path, thus ensuring the independence of the data transmitted by each data transmission path. Since only one shared SRAM is required and the utilization rate of storage space is improved, the cache area is significantly reduced without sacrificing performance, which is beneficial for further reducing the area of the graphics processor.
[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0013] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of a data transmission path in a graphics processor provided in an embodiment of this disclosure; Figure 2-1 A schematic diagram of a data transmission path in a graphics processor, provided for related technologies; Figure 2-2 In order to be in Figure 1 The diagram shows a specific structure using a shared single-port SRAM based on the given information. Figure 2-3 In order to be in Figure 1 The diagram shows a specific structure using a shared dual-port SRAM based on the shown example. Figure 3 A flowchart illustrating a streaming data processing method applied to a graphics processor, provided as an embodiment of this disclosure; Figure 4 A flowchart illustrating a method for determining a target request based on arbitration rules, provided as an embodiment of this disclosure; Figure 5 A branch flowchart of a streaming data processing method including a bypass mode, provided for embodiments of this disclosure; Figure 6 A schematic diagram of another data transmission path in a graphics processor provided in an embodiment of this disclosure; Figure 7 A structural block diagram of a streaming data processing device applied to a graphics processor, provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of a computing device suitable for performing a streaming data processing method, provided as an embodiment of the present disclosure. Detailed Implementation
[0014] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.
[0015] Figure 1 This diagram illustrates a data transmission path structure provided by related technologies to enable data to flow smoothly in each data transmission path, such as... Figure 1 As shown: In order to ensure that the data of each data transmission path can flow smoothly, a separate buffer is set up for each data transmission path to store the data it transmits. That is, buffer 1 is set up for data transmission path 1 to temporarily store the data transmitted by data transmission path 1, buffer 2 is set up for data transmission path 2 to temporarily store the data transmitted by data transmission path 2, and so on up to all data transmission paths N.
[0016] The applicant discovered that, in the use of Figure 1 The solution provided will generate a cache for the number of channels. This cache may be RAM (Random-Access Memory) or a register array. When there are many data transmission paths, the cache area will increase proportionally with the number of channels. However, this increase in area will not bring proportional performance optimization in some scenarios.
[0017] Therefore, in scenarios where multi-path data converges in the same module, this disclosure provides a method to reduce the pipeline buffer area required for multiple paths without compromising performance. Figure 2-1 The diagram shown illustrates the structure of the data transmission path. In this application within the GPU, the data transmission path includes: In multiple data transmission paths (e.g.) Figure 2-1 A shared SRAM is configured on the data transmission paths (1, 2...N) shown in the diagram. This shared SRAM has multiple input terminals and multiple output terminals, each input terminal and each output terminal being connected to a data transmission path (e.g., ...). Figure 2-1 As shown, data transmission paths 1, 2...N are all connected to different input terminals on the left side of the shared SRAM, and different output terminals on the right side of the shared SRAM are also connected to data transmission paths 1, 2...N.
[0018] The shared SRAM is used to store the pending stream data transmitted by the data transmission path that initiates the temporary storage request in the corresponding data storage space in the shared SRAM (that is, each data transmission path has its own dedicated data storage space in the shared SRAM). According to the preset stream data transmission rules, the target pending stream data of the first target data transmission path corresponding to the current clock cycle is determined from the pending stream data stored in the shared SRAM. The target pending stream data is then output to the first target data transmission path, so that it can be transmitted to a set location for convergence processing.
[0019] In this shared SRAM, each data transmission path has its own dedicated data storage space. That is, the total storage space of the shared SRAM is divided into multiple independent and isolated sub-storage spaces, which are allocated to each connected data transmission path. For example, sub-storage space 1 can be allocated to data transmission path 1 and used only to store the stream data to be processed received from data transmission path 1. Similarly, sub-storage space 2 can be allocated to data transmission path 2 and used only to store the stream data to be processed received from data transmission path 2, and so on, until a corresponding sub-storage space is allocated to each connected data transmission path. This ensures that even when using a shared SRAM, it can achieve similar functionality. Figure 1 The diagram illustrates the same effect of physically setting up a dedicated buffer for each data transmission path to temporarily store the streaming data to be processed.
[0020] It can be seen that the shared SRAM is actually set up on the data transmission paths of multiple data transmission channels. It aims to temporarily store the stream data to be processed on each data transmission channel according to the preset stream data transmission rules, so that it can be sent back to each data transmission channel in an orderly manner, and finally converged to the convergence model (that is, the convergence model is set at the set position) for convergence processing.
[0021] Based on the above embodiments, considering that SRAM can be further subdivided in practical situations: single-port SRAM (see...) Figure 2-2 ) and dual-port SRAM (see Figure 2-3 In a shared single-port SRAM, only one type of data processing operation can be performed per clock cycle, including write and read operations. In contrast, a shared dual-port SRAM can perform two types of data processing operations per clock cycle, meaning that the write and read operations mentioned above can be performed simultaneously.
[0022] It should be noted that storing the data to be processed in the shared SRAM is a write operation, that is, writing the data to be processed into the storage space of the shared SRAM. However, outputting the data to be processed stored in the shared SRAM to the corresponding data transmission path is usually not a write operation, but rather a read request initiated by the pre-read buffer set on the corresponding data transmission path. Therefore, for a shared single-port SRAM, it can only satisfy the temporary storage request initiated by one data transmission path to perform a write operation in one clock cycle, or only satisfy the read request initiated by the pre-read buffer on one data transmission path to perform a read operation. That is, read and write operations cannot be effective at the same time and conflict with each other.
[0023] In contrast, a shared dual-port SRAM can simultaneously fulfill both write operations initiated by a data transfer path's temporary storage request and read operations initiated by a read-ahead cache on another data transfer path within a single clock cycle. This means read and write operations can occur concurrently without conflict. To achieve this effect, which distinguishes it from a shared single-port SRAM, the shared dual-port SRAM requires a larger cache area.
[0024] Based on the above description of the data transmission path structure, to further understand how the shared SRAM is used to uniformly store the stream data to be processed transmitted by each data transmission path, please refer to [link to relevant documentation]. Figure 3 The flowchart shown illustrates a streaming data processing method applied to a GPU, wherein process 300 includes the following steps: Step 301: Store the pending stream data transmitted by the data transmission path that initiated the temporary storage request in the corresponding data storage space in the shared SRAM; This step aims to have the execution entity of the streaming data processing method (e.g., a controller in a GPU that manages the convergence of data transmitted through multiple data transmission paths into a single module) utilize a shared SRAM simultaneously set in multiple data transmission paths to store the streaming data to be processed transmitted by the data transmission path that initiated the temporary storage request in the corresponding data storage space of the shared SRAM.
[0025] Here, the data transmission path refers to the hardware path within the GPU that carries a specific data stream (referring to the data stream that needs to be converged for processing), such as the color, depth, or subsample data streams output by the pixel shader in multisampling anti-aliasing. In this case, each data transmission path is typically responsible for transmitting a logically independent data sequence. The shared SRAM refers to a physically unique but logically partitioned SRAM storage unit shared by several paths. Its core lies in integrating the cache resources that were originally exclusive to each path into a large-scale shared memory. Simultaneously, through address space partitioning, a dedicated storage area is reserved for each path. This preserves data independence while merging the small-capacity caches originally scattered across various paths into one place, thus significantly improving storage space utilization. Furthermore, from a memory organization perspective, it embodies a design concept of mapping multiple virtual memories to a single physical memory, specifically used to reduce cache area.
[0026] In actual deployment, this shared SRAM is placed at the intersection of all data transmission paths. Its data input and output terminals are connected to each path respectively. When a data transmission path has streaming data to be processed that needs to be cached, it can write the data into its corresponding storage area according to a preset address offset. Furthermore, the storage of the streaming data to be processed in this shared SRAM is short-term and temporary, meaning it does not need to be stored long-term, but rather refers to a brief stay before the data is retrieved by the downstream aggregation point module.
[0027] Step 302: According to the preset streaming data transmission rules, determine the target streaming data of the first target data transmission path corresponding to the current clock cycle from the streaming data to be processed stored in the shared SRAM; Building upon step 301, this step aims to have the aforementioned executing entity determine, according to pre-defined streaming data transmission rules, the target streaming data of the first target data transmission path corresponding to the current clock cycle from the streaming data stored in the shared SRAM. Here, the pre-defined streaming data transmission rules refer to a series of judgment logics that are fixed or configurable during the hardware design phase, used to rationally select data objects that should be processed in the current cycle among different channels.
[0028] The implementation of this step relies on the structured organization and state tracking of data stored in the shared SRAM. Each piece of pending stream data, in addition to its numerical value, typically includes identification information related to its channel, such as channel number, data type, or priority flag. Therefore, at the start of each clock cycle, the first target data transmission path—the logical path with the highest processing priority—is dynamically selected based on the current data backlog of each channel, the urgency of business processing, the preset rotation order, and the needs of the stream processing task. Subsequently, the pending data associated with this path and in a ready state is identified as the target pending stream data and prepared to enter the next output or processing step.
[0029] In practical terms, this streaming data transmission rule can be implemented by a scheduling state machine in conjunction with tag comparison logic. It continuously monitors the status of each path's corresponding storage area in SRAM, such as the presence of valid data, data retention time, or whether it meets externally triggered processing conditions. For example, in a system employing a strict round-robin strategy, the scheduling pointer will cycle through to the next channel; while in a system supporting priority scheduling, the urgency of data across different paths may be compared, always prioritizing the highest-priority data. To improve response timeliness, a "recently unserved" criterion is sometimes used to prevent any path from remaining unresponsive for an extended period. After determining the target path and data, the control circuit generates the corresponding SRAM read address and enable signal, ensuring that the correct data block is retrieved and sent to the designated data transmission path.
[0030] exist Figure 2-2 In the case of the shared single-port SRAM shown, this step can also be specifically manifested as using the shared single-port SRAM simultaneously set in multiple data transmission paths to temporarily store the stream data to be processed transmitted by each data transmission path; Figure 2-3 In the case of the shared dual-port SRAM shown, this step can also be specifically manifested as using the shared dual-port SRAM simultaneously set in multiple data transmission paths to temporarily store the stream data to be processed transmitted by each data transmission path.
[0031] Furthermore, where practical considerations allow, the previously adopted or initially implemented static rules can be upgraded to strategies with dynamic learning capabilities. This would allow for predictive activation of read operations in corresponding storage areas based on the statistical characteristics of historical data streams, such as burst intervals or periodic patterns in a particular channel. Even further, a service quality awareness mechanism could be introduced to dynamically fine-tune the priority weights of different functional channels based on the real-time load of the graphics rendering pipeline, such as the pressure comparison between vertex processing and pixel processing stages. This would allow resource allocation to better align with the changing needs of the actual task.
[0032] Step 303: Output the target stream data to be processed to the first target data transmission path, so that it can be transmitted to the set location for aggregation processing.
[0033] Building upon step 302, this step involves the aforementioned executing entity outputting the target stream data to be processed to the first target data transmission path, which then transmits the data to a designated location (e.g., a convergence point module or convergence model) for convergence processing. This step is the final step in completing the data flow, ensuring that the temporarily stored data is accurately released from the shared storage and returned to its predetermined path, ultimately completing the convergence.
[0034] From a technical perspective, the operation described in this step essentially involves selectively retrieving data from a centralized storage space and re-injecting it into a designated hardware path. The key lies in maintaining the correctness of data ownership relationships; that is, within a shared physical medium, it must always be clear which data belongs to which path and deliver it to the corresponding path at the correct time. Implementation relies on stable internal control logic. This logic should be able to clearly identify which path should receive data each clock cycle according to preset rules and accurately transmit the data stored at the corresponding location in SRAM. The entire process must strictly adhere to the timing requirements of the circuit to ensure that the data is stable and valid when read and placed on the target path.
[0035] In practice, the control unit first needs to locate the physical location of the first target stream data in the SRAM, which can be achieved through a lookup table or a fixed address offset mechanism. Once the address is determined, a read enable signal can be issued. For a single-port SRAM, this read operation is exclusive within that clock cycle. After the data is read from the single-port SRAM, it is sent to the target data transmission path to be sent to the subsequent link corresponding to that data transmission path.
[0036] The streaming data processing method provided in this disclosure uses a unique SRAM in multiple data transmission paths of a graphics processor as a shared memory for all data transmission paths, thus eliminating the need to set up an independent cache for each data transmission path. The shared SRAM is logically divided into dedicated storage spaces for each data transmission path, thereby ensuring the independence of the data transmitted by each data transmission path. Since only one shared SRAM is needed and the utilization rate of storage space is improved, the cache area is significantly reduced without sacrificing performance, which is beneficial for further reducing the area of the graphics processor.
[0037] Furthermore, considering that the depth of the shared SRAM is usually fixed, the bit width needs to be determined by comprehensively considering factors such as area and transmission efficiency. A preferred approach is to set the bit width of the shared SRAM to be greater than the bit width of the data transmitted through each data transmission path. For example, the bit width of the shared SRAM can be set to twice the bit width of the data transmitted through each data transmission path. That is, each piece of data stored in the SRAM is obtained by concatenating two consecutive data streams to be processed from the same data transmission path. Of course, it can also be a multiple of other values, or even a non-integer multiple.
[0038] From a technical perspective, since multiple data transmission paths need to time-share the common SRAM, if the bit width of the common SRAM is only equal to the data bit width of a single data transmission path, then in any given clock cycle, the common SRAM can only serve one data entry for one channel, spending most of its time idle or waiting, resulting in very low bandwidth utilization. Doubling the bit width essentially merges two logical accesses into one physical operation, allowing two consecutive data entries from the same channel to be stored simultaneously in a single write cycle. This is analogous to a single-lane highway: if only one car is allowed to pass at a time, its capacity is limited; but if the road is widened to allow two cars to travel side-by-side, the total number of vehicles passing per unit time increases. In practice, this means adding a data assembly stage before the data flows into the SRAM. Structurally, this can be achieved by adding a pre-assembly module to latch and concatenate the data from the current and previous cycles of the same channel, forming a composite data entry that conforms to the bit width of the common SRAM interface before writing it.
[0039] This approach not only effectively improves the efficient access bandwidth of SRAM and alleviates congestion caused by multiple channels competing for a single port, but also reduces dynamic power consumption by decreasing the total number of accesses. Furthermore, this strategy of doubling the bit width, combined with the shared SRAM architecture, helps optimize the overall chip area; by increasing the bit width, the ratio of depth to bit width is slightly smaller, thus saving overall chip area.
[0040] Furthermore, the bit width of this shared SRAM is not limited to a strict two-fold relationship. It can be flexibly set to four times the input data bit width or other non-integer multiples, depending on the system's specific data flow pattern and performance requirements, thereby further amplifying its bandwidth and area gains. Of course, higher multiples may also bring challenges such as increased data assembly latency and higher routing complexity, requiring more careful consideration in the design.
[0041] Based on any of the above embodiments, considering that multiple data transmission paths may simultaneously initiate temporary storage requests to the shared SRAM (i.e., requesting to temporarily store the stream data to be processed transmitted on the path itself into the shared SRAM), but in order to ensure the correct order, especially in the case of using a single-port SRAM, one clock cycle can only satisfy the temporary storage request of one data transmission path to write the stream data to be processed into the shared SRAM, an arbitration module can be added in the multiple data transmission paths located before the shared SRAM according to the data transmission direction. The aim is to use the arbitration module to determine the target request corresponding to the current clock cycle among the multiple temporary storage requests using preset arbitration rules, and to store the stream data to be processed carried by the target request into the shared SRAM.
[0042] In other words, when multiple data transfer paths in the graphics processor simultaneously need to submit temporary storage requests to the shared SRAM, an arbitration coordination mechanism is initiated. This mechanism, when faced with multiple concurrent temporary storage requests, determines one of them as the sole executable target request within the current clock cycle according to pre-defined arbitration rules, and stores its corresponding pending data stream into the shared SRAM. Essentially, arbitration establishes order among competitors vying for shared resources. For a shared single-port SRAM, it can only respond to one operation at any given time—either a read or a write. Without arbitration, multiple paths attempting to read or write simultaneously will lead to data conflicts or storage errors.
[0043] This pre-defined arbitration rule is essentially a set of pre-agreed decision-making rules used to autonomously determine the access order without central command. Common rules can include numbered priority, which grants priority according to a fixed order of access numbers. This method is simple to implement but may lack fairness. Another commonly used rule is the round-robin rule, which is similar to a call-a-number mechanism, ensuring that each access route receives service opportunities within a certain period and preventing some routes from being unresponsive for extended periods. Another type is the importance priority rule, which determines the order based on the nature or urgency of the data. For example, in graphics rendering, user interface element data may have a higher priority than background textures to ensure smooth interaction. Regardless of the rule used, the goal is to achieve efficient and conflict-free resource allocation at the hardware level.
[0044] In practical terms, the arbitration process can be implemented by a hardware state machine constituting the arbitration module. This machine continuously monitors request signals from each channel, and once it detects two or more valid requests simultaneously, it immediately calculates and selects the appropriate channel based on the currently effective rules. For example, in a system using round-robin rules, a counter might be maintained, incremented each cycle, and the channel selected accordingly, creating a cyclical scheduling effect. If importance rules are used, an additional labeling system is typically required to assign weights to different types of data. During implementation, it's crucial that the arbitration process is completed within one clock cycle to avoid slowing down the overall processing flow. To improve response efficiency, the arbitration logic should be placed as close as possible to the SRAM input ports to minimize signal transmission latency. Simultaneously, the stability of the arbitration result is also important; frequent target switching within consecutive cycles should be avoided to reduce control signal jitter.
[0045] For a specific implementation method, please refer to Figure 4 The flowchart shown, process 400 includes the following steps: Step 401: Based on the arbitration rules, determine the second target data transmission path corresponding to the current clock cycle from the data transmission paths to which each temporary request belongs; Step 402: Determine the temporary storage request corresponding to the second target data transmission path as the target temporary storage request corresponding to the current clock cycle.
[0046] First, arbitration rules are used to determine the data transmission path corresponding to each temporary request. Then, among multiple data transmission paths, the data transmission path corresponding to the current clock cycle is determined, which is the second target data transmission path (used to distinguish it from the previous one). Figure 3 The first target data transmission path mentioned in the embodiment is then used to determine the temporary request corresponding to the second target data transmission path as the target request corresponding to the current clock cycle.
[0047] Furthermore, considering the existence of an arbitration module, the assembly module mentioned in the previous embodiment can be specifically set in the multiple data transmission paths at a position before the arbitration module along the data transmission direction, for splicing the received transmitted data according to the bit width of a shared SRAM.
[0048] Based on the previous embodiment, see [link to previous embodiment]. Figure 5The branch diagram shown illustrates that, considering that in some cases the sub-storage space allocated in the shared SRAM for certain data transmission paths is empty (i.e., no prior pending data is stored), a data transmission bypass can be added, with a bypass module installed on it. The input of this bypass module is located after the assembly module and before the arbitration module in the data transmission direction of the multiple data transmission paths, and its output is located after the shared SRAM and before the preset pre-read cache. When the storage space allocated in the shared SRAM for the target data transmission path (which can be referred to as the third target data transmission path used to distinguish the first and second target data transmission paths) in the data transmission path that initiated the temporary storage request is empty, and the remaining storage space of the pre-read cache is not less than the required storage space, the pending data carried by the temporary storage request initiated by the third target data transmission path is stored in the pre-read cache through the preset bypass, so that it can be output to the third target data transmission path by the pre-read cache. The required storage space is the storage space corresponding to the sum of the pending stream data carried in the temporary storage request initiated by the third target data transmission path and the pending stream data of the previous clock cycle read from the shared SRAM (i.e., the corresponding storage space). Figure 5 (Branch of the bypass mode).
[0049] This embodiment adds a data transmission bypass and its associated bypass module to the multi-channel data stream processing architecture described in the above embodiments, aiming to further optimize critical path latency. This bypass is physically an independent data channel from the data access path via shared SRAM described above. Its existence is not intended to replace the core shared memory mechanism, but rather to provide a faster path under specific conditions.
[0050] From a technical perspective, this bypass operation relies on two conditions: First, it checks if the sub-memory area allocated in the shared SRAM for the target data transmission path is empty, meaning no previously stored but unread data remains there. Second, it assesses whether the downstream read-ahead cache has sufficient free capacity to meet the required storage requirements. This required storage capacity refers not only to the space occupied by the current stream of data but also, ideally, the total cache capacity required for this data plus any associated data from the previous clock cycle that needs to be retrieved from SRAM. Only when both conditions are met simultaneously will this "fast track" be activated, allowing data to bypass the arbitration queuing and SRAM write processes and be directly delivered to the read-ahead cache, ready for output.
[0051] In practical application, the bypass module is embedded as an independent control unit within the data path. Its input follows immediately after the assembly module, meaning the data has already undergone necessary formatting or splicing preparation; its output bypasses SRAM and connects directly to the pre-read cache entry. During each clock cycle, the bypass logic checks the aforementioned two conditions on each connected path. If a path meets the conditions, the bypass module directs the data from that path to the bypass channel, directly reaching the pre-read cache. This mechanism provides a high-speed path for simple scenarios that do not require mixing or computation with historical data. Especially in high-load scenarios with poor data locality, this design effectively reduces the average latency of data processing.
[0052] Furthermore, if the storage space allocated for the third target data transmission path in the shared SRAM is not empty or the remaining storage space in the pre-read cache is less than the required storage space, then a preset arbitration rule needs to be used to determine the target request corresponding to the current clock cycle from among multiple temporary requests, and to store the pending stream data carried by the target request into the shared SRAM. That is, in this case... Figure 5 Branches in the non-bypass mode that do not meet the activation conditions of the bypass mode should still be arbitrated before being stored in the shared SRAM.
[0053] To enhance understanding of the solutions described in the above embodiments, this embodiment also provides further explanation. Figure 6 A specific implementation scheme is presented based on the actual situation. Figure 6 The diagram shows the left and right transmission ends of multiple data transmission paths (transmission paths are from left to right), as well as the MUX_FIFO (Multiplexer First-In-First-Out) between the left and right transmission ends. This multiplexer first-in-first-out queue mainly consists of an assembly module, an arbitration module, a bypass module, a single-port SRAM, and a pre-read buffer.
[0054] The assembly module buffers and assembles the input data from each channel, concatenating it into a data width twice the input bit width. The arbitration module handles arbitration of multiple data channels. When multiple data channels require access to SRAM, it can grant access permissions according to a certain arbitration strategy. The bypass module provides a way for input data to be directly passed to the downstream without writing to SRAM, reducing the overall module latency and also reducing the SRAM access frequency to some extent. The single-port SRAM provides buffering for data from multiple channels, and the usage space of each channel is relatively independent and configurable. Only one access type (read or write) is allowed per cycle (clock period). The pre-read buffer buffers bypass data input from the bypass module or data read from SRAM and outputs it to the downstream module according to the input data bit width. The module has two modes: bypass mode and non-bypass mode. The two modes are automatically switched according to internal logic, and the two modes are mutually exclusive within the same channel. Mode 1: Bypass Mode When the SRAM space corresponding to a certain path is empty, and the downstream prefetch cache has enough space to cache bypass data or data read from SRAM in the previous step, it enters bypass mode. At this time, the input data of the path will not be stored in SRAM, but will be directly stored in the prefetch cache through bypass logic and then output. Mode 2: Non-bypass mode When the SRAM space corresponding to a certain path is not empty or the prefetch cache does not have enough space to store bypass data, it enters non-bypass mode. At this time, the data input to the path must be collected into two entries before being written to the single-port SRAM.
[0055] In the non-bypass processing flow, each channel's input and output interface is independent. Each channel performs an operation judgment for each cycle, with three possible outcomes: read, write, or bypass. These three outcomes are mutually exclusive and cannot be effective simultaneously. Excluding the bypass outcome, each channel's read or write operation will enter the arbitration module to request permission. Based on the set arbitration principles, permission will be obtained, and after obtaining permission, the SRAM will be read or written. The pre-read module's cache space is used to store bypass data or data read from SRAM. As long as there is data in the domain segment cache, it will actively initiate an output request to the downstream.
[0056] The technical solution provided in this embodiment uses a single-port SRAM and configures an independent cache space for each path. At the same time, the arbitration strategy for each path can be flexibly configured. The addition of bypass logic also reduces the overall path latency of the module and can reduce the power consumption of accessing the limited SRAM in certain scenarios. Of course, the most important thing is that using a single-port SRAM can greatly increase the cache area.
[0057] Further reference Figure 7As an implementation of the streaming data processing method described above, this disclosure provides an embodiment of a streaming data processing apparatus, which is similar to... Figure 3 Corresponding to the method embodiment shown, the device can be specifically applied to a GPU, which includes multiple data transmission paths and a shared SRAM disposed in the multiple data transmission paths, with each data transmission path having its own dedicated data storage space in the shared SRAM.
[0058] like Figure 7 As shown, the streaming data processing apparatus 700 of this embodiment may include: a stream data storage unit 701 to be processed, a target stream data determination unit 702, and an output unit 703. The stream data storage unit 701 is configured to store the stream data to be processed transmitted by the data transmission path that initiated the temporary storage request in a corresponding data storage space in a shared SRAM. The target stream data determination unit 702 is configured to determine, according to preset streaming data transmission rules, the target stream data to be processed for a first target data transmission path corresponding to the current clock cycle from the stream data to be processed stored in the shared SRAM. The output unit 703 is configured to output the target stream data to the first target data transmission path for convergence processing at a set location.
[0059] In this embodiment, the specific processing and technical effects of the stream data processing device 400, including the stream data storage unit 701, the target stream data determination unit 702, and the output unit 703, can be referred to respectively. Figure 3 The relevant descriptions of steps 301-303 in the corresponding embodiments will not be repeated here.
[0060] In some other optional implementations of this embodiment, the shared SRAM includes a shared single-port SRAM, which can only perform one type of data processing operation in each clock cycle. The data processing operations include: write operation and read operation.
[0061] In some other optional implementations of this embodiment, the shared SRAM includes a shared dual-port SRAM, which can perform two types of data processing operations simultaneously in each clock cycle, including write operations and read operations.
[0062] In some other optional implementations of this embodiment, the bit width of the shared SRAM is greater than the bit width of the data transmitted by each data transmission path.
[0063] In some other optional implementations of this embodiment, the bit width of the shared SRAM is twice the bit width of the data transmitted by each data transmission path; each piece of data stored in the shared SRAM is obtained by splicing together two consecutive pieces of data to be processed from the same data transmission path.
[0064] In some other optional implementations of this embodiment, the stream data storage unit 701 to be processed may include: The target temporary storage request determination subunit is configured to determine the target temporary storage request corresponding to the current clock cycle from multiple temporary storage requests in response to receiving temporary storage requests initiated by at least two data transmission paths simultaneously in the current clock cycle. The storage sub-unit is configured to store the pending stream data carried by the target temporary storage request into the corresponding data storage space in the shared SRAM; wherein, the corresponding data storage space is the data storage space corresponding to the data transmission path to which the target temporary storage request belongs.
[0065] In some other optional implementations of this embodiment, the target temporary storage request determination subunit is further configured to: Based on the arbitration rules, a second target data transmission path corresponding to the current clock cycle is determined from the data transmission paths to which each temporary request belongs. The temporary storage request corresponding to the second target data transmission path is determined as the target temporary storage request corresponding to the current clock cycle.
[0066] In some other optional implementations of this embodiment, the arbitration rules include any one of the following: Numbering priority rules corresponding to the channel numbering of each data transmission path; Each data transmission path takes turns following a rotation rule with the highest priority. Importance priority rules corresponding to the importance of the data transmitted on each data transmission path.
[0067] In some other optional implementations of this embodiment, the target temporary storage request determination subunit includes: The non-bypass mode determination module is configured to determine the target temporary storage request corresponding to the current clock cycle from multiple temporary storage requests in response to the storage space corresponding to the third target data transmission path being not empty or the remaining storage space of the preset pre-read cache being less than the required storage space. The third target data transmission path is the data transmission path that initiates the temporary storage request; the pre-read cache is set in multiple data transmission paths and is located after the shared SRAM along the data transmission direction; the required storage space is the storage space corresponding to the sum of the pending stream data carried by the temporary storage request initiated by the third target data transmission path and the pending stream data read from the shared SRAM in the previous clock cycle.
[0068] In some other optional implementations of this embodiment, the target temporary storage request determination subunit further includes: The bypass mode determination module is configured to respond to the fact that the storage space corresponding to the third target data transmission path is empty and the remaining storage space of the pre-read cache is not less than the required storage space, and to store the stream data to be processed carried by the temporary storage request initiated by the third target data transmission path into the pre-read cache through a preset bypass, so that the pre-read cache can transmit the stream data to be processed to the set location for aggregation processing through the third target data transmission path.
[0069] This embodiment exists as a device embodiment corresponding to the above method embodiment. The streaming data processing device provided in this embodiment sets a unique SRAM in multiple data transmission paths in the graphics processor as a shared memory for all data transmission paths, thereby eliminating the need to set an independent cache for each data transmission path. Moreover, the shared SRAM is logically divided into dedicated storage space for each data transmission path, thus ensuring the independence of the data transmitted by each data transmission path. Since only one shared SRAM needs to be set and the utilization rate of storage space is improved, the cache area is significantly reduced without sacrificing performance, which is beneficial to further reduce the area of the graphics processor.
[0070] According to embodiments of the present disclosure, the present disclosure also provides an electronic device, the electronic device comprising: at least one processor, and the at least one processor including a graphics processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the graphics processor to enable the graphics processor to implement the streaming data processing method described in any of the above embodiments.
[0071] According to embodiments of this disclosure, this disclosure also provides a readable storage medium storing computer instructions that enable a computer including a graphics processor to implement the streaming data processing method described in any of the above embodiments.
[0072] According to embodiments of this disclosure, this disclosure also provides a computer program product that, when executed by a processor, can implement the streaming data processing method described in any of the above embodiments.
[0073] Figure 8 A schematic block diagram of an example computing device 800 that can be used to implement embodiments of the present disclosure is shown, wherein the computing device 800 includes at least a GPU chip for providing graphics computing. The computing device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The computing device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0074] like Figure 8 As shown, the computing device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the computing device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.
[0075] Multiple components in the computing device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, optical disk, etc.; and a communication unit 809, such as a network interface card, modem, wireless transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0076] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as streaming data processing methods applied to a front-end processing module. For example, in some embodiments, the streaming data processing methods applied to a front-end processing module can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the computing device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the streaming data processing methods applied to a front-end processing module described above can be performed. Alternatively, in other embodiments, the computing unit 801 may be configured by any other suitable means (e.g., by means of firmware) to perform streaming data processing methods applied to the front-end processing module.
[0077] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0078] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0079] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0080] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0081] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.
[0082] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.
[0083] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0084] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A streaming data processing method, characterized in that, The method is applied to a graphics processing unit (GPU), which includes multiple data transmission paths and a shared static random access memory (SRAM) disposed within the multiple data transmission paths, each data transmission path having its own dedicated data storage space within the shared SRAM; the method includes: The pending stream data transmitted through the data transmission path that initiated the temporary storage request is stored in the corresponding data storage space in the shared SRAM. According to the preset streaming data transmission rules, the target streaming data of the first target data transmission path corresponding to the current clock cycle is determined from the streaming data to be processed stored in the shared SRAM. The target stream data to be processed is output to the first target data transmission path, so that it can be transmitted by the first target data transmission path to a set location for convergence processing.
2. The method according to claim 1, characterized in that, The shared SRAM includes a shared single-port SRAM, which can only perform one type of data processing operation per clock cycle. The data processing operations include: write operation and read operation.
3. The method according to claim 1, characterized in that, The shared SRAM includes a shared dual-port SRAM, which can perform two types of data processing operations simultaneously in each clock cycle, including write operations and read operations.
4. The method according to any one of claims 1-3, characterized in that, The bit width of the shared SRAM is greater than the bit width of the data transmitted by each of the data transmission paths.
5. The method according to claim 4, characterized in that, The bit width of the shared SRAM is twice the bit width of the data transmitted by each data transmission path; each piece of data stored in the shared SRAM is obtained by splicing together two consecutive pieces of data to be processed from the same data transmission path.
6. The method according to any one of claims 1-3, characterized in that, The step of storing the pending stream data transmitted by the data transmission path that initiated the temporary storage request in the corresponding data storage space in the shared SRAM includes: In response to receiving temporary storage requests initiated by at least two data transmission paths simultaneously during the current clock cycle, a target temporary storage request corresponding to the current clock cycle is determined from the plurality of temporary storage requests. The pending stream data carried by the target temporary storage request is stored in the corresponding data storage space in the shared SRAM; wherein, the corresponding data storage space is the data storage space corresponding to the data transmission path to which the target temporary storage request belongs.
7. The method according to claim 6, characterized in that, The step of determining the target temporary storage request corresponding to the current clock cycle from the plurality of temporary storage requests includes: Based on the arbitration rules, a second target data transmission path corresponding to the current clock cycle is determined from the data transmission paths to which each of the aforementioned temporary requests belongs. The temporary storage request corresponding to the second target data transmission path is determined as the target temporary storage request corresponding to the current clock cycle.
8. The method according to claim 7, characterized in that, The arbitration rules include any one of the following: Numbering priority rules corresponding to the channel numbering of each data transmission path; Each data transmission path takes turns following a rotation rule with the highest priority. Importance priority rules corresponding to the importance of the data transmitted on each data transmission path.
9. The method according to claim 6, characterized in that, Determining the target temporary storage request corresponding to the current clock cycle from the plurality of temporary storage requests includes: In response to the fact that the storage space corresponding to the third target data transmission path is not empty or the remaining storage space of the preset pre-read cache is less than the required storage space, a target temporary storage request corresponding to the current clock cycle is determined from the multiple temporary storage requests. Wherein, the third target data transmission path is the data transmission path that initiates the temporary storage request; the pre-read cache is set in the multiple data transmission paths and is located after the shared SRAM along the data transmission direction; the required storage space is the storage space corresponding to the sum of the pending stream data carried by the temporary storage request initiated by the third target data transmission path and the pending stream data read from the shared SRAM in the previous clock cycle.
10. The method according to claim 9, characterized in that, Also includes: In response to the fact that the storage space corresponding to the third target data transmission path is empty and the remaining storage space of the pre-read cache is not less than the required storage space, the pending stream data carried by the temporary storage request initiated by the third target data transmission path is stored in the pre-read cache through a preset bypass, so that the pre-read cache can transmit the pending stream data to the set location for aggregation processing through the third target data transmission path.
11. A streaming data processing apparatus, characterized in that, An application to a graphics processing unit (GPU) includes multiple data transmission paths and a shared static random access memory (SRAM) disposed within the multiple data transmission paths, each data transmission path having its own dedicated data storage space within the shared SRAM; the device includes: The pending stream data storage unit is configured to store the pending stream data transmitted by the data transmission path that initiates the temporary storage request in the corresponding data storage space in the shared SRAM. The target pending stream data determination unit is configured to determine the target pending stream data corresponding to the current clock cycle from the pending stream data stored in the shared SRAM according to a preset stream data transmission rule; The output unit is configured to output the target stream data to be processed to the first target data transmission path, so that it can be transmitted by the first target data transmission path to a set location for convergence processing.
12. An electronic device, characterized in that, include: At least one processor; wherein the at least one processor includes a graphics processor; A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which are executed by the graphics processor to enable the graphics processor to perform the streaming data processing method according to any one of claims 1-10.
13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause a computer including a graphics processor to perform the streaming data processing method according to any one of claims 1-10.
14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a graphics processor, it implements the steps of the streaming data processing method according to any one of claims 1-10.