FDIA detection method and system based on chain tensor decomposition, terminal and storage medium

Abstract

The invention relates to the technical field of computers, and discloses an FDIA detection method and system based on chain tensor decomposition, a terminal and a storage medium, and the method comprises the steps: combining embedding compression based on tensor training with a deep recommendation model, and compressing high-dimensional embedding into a low-rank core to update an original index table into a trainable TT embedding table, an index rearrangement strategy is introduced to optimize the model to obtain a target embedding table so as to enhance data locality and minimize redundant tensor operation, and finally, a prefetching embedding batch is formed according to indexes and embedding configuration to dynamically update the model, so that the FDIA detection cost is reduced. According to the method, the embedded compression based on tensor training is combined with the deep recommendation model, so that the detection accuracy is maintained, the memory occupation and the calculation overhead are remarkably reduced, the system response capability, the resource efficiency and the edge compatibility are improved, and the FDIA detection efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an FDIA detection method, system, terminal, and computer-readable storage medium based on chain tensor decomposition. Background Technology

[0002] False data injection attacks (FDIA) are among the most insidious and destructive cybersecurity threats to smart grids.

[0003] Due to the complexity of cybersecurity data, traditional FDIA detection typically incurs significant computational overhead, resulting in long response times and excessive resource consumption.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The main objective of this invention is to provide an FDIA detection method, system, terminal, and computer-readable storage medium based on chain tensor decomposition, aiming to solve the problems of low detection efficiency, long response time, and high resource costs caused by the large amount of computational overhead required in the existing FDIA detection technology.

[0006] To achieve the above objectives, the present invention provides an FDIA detection method based on chain tensor decomposition, the FDIA detection method based on chain tensor decomposition comprising the following steps: Obtain sparse features and an initial embedding table from the input ensemble model. Perform tensor network decomposition on the multidimensional tensors of the sparse features to obtain the product of multiple low-dimensional tensors. Introduce all the low-dimensional tensors into the initial embedding table for compression to obtain a tensor embedding table. Obtain all the original indices of the sparse feature, convert each original index into multiple tensor indices according to the tensor embedding table, calculate the embedding row of each tensor index for the original index, fuse all the embedding rows to obtain the embedding vector, and use the embedding vector to replace the position corresponding to the original index. Construct a pointer preparation array based on all the low-dimensional tensors, determine the reuse status of each tensor index in the tensor embedding table, and add pointer preparation addresses for multiple tensor indices based on the reuse status and the pointer preparation array, so as to reorder the tensor embedding table and obtain the target embedding table. A prefetch stack is constructed based on the target embedding table and all updated original indexes. The ensemble model is trained using the prefetch stack to obtain the target ensemble model. The target ensemble model is then used for FDIA detection to obtain the detection results.

[0007] This invention combines tensor-based embedding compression with a deep recommendation model, which significantly reduces memory usage and computational overhead while maintaining detection accuracy, thereby improving system responsiveness, resource efficiency, and edge compatibility. Attached Figure Description

[0008] Figure 1 This is a flowchart of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention; Figure 2 This is a framework diagram of Rec-Ad, a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 3 This is a DLRM framework diagram of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 4 This is a schematic diagram of the index mapping of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 5 This is a table lookup diagram of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 6 This is a schematic diagram of index reordering in a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 7 This is a schematic diagram of an indexed bijection of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 8 This is a schematic diagram of a write-read conflict of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 9 This is a schematic diagram illustrating the speed improvement under a single GPU in a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 10 This is a schematic diagram illustrating the speed improvement under multiple GPUs in a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 11 This is a schematic diagram illustrating the change in training throughput of a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 12 This is a schematic diagram illustrating the speed improvement of partial optimization training and pipeline optimization training in a preferred embodiment of the FDIA detection method based on chain tensor decomposition of the present invention. Figure 13 This is a structural diagram of a preferred embodiment of the FDIA detection system based on chain tensor decomposition of the present invention; Figure 14This is a structural diagram of a preferred embodiment of the terminal of the present invention. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0010] For existing FDIA detection problems, hybrid parallel training frameworks based on Rec-Ad (deep learning recommendation model, DLRM) already exist. These systems distribute the embedding table across multiple GPUs (Graphics Processing Units) for parallel training, while simultaneously applying the data in parallel to an MLP (Multilayer Perceptron). However, industrial-scale DLRMs often require dozens of GPUs, resulting in high costs.

[0011] Therefore, this invention proposes an integrated model framework (i.e., the Rec-Ad framework, Tensor Train–Enhanced deep Learning Recommendation for Efficient FDIA detection in SmartGrids, based on chained tensor decomposition for FDIA detection) that integrates tensor training decomposition and DLRM. It improves training efficiency and inference speed through embedding compression, optimizes data access using index rearrangement strategies, and significantly reduces memory communication overhead by adopting a pipelined training mechanism. This enhances edge computing capabilities and scalability, providing strong technical support for FDIA detection, significantly improving computational throughput and real-time detection performance, narrowing the attack window, and increasing attacker costs.

[0012] The preferred embodiment of the FDIA detection method based on chain tensor decomposition described in this invention, such as... Figure 1 As shown, the FDIA detection method based on chain tensor decomposition includes the following steps: Step S10: Obtain the sparse features and initial embedding table in the input ensemble model, perform TT (Tensor Train, a tensor network decomposition method) decomposition on the multidimensional tensor of the sparse features to obtain the product of multiple low-dimensional tensors, and introduce all the low-dimensional tensors into the initial embedding table for compression to obtain the tensor embedding table.

[0013] Among them, such as Figure 2As shown, Rec-Ad employs a multi-level collaborative optimization strategy across the algorithm, input, and system layers to address challenges including model complexity, data sparsity, and distributed training. Here, Effective TT represents the tensor embedding table (or TT embedding table) described in this invention, and TT core represents a low-dimensional tensor.

[0014] like Figure 3 The diagram shows the framework of DLRM, which combines two different types of input: dense features and sparse features. Dense features are first processed by a low-level MLP, which typically encodes dense features such as voltage values ​​in a smart grid. Sparse features consist of categorical variables encoded as binary vectors, typically representing entities such as bus IDs and generator identifiers. The mapping of these sparse vectors to dense features utilizes embedding lookup techniques, retrieving corresponding rows from a pre-trained initial embedding table to achieve a low-dimensional representation of each sparse vector. In the embodiments disclosed in this invention, software-managed embedded caching technology is used to reduce communication latency between the GPU and dRAM (dynamic random access memory), thereby improving the overall training throughput.

[0015] Specifically, sparse features and an initial embedding table are obtained from the input ensemble model, wherein the initial embedding table is used to retrieve the position of the original index of the sparse features; Tensor network decomposition is performed on the multidimensional tensor of the sparse features to obtain the product of multiple low-dimensional tensors: ; in, Represents a multidimensional tensor. , and They represent the 1st and 2nd respectively. k and d One dimension, , and They represent the 1st and 2nd respectively. k and d One hyperparameter, , and They represent the 1st and 2nd respectively. k and d The boundary rank of a low-dimensional tensor. , and They represent the 1st, 2nd and... d A low-dimensional tensor Denotes the boundary rank of the first and second low-dimensional tensors. This represents the boundary rank of the second and third low-dimensional tensors. Indicates the first d -1 and the first d Boundary rank of a low-dimensional tensor.

[0016] In the embodiments disclosed in this invention, the MLP model is first decomposed and compressed using tensor network decomposition. Tensor network decomposition provides a high compression ratio, thereby reducing accuracy loss. For multidimensional tensors with sparse features, tensor network decomposition yields the product of multiple low-dimensional tensors. In this process, the TT rank is introduced as a hyperparameter for each decomposed low-dimensional tensor. Through chain-like low-rank decomposition, the original high-dimensional embedding matrix (i.e., the multidimensional tensor) is decomposed into a set of smaller tensor kernels. This transformation reduces the storage complexity from an exponential relationship with the input dimension to a linear relationship, greatly enhancing scalability. Therefore, TT embeddings can effectively represent the massive embedding tables commonly used in recommendation systems and natural language processing.

[0017] Furthermore, multiple dimensions of the initial embedding table are obtained, and tensor network decomposition is performed on each dimension to obtain a product of multiple corresponding low-dimensional dimensions: ; ; in, M and N Both represent the dimensions of the initial embedded table. , and They respectively represent the following: M The compressed 1st, 2nd and 3rd d A low-dimensional tensor , and They respectively represent the following: N The compressed 1st, 2nd and 3rd d A low-dimensional tensor; Introducing all the aforementioned low-dimensional tensors into the initial embedding table after dimensionality decomposition, we obtain the tensor embedding table: ; Where V represents the tensor embedding table, , and They represent the 1st, 2nd, and 3rd dimensions after dimensionality decomposition, respectively. d Group of low-dimensional tensors, , and They represent the 1st and 2nd respectively. k and d Each dimension.

[0018] In the embodiments disclosed in this invention, such as Figure 4 As shown, the dimension of the initial embedded table is set to... M × N Then, by decomposing using tensor networks, the following are respectively... M and N The decomposition is broken down into a product of multiple low-dimensional tensors, and then the decomposed multidimensional tensor can be created using the initial embedding table after decomposition. ; Through the aforementioned series of reshaping processes, the initial embedding table can be reshaped into a TT embedding table. During model training, this invention directly calculates gradients relative to low-dimensional tensors and facilitates parameter updates in a memory-efficient manner. Furthermore, during inference, the structure of the TT embedding table allows for rapid reconstruction of embedding vectors, thereby increasing the model's degrees of freedom. Widely applicable in various fields, this invention not only reduces memory consumption and improves computational efficiency but also significantly enhances system performance and scalability.

[0019] Step S20: Obtain all original indices of the sparse feature, convert each original index into multiple tensor indices according to the tensor embedding table, calculate the embedding row of each tensor index for the original index, fuse all the embedding rows to obtain the embedding vector, and use the embedding vector to replace the position corresponding to the original index.

[0020] In the process of designing the TT embedding table, there are often repeated intermediate results during forward and backward propagation. Furthermore, embedding lookup and gradient evaluation in the TT format involve complex tensor shrinkage, which can lead to significant computational costs, especially during large-scale training. If these overheads are not mitigated, the overall training duration may increase significantly. Therefore, this invention extracts the reused intermediate results of the TT embedding table during iterative training and proposes an index-aware reordering and sorting strategy to enhance data locality and minimize redundant tensor operations.

[0021] Specifically, all the original indices of the sparse features are obtained, and each original index is converted into multiple corresponding tensor indices according to the tensor embedding table: ; ; in, express The first tensor index, express The second tensor index, mod is the modulo operation. and They respectively represent the following: M and N The compressed number k A low-dimensional tensord Indicates the number of dimensions; For each original index, the embedding rows of the first tensor index and the second tensor index corresponding to the original index are calculated respectively. All the embedding rows are fused to obtain the embedding vector corresponding to each original index.

[0022] In the embodiments disclosed in this invention, such as Figure 5 As shown, Figure 5 In this example, (a) represents the embedded table lookup technique. The input samples in a small batch contain multiple indexes. Taking index Index[1,2] (the index in the initial embedded table) as an example, to obtain Index[1,2], it is first necessary to extract the different rows of Index[1,2] from the initial embedded table. and Construct an embedding vector based on these two lines. Then, the elements are added row by row to different rows. At this point, the elements in the initial embedding table are filled. The indices in the initial embedding table need to be converted to tensor indices in the TT embedding table, such as... Figure 5 As shown in (b) in the figure, this is the technique for querying the TT table.

[0023] In the embodiments disclosed in this invention, it is assumed that the original index is The size of the embedded table is M × N This allows us to obtain the index of each tensor from the original index; for example, based on... Figure 5 In (b), it is assumed that M =2×2×2, the original index is [1,0], then the corresponding two tensor indices are: ; .

[0024] As can be seen, since the two tensor indices share values ​​in the first two dimensions, these two low-dimensional tensors are defined as the same TT slice. After retrieving the same slices for all tensor indices, the TT slice multiplication step is performed, for example: ; Where Slice[0,1] represents the 0th TT slice from the 1st low-dimensional tensor, and finally through... and Aggregate the embedding rows to obtain the final embedding vector. .

[0025] Further, for each original index, multiple TT slices for each embedded row are calculated, and all duplicate TT slices are extracted; all TT slices are fused to obtain an initial embedding vector corresponding to each original index; duplicate TT slices in the initial embedding vector are deleted to obtain an embedding vector corresponding to each original index.

[0026] Among them, due to and Since the two tensor indices share the same first two TT slices, the TT slices "Slice[0,0]=Slice[1,0]" and "Slice[0,1]=Slice[1,1]" can be replaced to obtain the final result. Simplified formula: ; That is, in In this case, the TT slice multiplication was reduced from 4 to 2.

[0027] Furthermore, in another embodiment of the present invention, consider a representation using three low-dimensional tensors. M × N A dimensional TT embedding table, for each input sample, is... k It consists of several indexes; in addition, let the average size of the transformed embedded table T in each dimension be ( m × n ), and let its average TT rank be R9 (to M Defined as , N Then it is represented as In this case, the computational complexity required to retrieve the tensor index associated with the TT embedding table is... It can be represented as: ; The computational complexity of retrieving samples from the TT embedding table is... Then it is: ; Since R is much larger than n, The substance is far greater than Ideally, if all tensor indices in the sample show partial equality in a given dimension, intermediate results from each embedding row can be recovered, resulting in a computational complexity of O(n log n). Therefore, utilizing intermediate results at the sample level can significantly reduce the computational complexity required to find the TT embedding table. These techniques leverage the inherent structural patterns in the input data and tensor decomposition layout to optimize memory access and improve computational throughput. By aligning data access patterns with the low-dimensional tensor kernel structure, lookup latency and gradient backpropagation overhead are greatly reduced.

[0028] Step S30: Construct a pointer preparation array based on all the low-dimensional tensors, determine the reuse status of each tensor index in the tensor embedding table, and add pointer preparation addresses to multiple tensor indexes based on the reuse status and the pointer preparation array to reorder the TT embedding table and obtain the target embedding table.

[0029] In order to better identify reusable intermediate results in the TT embedding table, this invention discloses a reuse buffer for storing intermediate products of low-dimensional tensors, which can effectively avoid computational redundancy in the forward and backward propagation processes.

[0030] Specifically, the product of each pair of low-dimensional tensors is calculated, a pointer preparation list is constructed based on each product and each pair of low-dimensional tensor products, and a pointer preparation array is constructed based on all the pointer preparation lists; it is determined whether each tensor index in the tensor embedding table is calculated and stored in different threads; if not, the address of the pointer list corresponding to the low-dimensional tensor in the tensor index is assigned to the tensor index, and the pointer list address is stored in a buffer until all tensor indices in the tensor embedding table have been stored in the buffer; the access frequency of each TT retrieval in all the threads is counted, and each TT retrieval is reordered according to the access frequency to obtain the target embedding table.

[0031] In one of the embodiments disclosed in this invention, a parallel pointer preparation kernel is proposed to perform batch GEMM (General Matrix-Matrix Multiplication) operations on necessary computational steps, which is beneficial for performing evidence multiplication simultaneously and merging it into a single thread computation process.

[0032] The list of pointers to the batch GEMM kernel consists of two low-dimensional tensors ( Pt_a and Pt_b ) and their product ( Pt_c This process can be constructed using the following algorithm 1: Algorithm 1: TT decomposition; Data preprocessing: Dense feature minima normalization.

[0033] input: . output: . Set auxiliary variables.

[0034]

[0035] for each do in parallel Find the buffer index of the row.

[0036] ; Verify the availability of the buffer at the Bufe index.

[0037] if then Update the buffer length.

[0038] ; ; ; ; ; ; end end".

[0039] According to Algorithm 1, the length of the low-dimensional tensor (length is 3) is calculated in the third line, and the reuse index is derived by dividing the index by a constant (this process is the number system conversion). This reuse index is used as the address for searching in the reuse buffer. Then, in each thread, it is checked whether the reuse index can skip redundant calculations (i.e., line 4 in Algorithm 1) until all reuse indices have been checked and recorded in a boolean array. If the boolean array is 1, it indicates that the intermediate result has been cached in the reuse buffer by other threads; otherwise, a pointer needs to be allocated to prepare the address. Pt_a , Pt_b and Pt_c To further perform GEMM calculations, once all pointers are ready, the batch GEMM kernel is invoked, using an array. Pt_a , Pt_b and Pt_c The intermediate results of the first two low-dimensional tensors are computed and stored in a reuse buffer. The specific process is as follows: Figure 6 As shown.

[0040] in, Figure 6This demonstrates the process of creating an indexed bijection, which involves counting the connections between points to obtain new connections and form new communities. Because the order of the input data has no impact on the result, representing it using a graph structure better illustrates the relationships between the input data, thereby improving the efficiency of data rearrangement and increasing the opportunities for data reuse.

[0041] Furthermore, during tensor network decomposition, high adjacency between multiple indices within a batch implies the existence of more similar tensor indices, leading to significant data overlap. Therefore, reusing intermediate results can improve data reuse, enhancing spatial locality of GPU memory access and increasing cache hit rate. However, without index reordering (such as...), Figure 7 As shown in (a) in the figure, the lookup process based on the TT embedding table will have the problem of poor data locality, which will reduce the training performance.

[0042] To address the problem of poor data locality, this invention proposes physically reordering the data layout for each batch (the result is as follows). Figure 7 As shown in (b) of this paper, this improves the locality of access within a batch. It should be noted that this invention does not reorder each row, but rather reorders the index. In the embodiments disclosed in this invention, each batch is represented as a set of indexes, defined as: ; Each index i After the bijective function ( After mapping, a unique identifier will be obtained, so the above index can be converted into the following definition: ; Performing this step before the embedding lookup can effectively improve data locality within each batch, thereby increasing the likelihood of reusing intermediate results and improving the computational efficiency of the TT embedding table.

[0043] In the embodiments disclosed in this invention, index rearrangement can be achieved using the following algorithm 2: "Algorithm 2: Index graph generator for training."

[0044] Input:

[0045] output:

[0046] Determine the threshold for thermal embedding.

[0047] ; Repeat each batch.

[0048] for each Batch in Batch_list do Global information: Index is obtained based on frequency.

[0049] ; Save the index of Hot embeddings.

[0050] ; Generate edges for the Batch in the local information.

[0051] ; Add to the edge list. ; end".

[0052] Step S40: Construct a prefetch stack based on the target embedding table and all updated original indexes, train the ensemble model using the prefetch stack to obtain the target ensemble model, and perform FDIA detection using the target ensemble model to obtain the detection result.

[0053] Based on tensor network decomposition, this invention proposes a hierarchical storage system that utilizes host memory expansion to enhance the scalability of Rec-Ad. When the TT embedding table is too large to accommodate the available high bandwidth GPU memory, the above method can effectively solve this problem.

[0054] Furthermore, this hierarchical storage system puts significant communication pressure on the GPU-CPU interface, leading to a decrease in training performance. Therefore, this invention proposes a pipelined training method based on tensor network decomposition to alleviate the communication latency problem.

[0055] Specifically, a prefetch stack is constructed based on the target embedding table and all updated original indexes, and the prefetch stack is input into the ensemble model. The ensemble model performs index lookup based on the prefetch stack. If a tensor index is not hit, the tensor index is synchronized with the embedding vector to update the target embedding table in real time. The ensemble model is trained based on the current target embedding table to obtain a target ensemble model. The current target embedding table is sent to the cache for reallocation, and multiple load parameters are defined using the current target embedding table and all updated original indexes. When a load parameter is 0, the corresponding tensor index and original index are deleted from the cache. Multiple target datasets are acquired, and the target ensemble model is used to perform FDIA detection on all target datasets to obtain detection results.

[0056] In the embodiments disclosed in this invention, after obtaining the reordered TT embedding table (i.e., the target embedding table) and the updated original index table, the target embedding table is synchronized from the host memory to cache the gradients for forward and backward propagation of the target embedding table. Before updating the low-dimensional tensor in each round, the gradients are synchronized between different devices through the ALLReduce operation (the core collective communication operation in distributed deep learning), thereby strengthening the gradient consistency between distributed training devices, minimizing redundant computation, and improving training efficiency.

[0057] In cases where the GPU's HBM (Graphics Processing Unit High Bandwidth Memory) cannot accommodate all embedding parameters, excess parameters are retained in the host device's memory. In this scenario, the CPU acts as a parameter server, adding host memory values ​​to the prefetch stacks of multiple GPUs to schedule the extraction of the next batch of embedding parameters. The GPU, acting as a computational worker, processes the target embedding table in a round-trip manner. It first collects embedding data from the target embedding table and the prefetch stack to construct the input representation for the next batch. Then, it uses data-parallel training to update the embeddings, reducing the gradients of the target embedding table through forward and backward propagation. The cache is populated before modifying the parameters of the target embedding table to ensure consistency. The server retrieves the gradients and updates the embedding parameters in the host memory, then transfers the gradients to the history queue for reuse and analysis.

[0058] Furthermore, this invention is based on a hierarchical memory architecture and uses pipelined execution technology for deep learning training. Embedded parameters are stored on the CPU, while the forward and backward MLP computations are performed on the GPU. Simultaneously, a write-after-read conflict optimization strategy is introduced into this pipelined operation: such as... Figure 8 As shown in (a) (where Pre-retrieve represents pre-retrieve, Forward & backward represent forward and backward propagation, and Update represents update), in this process, when the MLP on the GPU processes the i-th batch of samples, the i-th batch of samples is... The embedding parameters of the batch of samples are extracted in advance.

[0059] Since the gradient update operation has not yet been completed for the i-th batch, it is used for the i-th batch. The batch embedding parameters may contain values ​​that have not yet been refreshed (i.e., old values ​​exist), which can lead to a RAW (Rapid Rendering) vulnerability. To further address this issue, this invention discloses an adaptive filling strategy for cache synchronization: such as... Figure 8As shown in (b), a prefetch stack is constructed based on the target embedding table and all updated original indexes, forming a prefetch embedding batch. Further, upon receiving the prefetch stack, the GPU can perform an index lookup in the embedding cache. If a hit occurs, it indicates that the index being looked up is cached, meaning that the index can be reused; if the embedding has already been used in previous rounds, it can be synchronized with the L2 cache (represented as...). This ensures the consistency of the embedding table. After embedding synchronization, all embedding tables contain the latest embeddings, which can then be used for training. During training, this invention introduces a lifecycle control mechanism to reduce the memory footprint of the integrated cache. After training is complete, the used embeddings are moved to the cache for storage and marked for reallocation. Simultaneously, a load capacity parameter defines the maximum length of the request queue (including the gradient queue and the prefetch stack queue). Once the load capacity parameter reaches 0, the corresponding embedding is removed from the GPU's cache. This dynamic cache management strategy ensures efficient GPU memory operation and reduces synchronization overhead in high-throughput pipeline training environments.

[0060] In this invention, the results of write-after-read conflicts in different frameworks were compared, as shown in Table 1 below. The first framework is DLRM, the second framework is FAE (a front-end automated testing framework), and the third framework is TT-Rec (TALLRec: An Effective and Efficient Tuning Framework to Align Large Language Model with Recommendation). Rec-Ad is the Rec-Ad framework disclosed in this invention.

[0061] Table 1: Comparison of different frameworks

[0062] Table 1 clearly shows that Rec-Ad uses host memory to expand memory capacity and implements a three-stage pipeline to reduce CPU-GPU communication, thereby achieving real-time FDIA detection and mitigating write-after-read conflicts through a lightweight caching mechanism.

[0063] Furthermore, in the embodiments disclosed in this invention, the proposed Rec-Ad framework is validated using four commonly used datasets. These datasets include IEEE118-Bus (the first dataset, IEEE 118-Bus System, commonly used in power system teaching and research), Avazu (the second dataset, Avazu Click-Through Rate dataset, used for predicting click-through rates for mobile ads), CriteoTB (the third dataset), and CriteoKaggle (the fourth dataset) (CriteoTB and CriteoKaggle are both classic datasets in the field of click-through rate prediction). Detailed data for these four datasets is shown in Table 2 below. Table 2: Dataset Evaluation Table

[0064] Furthermore, when performing FDIA inspection tasks, model performance is mainly evaluated through three metrics: accuracy, recall, and F1 score (the core metric for evaluating the performance of binary classification models). Accuracy measures the overall accuracy of the model's predictions and is defined by the proportion of correctly classified samples out of all samples. Recall emphasizes the ability to detect attack samples and is defined as the proportion of correctly identified real attacks. The F1 score balances the conflicting relationship between accuracy and recall through the harmonic mean, comprehensively reflecting the model's classification ability.

[0065] In FDIA detection, a higher F1 score means the model can accurately detect attacks while maintaining a low false alarm rate, thus ensuring robust protection in complex power system environments. Therefore, this invention normalizes the training time of the baseline DLRM model to 1.0 and obtains the results shown in Table 3 below: Table 3: Comparison of IEEE 118 bus FDIA detection training time and detection performance ‌

[0066] To demonstrate the advantages of the proposed Rec-Ad model (ensemble model) in various scenarios, two evaluation environments were created in this experiment: (1) DLRM training on a single GPU or GPU resources; (2) DLRM training on multiple GPUs. To simulate resource-constrained scenarios, experiments were conducted using a single GPU on each platform. DLRM and FAE stored the embedding table parameters in host memory, while TT-Rec and Rec-Ad directly stored the compressed embeddings in the GPU HBM. A batch size of 4096 was used on both Tesla V100 GPU (a data center-grade GPU based on the Volta architecture) and Tesla T4 GPU (a data center-grade GPU based on the Turing architecture). The TT embedding dimension was set to 128 for Tesla V100 GPU and 64 for Tesla T4 GPU. Figure 9 and Figure 10 As shown (where Figure 9 This indicates a comparison on the Tesla V100 GPU. Figure 10 The comparison is shown on a Tesla T4 GPU (where Terabyte is a common unit of data storage; the Kaggle dataset contains data of various types and domains). It can be seen that Rec-Ad consistently achieves the best overall performance across all systems and datasets: on the Tesla V100, Rec-Ad achieves an average speed 3 times faster than DLRM; and because each parameter is stored on a single GPU and the target embedding table occupies very little memory, the communication overhead between the CPU and GPU is greatly reduced; compared to FAE, Rec-Ad is 1.5 times faster. Although FAE stores frequently accessed embeddings on the GPU, 25% of batch processing still requires CPU access and embedding computation, limiting FAE's performance ceiling; furthermore, Rec-Ad outperforms TTRec by an average of 1.4 times, optimizing and reducing the computational cost of TT embedding lookup and backpropagation, thus resulting in better throughput during training.

[0067] In another embodiment of this invention, to improve the scalability of Rec-Ad, this invention utilizes Rec-Ad and DLRM on the AWSp3.8xlarge platform (a high-performance computing platform) to achieve training throughput using 1 GPU and 4 GPUs, respectively. Figure 11As shown, RecAd (4 GPUs) has a training throughput 1.4 times higher than DLRM (4 GPUs). This is mainly because the target embedding table has a more compact memory footprint, supporting data-parallel embedding training across all GPUs, achieving efficient synchronization and parameter assignment. In contrast, DLRM distributes the embedding table across GPUs in a model-parallel manner, requiring frequent peer-to-peer communication between devices. As the number of GPUs increases, this overhead limits scalability and efficiency. In a 1-GPU setup, DLRM slightly outperforms Rec-Ad in terms of raw throughput, but introduces additional computational overhead, as shown in Table 4. Table 4: Comparison of Table Encapsulation and Embedding

[0068] Furthermore, to demonstrate the advantages of the TT-based pipelined training of this invention, in one embodiment, the maximum embedding table is compressed and stored in the target embedding table in the GPU HBM, and the remaining embeddings are stored in host memory; to isolate the effects of pipelined training, the length of the prefetch queue is set to 1, thereby disabling pipelined training, and the performance is compared with sequential training and other baselines, with specific results as follows: Figure 12 As shown, Rec-Ad (pipelined) achieves a 2.44x speedup compared to DLRM, outperforming DLRM in overlapping parameter updates, embedding lookups on GPUs, and MLP training on CPUs. The use of prefetching and gradient queues significantly reduces CPU-GPU communication overhead. Furthermore, Rec-Ad (pipelined) outperforms Rec-Ad (sequential) by an average of 1.30x. When the prefetch queue length in Rec-Ad (sequential) is set to 1, the pipeline degenerates into pure sequential execution. In this case, the GPU worker must wait for the CPU to complete parameter updates before accessing the next batch. Therefore, the pipelined training mode significantly improves model computational efficiency, enabling more resilient FDIA detection in various smart grid scenarios.

[0069] Furthermore, in another embodiment of the present invention, a 100MB-scale FDIA detection environment was constructed based on the IEEE 118 bus system. The performance of DLRM and the integrated model in this invention was compared with that of the present invention when the batch size was 1. The specific results are shown in Table 5 below: Table 5: Performance Comparison of DLRM and Rec-Ad on a 100 MB Dataset

[0070] As can be seen, the ensemble model outperforms the baseline DLRM model in several key metrics. With the same batch size, Rec-Ad, utilizing Tensor Train-based embedding compression and pipelined architecture, reduces inference latency from 25ms (DLRM) to 21.5ms, achieving a 14% latency reduction and significantly improving responsiveness and real-time performance. Correspondingly, throughput also increases from 40 samples per second to 46.5 samples per second, a 16% improvement, better supporting high-frequency sampling scenarios.

[0071] In terms of resource consumption, Rec-Ad also demonstrates high efficiency. Due to its parameter compression mechanism, runtime memory usage is reduced from 320MB to approximately 210MB, alleviating resource load by over 34%. Furthermore, the deployment size of the integrated model is reduced from 180MB to 95MB, making it particularly suitable for deployment on embedded edge terminals or resource-constrained industrial nodes, such as substation smart terminals and edge servers. When continuously processing 100MB of real-time data, the DLRM model takes approximately 3.47 hours to complete the detection task, while Rec-Ad reduces the total processing time to 3.0 hours, saving nearly 0.5 hours in the detection cycle, significantly improving efficiency in daily batch processing and rolling prediction tasks.

[0072] This invention combines tensor-based embedding compression with a deep recommendation model, which significantly reduces memory usage and computational overhead while maintaining detection accuracy, thereby improving system responsiveness, resource efficiency, and edge compatibility.

[0073] Furthermore, such as Figure 13 As shown, based on the above-described FDIA detection method based on chain tensor decomposition, the present invention also provides an FDIA detection system based on chain tensor decomposition, wherein the FDIA detection system based on chain tensor decomposition includes: Tensor decomposition module 51 is used to obtain sparse features and initial embedding table in the input ensemble model, perform tensor network decomposition on the multidimensional tensor of the sparse features to obtain the product of multiple low-dimensional tensors, and introduce all the low-dimensional tensors into the initial embedding table for compression to obtain tensor embedding table. The data reuse module 52 is used to obtain all the original indices of the sparse feature, convert each original index into multiple tensor indices according to the tensor embedding table, calculate the embedding row of each tensor index for the original index, fuse all the embedding rows to obtain the embedding vector, and use the embedding vector to replace the position corresponding to the original index. The index reordering module 53 is used to construct a pointer preparation array based on all the low-dimensional tensors, determine the reuse status of each tensor index in the tensor embedding table, and add pointer preparation addresses to multiple tensor indexes based on the reuse status and the pointer preparation array, so as to reorder the tensor embedding table and obtain the target embedding table. The model training module 54 is used to construct a prefetch stack based on the target embedding table and all updated original indexes, train the ensemble model using the prefetch stack to obtain the target ensemble model, and perform FDIA detection using the target ensemble model to obtain the detection result.

[0074] Furthermore, such as Figure 14 As shown, based on the above-mentioned FDIA detection method and system based on chain tensor decomposition, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 14 Only some of the terminal components are shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0075] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory. In other embodiments, the memory 20 may be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Further, the memory 20 may include both internal and external storage units. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code installed on the terminal. The memory 20 can also be used to temporarily store data that has been output or will be output. In one embodiment, the memory 20 stores an FDIA detection program 40 based on chain tensor decomposition, which can be executed by the processor 10 to implement the FDIA detection method based on chain tensor decomposition in this application.

[0076] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run program code stored in the memory 20 or process data, such as executing the FDIA detection method based on chain tensor decomposition.

[0077] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-screen liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display 30 is used to display information on the terminal and to display a visual user interface. The components of the terminal communicate with each other via a system bus.

[0078] In one embodiment, when the processor 10 executes the FDIA detection program 40 based on chain tensor decomposition in the memory 20, it implements the steps of the FDIA detection method based on chain tensor decomposition as described above.

[0079] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores an FDIA detection program based on chained tensor decomposition, and the FDIA detection program based on chained tensor decomposition implements the steps of the FDIA detection method based on chained tensor decomposition as described above when executed by a processor.

[0080] In summary, this invention provides an FDIA detection method and related equipment based on chained tensor decomposition. The method includes: acquiring sparse features and an initial embedding table from an input ensemble model; performing tensor network decomposition on the multidimensional tensors of the sparse features to obtain the product of multiple low-dimensional tensors; and introducing all the low-dimensional tensors into the initial embedding table for compression to obtain a TT embedding table; acquiring all the original indices of the sparse features; converting each original index into multiple tensor indices according to the TT embedding table; calculating the embedding row for each tensor index; and fusing all the embedding rows to obtain an embedding vector. The embedding vector is used to replace the position corresponding to the original index; a pointer preparation array is constructed based on all the low-dimensional tensors; the reuse status of each tensor index in the TT embedding table is determined; and pointer preparation addresses are added to multiple tensor indices based on the reuse status and the pointer preparation array to reorder the TT embedding table and obtain the target embedding table; a prefetch stack is constructed based on the target embedding table and all the updated original indexes; the ensemble model is trained using the prefetch stack to obtain the target ensemble model; and the target ensemble model is used for FDIA detection to obtain the detection result. This invention combines tensor-based embedding compression with a deep recommendation model, which significantly reduces memory usage and computational overhead while maintaining detection accuracy, and improves system responsiveness, resource efficiency, and edge compatibility.

[0081] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal that includes that element.

[0082] Of course, those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware (such as a processor, controller, etc.). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The computer-readable storage medium can be a memory, magnetic disk, optical disk, etc.

[0083] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for detecting FDIA based on chain tensor decomposition, characterized in that... The FDIA detection method based on chain tensor decomposition includes: Obtain sparse features and an initial embedding table from the input ensemble model. Perform tensor network decomposition on the multidimensional tensors of the sparse features to obtain the product of multiple low-dimensional tensors. Introduce all the low-dimensional tensors into the initial embedding table for compression to obtain a tensor embedding table. Obtain all the original indices of the sparse feature, convert each original index into multiple tensor indices according to the tensor embedding table, calculate the embedding row of each tensor index for the original index, fuse all the embedding rows to obtain the embedding vector, and use the embedding vector to replace the position corresponding to the original index. Construct a pointer preparation array based on all the low-dimensional tensors, determine the reuse status of each tensor index in the tensor embedding table, and add pointer preparation addresses for multiple tensor indices based on the reuse status and the pointer preparation array, so as to reorder the tensor embedding table and obtain the target embedding table. A prefetch stack is constructed based on the target embedding table and all updated original indexes. The ensemble model is trained using the prefetch stack to obtain the target ensemble model. The target ensemble model is then used for FDIA detection to obtain the detection results.

2. The FDIA detection method based on chain tensor decomposition according to claim 1, characterized in that... The process of obtaining sparse features and an initial embedding table from the input ensemble model, and performing tensor network decomposition on the multidimensional tensors of the sparse features to obtain the product of multiple low-dimensional tensors, specifically includes: Obtain sparse features and an initial embedding table from the input ensemble model, wherein the initial embedding table is used to retrieve the position of the original index of the sparse features; Tensor network decomposition is performed on the multidimensional tensor of the sparse features to obtain the product of multiple low-dimensional tensors: ； in, Represents a multidimensional tensor. , and They represent the 1st and 2nd respectively. k and d One dimension, , and They represent the 1st and 2nd respectively. k and d One hyperparameter, , and They represent the 1st and 2nd respectively. k and d The boundary rank of a low-dimensional tensor. , and They represent the 1st, 2nd and... d A low-dimensional tensor Denotes the boundary rank of the first and second low-dimensional tensors. This represents the boundary rank of the second and third low-dimensional tensors. Indicates the first d -1 and the first d Boundary rank of a low-dimensional tensor.

3. The FDIA detection method based on chain tensor decomposition according to claim 2, characterized in that... The step of compressing all the low-dimensional tensors into the initial embedding table to obtain a tensor embedding table specifically includes: Obtain multiple dimensions of the initial embedding table, and perform tensor network decomposition on each dimension to obtain the corresponding product of multiple low-dimensional dimensions: ； ； in, M and N Both represent the dimensions of the initial embedded table. , and They respectively represent the following: M The compressed 1st, 2nd and 3rd d A low-dimensional tensor , and They respectively represent the following: N The compressed 1st, 2nd and 3rd d A low-dimensional tensor; Introducing all the aforementioned low-dimensional tensors into the initial embedding table after dimensionality decomposition, we obtain the tensor embedding table: ； Where V represents the tensor embedding table, , and They represent the 1st, 2nd, and 3rd dimensions after dimensionality decomposition, respectively. d Group of low-dimensional tensors, , and They represent the 1st and 2nd respectively. k and d Each dimension.

4. The FDIA detection method based on chain tensor decomposition according to claim 1, characterized in that... The process of obtaining all original indices of the sparse feature, converting each original index into multiple tensor indices according to the tensor embedding table, calculating the embedding row for each tensor index, and fusing all the embedding rows to obtain the embedding vector specifically includes: Obtain all the original indices of the sparse feature, and convert each original index into multiple corresponding tensor indices according to the tensor embedding table: ； ； in, express The first tensor index, express The second tensor index, mod is the modulo operation. and They respectively represent the following: M and N The compressed number k A low-dimensional tensor d Indicates the number of dimensions; For each original index, the embedding rows of the first tensor index and the second tensor index corresponding to the original index are calculated respectively. All the embedding rows are fused to obtain the embedding vector corresponding to each original index.

5. The FDIA detection method based on chain tensor decomposition according to claim 4, characterized in that... The step of fusing all the embedded rows to obtain the embedded vector corresponding to each original index specifically includes: For each of the original indexes, calculate multiple TT slices for each of the embedded rows, and extract all duplicate TT slices; All the TT slices are fused to obtain the initial embedding vector corresponding to each original index; The duplicate TT slice combinations in the initial embedding vector are deleted to obtain the embedding vector corresponding to each original index.

6. The FDIA detection method based on chain tensor decomposition according to claim 2, characterized in that... The step of constructing a pointer preparation array based on all the low-dimensional tensors, determining the reuse status of each tensor index in the tensor embedding table, and adding pointer preparation addresses for multiple tensor indices based on the reuse status and the pointer preparation array to reorder the tensor embedding table and obtain the target embedding table specifically includes: Calculate the product of each pair of the low-dimensional tensors, construct a pointer preparation list based on each product and each pair of the low-dimensional tensors, and construct a pointer preparation array based on all the pointer preparation lists; Determine whether each tensor index in the tensor embedding table is calculated and stored in a different thread. If not, assign the pointer list address corresponding to the low-dimensional tensor in the tensor index to the tensor index and store the pointer list address in the buffer until all tensor indexes in the tensor embedding table have been stored in the buffer. The access frequency of each TT retrieval in all the threads is counted, and each TT retrieval is reordered according to the access frequency to obtain the target embedding table.

7. The FDIA detection method based on chain tensor decomposition according to claim 1, characterized in that... The process of constructing a prefetch stack based on the target embedding table and all updated original indexes, training the ensemble model using the prefetch stack to obtain a target ensemble model, and performing FDIA detection using the target ensemble model to obtain detection results specifically includes: A prefetch stack is constructed based on the target embedding table and all updated original indexes, and the prefetch stack is input into the ensemble model; The ensemble model performs index lookup based on the prefetch stack. If a tensor index is not hit, the tensor index is synchronized with the embedding vector to update the target embedding table in real time. The target ensemble model is obtained by training the ensemble model based on the current target embedding table; The current target embedding table is sent to the cache for reallocation, and multiple load parameters are defined using the current target embedding table and all updated original indexes. When a load parameter is 0, the corresponding tensor index and original index are deleted from the cache. Multiple target datasets are acquired, and the target ensemble model is used to perform FDIA detection on all the target datasets to obtain the detection results.

8. An FDIA detection system based on chain tensor decomposition, characterized in that... The FDIA detection system based on chain tensor decomposition is used to implement the FDIA detection method based on chain tensor decomposition as described in any one of claims 1-7, including: The tensor decomposition module is used to obtain sparse features and an initial embedding table in the input ensemble model, perform tensor network decomposition on the multidimensional tensors of the sparse features to obtain the product of multiple low-dimensional tensors, and introduce all the low-dimensional tensors into the initial embedding table for compression to obtain a tensor embedding table. The data reuse module is used to obtain all the original indices of the sparse feature, convert each original index into multiple tensor indices according to the tensor embedding table, calculate the embedding row of each tensor index for the original index, fuse all the embedding rows to obtain the embedding vector, and use the embedding vector to replace the position corresponding to the original index. The index reordering module is used to construct a pointer preparation array based on all the low-dimensional tensors, determine the reuse status of each tensor index in the tensor embedding table, and add pointer preparation addresses to multiple tensor indexes based on the reuse status and the pointer preparation array, so as to reorder the tensor embedding table and obtain the target embedding table. The model training module is used to construct a prefetch stack based on the target embedding table and all updated original indexes, train the ensemble model using the prefetch stack to obtain the target ensemble model, and perform FDIA detection using the target ensemble model to obtain the detection result.

9. A terminal, characterized in that... The terminal includes: a memory, a processor, and an FDIA detection program based on chain tensor decomposition stored in the memory and executable on the processor. When the FDIA detection program based on chain tensor decomposition is executed by the processor, it implements the steps of the FDIA detection method based on chain tensor decomposition as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that... The computer-readable storage medium stores an FDIA detection program based on chained tensor decomposition, which, when executed by a processor, implements the steps of the FDIA detection method based on chained tensor decomposition as described in any one of claims 1-7.

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