Tape driver, tape unit and storage system

Abstract

The invention relates to the technical field of magnetic tape units, in particular to a magnetic tape driver, a magnetic tape unit and a storage system.The magnetic tape driver comprises a read head, an analog equalization circuit and a digital processing chip; the read head is coupled with the analog equalization circuit, the analog equalization circuit is coupled with the digital processing chip, and the analog equalization circuit comprises an active filter; wherein the read head is used for reading an original analog signal from a magnetic tape of a magnetic tape unit and outputting the original analog signal to the analog equalization circuit; the analog equalization circuit is used for performing data equalization on the original analog signal through an active filter to obtain a first analog signal and outputting the first analog signal to the digital processing chip; the frequency response curve of the first analog signal is closer to the frequency response curve of a target signal type than the frequency response curve of the original analog signal, and the target signal type comprises partial response signals; and the digital processing chip is used for converting the analog signal into a digital signal and processing the digital signal. According to the embodiment of the invention, the order of the digital filter in the magnetic tape unit can be reduced.

Description

[0001] This application claims priority to the Chinese Patent Application No. 202411336854.7, filed on September 24, 2024, and entitled "A Magnetic Tape Drive, A Magnetic Tape Machine and a Storage System", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of magnetic tape machines, and in particular to a magnetic tape drive, a magnetic tape machine and a storage system. BACKGROUND

[0003] A magnetic tape machine is a technology based on magnetic tape medium storage. A write head can write a magnetic signal on a magnetic tape, and a read head can read the magnetic signal stored in the magnetic tape back. The magnetic signal data is processed and restored to realize the read-write storage of data. Since the magnetic signal read back from the magnetic tape by the read head is an analog signal, and the data transmission rate is very high, an Inter-Symbol Interference (ISI) effect will occur, resulting in data frequency response with inter-symbol interference from symbol crosstalk, which cannot be directly applied to data analysis. Therefore, data equalization needs to be performed on the read-back signal of the read head of the magnetic tape machine to cope with the influence of the ISI effect, prevent data distortion, and correctly analyze the data.

[0004] However, the current data equalization scheme for the magnetic tape machine needs to design a complex digital processing chip to complete it, and requires a digital filter (such as a FIR filter) in the chip to have a high order, so the demand for the computing power of the chip is high, resulting in a large difficulty in chip implementation, which is not conducive to design and production use. Therefore, how to provide a scheme that can reduce the order of the digital filter in the magnetic tape machine is an urgent problem to be solved. SUMMARY

[0005] The embodiments of the present application provide a magnetic tape drive, a magnetic tape machine and a storage system, which can reduce the order of the digital filter in the magnetic tape machine.

[0006] The present application will be described from different aspects below. It should be understood that the embodiments and advantages of the different aspects below can be mutually referred to.

[0007] In a first aspect, the present application provides a magnetic tape drive which can be applied to a magnetic tape machine, the magnetic tape drive comprising a read head, an analog equalization circuit and a digital processing chip; the read head is coupled with the analog equalization circuit, the analog equalization circuit is coupled with the digital processing chip, and the analog equalization circuit comprises one or more active filters; wherein,

[0008] The read head is configured to read an original analog signal from a magnetic tape of the magnetic tape machine and output the original analog signal to the analog equalization circuit.

[0009] The analog equalization circuit is configured to perform data equalization on the original analog signal through the one or more active filters to obtain a first analog signal and output the first analog signal to the digital processing chip; the first analog signal has a frequency response curve closer to a frequency response curve of a target signal type than a frequency response curve of the original analog signal, and the target signal type includes a partial response signal.

[0010] The digital processing chip is configured to convert the analog signal output by the analog equalization circuit into a digital signal and perform digital signal processing.

[0011] In the embodiment, the analog equalization circuit is arranged between the read head and the digital processing chip. Before the analog signal is input to the digital processing chip for digital processing, the analog equalization circuit can perform data equalization on the analog signal, convert the channel frequency response of the analog signal into a channel frequency response close to the frequency response of the target signal type, that is, perform data equalization in the analog front end in advance, thereby reducing the order of the digital filter required by the back-end digital processing, reducing the algorithm requirement of the digital processing chip of the tape drive, reducing the cost and difficulty of product implementation, and improving the data convergence speed, thereby improving the processing efficiency.

[0012] In addition, the amplitude of the original signal read from the magnetic tape by the read head is too small, and the signal needs to be amplified before being input to the analog-to-digital converter (ADC) of the digital processing chip. The active filter in the analog equalization circuit has a certain signal amplification function based on the structure design of the operational amplifier and the resistance-capacitance, and when the signal amplification effect can meet the demand of the ADC signal acquisition, an additional amplification circuit can be omitted to reduce the circuit overhead.

[0013] In a possible implementation, the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal specifically in that:

[0014] The FIR order required for converting the frequency response curve of the first analog signal into the frequency response curve of the target signal type is FIR1, the FIR order required for converting the frequency response curve of the original analog signal into the frequency response curve of the target signal type is FIR2, and FIR1 is less than FIR2.

[0015] In a possible implementation, the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal specifically in that:

[0016] The difference between the amplitude of the frequency response curve corresponding to the first analog signal and the amplitude of the frequency response curve corresponding to the target signal type is less than the difference between the amplitude of the frequency response curve corresponding to the original analog signal and the amplitude of the frequency response curve corresponding to the target signal type at the same frequency; or

[0017] The difference between the frequency of the frequency response curve corresponding to the first analog signal and the frequency of the frequency response curve corresponding to the target signal type is less than the difference between the frequency of the frequency response curve corresponding to the original analog signal and the frequency of the frequency response curve corresponding to the target signal type at the same amplitude.

[0018] In a possible implementation, the active filter comprises an operational amplifier, a first direct-current blocking capacitor, a second direct-current blocking capacitor, a first resistance-capacitance (RC) parallel branch, a second RC parallel branch, a third RC parallel branch, and a fourth RC parallel branch, the first RC parallel branch, the second RC parallel branch, the third RC parallel branch, and the fourth RC parallel branch are branches obtained by connecting at least one resistor and at least one capacitor in parallel; wherein,

[0019] The first ends of the first direct-current blocking capacitor and the second direct-current blocking capacitor are connected in parallel to the read head, the first end of the first RC parallel branch is connected to the second end of the first direct-current blocking capacitor, and the first end of the second RC parallel branch is connected to the second end of the second direct-current blocking capacitor; the second end of the first RC parallel branch is connected to the first input end of the operational amplifier, and the second end of the second RC parallel branch is connected to the second input end of the operational amplifier; the first end of the third RC parallel branch is connected to the first input end of the operational amplifier, and the second end of the third RC parallel branch is connected to the first output end of the operational amplifier; the first end of the fourth RC parallel branch is connected to the second input end of the operational amplifier, and the second end of the fourth RC parallel branch is connected to the second output end of the operational amplifier; the capacitances in the first RC parallel branch and the second RC parallel branch have the same capacitance value, and the resistances have the same resistance value; the capacitances in the third RC parallel branch and the fourth RC parallel branch have the same capacitance value, and the resistances have the same resistance value; the first analog signal is output from the first output end of the operational amplifier and the second output end of the operational amplifier to the digital processing chip.

[0020] In the embodiment of the application, the operational amplifier in the active filter is designed as a full differential operational amplifier, the positive input terminal and the negative input terminal of the operational amplifier each adopt the same resistance-capacitance circuit as an input circuit, the two input terminals and the output terminal of the operational amplifier each adopt the same resistance-capacitance circuit as a feedback circuit, and a direct-current blocking capacitor which can remove the direct-current component of a signal is adopted in the input circuit, the low-frequency cutoff frequency of the active filter is determined by the resistance and capacitance of the input circuit, the high-frequency cutoff frequency is determined by the resistance and capacitance of the feedback circuit, and the transfer function of the analog equalization circuit can be ensured to convert the frequency response of the original analog signal into a frequency response close to the frequency response of the target signal type, thereby completing data equalization.

[0021] In a possible implementation, the active filter comprises an operational amplifier, a third direct-current blocking capacitor, a fourth direct-current blocking capacitor, a fifth RC parallel branch, a sixth RC parallel branch, a first resistor and a second resistor; the fifth RC parallel branch and the sixth RC parallel branch are respectively branches obtained by connecting at least one third resistor and at least one capacitor in series and then connecting the series connection with at least one fourth resistor in parallel; wherein,

[0022] The first ends of the third direct-current blocking capacitor and the fourth direct-current blocking capacitor are connected in parallel to the read head, the first end of the fifth RC parallel branch is connected to the second end of the third direct-current blocking capacitor, and the first end of the sixth RC parallel branch is connected to the second end of the fourth direct-current blocking capacitor; the second end of the fifth RC parallel branch is connected to the first input terminal of the operational amplifier, and the second end of the sixth RC parallel branch is connected to the second input terminal of the operational amplifier; the two ends of the first resistor are respectively connected to the first input terminal and the first output terminal of the operational amplifier; the two ends of the second resistor are respectively connected to the second input terminal and the second output terminal of the operational amplifier; the capacitances of the capacitors in the fifth RC parallel branch and the sixth RC parallel branch are the same, and the resistances of the resistors are the same; the resistance of the first resistor is the same as that of the second resistor; the first analog signal is output from the first output terminal of the operational amplifier and the second output terminal of the operational amplifier to the digital processing chip.

[0023] In the embodiment of the present application, the operational amplifier in the active filter adopts a full-differential operational amplifier design, the positive input terminal and the negative input terminal of the operational amplifier each adopt the same resistance-capacitance circuit as an input circuit, the two input terminals and the output terminal of the operational amplifier each adopt the same resistance as a feedback circuit, and a direct-current blocking capacitor that can remove the direct-current component of a signal is adopted in the input circuit, the low-frequency cutoff frequency and the high-frequency cutoff frequency of the active filter are determined by the capacitance of the input circuit, the low-frequency gain of the active filter is determined by the resistance of the two resistors in the input circuit, the high-frequency gain is determined by the resistance of the two resistors in the input circuit and the resistance of the resistor in the feedback circuit, the gain is flat at the low-frequency end and the high-frequency end, and the transfer function of the analog equalization circuit can convert the frequency response of the original analog signal into a frequency response close to the frequency response of the target signal type, thereby completing data equalization.

[0024] In a possible implementation, the analog equalization circuit further includes one or more passive filters; the one or more active filters are connected in series with the one or more passive filters; and the analog equalization circuit is specifically configured to:

[0025] perform data equalization on the original analog signal through the series connection of the one or more active filters and the one or more passive filters, obtain a second analog signal, and output the second analog signal to the digital processing chip; and the frequency response curve of the second analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the first analog signal.

[0026] Different from the design in which the analog equalization circuit is implemented only through an active filter, in the embodiment of the present application, the analog equalization circuit can be implemented through the cascade design of an active filter and a passive filter, can convert the frequency response of the original analog signal into a frequency response closer to the frequency response of the target signal type, and has a better data equalization effect, thereby further reducing the order of the digital filter.

[0027] In a possible implementation, the passive filter includes a seventh RC parallel branch, an eighth RC parallel branch, a fifth resistor, and a sixth resistor; the seventh RC parallel branch and the eighth RC parallel branch are branches obtained by connecting at least one resistor and at least one capacitor in parallel; and the seventh RC parallel branch and the eighth RC parallel branch are connected in parallel with the fifth resistor and the sixth resistor.

[0028] The first end of the seventh RC parallel branch and the eighth RC parallel branch is connected in parallel to the output end of the active filter, and the second end of the seventh RC parallel branch and the eighth RC parallel branch is coupled with the digital processing chip respectively; the fifth resistor is connected between the second end of the seventh RC parallel branch and the ground wire, and the sixth resistor is connected between the second end of the eighth RC parallel branch and the ground wire; the capacitance in the seventh RC parallel branch and the eighth RC parallel branch has the same capacitance value, and the resistance has the same resistance value; the second analog signal is output from the second end of the seventh RC parallel branch and the eighth RC parallel branch to the digital processing chip.

[0029] In the embodiment of the application, the passive filter can supplement the data equalization of the analog signal output by the active filter in the low frequency part, so that the curve of the low frequency part of the frequency response curve of the analog signal can be closer to the curve of the low frequency part of the frequency response curve of the target signal type, the effect of data equalization is improved, and the order of the digital filter is further reduced.

[0030] In a possible implementation, the passive filter further includes a fifth capacitor and a sixth capacitor, and the fifth capacitor and the sixth capacitor have the same capacitance value; the fifth capacitor is connected in parallel with the fifth resistor between the second end of the seventh RC parallel branch and the ground wire, and the sixth capacitor is connected in parallel with the sixth resistor between the second end of the eighth RC parallel branch and the ground wire.

[0031] In the embodiment of the application, the passive filter can supplement the data equalization of the analog signal output by the active filter in the low frequency part and the high frequency part, so that the curve of the low frequency part and the high frequency part of the frequency response curve of the analog signal can be closer to the curve of the low frequency part and the high frequency part of the frequency response curve of the target signal type, the effect of data equalization is further improved, and the order of the digital filter is reduced.

[0032] In a possible implementation, the partial response signal includes one or more of a fourth type of partial response signal PR4, an enhanced fourth type of partial response signal EPR4, and an extended enhanced fourth type of partial response signal EEPR4.

[0033] In the embodiment of the application, the target signal type can be a signal in the format of PR4, EPR4, or EEPR4, and the analog equalization circuit converts the frequency response of the analog signal of the original data into an analog signal frequency response close to the frequency response of the signal in the format of PR4, EPR4, or EEPR4, which can effectively eliminate the influence of inter-symbol interference on data.

[0034] In a possible implementation, the magnetic tape drive further includes a gain amplifier, and the analog equalization circuit is coupled with the digital processing chip through the gain amplifier.

[0035] In the embodiments of the present application, the amplitude of the original signal read from the magnetic tape by the read head is too small, so the signal needs to be amplified first. If the operational amplifier of the active filter in the analog equalization circuit has limited amplification effect on the original signal, the gain amplifier can continue to amplify the signal output by the analog equalization circuit, so as to ensure that the ADC can normally collect the signal.

[0036] In a possible implementation, the offset between the center frequency of the frequency response curve of the first analog signal and the center frequency of the frequency response curve of the target signal type is less than or equal to 10%.

[0037] In a second aspect, the present application provides a tape drive, which comprises the tape drive according to any one of the possible implementation manners of the first aspect.

[0038] In a third aspect, the present application provides a storage system, which comprises the tape drive according to any one of the possible implementation manners of the first aspect, or the tape drive according to any one of the possible implementation manners of the second aspect.

[0039] In a fourth aspect, the present application provides an analog equalization circuit, which comprises a first interface, a second interface and a processing circuit; the processing circuit comprises one or more active filters;

[0040] The first interface is configured to receive an original analog signal.

[0041] The processing circuit is configured to perform data equalization on the original analog signal to obtain a first analog signal; the frequency response curve of the first analog signal is closer to the frequency response curve of a target signal type than the frequency response curve of the original analog signal, and the target signal type comprises a partial response signal.

[0042] The second interface is configured to output the analog signal output by the processing circuit.

[0043] In the embodiments of the present application, the analog equalization circuit can be a chip. The chip can perform data equalization on the analog signal through the analog equalization circuit, and convert the channel frequency response of the analog signal into a channel frequency response close to the frequency response of the target signal type, that is, the chip performs data equalization in advance, thereby reducing the order of the digital filter required by the back-end device (such as an analog front end), reducing the algorithmic demand of the digital processing chip by the back-end device (such as a tape drive), reducing the cost and difficulty of product implementation, improving the data convergence speed, and thus improving the processing efficiency.

[0044] In a possible implementation, the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal specifically in that:

[0045] The FIR order required to convert the frequency response curve of the first analog signal into the frequency response curve of the target signal type is FIR1, and the FIR order required to convert the frequency response curve of the original analog signal into the frequency response curve of the target signal type is FIR2, wherein FIR1 is less than FIR2.

[0046] In one possible implementation, the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, specifically as follows:

[0047] At the same frequency, the difference between the amplitude of the frequency response curve corresponding to the first analog signal and the amplitude of the frequency response curve corresponding to the target signal type is less than the difference between the amplitude of the frequency response curve corresponding to the original analog signal and the amplitude of the frequency response curve corresponding to the target signal type; or,

[0048] At the same amplitude, the difference between the frequency of the frequency response curve corresponding to the first analog signal and the frequency of the frequency response curve corresponding to the target signal type is less than the difference between the frequency of the frequency response curve corresponding to the original analog signal and the frequency of the frequency response curve corresponding to the target signal type.

[0049] In one possible implementation, the active filter includes an operational amplifier, a first DC blocking capacitor, a second DC blocking capacitor, a first RC parallel branch, a second RC parallel branch, a third RC parallel branch, and a fourth RC parallel branch, wherein the first RC parallel branch, the second RC parallel branch, the third RC parallel branch, and the fourth RC parallel branch are branches formed by at least one resistor and at least one capacitor connected in parallel, respectively; wherein,

[0050] The first terminals of the first and second DC blocking capacitors are connected in parallel to the first interface. The first terminal of the first RC parallel branch is connected to the second terminal of the first DC blocking capacitor, and the first terminal of the second RC parallel branch is connected to the second terminal of the second DC blocking capacitor. The second terminal of the first RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the second RC parallel branch is connected to the second input terminal of the operational amplifier. The first terminal of the third RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the third RC parallel branch is connected to the first output terminal of the operational amplifier. The first terminal of the fourth RC parallel branch is connected to the second input terminal of the operational amplifier, and the second terminal of the fourth RC parallel branch is connected to the second output terminal of the operational amplifier. The capacitors in the first and second RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The capacitors in the third and fourth RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The first and second output terminals of the operational amplifier are coupled to the second interface.

[0051] The first analog signal is output from the second interface.

[0052] In this embodiment, the operational amplifier in the active filter adopts a fully differential operational amplifier design. The positive and negative input terminals of the operational amplifier use the same RC circuit as the input circuit, and the two input terminals and the output terminal of the operational amplifier use the same RC circuit as the feedback circuit. In addition, the input circuit uses a DC blocking capacitor that can remove the DC component of the signal. The low-frequency cutoff frequency of the active filter is determined by the resistance and capacitance values ​​of the input circuit, and the high-frequency cutoff frequency is determined by the resistance and capacitance values ​​of the feedback circuit. This ensures that the transfer function of the analog equalization circuit can convert the frequency response of the original analog signal into a frequency response close to the target signal type, thereby completing data equalization.

[0053] In one possible implementation, the active filter includes an operational amplifier, a third DC blocking capacitor, a fourth DC blocking capacitor, a fifth RC parallel branch, a sixth RC parallel branch, a first resistor, and a second resistor; the fifth RC parallel branch and the sixth RC parallel branch are respectively branches formed by connecting at least one third resistor and at least one capacitor in series and then connecting them in parallel with at least one fourth resistor; wherein...

[0054] The first ends of the third and fourth DC blocking capacitors are respectively connected in parallel to the first interface; the first end of the fifth RC parallel branch is connected to the second end of the third DC blocking capacitor; the first end of the sixth RC parallel branch is connected to the second end of the fourth DC blocking capacitor; the second end of the fifth RC parallel branch is connected to the first input terminal of the operational amplifier; the second end of the sixth RC parallel branch is connected to the second input terminal of the operational amplifier; the two ends of the first resistor are respectively connected to the first input terminal and the first output terminal of the operational amplifier; the two ends of the second resistor are respectively connected to the second input terminal and the second output terminal of the operational amplifier; the capacitors in the fifth and sixth RC parallel branches have the same capacitance value, and the resistors have the same resistance value; the first resistor and the second resistor have the same resistance value; the first output terminal and the second output terminal of the operational amplifier are coupled to the second interface.

[0055] The first analog signal is output from the second interface.

[0056] In this embodiment, the operational amplifier in the active filter adopts a fully differential operational amplifier design. The positive and negative input terminals of the operational amplifier use the same RC circuit as the input circuit, and the two input terminals and the output terminal of the operational amplifier use the same resistor as the feedback circuit. The input circuit uses a DC blocking capacitor that can remove the DC component of the signal. The low-frequency cutoff frequency and high-frequency cutoff frequency of the active filter are determined by the capacitance value of the input circuit. The low-frequency gain of the active filter is determined by the resistance values ​​of the two resistors in the input circuit, and the high-frequency gain is jointly determined by the resistance values ​​of the two resistors in the input circuit and the resistance values ​​of the resistor in the feedback circuit. The low-frequency and high-frequency gains are flat, which can ensure that the transfer function of the analog equalization circuit can convert the frequency response of the original analog signal into a frequency response close to the target signal type, thereby completing data equalization.

[0057] In one possible implementation, the processing circuit further includes one or more passive filters; the one or more active filters are connected in series with the one or more passive filters; the processing circuit is specifically used for:

[0058] The original analog signal is subjected to data equalization by a series circuit of one or more active filters and one or more passive filters to obtain a second analog signal; the frequency response curve of the second analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the first analog signal.

[0059] Unlike analog equalization circuits that are implemented solely through active filters, in this embodiment, the analog equalization circuit can be implemented through a cascaded design of active and passive filters. This can convert the frequency response of the original analog signal into a frequency response that is closer to the target signal type, resulting in better data equalization and further reducing the order of the digital filter.

[0060] In one possible implementation, the passive filter includes a seventh RC parallel branch, an eighth RC parallel branch, a fifth resistor, and a sixth resistor; the seventh RC parallel branch and the eighth RC parallel branch are branches formed by connecting at least one resistor and at least one capacitor in parallel; wherein...

[0061] The first terminals of the seventh RC parallel branch and the eighth RC parallel branch are respectively connected to the output terminal of the active filter, and the second terminals of the seventh RC parallel branch and the eighth RC parallel branch are respectively coupled to the second interface; the fifth resistor is connected between the second terminal of the seventh RC parallel branch and the ground wire, and the sixth resistor is connected between the second terminal of the eighth RC parallel branch and the ground wire; the capacitors in the seventh RC parallel branch and the eighth RC parallel branch have the same capacitance value, and the resistors have the same resistance value;

[0062] The second analog signal is output from the second interface.

[0063] In this embodiment, the passive filter can supplement the analog signal output by the active filter in the low-frequency part by performing data equalization, so that the low-frequency part of the frequency response curve of the analog signal can be closer to the low-frequency part of the frequency response curve of the target signal type, thereby improving the effect of data equalization and further reducing the order of the digital filter.

[0064] The technical effects achieved in the above aspects can be referred to each other or to the beneficial effects in the method embodiments shown below, which will not be repeated here. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0066] Figure 1 This is a schematic diagram of the processing flow of a signal processing device;

[0067] Figure 2 This is a schematic diagram of the processing flow of a magnetic information playback device.

[0068] Figure 3 This is a schematic diagram of the structure of a magnetic tape drive provided in an embodiment of this application;

[0069] Figure 4 This is a schematic diagram of the structure of a magnetic tape drive provided in an embodiment of this application;

[0070] Figure 5 This is a functional schematic diagram of an analog driving circuit provided in an embodiment of this application;

[0071] Figure 6A This is a schematic diagram of the power spectral density curve of a raw analog signal provided in an embodiment of this application;

[0072] Figure 6B This is a schematic diagram of the channel response curve of another original analog signal provided in an embodiment of this application;

[0073] Figure 7 This is a schematic diagram of the characteristic curve of a target signal type provided in an embodiment of this application;

[0074] Figure 8 This is a schematic diagram of the ideal transfer function curve of an analog driving circuit provided in an embodiment of this application;

[0075] Figure 9A This is a schematic diagram of the structure of an analog driving circuit provided in an embodiment of this application;

[0076] Figure 9B This is a schematic diagram of the structure of an active filter provided in an embodiment of this application;

[0077] Figure 10 This is a schematic diagram of another active filter structure provided in an embodiment of this application;

[0078] Figure 11A This is a schematic diagram of another analog driving circuit provided in an embodiment of this application;

[0079] Figure 11B This is a schematic diagram of another analog driving circuit provided in the embodiments of this application;

[0080] Figure 12A This is a schematic diagram of the structure of a passive filter provided in an embodiment of this application;

[0081] Figure 12B This is a schematic diagram of another passive filter structure provided in an embodiment of this application;

[0082] Figure 13 This is a schematic diagram of the transfer function curve of an analog driving circuit provided in an embodiment of this application;

[0083] Figure 14 This is a schematic diagram of another magnetic tape drive provided in an embodiment of this application;

[0084] Figure 15This is a schematic diagram illustrating the effect of data balancing provided in an embodiment of this application;

[0085] Figure 16 This is a schematic diagram illustrating another data balancing effect provided in an embodiment of this application;

[0086] Figure 17 This is a schematic diagram illustrating the effect of another data balancing method provided in the embodiments of this application. Detailed Implementation

[0087] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0088] In the description of this application, the terms "first," "second," etc., are used only to distinguish different objects and do not limit the quantity or order of execution, nor do they imply that they must be different. For example, "first resistor" and "second resistor," etc., are merely used to distinguish different resistors and do not limit their order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0089] In the description of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one item", "one or more of the following", or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0090] In the description of this application, the words "exemplary," "exemplarily," or "for example" are used to indicate examples, illustrations, or illustrative purposes. Any embodiment or design described as "exemplary," "for example," or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the words "exemplary," "for example," or "for example" is intended to present the relevant concepts in a specific manner.

[0091] It is understood that in the description of this application, "when," "if," and "if" all refer to the device making a corresponding action under certain objective circumstances, and are not time-limited, nor do they require the device to make a judgment action when it is implemented, nor do they mean that there are other limitations.

[0092] In this application, "simultaneously" can be understood as at the same point in time, within a period of time, or within the same cycle; the specific meaning can be determined by considering the context.

[0093] In this application, the use of singular designations for elements is intended to represent "one or more" rather than "one and only one," unless otherwise specified.

[0094] It is understood that in the various embodiments of this application, "A and B correspond" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0095] I. Finite Impulse Response (FIR) Filter

[0096] FIR filters, also known as non-recursive filters, are fundamental components in digital signal processing systems. They can guarantee arbitrary amplitude-frequency characteristics while possessing strictly linear phase-frequency characteristics, and their unit sample response is finite. FIR filters have wide applications in communication, image processing, pattern recognition, and other fields. Currently, FIR filters are also widely used in the digital processing chips of tape drives for digital signal processing. However, digital processing chips have high requirements for the order of FIR filters, making hardware implementation difficult. Therefore, this application provides a solution that allows data equalization at the analog front end, thereby reducing the order of the FIR filter in the digital processing chip of the tape drive.

[0097] II. Inter-symbol Interference (ISI)

[0098] Intersymbol interference (ISI) is a phenomenon caused by signal waveform overlap, where code patterns interfere with adjacent code patterns. This interference occurs during signal transmission, especially when the signal duration is long and the interval between signals is small. ISI can be caused by various factors, including excessive pre-emphasis, characteristics of the data code pattern, the frequency response of the transmission channel to different frequencies of serial data codes, the order of data bits, and impedance mismatch. Currently, tape drive readers read analog signals from the tape at high data transfer rates, resulting in ISI. To address the impact of ISI, data equalization is needed on the data read back by the reader. This application provides a solution that allows data equalization at the analog front-end, reducing the order of the FIR filter in the tape drive's digital processing chip.

[0099] First, the specific technical problem to be solved in this application is analyzed and proposed. Current magnetic signal processing schemes include Scheme 1 (application number US9747161B2) and Scheme 2 (application number US11495248B2):

[0100] For Option 1 (application number US9747161B2), please refer to Figure 1 , Figure 1 This is a schematic diagram of the processing flow of a signal processing device, wherein the signal processing equipment includes:

[0101] A receiver receives multiple sequences of replay signals obtained by digitizing multiple readouts using multiple analog-to-digital converters; the multiple readouts are obtained by reading data from a magnetic tape containing data using multiple readout elements mounted in a readout head.

[0102] Multiple equalizers perform waveform equalization on multiple replay signal sequences received by a receiver. The multiple equalizers perform waveform equalization using multiple nonlinear filters that have been learned to reduce distortion that occurs nonlinearly in the multiple replay signal sequences based on conditions in the environment from which data is read from the magnetic amplifier. Through optimization based on the multiple readout results, the multiple nonlinear filters are optimized to suit the characteristics of the multiple readout elements.

[0103] For Option 2 (application number US11495248B2), please refer to Figure 2 , Figure 2This is a schematic diagram of the processing flow of a magnetic information playback device. Compared with the cases where the target signal itself is used in the extraction timing adjustment and the final decoding result is used in the extraction timing adjustment, it can balance the high-precision extraction of a specific target signal and the delay suppression that occurs in order to adjust the extraction timing. Specifically, at the extraction timing determined for extracting the target signal, the target signal is extracted from the input digital signal; the candidate decoding result of the extracted target signal is estimated by maximum likelihood decoding, and the maximum likelihood decoding result is detected to decode the target signal.

[0104] The two schemes described above have the following drawbacks: Scheme 1's data processing flow first amplifies the analog signal using an amplifier, then performs analog-to-digital conversion using an ADC, and finally performs data equalization at the digital end using an equalizer. The analog front-end only amplifies the signal; data equalization is entirely handled by the digital processing chip at the digital end. This requires designing complex digital processing chips, high-order FIR filters, and high computing power requirements, making implementation extremely difficult and costly. Similarly, Scheme 2 also performs data equalization at the digital end after the ADC, rather than before. This results in high-order FIR filters, high computing power requirements, complex algorithms, and slower FIR convergence. This is because when a tape drive reads back and writes data, the high signal storage density naturally generates ISI (Inter-symbol Crosstalk), making the read data uninterpretable. Data equalization must be performed before parsing. The digital processing chips in Schemes 1 and 2 use algorithms for equalization and parsing, typically PRML, NPML, or DD-NPML. The part of the algorithm used for data equalization is generally accomplished using a digital FIR filter. This FIR filter usually needs to be 16th order or even higher to ensure the effect of data equalization. The FIR filter has a high order.

[0105] To address this, this application proposes a magnetic tape drive, related devices, and a system. An analog equalization circuit is placed between the read head and the digital processing chip. Before digital processing, the analog signal read from the read head is pre-equalized by the analog equalization circuit, converting the channel frequency response of the analog signal into a channel frequency response close to that of the target signal type. The digital processing chip then performs digital processing on the equalized signal. This embodiment of the application performs data equalization at the analog front end using the analog equalization circuit, replacing part of the FIR filter function used for data equalization in the digital processing chip. This reduces the FIR filter order required for back-end digital processing, thereby reducing the computational power requirements of the magnetic tape drive on the digital processing chip, lowering the cost and difficulty of product implementation, and improving data convergence speed.

[0106] For ease of understanding, the technical solution provided in this application will be described below with reference to more accompanying drawings.

[0107] In this application, unless otherwise specified, the same or similar parts between various embodiments or implementations can be referred to each other. In the various embodiments of this application, and in the various implementation methods / methods / implementations within each embodiment, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments and between the various implementation methods / methods / implementations within each embodiment are consistent and can be mutually referenced. The technical features in different embodiments and the various implementation methods / methods / implementations within each embodiment can be combined according to their inherent logical relationships to form new embodiments, implementation methods, methods, or implementation approaches. The embodiments described below do not constitute a limitation on the scope of protection of this application.

[0108] See Figure 3 , Figure 3 This is a schematic diagram of the structure of a magnetic tape drive provided in an embodiment of this application. The magnetic tape drive

[10] may include a magnetic tape slot

[100] and a magnetic tape drive

[101] . The magnetic tape slot

[100] can be used to store magnetic tapes. The magnetic tape drive may include multiple magnetic tape slots to store and manage a large number of magnetic tapes. Magnetic tape is a storage medium used to store data. The storage capacity of a single magnetic tape can reach tens of TB or even higher. The magnetic tape drive

[101] is a device responsible for reading and writing magnetic tape data. It can write data to or read data from the magnetic tape in a specific format.

[0109] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a magnetic tape drive provided in an embodiment of this application. The magnetic tape drive

[101] may include a magnetic head module

[1010] , an analog equalization circuit

[1011] , and a digital processing chip

[1012] .

[0110] The magnetic head module

[1010] may include a write head for writing magnetic signals to the magnetic tape and a read head for reading magnetic signals from the magnetic tape. The write head and read head can be collectively referred to as magnetic heads. The write head and read head can be two independent magnetic heads, or a single magnetic head with read and write functions. This magnetic head can be called a write head when writing data and a read head when reading data. The magnetic head in the magnetic head module

[1010] can be a TFI magnetic head based on Thin-Film Inducted (TFI) technology, an AMR magnetic head based on Anisotropic Magneto Resistance (AMR) technology, a GMR magnetic head based on Giant Magneto Resistance (GMR) technology, a CMR magnetic head based on Colossal Magneto Resistance (CMR) technology, or a TMR magnetic head based on Tunnel Magneto Resistance (TMR) technology, etc., without specific limitations. In this embodiment of the application, the read head in the magnetic head module

[1010] is used to read the original analog signal of the original data from the magnetic tape of the magnetic tape drive, and output the original analog signal to the analog equalization circuit for data equalization.

[0111] The analog equalization circuit

[1011] may include one or more active filters. The analog equalization circuit

[1011] is used to perform data equalization on the original analog signal of the original data read by the read head through one or more active filters, and output the signal after data equalization (such as the first analog signal) to the digital processing chip

[1012] for digital signal processing. The channel frequency response curve of the analog signal output after data equalization by the analog equalization circuit

[1011] is closer to the channel frequency response curve of the target signal type than the channel frequency response curve of the original analog signal. The target signal type is a partial response (PR) signal. The partial response signal may be a first (I) type partial response signal (PR1), a second (II) type partial response signal (PR2), a third (III) type partial response signal (PR3), a fourth (IV) type partial response signal (PR4), an enhanced fourth (IV) type partial response signal (EPR4), an extended enhanced fourth (IV) type partial response signal (EEPR4), a fifth (V) type partial response signal (PR5), etc. For ease of understanding, this application will use PR4, EPR4 or EEPR4 as examples to illustrate the embodiments. It is understood that the target signal type can also be other partial response types of signals, and no specific limitation is made here.

[0112] Optionally, the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal specifically means that the FIR order required to convert the frequency response curve of the first analog signal to the frequency response curve of the target signal type is FIR1, and the FIR order required to convert the frequency response curve of the original analog signal to the frequency response curve of the target signal type is FIR2, where FIR1 is less than FIR2. For example, the FIR order required to convert the frequency response curve of the original analog signal to the frequency response curve of the EPR4 signal is 16, while the FIR order required to convert the frequency response curve of the first analog signal to the frequency response curve of the EPR4 signal is 12. Therefore, the frequency response curve of the first analog signal is closer to the frequency response curve of the EPR4 signal than the frequency response curve of the original analog signal.

[0113] Optionally, the frequency response curve of the first analog signal being closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal specifically means that, at the same frequency, the difference between the amplitude of the frequency response curve corresponding to the first analog signal and the amplitude of the frequency response curve corresponding to the target signal type is less than the difference between the amplitude of the frequency response curve corresponding to the original analog signal and the amplitude of the frequency response curve corresponding to the target signal type; or, at the same amplitude, the difference between the frequency of the frequency response curve corresponding to the first analog signal and the frequency of the frequency response curve corresponding to the target signal type is less than the difference between the frequency of the frequency response curve corresponding to the original analog signal and the frequency response curve corresponding to the target signal type.

[0114] For example, at the same frequency of 5MHz, the amplitude of the frequency response curve of the first analog signal is A1, the amplitude of the frequency response curve of the original analog signal is A2, and the amplitude of the frequency response curve of the EPR4 signal is A3. The difference between A1 and A3 is smaller than the difference between A2 and A3. Therefore, at a frequency of 5MHz, the frequency response curve of the first analog signal is closer to the frequency response curve of the EPR4 signal than the frequency response curve of the original analog signal.

[0115] For example, at the same amplitude of 0.8, the frequency of the frequency response curve of the first analog signal is f1, the frequency of the frequency response curve of the original analog signal is f2, and the frequency of the frequency response curve of the EPR4 signal is f3. The difference between f1 and f3 is smaller than the difference between f2 and f3. Therefore, at an amplitude of 0.8, the frequency response curve of the first analog signal is closer to the frequency response curve of the EPR4 signal than the frequency response curve of the original analog signal.

[0116] It should be noted that while the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than that of the original analog signal, it is not required that the amplitude difference between the frequency response curves of the first analog signal and the target signal type be smaller than that of the original analog signal at all frequency points; this requirement only applies to most frequency points. Similarly, it is not required that the frequency difference between the frequency response curves of the first analog signal and the target signal type be smaller than that of the original analog signal at all amplitudes; this requirement only applies to most amplitudes.

[0117] The digital processing chip

[1012] is used to convert the signal output by the analog equalization circuit

[1011] into a digital signal, and to perform digital processing and analysis on the digital signal. Finally, the analysis result can be output to other external devices (such as computers, displays, speakers, etc.). Optionally, when data needs to be stored, the digital processing chip

[1012] can also convert the digital signal of the data to be stored into a magnetic signal, and then write the magnetic signal onto a magnetic tape through a magnetic head (such as a write head) for data storage. In addition, the digital processing chip

[1012] can also perform data encoding, decoding, error detection and correction, etc., thereby ensuring the integrity and reliability of the data. For example, the digital processing chip

[1012] can be a digital signal processor (DSP) chip, a data processing unit (DPU) chip, or other types of digital signal processing chips, such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), etc., without specific limitations.

[0118] It should be noted that, due to the influence of ISI effect on the frequency response of the raw random data read back by the read head, the data frequency response contains inter-symbol interference from symbol crosstalk, which cannot be directly applied to the data processing and parsing process. Data equalization is required to convert the frequency response of the raw data into the frequency response of the desired target data type. To address the problem of high FIR filter order caused by data equalization being performed entirely by the digital processing chip, this application provides an analog equalization circuit for pre-equalizing the data at the analog front end. This converts the frequency response of the raw random data into a frequency response close to that of the target signal type, thereby completing part of the data equalization task in advance. This circuit undertakes part or all of the data equalization work in the digital processing chip, reducing the FIR filter order.

[0119] For ease of understanding, the design principle of the analog equalization circuit provided in the embodiments of this application will be illustrated below. Figure 5As shown, the function of the analog equalization circuit is to perform data equalization on the original data, converting the frequency response of the original data into an output signal frequency response that approximates the frequency response of the partial response signal. The goal is to ensure that the frequency response curve of the analog equalization circuit's output signal is as consistent as possible with the frequency response curve of the partial response signal. The partial response (PR) signal can be in formats such as PR4, EPR4, or EEPR4. Optionally, the transfer function of the analog equalization circuit can be referenced from the following formula:

[0120]

[0121] Here, Channel Response represents the original analog signal channel frequency response of the raw data, and PR Response represents the partial response signal channel frequency response.

[0122] For example, the power spectral density curve of the raw data is as follows: Figure 6A As shown in the curve, the channel frequency response (or simply raw channel response) curve of the original analog signal of the original data is as follows: Figure 6B As shown in the curve, the channel frequency response curve of the original analog signal can be obtained by smoothing the power spectral density curve.

[0123] Taking a PR signal in PR4, EPR4, or EEPRP4 format as an example, the frequency response (also known as the target channel response) curve of the target signal type is as follows: Figure 7 As shown.

[0124] Based on the above formula, by dividing the frequency response of the target signal type by the frequency response of the original analog signal, the ideal transfer function curve of the analog equalization circuit that can meet the data equalization requirements can be obtained. This ideal transfer function curve is shown below. Figure 8 As shown. To obtain as Figure 8 The transfer function shown illustrates how analog equalization circuits can utilize the frequency characteristics of capacitors and resistors to create a frequency response curve that, under ideal conditions, has a flat gain at both low and high frequencies, without any increase or decrease. The frequency variation within the intermediate data range can be used to fit the frequency variation of this ideal curve. In other words, the transfer function curve of the analog equalization circuit can be determined based on the frequency responses of the original analog signal and the target signal type. By designing the circuit based on this transfer function curve, it can be ensured that the original analog signal, after processing by the analog equalization circuit, produces a frequency response curve that is as consistent as possible with the desired target signal type, thus achieving data equalization.

[0125] In one possible implementation, the analog equalization circuit described above can be designed based solely on one or more active filters, such as... Figure 9AAs shown, an active filter is coupled to the read head. After the active filter obtains the original analog signal of the original data from the read head, it performs data equalization on the original analog signal to obtain the first analog signal and outputs it to the digital processing chip.

[0126] Optionally, the active filter in the analog equalization circuit

[1011] described above can be referenced as follows: Figure 9B Designed using the topology shown, the active filter may include an operational amplifier, a first DC blocking capacitor (e.g., C5), a second DC blocking capacitor (e.g., C6), a first RC parallel branch, a second RC parallel branch, a third RC parallel branch, and a fourth RC parallel branch. The first, second, third, and fourth RC parallel branches are branches formed by connecting at least one resistor (e.g., R1, R2, R3, or R4) and at least one capacitor (e.g., C1, C2, C3, or C4) in parallel.

[0127] The first terminals of the first and second DC blocking capacitors are respectively connected in parallel to the read head. The first terminal of the first RC parallel branch is connected to the second terminal of the first DC blocking capacitor, and the first terminal of the second RC parallel branch is connected to the second terminal of the second DC blocking capacitor. The second terminal of the first RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the second RC parallel branch is connected to the second input terminal of the operational amplifier. The first terminal of the third RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the third RC parallel branch is connected to the first output terminal of the operational amplifier. The first terminal of the fourth RC parallel branch is connected to the second input terminal of the operational amplifier, and the second terminal of the fourth RC parallel branch is connected to the second output terminal of the operational amplifier. The capacitors in the first and second RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The first analog signal is output from the first and second output terminals of the operational amplifier to the digital processing chip.

[0128] Optionally, the input to the active filter can come from the read head, in which case the two DC blocking capacitors of the active filter are connected in parallel to the read head, and the output of the active filter can be used as the input to the passive filter (as follows). Figure 11A The structure shown above), or as the input to a digital processing chip (in this case, the analog equalization circuit may not have a passive filter, as shown above). Figure 9A The structure shown below); or, the input to the active filter can also come from a passive filter (as shown below). Figure 11B(As shown in the structure), in this case, the two DC blocking capacitors of the active filter are connected in parallel to the output of the passive filter. The input of the passive filter comes from the read head, while the output of the active filter can be used as the input of the digital processing chip.

[0129] It should be noted that, regarding the above Figure 9B The active filter structure shown uses capacitors C5 and C6 as DC blocking capacitors to remove the DC component from the analog signal. The capacitance of capacitor C1 is equal to that of capacitor C3, and the capacitance of capacitor C2 is equal to that of capacitor C4. The resistances of resistors R1, R2, R3, and R4 are equal. Capacitor C1 is connected in parallel with R1 (one of the two first RC parallel branches) and then connected to the positive input of the operational amplifier. Capacitor C2 is connected in parallel with R2 (one of the two second RC parallel branches) as a feedback circuit, connected to the parallel branches of C1 and R1 (i.e., connected to the positive input of the operational amplifier) ​​and to the output of the operational amplifier. The operational amplifier uses a fully differential op-amp design. The other end of the differential op-amp (i.e., the negative input) has R3 and C3 (the other of the two first RC parallel branches), and C4 and R4 (the other of the two second RC parallel branches) connected in the same way as R1 and C1, and R2 and C2, respectively. For this active filter, the cutoff frequency in the low-frequency band is f = 1 / (2*π*R1*C1), and the cutoff frequency in the high-frequency band is f = 1 / (2*π*R2*C2).

[0130] Optionally, the active filter in the analog equalization circuit

[1011] described above can be referenced as follows: Figure 10 Designing an active filter using the topology shown, the active filter may include an operational amplifier, a third DC blocking capacitor (e.g., C5), a fourth DC blocking capacitor (e.g., C6), a fifth RC parallel branch, a sixth RC parallel branch, a first resistor (e.g., R5), and a second resistor (e.g., R6). The fifth and sixth RC parallel branches are respectively branches formed by connecting at least one third resistor (e.g., R2 or R4) and at least one capacitor (e.g., C1 or C3) in series, and then connecting them in parallel with at least one fourth resistor (e.g., R1 or R3).

[0131] The first ends of the third and fourth DC blocking capacitors are respectively connected in parallel to the read head; the first end of the fifth RC parallel branch is connected to the second end of the third DC blocking capacitor; the first end of the sixth RC parallel branch is connected to the second end of the fourth DC blocking capacitor; the second end of the fifth RC parallel branch is connected to the first input terminal of the operational amplifier; the second end of the sixth RC parallel branch is connected to the second input terminal of the operational amplifier; the two ends of the first resistor are respectively connected to the first input terminal and the first output terminal of the operational amplifier; the two ends of the second resistor are respectively connected to the second input terminal and the second output terminal of the operational amplifier; the capacitance values ​​of the capacitors in the fifth and sixth RC parallel branches are the same, and the resistance values ​​of the resistors are the same; the resistance values ​​of the first resistor and the second resistor are the same; the first analog signal is output from the first output terminal and the second output terminal of the operational amplifier to the digital processing chip.

[0132] Optionally, Figure 10 The input to an active filter can come from a read head (e.g., Figure 9A or Figure 11A The structure shown can be derived from a passive filter (such as...). Figure 11B (The structure shown); the output of an active filter can be used as the input of a passive filter (such as...). Figure 11A The structure shown), or as an input to a digital processing chip (such as... Figure 9A or Figure 11B (The structure shown is provided in the image). For details, please refer to [the image / reference]. Figure 9B The relevant descriptions of the input and output parts of the active filter are not repeated here.

[0133] It should be noted that, regarding the above Figure 10 The active filter structure shown has capacitor C1 with the same capacitance as capacitor C3. Resistors R1, R2, R3, and R4 have equal resistance, and resistor R5 has the same resistance as resistor R6. C1 is connected in series with R2 and then in parallel with R1 (one of the two third RC parallel branches), connected to the positive input of the operational amplifier. Resistor R5 acts as a feedback circuit, connected to both the positive input and output of the operational amplifier. The operational amplifier uses a fully differential design. The other end of the differential operational amplifier (the negative input) has R3, R4, and C3 (the other of the two third RC parallel branches) and R6 connected in the same way as the branches of R1, R2, and C1, and R5. For this active filter, the cutoff frequencies for the low and high frequencies are determined by C1. The low-frequency gain is Gain = R2 / R1, and the high-frequency gain is Gain = R5 / (R1||R2). The gain is flat at both the low and high frequencies.

[0134] It should be noted that when the analog equalization circuit described above includes multiple active filters, the topologies of these active filters can be the same or different; no specific limitations are imposed here. For example, if the analog equalization circuit includes two active filters, the topologies of these two active filters can both be as described above. Figure 9B or Figure 10 The structure shown, or the topology of one of these two active filters, can be as described above. Figure 9B In addition to the above structure, another active filter topology can be as described above. Figure 10 The structure shown.

[0135] In one possible implementation, the analog equalization circuit described above can also be designed based on a cascaded circuit of active and passive filters; that is, the analog equalization circuit may further include one or more passive filters; the one or more active filters are connected in series with the one or more passive filters; the analog equalization circuit is specifically used for:

[0136] The original analog signal is subjected to data equalization by a series circuit of one or more active filters and one or more passive filters to obtain a second analog signal, which is then output to the digital processing chip. The frequency response curve of the second analog signal is closer to the frequency response curve of the target signal type than that of the first analog signal.

[0137] For example, the structure of an analog equalization circuit based on one or more active filters and one or more passive filters can be referred to as follows: Figure 11A The structure shown is designed with an active filter and a passive filter cascaded. The active filter is coupled to the read head. After the active filter obtains the original analog signal of the original data from the read head, it first performs data equalization on the original analog signal and outputs the processing result to the passive filter. Then, the passive filter performs data equalization to obtain the second analog signal.

[0138] Alternatively, the structure of an analog equalization circuit based on one or more active filters and one or more passive filters can also be referenced as follows: Figure 11B The structure shown is designed with a passive filter and an active filter cascaded together. The passive filter is coupled to the read head. The passive filter obtains the original analog signal of the original data from the read head, performs data equalization on the original analog signal first, and outputs the processing result to the active filter. Then, the active filter performs data equalization again to obtain the second analog signal. Figure 11A The structure shown is compared to Figure 11B The structure shown has stronger anti-interference capability because there is an operational amplifier in the active filter. The active filter is coupled with the read head, so it can be amplified first, which improves the anti-interference capability of the signal.

[0139] Optionally, for the above Figure 11A and Figure 11B The analog equalization circuit shown above, and the active filter can be referenced as described above. Figure 9B or Figure 10 The design is based on the topology shown, and will not be elaborated further here.

[0140] Optionally, the above Figure 11A and Figure 11B The passive filter in the analog equalization circuit

[1011] shown can be referenced as follows: Figure 12A The passive filter can be designed using the topology shown, consisting of a seventh RC parallel branch, an eighth RC parallel branch, a fifth resistor (e.g., R6), and a sixth resistor (e.g., R8). The seventh and eighth RC parallel branches are branches formed by connecting at least one resistor (e.g., R5 or R7) and at least one capacitor (e.g., C5 or C7) in parallel.

[0141] The first ends of the seventh RC parallel branch and the eighth RC parallel branch are respectively connected in parallel to the output terminal of the active filter, and the second ends of the seventh RC parallel branch and the eighth RC parallel branch are respectively coupled to the digital processing chip; the fifth resistor is connected between the second end of the seventh RC parallel branch and the ground wire, and the sixth resistor is connected between the second end of the eighth RC parallel branch and the ground wire; the capacitors in the seventh RC parallel branch and the eighth RC parallel branch have the same capacitance value, and the resistors have the same resistance value; the second analog signal is output from the second ends of the seventh RC parallel branch and the eighth RC parallel branch to the digital processing chip.

[0142] It should be noted that, regarding the above Figure 12A The passive filter structure shown has the same resistance values ​​among resistors R5, R6, R7, and R8. The capacitance values ​​of capacitor C5 and C7 are the same. C5 is connected in parallel with R5 and then connected to one end of R6, with the other end of R6 grounded. C7 is connected in parallel with R7 and then connected to one end of R8, with the other end of R8 grounded.

[0143] Further optional, such as Figure 12B As shown, the passive filter may further include a fifth capacitor (such as C6) and a sixth capacitor (such as C8), the fifth capacitor and the sixth capacitor having the same capacitance value; the fifth capacitor and the fifth resistor are connected in parallel between the second terminal of the seventh RC parallel branch and the ground wire, and the sixth capacitor and the sixth resistor are connected in parallel between the second terminal of the eighth RC parallel branch and the ground wire.

[0144] It should be noted that, regarding the above Figure 12BIn the passive filter structure shown, the capacitance of capacitor C6 is the same as that of capacitor C8. C6 and R6 are connected in parallel between the parallel branch of C5 and R5 and the ground wire, and C8 and R8 are connected in parallel between the parallel branch of C7 and R7 and the ground wire.

[0145] Optionally, Figure 12A or Figure 12B The input to a passive filter can come from the read head, or it can come from an active filter; the output of a passive filter can be used as the input to an active filter, or as the input to a digital processing chip (in which case the passive filter's input comes from the active filter). See reference for details. Figure 9B The relevant descriptions of the corresponding parts will not be repeated here.

[0146] It should be noted that when the analog equalization circuit described above includes multiple passive filters, the topologies of these passive filters can be the same or different, and no specific limitations are imposed here. For example, if the analog equalization circuit includes two passive filters, the topologies of these two passive filters can both be as described above. Figure 12A or Figure 12B The structure shown, or the topology of one of these two passive filters, can be as described above. Figure 12A In addition to the above structure, another passive filter topology can be as described above. Figure 12B The structure shown is illustrated. Furthermore, the analog equalization circuit in this embodiment can also be designed based solely on one or more passive filters. The passive filter is coupled to the read head; after acquiring the original analog signal of the original data from the read head, the passive filter performs data equalization on the original analog signal and outputs it to the digital processing chip.

[0147] Based on the above Figure 9B or Figure 10 The active filter shown is the same as the one described above. Figure 12B The analog equalization circuit obtained by cascading passive filters shown can achieve, for example... Figure 13 The frequency response curve shown, i.e., the transfer function curve of the analog equalization circuit in this embodiment, can be as follows: Figure 13 As shown, Figure 13 The curve shown is Figure 8 The ideal curves of the transfer functions shown have a very high degree of similarity. Therefore, the analog equalization circuit provided in this application embodiment can achieve the main waveform fitting effect of data equalization at the analog front end. Optionally, based on the fact that the front end can meet the waveform fitting effect of data equalization, the back end can also be designed with a general low-pass filter to improve the signal-to-interference-plus-noise ratio (SINR) of the data.

[0148] In one possible implementation, such asFigure 14 As shown, the tape drive also includes a gain amplifier

[1013] , and the analog equalization circuit

[1011] is coupled to the digital processing chip

[1012] through the gain amplifier

[1013] . Since the amplitude of the original signal read back from the tape by the read head is too small, the gain amplifier can first amplify the signal output by the analog equalization circuit to ensure that the analog-to-digital converter (ADC) of the digital processing chip can normally acquire the signal. This method is applicable to scenarios where the operational amplifier of the active filter in the analog equalization circuit has limited amplification effect on the original signal, and cannot guarantee the ADC acquisition effect.

[0149] In one possible implementation, the offset between the center frequency of the frequency response curve of the first analog signal and the center frequency of the frequency response curve of the target signal type is less than or equal to 10%. For example, if the center frequency of the frequency response curve of the first analog signal is 18MHz and the center frequency of the frequency response curve of the target signal type is 20MHz, then the offset between their center frequencies is (20-18) / 20 = 10%.

[0150] The following will demonstrate the data equalization effect of the analog equalization circuit in the embodiments of this application, with reference to several accompanying figures.

[0151] For ease of understanding, the following will first explain based on the above. Figure 9B or Figure 10 The diagram illustrates the data equalization effect of the analog equalization circuit designed using the active filter structure shown. Taking the analog equalization circuit primarily performing data equalization on the original analog signal within the 0-40MHz frequency range as an example, ... Figure 15 As shown, curve 1 is the power spectral density curve of the original data, curve 2 is the channel frequency response curve of the original analog signal (curve 2 can be obtained by smoothing curve 1), curve 3 is the frequency response curve of the EPR4 signal (i.e., the target signal type), and curve 4 is the frequency response curve of the analog signal output after data equalization by the analog equalization circuit. From the curve shapes of curves 2, 3, and 4, the standard amplitude values ​​corresponding to different curves at the same frequency point, and the frequency points corresponding to different curves at the same standard amplitude value, it can be seen that curve 4 is closer to curve 3 than curve 2. Understandably, the frequency range for data equalization by the analog equalization circuit can also be other values, such as 0-50MHz, 10-60MHz, etc., which are not specifically limited here.

[0152] The following is based on the above Figure 9B or Figure 10 The active filter structure shown is the same as the one described above. Figure 12AThe diagram illustrates the data equalization effect of an analog equalization circuit obtained by cascading passive filter structures, taking the analog equalization circuit primarily performing data equalization on the original analog signal within the 0-40MHz frequency range as an example. Figure 16 As shown, curve 1 is the power spectral density curve of the original data, curve 2 is the channel frequency response curve of the original analog signal (curve 2 can be obtained by smoothing curve 1), curve 3 is the frequency response curve of the EPR4 signal (i.e., the target signal type), and curve 4 is the frequency response curve of the analog signal output after data equalization by the analog equalization circuit. From the curve shapes of curves 2, 3, and 4, the standard amplitude values ​​corresponding to different curves at the same frequency point, and the frequency points corresponding to different curves at the same standard amplitude value, it can be seen that curve 4 is closer to curve 3 than curve 2. Furthermore, a comparison... Figure 15 The curve 4 shown is Figure 16 As shown in curve 4, it can be observed that in the low-frequency range (e.g., 0-10MHz), Figure 16 Curve 4 is closer to curve 3 because the passive filter supplements the analog signal output by the active filter with data equalization in the low-frequency part.

[0153] The following is based on the above Figure 9B or Figure 10 The active filter structure shown is the same as the one described above. Figure 12B The diagram illustrates the data equalization effect of an analog equalization circuit obtained by cascading passive filter structures, taking the analog equalization circuit primarily performing data equalization on the original analog signal within the 0-40MHz frequency range as an example. Figure 17 As shown, curve 1 is the power spectral density curve of the original data, curve 2 is the channel frequency response curve of the original analog signal (curve 2 can be obtained by smoothing curve 1), curve 3 is the frequency response curve of the EPR4 signal (i.e., the target signal type), and curve 4 is the frequency response curve of the analog signal output after data equalization by the analog equalization circuit. From the curve shapes of curves 2, 3, and 4, the standard amplitude values ​​corresponding to different curves at the same frequency point, and the frequency points corresponding to different curves at the same standard amplitude value, it can be seen that curve 4 is closer to curve 3 than curve 2. Furthermore, a comparison... Figure 16 The curve 4 shown is Figure 17 As shown in curve 4, it can be observed that in the high-frequency range (e.g., 30-40MHz), Figure 17 Curve 4 is closer to curve 3 because, in addition to providing data equalization in the low-frequency range, the passive filter also provides data equalization to the analog signal output by the active filter in the high-frequency range.

[0154] This application also provides a magnetic tape drive, which includes the magnetic tape driver provided in all the above embodiments of this application. It is understood that the functions and roles of the various parts of the magnetic tape driver can be referred to the above descriptions. Figure 4 The specific implementation methods in each embodiment will not be described in detail here.

[0155] This application also provides a storage system, which includes the magnetic tape drive or magnetic tape drive provided in all the above embodiments of this application. It is understood that the functions and roles of the various parts of the magnetic tape drive can be referred to the above descriptions. Figure 4 The specific implementation methods in each embodiment will not be described in detail here.

[0156] This application also provides an analog equalization circuit, which includes a first interface, a second interface, and a processing circuit; the processing circuit includes one or more active filters.

[0157] The first interface is used to receive raw analog signals;

[0158] The processing circuit is used to perform data equalization on the original analog signal to obtain a first analog signal; the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, and the target signal type includes a partial response signal;

[0159] The second interface is used to output the analog signal output by the processing circuit.

[0160] In this embodiment, the analog equalization circuit can be a chip that can perform data equalization on analog signals, converting the channel frequency response of the analog signal into a channel frequency response close to that of the target signal type. In other words, the chip performs data equalization in advance, thereby reducing the order of digital filters required by back-end devices (such as analog front-ends), thereby reducing the computing power requirements of back-end devices (such as tape drives) on digital processing chips, reducing the cost and difficulty of product implementation, and improving data convergence speed, thereby improving processing efficiency.

[0161] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0162] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0163] In the several embodiments provided in this application, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or it may be an electrical, mechanical or other form of connection.

[0164] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A magnetic tape drive, characterized in that, Applied to a magnetic tape drive, the magnetic tape drive includes a read head, an analog equalization circuit, and a digital processing chip; the read head is coupled to the analog equalization circuit, the analog equalization circuit is coupled to the digital processing chip, and the analog equalization circuit includes one or more active filters; wherein... The read head is used to read the original analog signal from the magnetic tape of the magnetic tape drive and output the original analog signal to the analog equalization circuit; The analog equalization circuit is used to perform data equalization on the original analog signal through the one or more active filters to obtain a first analog signal and output it to the digital processing chip; the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, and the target signal type includes a partial response signal. The digital processing chip is used to convert the analog signal output by the analog equalization circuit into a digital signal and perform digital signal processing.

2. The magnetic tape drive as claimed in claim 1, characterized in that, The frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, specifically as follows: The FIR order required to convert the frequency response curve of the first analog signal into the frequency response curve of the target signal type is FIR1, and the FIR order required to convert the frequency response curve of the original analog signal into the frequency response curve of the target signal type is FIR2, wherein FIR1 is less than FIR2.

3. The magnetic tape drive as described in claim 1 or 2, characterized in that, The frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, specifically as follows: At the same frequency, the difference between the amplitude of the frequency response curve corresponding to the first analog signal and the amplitude of the frequency response curve corresponding to the target signal type is less than the difference between the amplitude of the frequency response curve corresponding to the original analog signal and the amplitude of the frequency response curve corresponding to the target signal type. or, At the same amplitude, the difference between the frequency of the frequency response curve corresponding to the first analog signal and the frequency of the frequency response curve corresponding to the target signal type is less than the difference between the frequency of the frequency response curve corresponding to the original analog signal and the frequency of the frequency response curve corresponding to the target signal type.

4. The magnetic tape drive as described in any one of claims 1-3, characterized in that, The active filter includes an operational amplifier, a first DC blocking capacitor, a second DC blocking capacitor, a first RC parallel branch, a second RC parallel branch, a third RC parallel branch, and a fourth RC parallel branch. The first, second, third, and fourth RC parallel branches are each branches formed by at least one resistor and at least one capacitor connected in parallel. The first terminals of the first and second DC blocking capacitors are connected in parallel to the read head. The first terminal of the first RC parallel branch is connected to the second terminal of the first DC blocking capacitor, and the first terminal of the second RC parallel branch is connected to the second terminal of the second DC blocking capacitor. The second terminal of the first RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the second RC parallel branch is connected to the second input terminal of the operational amplifier. The first terminal of the third RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the third RC parallel branch is connected to the first output terminal of the operational amplifier. The first terminal of the fourth RC parallel branch is connected to the second input terminal of the operational amplifier, and the second terminal of the fourth RC parallel branch is connected to the second output terminal of the operational amplifier. The capacitors in the first and second RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The capacitors in the third and fourth RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The first analog signal is output from the first output terminal and the second output terminal of the operational amplifier to the digital processing chip.

5. The magnetic tape drive as described in any one of claims 1-4, characterized in that, The active filter includes an operational amplifier, a third DC blocking capacitor, a fourth DC blocking capacitor, a fifth RC parallel branch, a sixth RC parallel branch, a first resistor, and a second resistor; the fifth RC parallel branch and the sixth RC parallel branch are branches formed by connecting at least one third resistor and at least one capacitor in series, and then connecting them in parallel with at least one fourth resistor; wherein... The first ends of the third and fourth DC blocking capacitors are respectively connected in parallel to the read head; the first end of the fifth RC parallel branch is connected to the second end of the third DC blocking capacitor; the first end of the sixth RC parallel branch is connected to the second end of the fourth DC blocking capacitor; the second end of the fifth RC parallel branch is connected to the first input terminal of the operational amplifier; the second end of the sixth RC parallel branch is connected to the second input terminal of the operational amplifier; the two ends of the first resistor are respectively connected to the first input terminal and the first output terminal of the operational amplifier; the two ends of the second resistor are respectively connected to the second input terminal and the second output terminal of the operational amplifier; the capacitors in the fifth and sixth RC parallel branches have the same capacitance value, and the resistors have the same resistance value; the first resistor and the second resistor have the same resistance value. The first analog signal is output from the first output terminal and the second output terminal of the operational amplifier to the digital processing chip.

6. The magnetic tape drive as claimed in any one of claims 1-5, characterized in that, The analog equalization circuit further includes one or more passive filters; the one or more active filters are connected in series with the one or more passive filters; the analog equalization circuit is specifically used for: The original analog signal is subjected to data equalization by a series circuit of one or more active filters and one or more passive filters to obtain a second analog signal, which is then output to the digital processing chip. The frequency response curve of the second analog signal is closer to the frequency response curve of the target signal type than that of the first analog signal.

7. The magnetic tape drive as claimed in claim 6, characterized in that, The passive filter includes a seventh RC parallel branch, an eighth RC parallel branch, a fifth resistor, and a sixth resistor; the seventh RC parallel branch and the eighth RC parallel branch are branches obtained by connecting at least one resistor and at least one capacitor in parallel; wherein... The first terminals of the seventh RC parallel branch and the eighth RC parallel branch are respectively connected to the output terminal of the active filter, and the second terminals of the seventh RC parallel branch and the eighth RC parallel branch are respectively coupled to the digital processing chip; the fifth resistor is connected between the second terminal of the seventh RC parallel branch and the ground wire, and the sixth resistor is connected between the second terminal of the eighth RC parallel branch and the ground wire; the capacitors in the seventh RC parallel branch and the eighth RC parallel branch have the same capacitance value, and the resistors have the same resistance value; The second analog signal is output from the second end of the seventh RC parallel branch and the eighth RC parallel branch to the digital processing chip.

8. The magnetic tape drive as claimed in claim 7, characterized in that, The passive filter also includes a fifth capacitor and a sixth capacitor, which have the same capacitance value; the fifth capacitor and the fifth resistor are connected in parallel between the second terminal of the seventh RC parallel branch and the ground wire, and the sixth capacitor and the sixth resistor are connected in parallel between the second terminal of the eighth RC parallel branch and the ground wire.

9. The magnetic tape drive as claimed in any one of claims 1-8, characterized in that, The partial response signal includes one or more of the following: Type IV partial response signal PR4, Enhanced Type IV partial response signal EPR4, and Extended Enhanced Type IV partial response signal EEPR4.

10. The magnetic tape drive as claimed in any one of claims 1-9, characterized in that, The tape drive also includes a gain amplifier, and the analog equalization circuit is coupled to the digital processing chip through the gain amplifier.

11. The magnetic tape drive as claimed in any one of claims 1-10, characterized in that, The offset between the center frequency of the frequency response curve of the first analog signal and the center frequency of the frequency response curve of the target signal type is less than or equal to 10%.

12. A magnetic tape drive, characterized in that, The tape drive includes a tape drive as claimed in any one of claims 1-11.

13. A storage system, characterized in that, The storage system includes a magnetic tape drive as described in any one of claims 1-11, or a magnetic tape drive as described in claim 12.

14. An analog equalization circuit, characterized in that, It includes a first interface, a second interface, and a processing circuit; the processing circuit includes one or more active filters; the processing circuit is coupled to the first interface and the second interface respectively; The first interface is used to receive raw analog signals; The processing circuit is used to perform data equalization on the original analog signal through the one or more active filters to obtain a first analog signal; the frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, and the target signal type includes a partial response signal; The second interface is used to output the analog signal output by the processing circuit.

15. The analog equalization circuit as described in claim 14, characterized in that, The frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, specifically as follows: The FIR order required to convert the frequency response curve of the first analog signal into the frequency response curve of the target signal type is FIR1, and the FIR order required to convert the frequency response curve of the original analog signal into the frequency response curve of the target signal type is FIR2, wherein FIR1 is less than FIR2.

16. The analog equalization circuit as described in claim 14 or 15, characterized in that, The frequency response curve of the first analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the original analog signal, specifically as follows: At the same frequency, the difference between the amplitude of the frequency response curve corresponding to the first analog signal and the amplitude of the frequency response curve corresponding to the target signal type is less than the difference between the amplitude of the frequency response curve corresponding to the original analog signal and the amplitude of the frequency response curve corresponding to the target signal type. or, At the same amplitude, the difference between the frequency of the frequency response curve corresponding to the first analog signal and the frequency of the frequency response curve corresponding to the target signal type is less than the difference between the frequency of the frequency response curve corresponding to the original analog signal and the frequency of the frequency response curve corresponding to the target signal type.

17. The analog equalization circuit as described in any one of claims 14-16, characterized in that, The active filter includes an operational amplifier, a first DC blocking capacitor, a second DC blocking capacitor, a first RC parallel branch, a second RC parallel branch, a third RC parallel branch, and a fourth RC parallel branch. The first, second, third, and fourth RC parallel branches are each branches formed by at least one resistor and at least one capacitor connected in parallel. The first terminals of the first and second DC blocking capacitors are connected in parallel to the first interface. The first terminal of the first RC parallel branch is connected to the second terminal of the first DC blocking capacitor, and the first terminal of the second RC parallel branch is connected to the second terminal of the second DC blocking capacitor. The second terminal of the first RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the second RC parallel branch is connected to the second input terminal of the operational amplifier. The first terminal of the third RC parallel branch is connected to the first input terminal of the operational amplifier, and the second terminal of the third RC parallel branch is connected to the first output terminal of the operational amplifier. The first terminal of the fourth RC parallel branch is connected to the second input terminal of the operational amplifier, and the second terminal of the fourth RC parallel branch is connected to the second output terminal of the operational amplifier. The capacitors in the first and second RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The capacitors in the third and fourth RC parallel branches have the same capacitance value, and the resistors have the same resistance value. The first and second output terminals of the operational amplifier are coupled to the second interface. The first analog signal is output from the second interface.

18. The analog equalization circuit as described in any one of claims 14-17, characterized in that, The active filter includes an operational amplifier, a third DC blocking capacitor, a fourth DC blocking capacitor, a fifth RC parallel branch, a sixth RC parallel branch, a first resistor, and a second resistor; the fifth RC parallel branch and the sixth RC parallel branch are branches formed by connecting at least one third resistor and at least one capacitor in series, and then connecting them in parallel with at least one fourth resistor; wherein... The first ends of the third and fourth DC blocking capacitors are respectively connected in parallel to the first interface; the first end of the fifth RC parallel branch is connected to the second end of the third DC blocking capacitor; the first end of the sixth RC parallel branch is connected to the second end of the fourth DC blocking capacitor; the second end of the fifth RC parallel branch is connected to the first input terminal of the operational amplifier; the second end of the sixth RC parallel branch is connected to the second input terminal of the operational amplifier; the two ends of the first resistor are respectively connected to the first input terminal and the first output terminal of the operational amplifier; the two ends of the second resistor are respectively connected to the second input terminal and the second output terminal of the operational amplifier; the capacitors in the fifth and sixth RC parallel branches have the same capacitance value, and the resistors have the same resistance value; the first resistor and the second resistor have the same resistance value; the first output terminal and the second output terminal of the operational amplifier are coupled to the second interface. The first analog signal is output from the second interface.

19. The analog equalization circuit as described in any one of claims 14-18, characterized in that, The processing circuit further includes one or more passive filters; the one or more active filters are connected in series with the one or more passive filters; the processing circuit is specifically used for: The original analog signal is subjected to data equalization by a series circuit of one or more active filters and one or more passive filters to obtain a second analog signal; the frequency response curve of the second analog signal is closer to the frequency response curve of the target signal type than the frequency response curve of the first analog signal.

20. The analog equalization circuit as described in claim 19, characterized in that, The passive filter includes a seventh RC parallel branch, an eighth RC parallel branch, a fifth resistor, and a sixth resistor; the seventh RC parallel branch and the eighth RC parallel branch are branches obtained by connecting at least one resistor and at least one capacitor in parallel; wherein... The first terminals of the seventh RC parallel branch and the eighth RC parallel branch are respectively connected to the output terminal of the active filter, and the second terminals of the seventh RC parallel branch and the eighth RC parallel branch are respectively coupled to the second interface; the fifth resistor is connected between the second terminal of the seventh RC parallel branch and the ground wire, and the sixth resistor is connected between the second terminal of the eighth RC parallel branch and the ground wire; the capacitors in the seventh RC parallel branch and the eighth RC parallel branch have the same capacitance value, and the resistors have the same resistance value; The second analog signal is output from the second interface.

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