A pixel readout circuit and vision sensor

Abstract

The application provides a pixel readout circuit and a visual sensor, the pixel readout circuit comprises an intensity value readout module and an event detection module, inputs of the intensity value readout module and the event detection module are connected with an output of a detector, the intensity value readout module comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an integration capacitor and a sampling capacitor, the event detection module comprises a current-to-voltage unit, an amplification unit, a comparison unit and an asynchronous digital logic unit. The pixel readout circuit provided by the embodiment can be divided into the intensity value readout module and the event detection module, synchronous intensity information readout and asynchronous event detection are supported respectively, and the two modules do not affect each other.

Description

Technical Field

[0001] This application relates to the field of sensors, specifically to a pixel readout circuit and a vision sensor. Background Technology

[0002] In the prior art, dynamic vision sensors mainly include dynamic vision sensors and sensors that combine dynamic and frame-synchronized imaging.

[0003] Dynamic vision sensors, based on an event-driven mechanism, can respond in real time to changes in light intensity in a scene and output data in the form of asynchronous event streams, offering advantages such as low latency and high temporal resolution. However, dynamic vision sensors typically only support asynchronous detection modes and cannot directly provide complete image intensity information, resulting in significant limitations in applications requiring synchronous intensity data.

[0004] Sensors that combine dynamic and frame-synchronized imaging attempt to compensate for the shortcomings of dynamic vision sensors by combining dynamic event detection with the frame-synchronized imaging function of active pixel sensors. However, their architecture usually requires switching between asynchronous event detection and synchronous intensity readout, or relies on complex signal fusion processing, which leads to increased sensor power consumption, data redundancy and reduced real-time performance.

[0005] Therefore, existing technologies still lack a sensor solution that can simultaneously and efficiently support asynchronous event detection and synchronous intensity information readout to meet the stringent requirements of applications such as robot navigation and high-speed target tracking that demand real-time performance and information integrity. Summary of the Invention

[0006] In view of the above problems, this application provides a pixel readout circuit that overcomes or at least partially solves the problem that existing sensors cannot simultaneously and efficiently support asynchronous event detection and synchronous intensity information readout.

[0007] This application provides a pixel readout circuit, including an intensity value readout module and an event detection module, wherein the inputs of the intensity value readout module and the event detection module are both connected to the output of the detector.

[0008] The intensity value readout module includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an integrating capacitor, and a sampling capacitor.

[0009] The source of the first MOSFET is connected to the output of the detector, the drain of the first MOSFET is connected to the first terminal of the integrating capacitor, and the gate of the first MOSFET is connected to the first voltage.

[0010] The source of the second MOSFET is connected to the first terminal of the integrating capacitor, the drain of the second MOSFET is connected to the second voltage, and the gate of the second MOSFET is connected to the third voltage.

[0011] The source of the third MOSFET is connected to the second voltage, the drain of the third MOSFET is connected to the first terminal of the integrating capacitor, and the gate of the third MOSFET is connected to the fourth voltage.

[0012] The source of the fourth MOSFET is connected to the first terminal of the sampling capacitor, the drain of the fourth MOSFET is connected to the first terminal of the integrating capacitor, and the gate of the fourth MOSFET is connected to the fifth voltage.

[0013] The source of the fifth MOSFET is connected to the second voltage, the drain of the fifth MOSFET is connected to the first terminal of the sampling capacitor, and the gate of the fifth MOSFET is connected to the sixth voltage.

[0014] The source of the sixth MOSFET is connected to the drain of the seventh MOSFET, the drain of the sixth MOSFET is connected to the second voltage, and the gate of the sixth MOSFET is connected to the first terminal of the sampling capacitor.

[0015] The source of the seventh MOS transistor serves as the output of the intensity value readout module, the gate of the seventh MOS transistor is connected to the seventh voltage, and the second terminal of the integrating capacitor and the second terminal of the sampling capacitor are grounded.

[0016] The event detection module includes a current-to-voltage conversion unit, an amplification unit, a comparison unit, and an asynchronous digital logic unit. The input of the current-to-voltage conversion unit is connected to the output of the detector; the output of the current-to-voltage conversion unit is connected to the input of the amplification unit; the output of the amplification unit is connected to the input of the comparison unit; the output of the comparison unit is connected to the input of the asynchronous digital logic unit; and the output of the asynchronous digital logic unit serves as the output of the event detection module.

[0017] In this embodiment, when the third MOSFET is turned on, the integrating capacitor charges, and the first MOSFET is used to extract the charge from the integrating capacitor. During the integration time when the third MOSFET is off, the larger the detector's output current, the smaller the voltage across the integrating capacitor. When the fifth MOSFET is turned on, the sampling capacitor resets, and then the fourth MOSFET is turned on, distributing charge between the integrating capacitor and the sampling capacitor. The source voltage of the sixth MOSFET reflects the voltage across the sampling capacitor, which in turn reflects the voltage across the integrating capacitor, which reflects the magnitude of the detector's output current. When the seventh MOSFET is turned on, the source voltage of the sixth MOSFET can be read to obtain the intensity information.

[0018] The current-to-voltage unit can convert the detector's output current into a detection voltage. The amplification unit can amplify the detection voltage for subsequent processing. The comparison unit can determine the magnitude relationship between the detection voltage and the second and third reference voltages, thereby determining the trend of the detector's output current. The asynchronous digital logic unit is used to read out the trend of the detector's output current.

[0019] Thus, the pixel readout circuit provided in this embodiment can be divided into an intensity value readout module and an event detection module, which respectively support synchronous intensity information readout and asynchronous event detection, and the two modules do not affect each other. The intensity value readout module can read and process the intensity information output by the detector in real time, maintaining high precision and high stability. For high light intensity environments, the second MOS transistor can achieve anti-halo readout function, accurately capture large current signals, and avoid signal distortion caused by charge saturation or overload. This allows the pixel readout circuit provided in this application to operate stably under extreme lighting conditions, making it suitable for high-demand scenarios such as high-brightness monitoring, industrial inspection, and night vision imaging. The event detection module has high-speed and high-sensitivity dynamic change detection capabilities, can quickly respond to changes in light intensity and output data, and capture small or rapid dynamic changes in the scene. It has extremely low latency and fast data output capabilities, making the pixel readout circuit provided in this application suitable for high-dynamic and real-time applications such as high-speed moving object detection, dynamic scene analysis, autonomous driving, and robot vision.

[0020] In one alternative approach, the first MOSFET operates in a subthreshold state.

[0021] In one alternative configuration, the first, second, sixth, and seventh MOSFETs are all NMOS transistors; the third, fourth, and fifth MOSFETs are PMOS transistors.

[0022] In one alternative configuration, the third, fourth, fifth, sixth, and seventh MOSFETs are all digital MOSFETs.

[0023] In one alternative embodiment, the current-to-voltage unit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, and a thirteenth MOSFET.

[0024] The source of the eighth MOSFET is connected to the second voltage, the drain of the eighth MOSFET is connected to the drain of the ninth MOSFET, and the gate of the eighth MOSFET is connected to the first bias voltage. The source of the ninth MOSFET is connected to the drain of the thirteenth MOSFET, and the gate of the ninth MOSFET is connected to the second bias voltage. The source of the tenth MOSFET is connected to the second voltage, the drain of the tenth MOSFET is connected to the source of the twelfth MOSFET, and the gate of the tenth MOSFET is connected to the third bias voltage. The source of the eleventh MOSFET is connected to the detector output, the drain of the eleventh MOSFET is connected to the source of the first MOSFET, and the gate of the eleventh MOSFET is connected to the drain of the eighth MOSFET. The drain of the twelfth MOSFET is grounded, and the gate of the twelfth MOSFET is connected to the source of the ninth MOSFET. The source of the thirteenth MOSFET is grounded, and the gate of the thirteenth MOSFET is connected to the detector output.

[0025] In one alternative embodiment, the amplification unit includes a first capacitor, a second capacitor, a third capacitor, a third transmission gate, a fourteenth MOSFET, and an amplifier.

[0026] In this configuration, the first terminal of the first capacitor is connected to the first terminal of the third capacitor, the second terminal of the third capacitor is connected to the drain of the tenth MOSFET, and the second terminal of the first capacitor is connected to the output terminal of the amplifier. The first terminal of the second capacitor is connected to the second terminal of the first capacitor, the second terminal of the second capacitor is also connected to the output terminal of the third transmission gate, and the second terminal of the second capacitor is connected to the source of the fourteenth MOSFET. The drain of the fourteenth MOSFET is connected to the first terminal of the first capacitor, and the gate of the fourteenth MOSFET is connected to the eighth voltage. The first input terminal of the amplifier is connected to the first terminal of the third capacitor, and the second input terminal of the amplifier is connected to the first reference voltage. The input terminal of the third transmission gate is connected to the first terminal of the third capacitor, the output terminal of the third transmission gate is connected to the output terminal of the amplifier, the first control terminal of the third transmission gate is connected to the first output terminal of the asynchronous digital logic unit, and the second control terminal of the third transmission gate is connected to the second output terminal of the asynchronous digital logic unit.

[0027] In one alternative embodiment, the comparison unit includes a first comparator and a second comparator, the first input terminal of the first comparator is connected to the output terminal of the amplifier, the second input terminal of the first comparator is connected to a second reference voltage, and the output terminal of the first comparator is connected to the first input terminal of the asynchronous digital logic unit.

[0028] The first input terminal of the second comparator is connected to the output terminal of the amplifier, the second input terminal of the second comparator is connected to the third reference voltage, and the output terminal of the second comparator is connected to the second input terminal of the asynchronous digital logic unit.

[0029] In one alternative embodiment, the asynchronous digital logic unit includes a first latch subunit, a second latch subunit, a first transmission gate, a second transmission gate, a NOR gate, an inverter, and a fifteenth MOS transistor.

[0030] The first input terminal of the first latch subunit serves as the first input terminal of the asynchronous digital logic unit. The second input terminal of the first latch subunit receives a reset signal. The output terminal of the first latch subunit is connected to the first input terminal of the NOR gate.

[0031] The first input terminal of the second latch subunit serves as the second input terminal of the asynchronous digital logic unit. The second input terminal of the second latch subunit receives a reset signal, and the output terminal of the second latch subunit is connected to the second input terminal of the NOR gate.

[0032] The output of the NOR gate serves as the first output of the asynchronous digital logic unit. The output of the NOR gate is also connected to the input of the inverter, and the output of the inverter serves as the second output of the asynchronous digital logic unit.

[0033] The output of the inverter is also connected to the gate of the fifteenth MOS transistor, the drain of the fifteenth MOS transistor is connected to the arbitrator, and the source of the fifteenth MOS transistor is grounded.

[0034] The output of the first latch subunit is also connected to the input of the first transmission gate. The first control terminal of the first transmission gate receives the first response signal, the second control terminal of the first transmission gate receives the second response signal, and the output of the first transmission gate serves as the first output of the event detection module.

[0035] The output of the second latch subunit is also connected to the input of the second transmission gate. The first control terminal of the second transmission gate receives the third response signal, the second control terminal of the second transmission gate receives the fourth response signal, and the output of the second transmission gate serves as the second output of the event detection module.

[0036] In some embodiments, the eighth MOSFET is a PMOS transistor, the ninth MOSFET is an NMOS transistor, the tenth MOSFET is a PMOS transistor, the eleventh MOSFET is an NMOS transistor, the twelfth MOSFET is a PMOS transistor, and the thirteenth MOSFET is an NMOS transistor.

[0037] A second aspect of this application provides a visual sensor, including the pixel readout circuit provided in the first aspect of this application.

[0038] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This application provides a pixel readout circuit as an embodiment.

[0041] Figure 2 A schematic diagram of a first comparator provided for some embodiments of this application.

[0042] Figure 3 This is a schematic diagram of another first comparator provided for some embodiments of this application.

[0043] Figure 4 This is a schematic diagram of yet another first comparator provided for some embodiments of this application.

[0044] Figure 5 This is a circuit diagram of an asynchronous digital logic unit provided for some embodiments of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0047] The terms "comprising" and "having," and any variations thereof, used in the specification, claims, and drawings of this application are intended to cover without excluding other meanings. The words "a" or "an" do not exclude the existence of multiple entities.

[0048] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0050] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0051] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, "connection" or "linkage" in mechanical structures can refer to a physical connection, such as a fixed connection, for example, a connection fixed by fasteners, such as a connection fixed by screws, bolts, or other fasteners; a physical connection can also be a detachable connection, such as a snap-fit ​​or interlocking connection; a physical connection can also be an integral connection, such as a connection formed by welding, bonding, or integral molding. In circuit structures, "connection" or "linkage" can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected; it can also refer to the internal connection of two components. Signal connection can refer not only to signal connection through a circuit but also to signal connection through a media, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0052] Figure 1 A pixel readout circuit provided in an embodiment of this application, referenced Figure 1 The pixel readout circuit provided in this application embodiment includes an intensity value readout module (a) and an event detection module (b), the inputs of which are connected to the output of the detector V.

[0053] The intensity value reading module (a) includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, and an integrating capacitor C.int and sampling capacitor C sh .

[0054] The source of the first MOSFET M1 is connected to the output of the detector V, and the drain of the first MOSFET M1 is connected to the integrating capacitor C. int The first terminal is connected, and the gate of the first MOSFET M1 is connected to the first voltage GPOL. The first MOSFET M1 is a direct injection transistor.

[0055] The source of the second MOSFET M2 and the integrating capacitor C int The first terminal is connected, the drain of the second MOSFET M2 is connected to the second voltage VDDA, and the gate of the second MOSFET M2 is connected to the third voltage ANTIBLM. For example, the third voltage ANTIBLM can be 1.7V.

[0056] It is worth noting that the first MOSFET is in a subthreshold operating state. Furthermore, by controlling the value of the first voltage GPOL, the first MOSFET can be made to operate in a subthreshold state. For example, the first voltage GPOL can be 1.4 volts (V).

[0057] The source of the third MOSFET M3 is connected to the second voltage VDDA, and the drain of the third MOSFET M3 is connected to the integrating capacitor C. int The first terminal is connected, and the gate of the third MOSFET M3 is connected to the fourth voltage INTRST. The second voltage VDDA can be 2.5V.

[0058] The source of the fourth MOSFET M4 and the sampling capacitor C sh The first terminal is connected to the drain of the fourth MOSFET M4 and the integrating capacitor C. int The first terminal is connected, and the gate of the fourth MOSFET M4 is connected to the fifth voltage SHS.

[0059] The source of the fifth MOSFET M5 is connected to the second voltage VDDA, and the drain of the fifth MOSFET M5 is connected to the sampling capacitor C. sh The first terminal is connected, and the gate of the fifth MOSFET M5 is connected to the sixth voltage SHRST.

[0060] The source of the sixth MOSFET M6 is connected to the drain of the seventh MOSFET M7. The drain of the sixth MOSFET M6 is connected to the second voltage VDDA. The gate of the sixth MOSFET M6 is connected to the sampling capacitor C. sh The first end is connected.

[0061] The source of the seventh MOSFET M7 serves as the output of the intensity value readout module, and the gate of the seventh MOSFET M7 is connected to the seventh voltage ROWSEL. The integrating capacitor C... int The second terminal is connected to the sampling capacitor C shThe second terminal is grounded to VSSA.

[0062] In practical applications, the first MOSFET M1, the second MOSFET M2, the sixth MOSFET M6, and the seventh MOSFET M7 are all NMOS transistors; the third MOSFET M3, the fourth MOSFET M4, and the fifth MOSFET M5 are PMOS transistors.

[0063] In practical applications, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 are all digital MOSFETs. This allows control over the high- or low-level transitions of the fourth voltage INTRST, the fifth voltage SHS, the sixth voltage SHRST, and the seventh voltage ROWSEL within a specific timing sequence.

[0064] The event detection module (b) includes a current-to-voltage unit 01, an amplification unit 02, a comparison unit 03, and an asynchronous digital logic unit 04. The input of the current-to-voltage unit 01 is connected to the output of the detector V, the output of the current-to-voltage unit 01 is connected to the input of the amplification unit 02, the output of the amplification unit 02 is connected to the input of the comparison unit 03, the output of the comparison unit 03 is connected to the input of the asynchronous digital logic unit 04, and the output of the asynchronous digital logic unit 04 serves as the output of the event detection module (b).

[0065] In this embodiment, the output of the detector refers to the induced current generated by the detector. For example, an intensity value reading operation can be performed every 100 microseconds, and the intensity value read can be considered as the magnitude of the induced current generated by the detector.

[0066] In this embodiment, when the third MOS transistor M3 is turned on, for example, when the fourth voltage INTRST is high, the integrating capacitor C... int During charging, the first MOSFET M1 is used to draw the integrating capacitor C. int The charge on the capacitor. During the integration time when the third MOSFET M3 is off, the larger the output current of the detector v, the greater the integration capacitor C. int The smaller the voltage across the terminals, the lower the voltage. When the fifth MOSFET M5 is turned on, the sampling capacitor C... sh The system is reset, which then turns on the fourth MOSFET M4, and the integrating capacitor C... int and sampling capacitor C sh The charge is distributed between these intervals and isolated from the next integration time; for example, an integration time could be 80 microseconds. This is because the source voltage of the sixth MOSFET M6 and the sampling capacitor C... sh The voltages at both ends differ by a maximum gate-source voltage; therefore, the source voltage of the sixth MOSFET M6 can reflect the voltage across the sampling capacitor C. sh The voltage across the two ends. Also, because the sampling capacitor C... shThe voltage across the terminals can reflect the performance of the integrating capacitor C. int The voltage across the terminals, the integrating capacitor C int The voltage across the terminals reflects the magnitude of the output current of detector V; that is, the source voltage of the sixth MOSFET M6 expresses the magnitude of the output current of detector V. The seventh MOSFET M7 is used to control the readout of intensity information. For example, when the seventh MOSFET M7 is turned on, the source voltage of the sixth MOSFET M6 can be read to obtain the intensity information.

[0067] It is worth noting that when the first MOSFET is in subthreshold operation, the second MOSFET M2 can be an anti-corona transistor. Thus, if the output current of the detector V is too large, the first MOSFET M1 will quickly deplete the integrating capacitor C. int When a charge is applied, the second MOSFET M2 turns on. For example, the integrating capacitor C int The minimum voltage across the terminals can be 800 millivolts. Therefore, issues caused by the integrating capacitor C can be avoided. int Signal distortion caused by charge saturation or overload enables the pixel readout circuit provided in this application to operate stably under extreme lighting conditions.

[0068] It should be noted that in practical applications, by adjusting the switching timing of the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the seventh MOSFET M7, the intensity value reading module (a) can achieve the function of integrating first and then reading the intensity information or integrating while reading the intensity information.

[0069] The current-to-voltage unit 01 can convert the output current of the detector V into a detection voltage. The amplification unit 02 can amplify the detection voltage for subsequent processing. The comparison unit 03 can determine the magnitude relationship between the detection voltage and the second reference voltage VREF2 and the third reference voltage VREF3, thereby determining the trend of the output current of the detector V. The asynchronous digital logic unit 04 is used to read the trend of the output current of the detector V.

[0070] Thus, the pixel readout circuit provided in this embodiment can be divided into an intensity value readout module (a) and an event detection module (b), which respectively support synchronous intensity information readout and asynchronous event detection, and the two modules do not affect each other. The intensity value readout module (a) can read and process the intensity information output by the detector V in real time, maintaining high accuracy and high stability. For high light intensity environments, the second MOS transistor M2 can be used to achieve anti-halo readout function, accurately capture large current signals, and avoid the impact of the integrating capacitor C. intSignal distortion caused by charge saturation or overload allows the pixel readout circuit provided in this application to operate stably under extreme lighting conditions, making it suitable for demanding scenarios such as high-brightness monitoring, industrial inspection, and night vision imaging. The event detection module (b) possesses high-speed and high-sensitivity dynamic change detection capabilities, enabling it to quickly respond to and output changes in light intensity, capturing minute or rapid dynamic changes in the scene. It features extremely low latency and fast data output capabilities, making the pixel readout circuit provided in this application suitable for applications with high dynamic and real-time requirements, such as the detection of high-speed moving objects, dynamic scene analysis, autonomous driving, and robot vision.

[0071] In some embodiments, the current-to-voltage conversion unit 01 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, and a thirteenth MOSFET M13. The source of the eighth MOSFET M8 is connected to the second voltage VDDA, the drain of the eighth MOSFET M8 is connected to the drain of the ninth MOSFET M9, and the gate of the eighth MOSFET M8 is connected to the first bias voltage VB1. The source of the ninth MOSFET M9 is connected to the drain of the thirteenth MOSFET M13, and the gate of the ninth MOSFET M9 is connected to the second bias voltage VB2. The source of the tenth MOSFET M10 is connected to the second voltage VDDA, the drain of the tenth MOSFET M10 is connected to the source of the twelfth MOSFET M12, and the gate of the tenth MOSFET M10 is connected to the third bias voltage VB3. The source of the eleventh MOSFET M11 is connected to the output of the detector V, and the source of the eleventh MOSFET M11 serves as the input of the event detection module (b). The drain of the eleventh MOSFET M11 is connected to the source of the first MOSFET M1, and the gate of the eleventh MOSFET M11 is connected to the drain of the eighth MOSFET M8. The drain of the twelfth MOSFET M12 is grounded to VSSA, and the gate of the twelfth MOSFET M12 is connected to the source of the ninth MOSFET M9. The source of the thirteenth MOSFET M13 is grounded, and the gate of the thirteenth MOSFET M13 is connected to the output of detector V. The eleventh MOSFET M11 is in subthreshold operation.

[0072] In this embodiment, the first bias voltage VB1 provides a bias current to enable the ninth MOSFET M9 to operate, and the second bias voltage VB2 provides a bias current to enable the twelfth MOSFET M12 to operate. The twelfth MOSFET M12 is connected to the ninth MOSFET M9 to form a source follower structure, which can isolate the influence of the subsequent circuit on the preceding circuit. The thirteenth MOSFET M13 is used to make the voltage output of the current-to-voltage unit fluctuate within a certain range. By reasonably adjusting the bias values ​​of the first bias voltage VB1, the second bias voltage VB2, and the third bias voltage VB3, current detection and conversion from the picoampere level to hundreds of nanoamperes of the detector V can be achieved.

[0073] In practical applications, the eighth MOSFET M8 is a PMOS transistor, the ninth MOSFET M9 is an NMOS transistor, the tenth MOSFET M10 is a PMOS transistor, the eleventh MOSFET M11 is an NMOS transistor, the twelfth MOSFET M12 is a PMOS transistor, and the thirteenth MOSFET M13 is an NMOS transistor.

[0074] The amplification unit 02 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a third transmission gate TG3, a fourteenth MOS transistor M14, and an amplifier A.

[0075] In this configuration, the first terminal of the first capacitor C1 is connected to the first terminal of the third capacitor C3, the second terminal of the third capacitor C3 is connected to the drain of the tenth MOSFET M10, and the second terminal of the first capacitor C1 is connected to the output terminal of amplifier A. The first terminal of the second capacitor C2 is connected to the second terminal of the first capacitor C1, the second terminal of the second capacitor C2 is also connected to the output terminal of the third transmission gate TG3, and the second terminal of the second capacitor C2 is connected to the source of the fourteenth MOSFET M14. The drain of the fourteenth MOSFET M14 is connected to the first terminal of the first capacitor C1, and the gate of the fourteenth MOSFET M14 is connected to the eighth voltage GAIN. The first input terminal of amplifier A is connected to the first terminal of the third capacitor C3, and the second input terminal of amplifier A is connected to the first reference voltage VREF1. The input terminal of the third transmission gate TG3 is connected to the first terminal of the third capacitor C3, the output terminal of the third transmission gate TG3 is connected to the output terminal of amplifier A, the first control terminal C of the third transmission gate TG3 is connected to the first output terminal EA of the asynchronous digital logic unit 04, and the second control terminal C' of the third transmission gate TG3 is connected to the second output terminal EN of the asynchronous digital logic unit 04.

[0076] The fourteenth MOSFET, M14, is a PMOS transistor and a digital MOSFET. Its gate voltage is externally input, and the eighth voltage, GAIN, can be either high or low. The second capacitor, C2, is a gain adjustment capacitor. When the front-end signal changes significantly, the fourteenth MOSFET, M14, can be turned on to reduce the detection sensitivity. In this case, the voltage amplification gain is C3 / (C1 + C2) times, enabling it to detect large signal changes. Conversely, when the front-end signal changes slightly, the fourteenth MOSFET, M14, can be turned on to increase the detection sensitivity. In this case, the voltage amplification gain is C3 / C1 times.

[0077] The comparison unit 03 includes a first comparator 031 and a second comparator 032. The first input terminal of the first comparator 031 is connected to the output terminal of amplifier A, the second input terminal of the first comparator 031 is connected to the second reference voltage VREF2, and the output terminal of the first comparator 031 is connected to the first input terminal of the asynchronous digital logic unit 04.

[0078] The first input terminal of the second comparator 032 is connected to the output terminal of amplifier A, the second input terminal of the second comparator 032 is connected to the third reference voltage VREF3, and the output terminal of the second comparator 032 is connected to the second input terminal of the asynchronous digital logic unit 04.

[0079] The second reference voltage VREF2 refers to the voltage rise threshold voltage, and the third reference voltage VREF3 refers to the voltage fall threshold voltage. For example, when the voltage value output by amplifier A is greater than the second reference voltage VREF2, the current of detector V can be considered to be increasing. When the voltage value output by amplifier A is less than the third reference voltage VREF3, the current of detector V can be considered to be decreasing.

[0080] Figure 2 A schematic diagram of a first comparator provided for some embodiments of this application. (See also...) Figure 2 The first comparator 031 may include the sixteenth MOSFET M16, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, and the twentieth MOSFET M20.

[0081] The gate of the sixteenth MOSFET M16 is connected to the gate of the seventeenth MOSFET M17. The gate of the sixteenth MOSFET M16 is also connected to the drain of the eighteenth MOSFET M18. The sources of both the sixteenth MOSFET M16 and the seventeenth MOSFET M17 are connected to the second voltage VDDA. The drain of the seventeenth MOSFET M17 is connected to the drain of the nineteenth MOSFET M19, serving as the output of the first comparator 031. The gate of the nineteenth MOSFET M19 serves as the first input of the first comparator 031. The gate of the eighteenth MOSFET M18 is connected to the second reference voltage VREF2, serving as the second input of the first comparator 031. The source of the eighteenth MOSFET M18 is connected to the drain of the twentieth MOSFET M20. The source of the twentieth MOSFET M20 is grounded, its gate is connected to the fourth bias voltage VB4, and its drain is connected to the source of the nineteenth MOSFET M19. The sixteenth MOSFET M16 and the seventeenth MOSFET M17 are PMOS transistors, while the eighteenth MOSFET M18, the nineteenth MOSFET M19, and the twentieth MOSFET M20 are NMOS transistors.

[0082] In this embodiment, the second reference voltage VREF2 and the third reference voltage VREF3 can be uniformly input from an external source, allowing for highly flexible adjustment. The first comparator 031 adopts a five-transistor fully differential plus common-source two-stage structure, which has the advantages of high gain and large bandwidth. This allows the first comparator 031 to respond quickly when the input signal reaches a certain threshold, improving the sensitivity and switching speed of the first comparator 031. Furthermore, this structure has strong common-mode rejection capability, effectively suppressing common-mode noise and interference, thereby improving the stability and accuracy of the first comparator 031 in noisy environments. It is suitable for applications requiring good signal symmetry and strong interference suppression.

[0083] Figure 3 A schematic diagram of another first comparator provided for some embodiments of this application. (See reference) Figure 3 The first comparator 031 may include a 21st MOSFET M21 and a 22nd MOSFET M22. The gate of the 21st MOSFET M21 is the first input terminal of the first comparator 031, and the gate of the 22nd MOSFET M22 is the second input terminal. The source of the 21st MOSFET M21 is connected to a second voltage VDDA, and the drains of the 21st MOSFET M21 and the 22nd MOSFET M22 are connected. The drains of the 21st MOSFET M21 and the 22nd MOSFET M22 together serve as the output terminal of the first comparator 031. The source of the 22nd MOSFET M22 is grounded. The 21st MOSFET M21 is a PMOS transistor, and the 22nd MOSFET M22 is an NMOS transistor.

[0084] Figure 4 This is a schematic diagram of yet another first comparator provided for some embodiments of this application. (See reference...) Figure 4 The first comparator 031 may include the twenty-third MOSFET M23, the twenty-fourth MOSFET M24, the twenty-fifth MOSFET M25, the twenty-sixth MOSFET M26, the twenty-seventh MOSFET M27, the twenty-eighth MOSFET M28, and the twenty-ninth MOSFET M29.

[0085] The gate of the 23rd MOSFET M23 is connected to the gate of the 24th MOSFET M24. The gate of the 23rd MOSFET M23 is also connected to the drain of the 25th MOSFET M25. The gate of the 23rd MOSFET M23 is also connected to the drain of the 23rd MOSFET M24. The sources of both the 23rd MOSFET M23 and the 24th MOSFET M24 are connected to the second voltage VDDA. The drain of the 24th MOSFET M24 is connected to the drain of the 26th MOSFET M26. The drain of the 26th MOSFET M26 is also connected to the gate of the 28th MOSFET M28. The gate of the 26th MOSFET M26 serves as the first input terminal of the first comparator 031. The gate of the 25th MOSFET M25 is connected to the second reference voltage VREF2. The gate of the 25th MOSFET M25 serves as the second input terminal of the first comparator 031. The source of the 25th MOSFET M25 is connected to the drain of the 27th MOSFET M27. The source of the 27th MOSFET M27 is grounded, its gate is connected to the fifth bias voltage VB5, and its drain is connected to the source of the 26th MOSFET M26. The source of the 28th MOSFET M28 is also connected to the second voltage VDDA, and its drain is also connected to the drain of the 29th MOSFET M29. The drains of the 28th MOSFET M28 and the 29th MOSFET M29 serve as the output terminals of the first comparator 031. The gate of the 29th MOSFET M29 is connected to the fifth bias voltage VB5, and its source is grounded.

[0086] The 23rd MOSFET M23, the 24th MOSFET M24, and the 28th MOSFET M28 are PMOS transistors, while the 25th MOSFET M25, the 26th MOSFET M26, the 27th MOSFET M27, and the 29th MOSFET M29 are NMOS transistors.

[0087] It should be noted that the second comparator 032 has the same structure as the first comparator 031, and the structure of the second comparator 032 will not be described again in this application.

[0088] Figure 5 A circuit diagram of an asynchronous digital logic unit provided for some embodiments of this application, see reference. Figure 5 The asynchronous digital logic unit 04 includes a first latch subunit RS_P, a second latch subunit RS_N, a first transmission gate TG1, a second transmission gate TG2, a NOR gate, an inverter INV, and a fifteenth MOS transistor M15.

[0089] The first input terminal of the first latch subunit RS_P serves as the first input terminal of the asynchronous digital logic unit 04. The second input terminal of the first latch subunit RS_P receives the reset signal RST. The output terminal of the first latch subunit RS_P is connected to the first input terminal of the NOR gate. If the output terminal of the first latch subunit RS_P outputs an ON event, it indicates that the output current of the detector V is in a state of increasing current.

[0090] The first input terminal of the second latch subunit RS_N serves as the second input terminal of the asynchronous digital logic unit 04. The second input terminal of the second latch subunit RS_N receives the reset signal RST'. The output terminal of the second latch subunit RS_N is connected to the second input terminal of the NOR gate. If the output terminal of the second latch subunit RS_N outputs an OFF event, it indicates that the output current of the detector V is in a state of decreasing current.

[0091] The output of the NOR gate serves as the first output of the asynchronous digital logic unit 04. The output of the NOR gate is also connected to the input of the inverter INV, and the output of the inverter INV serves as the second output of the asynchronous digital logic unit 04.

[0092] For example, if the output of the first latch subunit RS_P does not output, and the output of the second latch subunit RS_N outputs an OFF event, then the output of the NOR gate is 0, and the output of the inverter INV is 1. At this time, the third transmission gate TG3 is closed, cutting off the output of the amplifier unit 02 to wait for the next detection.

[0093] For example, if the output of the first latch subunit RS_P outputs an ON event, and the output of the second latch subunit RS_N does not output, then the output of the NOR gate is 0, and the output of the inverter INV is 1. At this time, the third transmission gate TG3 is closed, cutting off the output of the amplifier unit 02 to wait for the next detection.

[0094] For example, if the output of the first latch subunit RS_P does not output, and the output of the second latch subunit RS_N does not output, then the output of the NOR gate is 1, and the output of the inverter INV is 0. This indicates that the output current of the detector V has not changed significantly during one detection time. At this time, the third transmission gate TG3 is opened to continue detecting whether the current of the detector V has changed.

[0095] The output of inverter INV is also connected to the gate of the fifteenth MOSFET M15, the drain of the fifteenth MOSFET M15 is connected to the arbitrator, and the source of the fifteenth MOSFET M15 is grounded. The drain of the fifteenth MOSFET M15 sends a request signal to the arbitrator.

[0096] The output of the first latch subunit RS_P is also connected to the input of the first transmission gate TG1. The first control terminal of the first transmission gate TG1 receives the first response signal, the second control terminal of the first transmission gate TG1 receives the second response signal, and the output of the first transmission gate TG1 serves as the first output of the event detection module (b).

[0097] The output of the second latch subunit RS_N is also connected to the input of the second transmission gate TG2. The first control terminal of the second transmission gate TG2 receives the third response signal, the second control terminal of the second transmission gate TG2 receives the fourth response signal, and the output of the second transmission gate TG2 serves as the second output of the event detection module (b).

[0098] It is understood that the first and second control terminals of the first transmission gate TG1 and the first and second control terminals of the second transmission gate TG2 are all connected to the arbitrator. When the output terminal of the first latch subunit RS_P outputs an ON event, the drain of the fifteenth MOS transistor M15 sends a request signal to the arbitrator. When the first transmission gate TG1 receives the first and second response signals from the arbitrator, the first transmission gate TG1 outputs an ON event to realize the output of the event detection module (b).

[0099] When the output terminal of the second latch subunit RS_N outputs an OFF event, the drain of the fifteenth MOS transistor M15 sends a request signal to the arbitrator. When the second transmission gate TG2 receives the third and fourth response signals from the arbitrator, the second transmission gate TG2 outputs the OFF event to realize the output of the event detection module (b).

[0100] Understandably, when the asynchronous digital logic unit 04 receives the signal output by the comparison unit 03, the first latch subunit RS_P or the second latch subunit RS_N immediately latches the signal and sends a request signal to the arbitrator through the drain of the fifteenth MOS transistor M15. After receiving the arbitrator's response signal, the latched ON or OFF event is read out through the first transmission gate TG1 or the second transmission gate TG2, and then an external reset signal RST or reset signal RST' is input, thus completing the detection of one event. The entire process takes no more than 1 microsecond. Moreover, the embodiments of this application have optimized the bandwidth, improving the response speed of the signal link and enabling stable capture of changing signals within a 1MHz frequency range.

[0101] In practical applications, the connection aperture between the detector V and the pixel readout circuit can extend to the top metal layer of the pixel readout circuit to facilitate the growth and coupling of the detector V. The pixel readout circuit provided in this application embodiment has reserved connection ports for various types of detectors, which can be adapted to photovoltaic detectors such as silicon photodiodes, MoTe2 detectors, and mercury cadmium telluride detectors. It can also support photoconductive detectors made of novel two-dimensional materials such as MoS2, thereby achieving high detector matching capability and improving the scalability and application range of the system.

[0102] Another embodiment of this application also provides a visual sensor, including the pixel readout circuit provided in the foregoing embodiments of this application, which can support synchronous intensity information readout and asynchronous event detection.

[0103] Those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0104] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A pixel readout circuit, characterized in that, The circuit includes: An intensity value readout module and an event detection module are provided, with the inputs of both modules connected to the output of the detector. The intensity value readout module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an integrating capacitor, and a sampling capacitor; The source of the first MOS transistor is connected to the output of the detector, the drain of the first MOS transistor is connected to the first terminal of the integrating capacitor, and the gate of the first MOS transistor is connected to the first voltage. The source of the second MOS transistor is connected to the first terminal of the integrating capacitor, the drain of the second MOS transistor is connected to the second voltage, and the gate of the second MOS transistor is connected to the third voltage. The source of the third MOS transistor is connected to the second voltage, the drain of the third MOS transistor is connected to the first terminal of the integrating capacitor, and the gate of the third MOS transistor is connected to the fourth voltage. The source of the fourth MOS transistor is connected to the first terminal of the sampling capacitor, the drain of the fourth MOS transistor is connected to the first terminal of the integrating capacitor, and the gate of the fourth MOS transistor is connected to the fifth voltage. The source of the fifth MOS transistor is connected to the second voltage, the drain of the fifth MOS transistor is connected to the first terminal of the sampling capacitor, and the gate of the fifth MOS transistor is connected to the sixth voltage. The source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor, the drain of the sixth MOS transistor is connected to the second voltage, and the gate of the sixth MOS transistor is connected to the first terminal of the sampling capacitor. The source of the seventh MOS transistor serves as the output of the intensity value readout module, and the gate of the seventh MOS transistor is connected to the seventh voltage. The second terminal of the integrating capacitor is grounded; The event detection module includes a current-to-voltage conversion unit, an amplification unit, a comparison unit, and an asynchronous digital logic unit; The input of the current-to-voltage unit is connected to the output of the detector, the output of the current-to-voltage unit is connected to the input of the amplification unit, the output of the amplification unit is connected to the input of the comparison unit, the output of the comparison unit is connected to the input of the asynchronous digital logic unit, and the output of the asynchronous digital logic unit serves as the output of the event detection module.

2. The circuit according to claim 1, characterized in that, The first MOSFET is in a subthreshold operating state.

3. The circuit according to claim 1, characterized in that, The first MOS transistor, the second MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are all NMOS transistors; the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are PMOS transistors.

4. The circuit according to claim 1, characterized in that, The third, fourth, fifth, sixth, and seventh MOS transistors are all digital MOS transistors.

5. The circuit according to claim 1, characterized in that, The current-to-voltage conversion unit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, and a thirteenth MOSFET; The source of the eighth MOS transistor is connected to the second voltage, the drain of the eighth MOS transistor is connected to the drain of the ninth MOS transistor, and the gate of the eighth MOS transistor is connected to the first bias voltage. The source of the ninth MOS transistor is connected to the drain of the thirteenth MOS transistor, and the gate of the ninth MOS transistor is connected to the second bias voltage. The source of the tenth MOS transistor is connected to the second voltage, the drain of the tenth MOS transistor is connected to the source of the twelfth MOS transistor, and the gate of the tenth MOS transistor is connected to the third bias voltage. The source of the eleventh MOS transistor is connected to the output of the detector, the drain of the eleventh MOS transistor is connected to the source of the first MOS transistor, and the gate of the eleventh MOS transistor is connected to the drain of the eighth MOS transistor. The drain of the twelfth MOS transistor is grounded, and the gate of the twelfth MOS transistor is connected to the source of the ninth MOS transistor. The source of the thirteenth MOS transistor is grounded, and the gate of the thirteenth MOS transistor is connected to the output of the detector.

6. The circuit according to claim 5, characterized in that, The amplification unit includes a first capacitor, a second capacitor, a third capacitor, a third transmission gate, a fourteenth MOS transistor, and an amplifier; Wherein, the first terminal of the first capacitor is connected to the first terminal of the third capacitor, the second terminal of the third capacitor is connected to the drain of the tenth MOS transistor, and the second terminal of the first capacitor is connected to the output terminal of the amplifier; The first terminal of the second capacitor is connected to the second terminal of the first capacitor, the second terminal of the second capacitor is also connected to the output terminal of the third transmission gate, and the second terminal of the second capacitor is connected to the source of the fourteenth MOS transistor. The drain of the fourteenth MOS transistor is connected to the first terminal of the first capacitor, and the gate of the fourteenth MOS transistor is connected to the eighth voltage. The first input terminal of the amplifier is connected to the first terminal of the third capacitor, and the second input terminal of the amplifier is connected to the first reference voltage. The input terminal of the third transmission gate is connected to the first terminal of the third capacitor, the output terminal of the third transmission gate is connected to the output terminal of the amplifier, the first control terminal of the third transmission gate is connected to the first output terminal of the asynchronous digital logic unit, and the second control terminal of the third transmission gate is connected to the second output terminal of the asynchronous digital logic unit.

7. The circuit according to claim 6, characterized in that, The comparison unit includes a first comparator and a second comparator. The first input terminal of the first comparator is connected to the output terminal of the amplifier, the second input terminal of the first comparator is connected to a second reference voltage, and the output terminal of the first comparator is connected to the first input terminal of the asynchronous digital logic unit. The first input terminal of the second comparator is connected to the output terminal of the amplifier, the second input terminal of the second comparator is connected to the third reference voltage, and the output terminal of the second comparator is connected to the second input terminal of the asynchronous digital logic unit.

8. The circuit according to claim 7, characterized in that, The asynchronous digital logic unit includes a first latch subunit, a second latch subunit, a first transmission gate, a second transmission gate, a NOR gate, an inverter, and a fifteenth MOS transistor; The first input terminal of the first latch subunit serves as the first input terminal of the asynchronous digital logic unit, the second input terminal of the first latch subunit receives a reset signal, and the output terminal of the first latch subunit is connected to the first input terminal of the NOR gate. The first input terminal of the second latch subunit serves as the second input terminal of the asynchronous digital logic unit. A reset signal is input to the second input terminal of the second latch subunit. The output terminal of the second latch subunit is connected to the second input terminal of the NOR gate. The output of the NOR gate serves as the first output of the asynchronous digital logic unit. The output of the NOR gate is also connected to the input of the inverter. The output of the inverter also serves as the second output of the asynchronous digital logic unit. The output terminal of the inverter is also connected to the gate of the fifteenth MOS transistor, the drain of the fifteenth MOS transistor is connected to the arbitrator, and the source of the fifteenth MOS transistor is grounded. The output terminal of the first latch subunit is also connected to the input terminal of the first transmission gate. The first control terminal of the first transmission gate receives a first response signal, the second control terminal of the first transmission gate receives a second response signal, and the output terminal of the first transmission gate serves as the first output terminal of the event detection module. The output of the second latch subunit is also connected to the input of the second transmission gate. The first control terminal of the second transmission gate receives the third response signal, the second control terminal of the second transmission gate receives the fourth response signal, and the output of the second transmission gate serves as the second output of the event detection module.

9. The circuit according to claim 5, characterized in that, The eighth MOS transistor is a PMOS transistor, the ninth MOS transistor is an NMOS transistor, the tenth MOS transistor is a PMOS transistor, the eleventh MOS transistor is an NMOS transistor, the twelfth MOS transistor is a PMOS transistor, and the thirteenth MOS transistor is an NMOS transistor.

10. A vision sensor, characterized in that, Includes the pixel readout circuit as described in any one of claims 1-9.

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