Display panel and display device

Abstract

Embodiments of the present disclosure provide a display panel and a display device, relating to the technical field of display, for improving the anti-extrusion performance of the transition area. The display panel comprises a display area, a frame area located at least one side of the display area, a binding area, a substrate, a gate layer and a source-drain metal layer. The binding area is located at a side of the frame area away from the display area and is bent to the back of the display panel. A part of the frame area close to the binding area is provided with a transition area. In the frame area, the gate layer comprises a plurality of first signal lines. In the binding area, the source-drain metal layer comprises a plurality of second signal lines. In the transition area, the plurality of first signal lines and the plurality of second signal lines are one-to-one corresponding and electrically connected. In the transition area, the display panel further comprises a support layer. In the orthographic projection towards the substrate, the support layer has an outer boundary, and the area where the first signal lines and the second signal lines are electrically connected is located within the area enclosed by the outer boundary of the support layer. The above-mentioned display panel is used for displaying images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have been widely used in the display field due to their advantages such as self-illumination, low driving voltage, high luminous efficiency, fast response speed, and flexible display capabilities. To achieve a higher screen-to-body ratio in OLED display panels, flexible pad bending (PB) technology has been developed. This technology involves setting a bonding area on one side of the display area of ​​the display panel. After the signal lines that provide control signals to the display area converge at the bonding area, the bonding area can be folded back onto the back of the display panel, taking advantage of the flexibility of the OLED display panel.

[0003] However, different film layers have different bending properties. In order to improve the bending performance of the bonding area, it is necessary to design a signal line adapter to realize the signal line layer switching. The different settings of the signal line adapter structure have an important impact on the compression resistance of the signal line adapter structure. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel and display device for improving the compression resistance of the signal line transfer structure in the transfer area.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a display panel is provided, the display panel comprising: a display area and a bezel area, a bonding area, a substrate, a gate layer, and a source / drain metal layer located on at least one side of the display area, the bonding area being located on the side of the bezel area away from the display area and bent to the back of the display panel; a transition area is provided in the portion of the bezel area near the bonding area; the gate layer and the source / drain metal layer are sequentially disposed in a direction away from the substrate; in the bezel area, the gate layer includes a plurality of first signal lines; in the bonding area, the source / drain metal layer includes a plurality of second signal lines; in the transition area, the plurality of first signal lines and the plurality of second signal lines are electrically connected in a one-to-one correspondence; wherein, in the transition area, the display panel further comprises: a support layer; in a projected onto the substrate, the support layer has an outer boundary, and the area where the first signal lines and the second signal lines are electrically connected is located within the area enclosed by the outer boundary of the support layer.

[0007] In the aforementioned display panel, the support layer can improve the resistance of the transition area to extrusion deformation.

[0008] In some embodiments, the source / drain metal layer includes: a first source / drain metal layer and a second source / drain metal layer, the first source / drain metal layer and the second source / drain metal layer being disposed along a direction away from the substrate; a plurality of second signal lines being located in the second source / drain metal layer; in the transition region, the first source / drain metal layer is provided with a plurality of transition lines, and the plurality of first signal lines, the plurality of transition lines and the plurality of second signal lines are electrically connected one-to-one.

[0009] In some embodiments, in a projection onto the substrate, the plurality of the transition lines are located within the area enclosed by the outer boundary of the support layer.

[0010] In some embodiments, in orthographic projection onto the substrate, the minimum distance between the adapter line and the outer boundary of the support layer ranges from 1µm to 10µm.

[0011] In some embodiments, the display panel further includes: a light-shielding layer located on the side of the gate layer near the substrate, and a support layer located on the light-shielding layer.

[0012] In some embodiments, the light-shielding layer further includes: a portion located in the display area and a connecting portion located in the border area, the connecting portion being located between the support layer and the portion of the light-shielding layer located in the display area, and the connecting portion connecting the support layer and the portion of the light-shielding layer located in the display area.

[0013] In some embodiments, the connecting portion is mesh-like.

[0014] In some embodiments, in the border area, the first source / drain metal layer further includes a power signal line, and the support layer is electrically connected to the power signal line.

[0015] In some embodiments, in the border region, the first source / drain metal layer further includes a reference voltage line, and the support layer is electrically connected to the reference voltage line.

[0016] In some embodiments, the thickness of the support layer ranges from 0.1µm to 0.5µm.

[0017] In some embodiments, the display panel further includes: a third source / drain metal layer located on the side of the second source / drain metal layer away from the substrate, and the support layer located on the third source / drain metal layer.

[0018] In some embodiments, the support layer is provided with a plurality of vent holes penetrating the support layer.

[0019] In some embodiments, the ratio of the area of ​​the vent hole to the area of ​​the support layer ranges from 1 / 9 to 1.

[0020] In some embodiments, the display panel further includes: an inorganic encapsulation layer located on the side of the second source / drain metal layer away from the substrate, and a support layer located on the inorganic encapsulation layer.

[0021] In some embodiments, the display panel further includes: a touch layer located on the side of the second source / drain metal layer away from the substrate, and a support layer located on the touch layer.

[0022] In some embodiments, the display panel further includes: a passivation layer and a first planarization layer located between the first source / drain metal layer and the second source / drain metal layer, the passivation layer and the first planarization layer being disposed in a direction away from the substrate; the adapter line and the second signal line being electrically connected through a second adapter hole penetrating the first planarization layer and the passivation layer; wherein, in a positive projection onto the substrate, the passivation layer covers the area of ​​the adapter region other than the area where the second adapter hole is located.

[0023] In some embodiments, the display panel further includes a passivation layer located between the first source / drain metal layer and the second source / drain metal layer; wherein, in a positive projection onto the substrate, the passivation layer does not overlap with the transition region.

[0024] In some embodiments, the display panel further includes: a first insulating layer and a first planarization layer, wherein the first insulating layer is located between the gate layer and the first source / drain metal layer, and the first signal line and the adapter line are electrically connected through a first adapter hole penetrating the first insulating layer; the adapter line and the second signal line are electrically connected through a second adapter hole penetrating the first planarization layer; wherein, in orthographic projection onto the substrate, the minimum spacing between the passivation layer and the target adapter hole ranges from 1.5µm to 6µm, and the target adapter hole is the adapter hole of the first adapter hole and the second adapter hole that is closest to the passivation layer.

[0025] In some embodiments, the display panel further includes: a first insulating layer and a first planarization layer; the adapter cable includes: a first segment and a second segment connected along a first direction; the first signal line and the first segment are electrically connected through a first adapter hole penetrating the first insulating layer, and the second segment and the second signal line are electrically connected through a second adapter hole penetrating the first planarization layer; the first direction is the extension direction of the first signal line; the first adapter hole and the second adapter hole connected to one adapter cable are arranged along the first direction; along a second direction, the first adapter hole and the second adapter hole connected to different adapter cables are alternately arranged; the second direction intersects the first direction; wherein, the dimension of the first segment in the second direction is smaller than the dimension of the second segment in the second direction.

[0026] In some embodiments, the thickness of the support layer ranges from 0.1µm to 3µm.

[0027] In some embodiments, the display panel includes at least two of the following: a light-shielding layer, a third source / drain metal layer, an inorganic encapsulation layer, and a touch layer, wherein the support layer is disposed on at least two of the following: the light-shielding layer, the third source / drain metal layer, the inorganic encapsulation layer, and the touch layer.

[0028] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments and a driver chip, the driver chip being used to drive the display panel to display.

[0029] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0032] Figure 2 According to Figure 1 An enlarged view of point D of the provided display device;

[0033] Figure 3 This is a structural diagram of a display panel according to some embodiments;

[0034] Figure 4 According to Figure 1 A structural diagram of a signal line at point D in the provided display device;

[0035] Figure 5 This is a structural diagram of a transition area according to some embodiments;

[0036] Figure 6 This is a structural diagram of another transition area according to some embodiments;

[0037] Figure 7 According to Figure 6 The provided cross-sectional view of the transition area along section line EE;

[0038] Figure 8 This is a structural diagram of the first gate layer according to some embodiments;

[0039] Figure 9 This is a structural diagram of a first gate layer and a second gate layer stack according to some embodiments;

[0040] Figure 10 This is a structural diagram of a stack of a first gate layer, a second gate layer, and a first via according to some embodiments;

[0041] Figure 11 This is a structural diagram of a stacked first gate layer, second gate layer, first via, and first source / drain metal layer according to some embodiments;

[0042] Figure 12 This is a structural diagram of a first gate layer, a second gate layer, a first via, a first source / drain metal layer, and a second via stacked according to some embodiments;

[0043] Figure 13 This is a structural diagram of another transition area according to some embodiments;

[0044] Figure 14 According to Figure 13 The provided cross-sectional view of the transition area along section line FF;

[0045] Figure 15 According to Figure 13 The provided cross-sectional view of the transition area along section line GG;

[0046] Figure 16 This is a structural diagram of a light-shielding layer according to some embodiments;

[0047] Figure 17 This is a structural diagram of another light-shielding layer according to some embodiments;

[0048] Figure 18This is a structural diagram of a light-shielding layer, a first gate layer, and a second gate layer stacked according to some embodiments;

[0049] Figure 19 This is a structural diagram of a stacked light-shielding layer, a first gate layer, a second gate layer, a first source / drain metal layer, and a second source / drain metal layer according to some embodiments;

[0050] Figure 20 According to Figure 19 The provided cross-sectional view of the display panel along section line HH;

[0051] Figure 21 This is a structural diagram of the support layer according to some embodiments;

[0052] Figure 22 This is a structural diagram of the support layer and the first gate layer stack according to some embodiments;

[0053] Figure 23 This is a structural diagram of a support layer, a first gate layer, and a second gate layer stacked according to some embodiments;

[0054] Figure 24 This is a structural diagram of a stack of a support layer, a first gate layer, a second gate layer, and an interlayer insulating layer according to some embodiments;

[0055] Figure 25 This is a structural diagram of a stacked support layer, a first gate layer, a second gate layer, an interlayer insulating layer, and a first source / drain metal layer according to some embodiments;

[0056] Figure 26 This is a structural diagram of a stack of a support layer, a first gate layer, a second gate layer, an interlayer insulating layer, a first source / drain metal layer, and a passivation layer according to some embodiments;

[0057] Figure 27 This is a structural diagram of a stack of a support layer, a first gate layer, a second gate layer, an interlayer insulating layer, a first source / drain metal layer, a passivation layer, and a first planarization layer according to some embodiments;

[0058] Figure 28 This is a structural diagram of a stacked support layer, a first gate layer, a second gate layer, an interlayer insulating layer, a first source / drain metal layer, a passivation layer, a first planarization layer, and a second source / drain metal layer according to some embodiments;

[0059] Figure 29 This is a structural diagram of another transition area according to some embodiments;

[0060] Figure 30 According to Figure 29 The provided cross-sectional view of the transition area along the section line MM;

[0061] Figure 31 According to Figure 6 A cross-sectional view of the transition area along the cross-section line NN is provided;

[0062] Figure 32 According to Figure 6 Another cross-sectional view of the transition area along section line NN is provided;

[0063] Figure 33 According to Figure 6 Another cross-sectional view of the transition area along the cross-section line NN is provided. Detailed Implementation

[0064] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0065] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0066] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0067] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0068] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0069] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0070] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0071] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0072] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0073] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0074] like Figure 1and Figure 2 As shown, an embodiment of this disclosure provides a display device 1000, which includes a display panel 100 and a driver chip 200. The driver chip 200 drives the display panel 100 to perform a display. The driver chip 200 is a driver IC, for example, the driver IC includes a source driver. For example, the display panel 100 includes a plurality of sub-pixels arranged in an array, the sub-pixels being the smallest unit of display on the display panel 100. The driver chip 200 is configured to provide driving signals to each sub-pixel in the display panel 100, for example, the driving signals include data signals, to drive the display panel 100 to perform a display.

[0075] For example, such as Figure 1 As shown, the display panel 100 includes a display area AA and a border area BB located on at least one side of the display area AA. An embodiment of this disclosure is illustrated by the border area BB surrounding the display area AA.

[0076] To achieve a higher screen-to-body ratio for OLED display panels, a flexible pad bending (PB) technology was developed. This technology involves setting a bonding area CC on the side of the bezel area BB away from the display area AA. After the signal lines that provide control signals to the display area AA converge in the bonding area CC, the bonding area CC can be folded back to the back of the display panel 100 due to the flexibility of the OLED display panel.

[0077] For example, a binding area CC is connected to the bezel area BB located below the display area AA. The lower side of the display area AA can be referred to as the lower Pad side. The binding area CC is used to bend to the back of the display panel 100 to reduce the size of the lower Pad side. After bending, the structure of the display panel 100 is as follows: Figure 3 As shown.

[0078] For example, such as Figure 2 and Figure 4 As shown, the circuit of the display area AA includes a pixel driving circuit, etc., and the circuit of the border area BB includes a GOA (Gate on Array, array substrate row driving) circuit 30, etc. The circuits of the display area AA and the border area BB are coupled to the driving chip 200 to drive the display area AA to realize the display function.

[0079] For example, the display panel 100 includes: a first gate line Gate1, a second gate line Gate2, a power signal line VDD, a reference voltage line VSS, a data signal line Data, and an initialization signal line Vinit. The first gate line Gate1 is used to transmit a first gate signal to the pixel driving circuit, the second gate line Gate2 is used to transmit a second gate signal to the pixel driving circuit, the power signal line VDD is used to transmit a first voltage signal to the pixel driving circuit, the reference voltage line VSS is used to transmit a second voltage signal to the pixel driving circuit, the voltage of the first voltage signal can be greater than the voltage of the second voltage signal, the data signal line Data is used to transmit a data signal to the pixel driving circuit, and the initialization signal line Vinit is used to transmit an initialization signal to the pixel driving circuit.

[0080] The first gate line Gate1, the second gate line Gate2, the power signal line VDD, the reference voltage line VSS, and the initialization signal line Vinit, etc., converge in the binding area CC through the frame area BB on the lower Pad side, and then bend to the back of the display panel 100.

[0081] For example, such as Figure 2 and Figure 4 As shown, the bezel area BB on the lower Pad side includes a first fan-out area S1, and the portion of the display device 1000 bent to the back of the display panel 100 also includes a second fan-out area S2, an electrostatic discharge area S3, a high-multiplexing area S4, and a third fan-out area S5 arranged in sequence to enable the signal lines to be connected to the driver chip 200.

[0082] However, as Figures 2-4 As shown, different film layers have different bending properties. For example, aluminum (Al) and organic layers are resistant to bending, but molybdenum (Mo), inorganic silicon nitride (SiNx) or silicon oxide (SiOx) are not resistant to bending. Therefore, a transition area B1 is provided in the frame area BB on the lower Pad side to realize the switching of signal lines.

[0083] For example, both the GOA circuit 30 and the data signal line Data are connected using Mo. To improve the bending performance of the bonding area CC, a transition for the signal line needs to be designed to achieve layer switching. Different transition structures have a significant impact on the compression resistance of the transition structure. By improving the compression resistance of the transition area B1, the problem of film layer breakage can be effectively prevented, thereby ensuring the effective electrical connection of the signal line.

[0084] To more clearly illustrate how to improve the compression resistance of the transition area B1, the following exemplarily describes the film layer structure of the display panel 100. It is understood that some embodiments of this disclosure are not limited thereto.

[0085] In some embodiments, such as Figure 5 , Figure 6 and Figure 7 As shown, the display panel 100 includes: a substrate 101 and a gate layer 103, a first insulating layer 41, and a source / drain metal layer SD located on one side of the substrate. In the bezel region BB, the gate layer 103 includes multiple first signal lines G1; in the bonding region CC, the source / drain metal layer SD includes multiple second signal lines 181; in the transition region B1, the multiple first signal lines G1 and the multiple second signal lines 181 are electrically connected in a one-to-one correspondence.

[0086] For example, substrate 101 may include a first flexible material layer, a first inorganic material layer, and a second flexible material layer. The first and second flexible material layers may be made of polyimide (PI), and the first inorganic material layer may be made of silicon nitride or silicon oxide, etc., to improve the substrate's resistance to water and oxygen.

[0087] For example, an active layer (not shown) is also disposed between the substrate 101 and the gate layer 103.

[0088] For example, the material of the gate layer 103 includes Mo.

[0089] For example, the gate layer 103 includes a first gate layer 1031 and a second gate layer 1032, and the plurality of first signal lines G1 include a plurality of first gate lines Gate1 and a plurality of second gate lines Gate2. The plurality of first gate lines Gate1 are located in the first gate layer 1031, and the plurality of second gate lines Gate2 are located in the second gate layer 1032. Both the first gate lines Gate1 and the second gate lines Gate2 extend along a first direction Y. Along a second direction X, the first gate lines Gate1 and the second gate lines Gate2 are alternately arranged, and the second direction X intersects the first direction Y.

[0090] For example, the second direction X intersects the first direction Y, meaning there is an angle between them. For example, the second direction X and the first direction Y are perpendicular to each other. For example, the angle between the second direction X and the first direction Y is an acute angle. The embodiments of this disclosure are exemplified by the second direction X being perpendicular to the first direction Y.

[0091] For example, the display panel 100 further includes a gate insulating layer 102 located between the active layer and the gate layer 103. The gate insulating layer 102 includes a first gate insulating layer and a second gate insulating layer. The first gate insulating layer, the first gate layer 1031, the second gate insulating layer and the second gate layer 1032 are sequentially disposed in a direction away from the substrate 101.

[0092] For example, the display panel 100 further includes an interlayer insulating layer 104 located between the second gate layer 1032 and the source / drain metal layer SD. Therefore, the first insulating layer 41 between the first gate layer 1031 and the source / drain metal layer SD includes a second gate insulating layer and an interlayer insulating layer 104, and the first insulating layer 41 between the second gate layer 1032 and the source / drain metal layer SD is the interlayer insulating layer 104.

[0093] For example, the material of the source / drain metal layer SD includes Al.

[0094] For example, the source / drain metal layer SD includes: a first source / drain metal layer 105 and a second source / drain metal layer 108, the first source / drain metal layer 105 and the second source / drain metal layer 108 being disposed in a direction away from the substrate 101; and a plurality of second signal lines 181 located in the second source / drain metal layer 108.

[0095] For example, the display panel 100 further includes a passivation layer 106 and a first planarization layer 107 located between the first source / drain metal layer 105 and the second source / drain metal layer 108, wherein the passivation layer 106 and the first planarization layer 107 are disposed in a direction away from the substrate 101.

[0096] In other words, such as Figures 5-7 As shown, the display panel 100 includes: a substrate 101 and an active layer (not shown in the figure), a first gate insulating layer, a first gate layer 1031, a second gate insulating layer, a second gate layer 1032, an interlayer insulating layer 104, a first source / drain metal layer 105, a passivation layer 106, a first planarization layer 107 and a second source / drain metal layer 108, and a second planarization layer 109 located on the side of the second source / drain metal layer 108 away from the substrate 101.

[0097] For example, in the transition area B1, the first source-drain metal layer 105 is provided with multiple transition lines 151. The first signal line G1 of the gate layer 103 is electrically connected to the second signal line 181 of the second source-drain metal layer 108 through the transition lines 151 to realize the switching of signal lines.

[0098] In some examples, such as Figure 5 and Figure 7As shown, the first signal line G1 and the adapter line 151 are electrically connected through the first adapter hole K1 penetrating the first insulating layer 41, and the adapter line 151 and the second signal line 181 are electrically connected through the second adapter hole K2 penetrating the first planarization layer 107. It should be noted that in the transition area B1 where the first signal line G1 and the second signal line 181 switch layers, a passivation layer 106 may be provided, a partial passivation layer 106 may be provided, or no passivation layer 106 may be provided. When a passivation layer 106 is provided, the second adapter hole K2 also penetrates the passivation layer 106. Regarding the setting of the passivation layer 106, please refer to the following content, which will not be described in detail here.

[0099] For example, the multiple first signal lines G1 include multiple first gate lines Gate1 and multiple second gate lines Gate2. For ease of description, the multiple adapter lines 151 are divided into multiple first adapter lines 1511 and multiple second adapter lines 1512 extending along the first direction Y. The multiple second signal lines 181 are used to bend to the back of the display panel 100, and the multiple second signal lines 181 are divided into multiple first bend lines 1811 and multiple second bend lines 1812.

[0100] For example, the first adapter wire 1511 is electrically connected to the first gate wire Gate1 through a plurality of first adapter holes K1 spaced apart along the first direction Y, and the first adapter wire 1511 is electrically connected to the first bent wire 1811 through a second adapter hole K2. The first adapter hole K1 can be referred to as a first type via H1, and the first insulating layer 41 through which the first type via H1 penetrates includes the second gate insulating layer and the interlayer insulating layer 104.

[0101] For example, the second adapter wire 1512 is electrically connected to the second gate wire Gate2 through a plurality of first adapter holes K1 spaced apart along the first direction Y, and the second adapter wire 1512 is electrically connected to the second bent wire 1812 through the second adapter hole K2. The first adapter hole K1 can be referred to as the second type of via H2, and the first insulating layer 41 penetrated by the second type of via H2 is the interlayer insulating layer 104.

[0102] Since the first insulating layer 41 is an inorganic insulating layer, the first adapter hole K1 is generally small in size, and in order to ensure the effectiveness of the signal connection, there are multiple first adapter holes K1. Since the second adapter hole K2 penetrates the first planarization layer 107, which is an organic insulating layer, the second adapter hole K2 is larger in size.

[0103] That is, the size of the second adapter hole K2 in the first direction Y is greater than the size of the first adapter hole K1 in the first direction Y, and the size of the second adapter hole K2 in the second direction X is greater than the size of the first adapter hole K1 in the second direction X.

[0104] Wherein, when the width of the first signal line G1 of the gate layer 103 is large, for example, the width of the first signal line G1 is in the range of 15μm to 20μm, the arrangement of the first adapter hole K1 and the second adapter hole K2 along the first direction Y is consistent. For example, combined with Figure 4 The first adapter hole K1 is closer to the display area AA than the second adapter hole K2. The first adapter hole K1 and the second adapter hole K2, which are connected to different adapter cables 151, are arranged in the same direction.

[0105] In other examples, such as Figure 6 and Figure 7 As shown, in order to further achieve a narrow bezel for the display panel 100, the width of the signal lines will be further reduced, and adjacent signal lines will be designed with staggered alignment to achieve effective signal line connection.

[0106] For example, the adapter cable 151 includes: a first segment 151a and a second segment 151b connected along a first direction Y, the first signal line G1 and the first segment 151a being electrically connected through a first adapter hole K1 penetrating the first insulating layer 41, and the second segment 151b and the second signal line 181 being electrically connected through a second adapter hole K2 penetrating the first planarization layer 107.

[0107] The first adapter hole K1 and the second adapter hole K2, which are connected to an adapter cable 151, are arranged along the first direction Y. Along the second direction X, the first adapter hole K1 and the second adapter hole K2, which are connected to different adapter cables 151, are arranged alternately.

[0108] In other words, in two adjacent adapter lines 151, the arrangement of the first segment 151a and the second segment 151b along the first direction Y of one adapter line 151 is opposite to the arrangement of the first segment 151a and the second segment 151b along the first direction Y of the other adapter line 151, so as to achieve the staggered design of adjacent signal lines.

[0109] Since the size of the first adapter hole K1 is smaller than that of the second adapter hole K2, the size of the first segment 151a in the second direction X can be set to be smaller than that of the second segment 151b in the second direction X, so as to increase the arrangement density of the adapter cable 151, which is more conducive to the narrow bezel of the display panel 100.

[0110] To facilitate understanding of the membrane layer configuration in transition region B1, the following diagram illustrates the membrane layer structure of transition region B1. Figure 8 This is a structural diagram of the first gate layer 1031 according to some embodiments. Figure 9 This is a structural diagram of the stacked first gate layer 1031 and second gate layer 1032 according to some embodiments. Figure 10 This is a structural diagram showing the stacked first gate layer 1031, second gate layer 1032, and first transition via K1 according to some embodiments. Figure 11 This is a structural diagram showing the stacked first gate layer 1031, second gate layer 1032, first via K1, and first source / drain metal layer 105 according to some embodiments. Figure 12 This is a structural diagram of a stacked first gate layer 1031, second gate layer 1032, first transition hole K1, first source / drain metal layer 105, and second transition hole K2 according to some embodiments.

[0111] pass Figure 11 and Figure 6 It can be seen that the misalignment design of adjacent signal lines leads to a differentiated boundary of the adapter 151. Specifically, a differentiated boundary is formed at the connection point L1 between the first segment 151a and the second segment 151b, which makes the membrane layer more prone to breakage. Therefore, improving the compression resistance of the adapter area B1 is of great significance in effectively preventing membrane layer breakage.

[0112] Based on this, such as Figure 13 and Figure 14 As shown, in the transition area B1, the display panel 100 further includes a support layer 50; in the orthographic projection onto the substrate 101, the support layer 50 has an outer boundary J1, and the area where the first signal line G1 and the second signal line 181 are electrically connected is located within the area enclosed by the outer boundary J1 of the support layer 50.

[0113] In other words, in the transition area B1, in addition to the functional layers such as the first signal line G1, the second signal line 181, and the transition line 151, as well as the insulating layer between these functional layers, a support layer 50 is also provided to support the transition area B1. The support layer 50 can be made of a high-strength material and supports the membrane layer of the transition area B1 to improve the resistance of the transition area B1, which has the function of signal line transition layer, to extrusion deformation.

[0114] The support layer 50 may have a closed outer boundary J1, meaning that the support layer 50 may be an independent pattern located within a certain film layer; or, in addition to the portion located in the transition region B1, the support layer 50 may also include a portion located outside the transition region B1, for example, this portion is used to provide a stable electrical signal to the support layer 50. This example can be referred to later. Figure 17 The support layer 50 shown is located on the light-shielding layer 51, and the support layer 50 and the light-shielding layer 51 are integrated in the display area AA. At this time, the part of the light-shielding layer 51 located in the transition area B1 is the support layer 50. The boundary of the transition area B1 can be understood as the outer boundary J1 of the support layer 50. Please refer to the following content for details. It will not be described in detail here.

[0115] For example, the material of the support layer 50 can be molybdenum, silicon nitride or silicon oxide, etc., and there is no limitation here.

[0116] For example, such as Figure 14 As shown, the display panel 100 further includes a light-shielding layer 51, which is located on the side of the gate layer 103 near the substrate 101, and a support layer 50 is located on the light-shielding layer 51.

[0117] In other examples, such as Figure 29 and Figure 30 As shown, the display panel 100 also includes a third source / drain metal layer 52, which is located on the side of the second source / drain metal layer 108 away from the substrate 101, and a support layer 50 is located on the third source / drain metal layer 52.

[0118] In some other examples, such as Figure 13 and Figure 15 As shown, the display panel 100 further includes an inorganic encapsulation layer 53, which is located on the side of the second source / drain metal layer 108 away from the substrate 101, and a support layer 50 is located on the inorganic encapsulation layer 53.

[0119] In some other examples, such as Figure 13 and Figure 15 As shown, the display panel 100 also includes a touch layer 54, which is located on the side of the second source / drain metal layer 108 away from the substrate 101, and a support layer 50 is located on the touch layer 54.

[0120] For example, the number of support layers 50 is one, or the number of support layers 50 is multiple, that is, the display panel 100 is provided with multiple support layers 50, and the support layers 50 may be located in at least two of the light-shielding layer 51, the third source-drain metal layer 52, the inorganic encapsulation layer 53 and the touch layer 54 respectively.

[0121] The existing film layer of the display panel 100 is used as a support layer 50 in the transition area B1 to facilitate the formation of the support layer 50.

[0122] Regarding the data on how the support layer 50 can improve the resistance of the transition area B1 to extrusion deformation, please refer to the following content; it will not be described in detail here.

[0123] In some embodiments, such as Figure 14 As shown, the thickness d1 of the support layer 50 ranges from 0.1µm to 3µm.

[0124] For example, the thickness d1 of the support layer 50 can be 0.1µm, 0.2µm, 0.3µm, 0.5µm, 0.8µm, 1µm, 1.3µm, 1.5µm, 1.7µm, 1.9µm, 2µm, 2.3µm, 2.6µm, 2.8µm or 3µm, etc., and there is no limit here.

[0125] By setting the thickness d1 of the support layer 50 to range from 0.1µm to 3µm, the influence of the support layer 50 on the flatness of other membrane layers is minimized, and it provides good support for the transition area B1, thereby improving the resistance of the transition area B1 to extrusion deformation.

[0126] In some embodiments, such as Figure 13 and Figure 14 As shown, in the orthographic projection onto the substrate 101, multiple adapter lines 151 are located within the area enclosed by the outer boundary J1 of the support layer 50.

[0127] In other words, such as Figures 12-14 As shown, when multiple adapter lines 151 are provided in the transition area B1, in order to ensure the effective connection of the adapter lines 151, the size of the adapter lines 151 will exceed the area where multiple first adapter holes K1 and second adapter holes K2 are located. The multiple adapter lines 151 are located within the area enclosed by the outer boundary J1 of the support layer 50, so as to improve the support effect of the support layer 50 on each film layer of the transition area B1.

[0128] In some embodiments, such as Figure 14 As shown, in the orthographic projection onto the substrate 101, the minimum distance d2 between the adapter line 151 and the outer boundary J1 of the support layer 50 ranges from 1µm to 10µm.

[0129] For example, in the orthographic projection onto the substrate 101, the minimum distance d2 between the adapter line 151 and the outer boundary J1 of the support layer 50 is 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm or 10µm, etc., and there is no limit here.

[0130] By setting the minimum distance d2 between the transition line 151 and the outer boundary J1 of the support layer 50 in the orthogonal projection onto the substrate 101 to be in the range of 1µm to 10µm, the support effect of the support layer 50 on each film layer of the transition area B1 is improved.

[0131] The following provides specific examples of the support layer 50 located in different membrane layers.

[0132] In some embodiments, such as Figure 13 and Figure 14 As shown, the support layer 50 is located on the light-shielding layer 51.

[0133] For example, compared with no support layer 50, the strength of the transition area B1 is increased by about 5% when the support layer 50 is provided in the light-shielding layer 51.

[0134] For example, such as Figure 16As shown, in the display area AA, a light-shielding layer 51 is provided in the area where each sub-pixel is located. The light-shielding layer 51 is used to connect a stable signal to ensure the stability of the transistor characteristics of the pixel driving circuit of the display area AA.

[0135] For example, when the support layer 50 is located on the light-shielding layer 51, the thickness d1 of the support layer 50 is in the range of 0.1µm to 0.5µm. For example, the thickness d1 of the support layer 50 is 0.1µm, 0.2µm, 0.3µm, 0.4µm or 0.5µm, etc., and there is no limitation here.

[0136] Since the light-shielding layer 51 is located on the side of the gate layer 103 close to the substrate 101, the presence of the support layer 50 will raise the film layer on the side away from the substrate 101. Therefore, the support layer 50 has a thinner thickness d1 and a higher Young's modulus to provide sufficient support.

[0137] In some embodiments, such as Figure 14 , Figure 17 and Figure 18 As shown, the light-shielding layer 51 has a portion located in the display area AA. The light-shielding layer 51 also includes a connecting portion 51a located in the border area BB. The connecting portion 51a is located between the support layer 50 and the portion of the light-shielding layer 51 located in the display area AA, and the connecting portion 51a connects the support layer 50 and the portion of the light-shielding layer 51 located in the display area AA.

[0138] In other words, the portion of the support layer 50 located in the display area AA is connected to the light-shielding layer 51, and the support layer 50 is connected to a stable signal. Figure 4 As can be seen, power signal line VDD and reference voltage line VSS are set on both sides of the data signal line Data. Writing the data signal will cause the signal of the signal line around the data signal line Data to fluctuate. By providing a stable electrical signal to the support layer 50, the problem of signal fluctuation caused by the surrounding signals during the writing of the data signal can be effectively solved.

[0139] For example, the connecting part 51a is mesh-like, such as multiple mesh lines arranged in a longitudinal and transverse manner, which can improve the stability of the signal accessed by the support layer 50.

[0140] For example, the portion of the light-shielding layer 51 located in the display area AA, the connecting portion 51a, and the support layer 50 can be an integral structure. It should be noted that, in this example, the portion of the light-shielding layer 51 located in the transition area B1 is the support layer 50, and the boundary of the transition area B1 can be understood as the outer boundary J1 of the support layer 50.

[0141] In some embodiments, such as Figure 4 , Figure 14 , Figure 19 and Figure 20As shown, in the border area BB, the first source / drain metal layer 105 also includes a power signal line VDD, and the support layer 50 is electrically connected to the power signal line VDD.

[0142] For example, a power signal line VDD located on the first source-drain metal layer 105 is provided in the border area BB of the transition area B1 near the display area AA. The power signal line VDD in this area can be a large pattern to reduce the voltage drop of the first voltage signal transmission. The support layer 50 can be electrically connected to the power signal line VDD in this area.

[0143] For example, in the bonding area CC, the power signal line VDD is located in the second source-drain metal layer 108. In the transition area B1, the portion of the power signal line VDD located in the first source-drain metal layer 105 overlaps with the portion of the power signal line VDD located in the second source-drain metal layer 108.

[0144] For example, a third adapter hole K3 is provided on the interlayer insulation layer 104, and the support layer 50 is electrically connected to the power signal line VDD through the third adapter hole K3.

[0145] To facilitate understanding of the signal line settings in the adapter area B1 and the bonding area CC Figures 21-28 According to Figure 4 A diagram showing the film structure of the transition area B1 and the bonding area CC at point I of the provided display device 1000. Figure 21 This is a structural diagram of the support layer 50 according to some embodiments. Figure 22 This is a structural diagram of the stacked support layer 50 and first gate layer 1031 according to some embodiments. Figure 23 This is a structural diagram of a support layer 50, a first gate layer 1031, and a second gate layer 1032 stacked according to some embodiments. Exemplarily, in this region, the data signal line Data is located in the second gate layer 1032.

[0146] Figure 24 This is a structural diagram showing the stacked support layer 50, first gate layer 1031, second gate layer 1032, and interlayer insulating layer 104 according to some embodiments. Figure 25 This is a structural diagram showing the stacked support layer 50, first gate layer 1031, second gate layer 1032, interlayer insulating layer 104, and first source / drain metal layer 105 according to some embodiments. Figure 26 This is a structural diagram of a stacked support layer 50, a first gate layer 1031, a second gate layer 1032, an interlayer insulating layer 104, a first source / drain metal layer 105, and a passivation layer 106 according to some embodiments.

[0147] Figure 27This is a structural diagram of a stacked support layer 50, a first gate layer 1031, a second gate layer 1032, an interlayer insulating layer 104, a first source / drain metal layer 105, a passivation layer 106, and a first planarization layer 107 according to some embodiments. Figure 28 This is a structural diagram of a stacked support layer 50, a first gate layer 1031, a second gate layer 1032, an interlayer insulating layer 104, a first source / drain metal layer 105, a passivation layer 106, a first planarization layer 107, and a second source / drain metal layer 108, according to some embodiments.

[0148] For example, the power signal line VDD, the reference voltage line VSS, and the initialization signal line Vinit may be located in at least one of the first source-drain metal layers 105 and the second source-drain metal layer 108. When the source-drain metal layer SD includes three or more layers, the power signal line VDD, the reference voltage line VSS, and the initialization signal line Vinit may be located in at least one of the source-drain metal layers SD.

[0149] In other embodiments, such as Figure 4 and Figure 14 As shown, the support layer 50 is electrically connected to the reference voltage line VSS.

[0150] Connecting the support layer 50 to the power signal line VDD or the reference voltage line VSS, and connecting the support layer 50 to a stable signal, can effectively solve the problem of signal fluctuations caused by the surrounding signals being driven when the data signal is written.

[0151] In some embodiments, such as Figure 29 and Figure 30 As shown, the display panel 100 also includes a third source / drain metal layer 52, which is located on the side of the second source / drain metal layer 108 away from the substrate 101, and a support layer 50 is located on the third source / drain metal layer 52.

[0152] For example, compared with no support layer 50, the strength of the transition area B1 is increased by about 3% when the support layer 50 is provided in the third source / drain metal layer 52.

[0153] For example, the display panel 100 further includes a third planarization layer 110, which is located on the side of the third source / drain metal layer 52 away from the substrate 101.

[0154] For example, in combination Figure 4In the display area AA, the third source-drain metal layer 52 serves as the functional layer for the sub-pixels. For example, the third source-drain metal layer 52 can be configured with signal lines, such as power signal lines VDD or reference voltage lines VSS, etc., without limitation. Alternatively, the third source-drain metal layer 52 can be configured with transition patterns. For example, if a light-emitting device is disposed on the side of the pixel driving circuit away from the substrate 101, the transition pattern of the third source-drain metal layer 52 is used to connect the pattern of the second source-drain metal layer 108 and the electrode pattern of the light-emitting device to achieve electrical connection between the pixel driving circuit and the light-emitting device. In the transition area B1, the third source-drain metal layer 52 does not have signal lines. In this case, the third source-drain metal layer 52 is configured as a support layer 50 to improve the resistance to extrusion deformation of the transition area B1, which has the function of signal line transition layer switching.

[0155] In some embodiments, such as Figure 29 and Figure 30 As shown, the support layer 50 is provided with multiple vent holes Q that penetrate the support layer 50.

[0156] For example, in the orthographic projection onto the substrate 101, the vent hole Q can be square, triangular, or circular, etc., and there is no limitation here.

[0157] On the side of the third source / drain metal layer 52 near the substrate 101, a first planarization layer 107 and a second planarization layer 109 are provided. The materials of the first planarization layer 107 and the second planarization layer 109 can be polyimide. The materials of the first planarization layer 107 and the second planarization layer 109 are prone to generating gas. If the gas is not discharged in time, it will affect the performance of the display panel 100. In order to facilitate the discharge of gas, an exhaust hole Q is provided on the support layer 50 to improve the performance of the display panel 100.

[0158] It should be noted that, due to the presence of the vent hole Q, in the orthogonal projection onto the substrate 101, at least a portion of the first transition hole K1 and / or the second transition hole K2 will not overlap with the support layer 50, i.e., this portion overlaps with the vent hole Q. However, this portion is located within the area enclosed by the outer boundary J1 of the support layer 50, and the support layer 50 with the vent hole Q can also improve the compression resistance of the transition area B1.

[0159] In some embodiments, such as Figure 29 As shown, the ratio of the area of ​​the vent Q to the area of ​​the support layer 50 ranges from 1 / 9 to 1.

[0160] For example, the ratio of the area of ​​the vent Q to the area of ​​the support layer 50 can be 1 / 9, 2 / 9, 1 / 3, 4 / 9, 7 / 9, or 1, etc., and there is no limit here.

[0161] By setting the ratio of the area of ​​the exhaust hole Q to the area of ​​the support layer 50 to be in the range of 1 / 9 to 1, it is possible to ensure that the gas can be effectively discharged, and the support layer 50 located in the third source drain metal layer 52 can also improve the ability of the transition area B1 to resist extrusion deformation.

[0162] In some embodiments, such as Figure 13 and Figure 15 As shown, the support layer 50 is located on the inorganic encapsulation layer 53.

[0163] For example, such as Figure 4 , Figure 13 and Figure 15 As shown, in the display area AA, the inorganic encapsulation layer 53 is used to encapsulate the sub-pixels and to prevent moisture from entering the display panel 100.

[0164] For example, the material of the inorganic encapsulation layer 53 is silicon nitride or silicon oxide.

[0165] For example, compared with no support layer 50, the strength of the transition area B1 is increased by about 3% when the support layer 50 is provided in the inorganic encapsulation layer 53.

[0166] Therefore, by setting the support layer 50 located in the inorganic encapsulation layer 53, the ability of the transition area B1 to resist extrusion deformation is improved.

[0167] In some embodiments, such as Figure 13 and Figure 15 As shown, the support layer 50 is located on the touch layer 54.

[0168] For example, in combination Figure 4 The display area AA of the display panel 100 is provided with multiple touch sensing lines and multiple touch driving lines that are insulated from each other. The touch sensing lines and touch driving lines are arranged vertically to realize the touch function of the display panel 100. The touch layer 54 includes: a first touch metal layer and a second touch metal layer. The touch sensing lines are located in the first touch metal layer, and the touch driving lines are located in the second touch metal layer.

[0169] In the transition area B1, the first touch metal layer can be used as the support layer 50, and / or the second touch metal layer can be used as the support layer 50.

[0170] For example, compared to not having a support layer 50, having a support layer 50 on the touch layer 54 increases the strength of the transition area B1 by about 3%.

[0171] Therefore, by setting the support layer 50 located in the touch layer 54, the ability of the transition area B1 to resist extrusion deformation is improved.

[0172] The following describes the setting of the passivation layer 106 in the transition area B1.

[0173] In some embodiments, such as Figure 7 As shown, in the orthographic projection onto the substrate 101, the passivation layer 106 is located at the boundary J2 of the frame region BB, which is located between the first transition hole K1 and the second transition hole K2. That is, in the orthographic projection onto the substrate 101, the passivation layer 106 partially overlaps with the transition region B1, which can also be referred to as the passivation layer 106 partially covering the transition region B1.

[0174] The following structural design of the passivation layer 106 improves the compression resistance of the transition area B1.

[0175] In some embodiments, such as Figure 6 and Figure 31 As shown, in the orthographic projection onto the substrate 101, the passivation layer 106 covers the area of ​​the transition region B1 except for the area where the second transition hole K2 is located.

[0176] Since the second segment 151b of the adapter cable 151 is electrically connected to the second signal line 181 through the second adapter hole K2, the second adapter hole K2 needs to penetrate the insulating layer between the first source / drain metal layer 105 and the second source / drain metal layer 108. Therefore, when the passivation layer 106 is disposed in the transition region B1, the second adapter hole K2 needs to penetrate the passivation layer 106 and the first planarization layer 107. Therefore, in the orthographic projection onto the substrate 101, the area of ​​the second adapter hole K2 cannot be provided with the passivation layer 106. This example can also be referred to as the passivation layer 106 covering the transition region B1.

[0177] Compared to the example where the boundary J2 of the passivation layer 106 is located between the first transition hole K1 and the second transition hole K2 in the orthogonal projection onto the substrate 101, this example shows an increased area of ​​the passivation layer 106 in the transition region B1.

[0178] By covering the area of ​​the transition region B1, excluding the area where the second transition hole K2 is located, with the passivation layer 106 in the orthogonal projection onto the substrate 101, the resistance of the transition region B1 to extrusion deformation can be improved. For data on the resistance of the transition region B1 to extrusion deformation, please refer to the following content, which will not be described in detail here.

[0179] In some embodiments, such as Figure 6 and Figure 32 As shown, in the orthographic projection onto the substrate 101, the passivation layer 106 does not overlap with the transition region B1. This example can also be described as the passivation layer 106 not covering the transition region B1.

[0180] For example, a perforation is provided on the passivation layer 106, and in the orthographic projection onto the substrate 101, the transition area B1 is located in the perforation.

[0181] Compared to a scenario where the boundary J2 of the passivation layer 106 is located between the first transition hole K1 and the second transition hole K2 in the orthographic projection onto the substrate 101, this example improves the resistance of the transition region B1 to extrusion deformation by setting the passivation layer 106 and the transition region B1 to not overlap in the orthographic projection onto the substrate 101.

[0182] In some embodiments, such as Figure 6 and Figure 32 As shown, in the orthographic projection onto the substrate 101, the minimum distance d3 between the passivation layer 106 and the target transition hole K0 ranges from 1.5µm to 6µm. The target transition hole K0 is the transition hole of the first transition hole K1 and the second transition hole K2 that is closest to the passivation layer 106.

[0183] For example, in combination Figure 4 The first adapter hole K1 is located on the side of the second adapter hole K2 that is close to the display area AA. The first adapter hole K1 that is closest to the display area AA is the target adapter hole K0.

[0184] For example, such as Figure 32 As shown, there is a gap between the passivation layer 106 and the transition line 151 located on the first source / drain metal layer 105. In other examples, such as Figure 33 As shown, the passivation layer 106 can cover a portion 151x of the adapter cable 151, which is the portion of the adapter cable 151 that is away from the first adapter hole K1 and the second adapter hole K2.

[0185] By setting the minimum spacing d3 between the passivation layer 106 and the target transition hole K0 in the orthogonal projection onto the substrate 101 to be in the range of 1.5µm to 6µm, the design of the passivation layer 106 not covering the transition area B1 is achieved.

[0186] Based on the structure of the above display panel 100, the following comparative examples and examples 1 to 5 are provided.

[0187] Comparative Example

[0188] The structure of the display panel 100 is as follows: Figure 7 As shown, the passivation layer 106 is located at the boundary J2 of the border area BB, which is between the first transition hole K1 and the second transition hole K2. That is, the passivation layer 106 partially covers the transition area B1.

[0189] Example 1

[0190] Compared with the comparative example, combined Figure 30 The display panel 100 includes a support layer 50 located on the third source / drain metal layer 52.

[0191] Example 2

[0192] Compared with the comparative example, combined Figure 15The display panel 100 includes a support layer 50 located on the touch layer 54.

[0193] Example 3

[0194] Compared to the comparative example, such as Figure 31 As shown, the passivation layer 106 covers the transition region B1.

[0195] Example 4

[0196] Compared with the comparative example, combined Figure 14 The display panel 100 includes a support layer 50 located on the light-shielding layer 51.

[0197] Example 5

[0198] Compared with the comparative example, combined Figure 15 and Figure 30 The display panel 100 includes three support layers 50, which respectively include a light-shielding layer 51, a touch layer 54, and a third source / drain metal layer 52, and a passivation layer 106 covers the transition area B1. That is, Example 5 is a combination of Examples 1 to 4.

[0199] The simulation values ​​of the structure and performance of the display panel 100 in the above comparative examples and examples 1 to 5 are shown in Table 1 below.

[0200] Table 1. Simulation values ​​of the structure and performance of the display panel 100 in comparative examples and Examples 1-5.

[0201]

[0202] As shown in Table 1, the maximum stress represents the internal stress generated when the transition area B1 is subjected to external compression. A larger value indicates a greater internal stress in the transition area B1, suggesting a weaker resistance to extrusion deformation; a smaller value indicates a smaller internal stress in the transition area B1, suggesting a better resistance to extrusion deformation. The stress change rate represents the rate of change of the maximum stress in Examples 1-5 compared to the maximum stress in the comparative example. A larger stress change rate indicates a greater internal stress in the transition area B1, suggesting a weaker resistance to extrusion deformation; a smaller stress change rate indicates a smaller internal stress in the transition area B1, suggesting a better resistance to extrusion deformation.

[0203] As shown in Table 1, compared to the absence of a support layer 50, in Examples 1, 2, and 4, the resistance to extrusion deformation of the transition region B1 is improved when a single support layer 50 is provided. In Example 3, in the orthogonal projection onto the substrate 101, the passivation layer 106 covers the area of ​​the transition region B1 except for the area where the second transition hole K2 is located, resulting in a significant increase in the resistance to extrusion deformation of the transition region B1. In Example 5, the improvement in the resistance to extrusion deformation of the transition region B1 is further increased by combining the three support layers 50 and the passivation layer 106 covering the transition region B1.

[0204] In summary, by covering the transition area B1 with a support layer 50 and / or a passivation layer 106, the ability of the transition area B1 to resist extrusion deformation can be improved, thereby effectively preventing membrane breakage and improving the effectiveness of signal electrical connection.

[0205] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: The display area and the border area located on at least one side of the display area; A binding area is located on the side of the border area away from the display area and bends to the back of the display panel; a transition area is provided on the portion of the border area near the binding area; The system comprises a substrate, a gate layer, and source / drain metal layers, wherein the gate layer and the source / drain metal layers are sequentially disposed in a direction away from the substrate; in the border region, the gate layer includes multiple first signal lines; in the bonding region, the source / drain metal layers include multiple second signal lines; and in the transition region, the multiple first signal lines and the multiple second signal lines are electrically connected in a one-to-one correspondence. In the transition area, the display panel further includes a support layer; in a projection onto the substrate, the support layer has an outer boundary, and the area where the first signal line and the second signal line are electrically connected is located within the area enclosed by the outer boundary of the support layer.

2. The display panel according to claim 1, characterized in that, The source / drain metal layer includes: a first source / drain metal layer and a second source / drain metal layer, wherein the first source / drain metal layer and the second source / drain metal layer are disposed along a direction away from the substrate; and a plurality of second signal lines are located in the second source / drain metal layer. In the switching area, the first source-drain metal layer is provided with multiple switching wires, and multiple first signal lines, multiple switching wires and multiple second signal lines are electrically connected one-to-one.

3. The display panel according to claim 2, characterized in that, In a projection onto the substrate, the multiple transition lines are located within the area enclosed by the outer boundary of the support layer.

4. The display panel according to claim 3, characterized in that, In the orthographic projection onto the substrate, the minimum distance between the adapter line and the outer boundary of the support layer ranges from 1µm to 10µm.

5. The display panel according to claim 2, characterized in that, Also includes: A light-shielding layer is located on the side of the gate layer near the substrate, and a support layer is located on the light-shielding layer.

6. The display panel according to claim 5, characterized in that, The light-shielding layer further includes: a portion located in the display area and a connecting portion located in the border area, the connecting portion being located between the support layer and the portion of the light-shielding layer located in the display area, and the connecting portion connecting the support layer and the portion of the light-shielding layer located in the display area.

7. The display panel according to claim 6, characterized in that, The connecting part is mesh-like.

8. The display panel according to claim 5, characterized in that, In the border area, the first source-drain metal layer further includes a power signal line, and the support layer is electrically connected to the power signal line.

9. The display panel according to claim 5, characterized in that, In the border area, the first source / drain metal layer further includes a reference voltage line, and the support layer is electrically connected to the reference voltage line.

10. The display panel according to claim 5, characterized in that, The thickness of the support layer ranges from 0.1µm to 0.5µm.

11. The display panel according to claim 2, characterized in that, Also includes: A third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate, and the support layer is located on the third source / drain metal layer.

12. The display panel according to claim 11, characterized in that, The support layer is provided with multiple vent holes that penetrate the support layer.

13. The display panel according to claim 12, characterized in that, The ratio of the area of ​​the vent hole to the area of ​​the support layer ranges from 1 / 9 to 1.

14. The display panel according to claim 2, characterized in that, Also includes: An inorganic encapsulation layer is located on the side of the second source / drain metal layer away from the substrate, and a support layer is located on the inorganic encapsulation layer.

15. The display panel according to claim 2, characterized in that, Also includes: A touch layer is located on the side of the second source / drain metal layer away from the substrate, and a support layer is located on the touch layer.

16. The display panel according to claim 2, characterized in that, Also includes: A passivation layer and a first planarization layer are located between the first source / drain metal layer and the second source / drain metal layer, wherein the passivation layer and the first planarization layer are disposed in a direction away from the substrate; The adapter cable and the second signal line are electrically connected through a second adapter hole that passes through the first planarization layer and the passivation layer; In the orthographic projection onto the substrate, the passivation layer covers the area of ​​the transition region except for the area where the second transition hole is located.

17. The display panel according to claim 2, characterized in that, Also includes: A passivation layer is located between the first source / drain metal layer and the second source / drain metal layer; In the orthographic projection onto the substrate, the passivation layer and the transition region do not overlap.

18. The display panel according to claim 17, characterized in that, Also includes: A first insulating layer and a first planarization layer, wherein the first insulating layer is located between the gate layer and the first source / drain metal layer, and the first signal line and the adapter line are electrically connected through a first adapter hole penetrating the first insulating layer; the adapter line and the second signal line are electrically connected through a second adapter hole penetrating the first planarization layer. In the orthographic projection onto the substrate, the minimum distance between the passivation layer and the target adapter hole ranges from 1.5µm to 6µm, and the target adapter hole is the adapter hole of the first adapter hole and the second adapter hole that is closest to the passivation layer.

19. The display panel according to claim 2, characterized in that, Also includes: First insulating layer and first planarization layer; The adapter cable includes: a first segment and a second segment connected along a first direction; the first signal line and the first segment are electrically connected through a first adapter hole penetrating the first insulating layer, and the second segment and the second signal line are electrically connected through a second adapter hole penetrating the first planarization layer; the first direction is the extension direction of the first signal line; The first adapter hole and the second adapter hole connected to one of the adapter cables are arranged along the first direction; along the second direction, the first adapter hole and the second adapter hole connected to different adapter cables are arranged alternately; the second direction intersects the first direction; Wherein, the dimension of the first segment in the second direction is smaller than the dimension of the second segment in the second direction.

20. The display panel according to claim 1, characterized in that, The thickness of the support layer ranges from 0.1µm to 3µm.

21. The display panel according to any one of claims 1 to 20, characterized in that, The display panel includes at least two of the following: a light-shielding layer, a third source / drain metal layer, an inorganic encapsulation layer, and a touch layer. The support layer is provided on at least two of the following: the light-shielding layer, the third source / drain metal layer, the inorganic encapsulation layer, and the touch layer.

22. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 21; A driver chip is used to drive the display panel to display.

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