Automatic high speed shutdown for C-PHY receivers

Abstract

An interface circuit has a data recovery circuit, a protocol interface circuit, and a controller or processor that can be implemented using a finite state machine. The data recovery circuit may be configured to receive a stream of symbols through three wires of a serial bus according to a high speed mode defined by a Mobile Industry Processor Interface Alliance (C-PHY) protocol. The protocol interface circuit may be coupled to an output of the data recovery circuit and configured to receive data from the data recovery circuit. The finite state machine may be configured to disable the data recovery circuit when an end of transmission is indicated in a first end of transmission signal received from the protocol interface circuit.

Description

Cross Reference to Related Applications

[0001] This patent application claims priority to pending U.S. Non-Provisional Application No. 18 / 460,905, filed September 5, 2023, which is assigned to the assignee of the present application, and is hereby expressly incorporated by reference as if fully set forth below and for all applicable purposes. TECHNICAL FIELD

[0002] The present disclosure relates generally to serial communication over serial buses in wireless communication devices, and more particularly, to timely termination of high-speed C-PHY interface circuits. BACKGROUND

[0003] Mobile communication devices often include various components, such as circuit boards, integrated circuit (IC) devices, application-specific integrated circuit (ASIC) devices, and / or system-on-a-chip (SoC) devices. The types of these components can include processing circuitry, user interface components, storage, and other peripheral components that communicate over serial buses. The serial buses can operate according to standardized protocols or proprietary protocols. In one example, the serial buses can operate according to the Inter-Integrated Circuit (I2C or I 2 C) communication protocol. The I2C bus is configured as a multi-drop bus and was developed for connecting low-speed peripheral devices to a processor. Two wires of the I2C bus include a serial data line (SDA) that carries a data signal and a serial clock line (SCL) that carries a clock signal.

[0004] A number of standards are defined for interconnecting certain types of components in mobile communication devices. For example, different types of interfaces can be used for communication between an application processor and a display or camera component in a mobile communication device. Some displays or camera components employ interfaces that conform to standards or protocols specified by the Mobile Industry Processor Interface (MIPI) Alliance for camera serial interfaces (CSI) and display serial interfaces (DSI).

[0005] The MIPI Alliance DSI, DSI-2 (referred to individually or collectively as DSI herein), and CSI and CSI-2 (referred to individually or collectively as CSI herein) standards define wired interfaces that can be deployed within an IC or between an IC device and a SoC device. The CSI protocol can be used to couple a camera and an application processor. The DSI protocol can be used to couple an application processor and a display subsystem. The low-level physical layer (PHY) interface in each of these applications is implemented according to the MIPI Alliance C-PHY standard and protocol. High-speed and low-power modes of communication are defined for the C-PHY interface. The C-PHY high-speed mode uses low-voltage multiphase signals transmitted in different phases over a 3-wire link. The C-PHY low-power mode provides a lower data rate and transmits signals at a higher voltage than the high-speed mode.

[0006] With advancements in device technology, higher data rate requirements on serial buses have sometimes been met by increasing the clock rate used for signaling control on the serial interface. For example, the version 2.0 specification for the MIPI C-PHY interface provides transmit clock rates between 4.5 GHz and 6.0 GHz. Increasing the transmit clock frequency reduces the tolerances and margins defined for the data signals. Certain control sequences are transmitted during C-PHY transactions before the C-PHY interface's operating mode changes. Receiving devices can use timers to control the shutdown or disabling of high-speed physical layer circuitry. Timers can be configured to expire after a duration longer than required to allow buffered symbols and data to be processed before the high-speed physical layer circuitry is disabled or reconfigured for different operating modes. The additional time allowed by timers results in unnecessary power consumption in the high-speed physical layer circuitry. Reducing unnecessary power consumption in the C-PHY interface remains necessary to conserve battery power and limit heat generation and dissipation in portable devices. Summary of the Invention

[0007] Certain aspects of this disclosure relate to systems, apparatus, methods, and techniques that enable mobile communication devices and other portable devices to detect and respond to the end-of-transmission status in a C-PHY interface. A receiving device may be configured to automatically shut down or disable the high-speed physical layer circuitry in its C-PHY interface once the last coded symbol has been decoded and / or after a data buffer controlled by high-speed physical layer circuitry has been flushed.

[0008] In various aspects of this disclosure, an interface circuit includes a data recovery circuit, a protocol interface circuit, and a controller or processor that can be implemented using a finite state machine. The data recovery circuit can be configured to receive a symbol stream via three wires of a serial bus in a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol. The protocol interface circuit can be coupled to the output of the data recovery circuit and configured to receive data from the data recovery circuit. The finite state machine can be configured to disable the data recovery circuit when a first End-of-Transmission (EOT) signal received from the protocol interface circuit indicates the end of transmission.

[0009] In various aspects of this disclosure, a method for operating a communication interface circuit includes: converting a symbol stream into a plurality of data words at a data recovery circuit, the symbol stream being received via three wires of a serial bus according to a high-speed mode defined by the MIPI Alliance C-PHY protocol; providing the plurality of data words to the protocol interface circuit; and disabling the data recovery circuit when a first EOT signal received from the protocol interface circuit indicates the end of transmission.

[0010] In various aspects of this disclosure, an apparatus includes: components for converting a symbol stream into a plurality of data words at a data recovery circuit; components including protocol interface circuitry for processing the plurality of data words; and components for disabling the data recovery circuitry when a first EOT signal received from the protocol interface circuitry indicates the end of transmission. The symbol stream may be received via three wires of a serial bus in a high-speed mode defined by the MIPI Alliance C-PHY protocol.

[0011] In various aspects of this disclosure, a processor-readable storage medium includes code configured to cause processing circuitry to perform the following operations: converting a symbol stream at a data recovery circuit to provide a plurality of data words, the symbol stream being received via three wires of a serial bus according to a high-speed mode defined by the MIPI Alliance C-PHY protocol; providing the plurality of data words to a protocol interface circuit; and disabling the data recovery circuit when a first EOT signal received from the protocol interface circuit indicates the end of transmission.

[0012] In some respects, after indicating the end of the transmission, signaling defined for switching the serial bus to a low-speed mode as defined by the MIPI Alliance C-PHY protocol is received at the interface circuitry. When indicating the end of the transmission, a continuous symbol mode corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol can be received.

[0013] In some respects, the transmission ends when the protocol interface circuit has finished processing the data received from the data recovery circuit. A first-in, first-out (FIFO) buffer circuit can be used to couple the protocol interface circuit to the output of the data recovery circuit. The FIFO buffer circuit can be configured to store multiple data words received from the data recovery circuit. The transmission ends when the FIFO buffer is empty of these multiple data words.

[0014] In one aspect, a clock generation circuit is configured to provide a protocol interface clock signal that controls the operation of the protocol interface circuitry. When the data recovery circuitry is disabled, the protocol interface clock signal can be suppressed.

[0015] In some implementations, the synchronization circuit is configured to propagate the first EOT signal as the second EOT signal according to the timing provided by the internally generated clock signal used by the finite state machine. Attached Figure Description

[0016] Figure 1 An example is shown of a device that employs a data link between IC devices and operates selectively according to a standard or proprietary protocol.

[0017] Figure 2 Examples of interface circuits that can be adapted to certain aspects of this disclosure are illustrated.

[0018] Figure 3 The system architecture of a device employing a C-PHY data link between IC devices is illustrated.

[0019] Figure 4 Examples of C-PHY interfaces that can be adapted according to certain aspects disclosed herein are provided.

[0020] Figure 5 Examples N Signaling in an example of a phase polarity encoded interface.

[0021] Figure 6 This is a state diagram illustrating the signaling states and transitions between signaling states in a C-PHY interface implemented according to certain aspects disclosed herein.

[0022] Figure 7 This document illustrates certain aspects of data transmission in a C-PHY interface adapted to certain aspects disclosed herein.

[0023] Figure 8 An example of a lookup table is shown that can be used to control the shutdown of high-speed physical layer circuitry in a C-PHY interface.

[0024] Figure 9An example is shown of a C-PHY interface that supports automatic shutdown of high-speed physical layer circuitry according to certain aspects of this disclosure.

[0025] Figure 10 An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0026] Figure 11 This is a flowchart illustrating a method for operating a communication interface circuit according to certain aspects disclosed herein.

[0027] Figure 12 A first example of a hardware implementation of a communication device adapted to certain aspects disclosed herein is illustrated. Detailed Implementation

[0028] The detailed description below, illustrated with reference to the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0029] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0030] Data communication links used by SoCs and other IC devices to connect the processor to modems and other peripherals can operate according to industry or proprietary standards or protocols associated with certain functions or types of devices. In examples of display panels, display subsystems, and display drivers, communication standards and protocols defined by the MIPI Alliance are frequently used. For example, the Display Serial Interface (DSI)... ® It provides the C-PHY standard and protocol for defining, configuring, and controlling the high-speed serial interface between the host processor and the display module.

[0031] Certain aspects of this disclosure relate to a serial bus configuration in which two or more devices can communicate at different times. The described serial bus typically operates in a hierarchical manner, as one device controls communication during a transaction. The controlling device may be referred to as a master device, bus master, management device, or another term supported by a standard defining a protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communication during all transactions conducted via the serial bus. In other serial bus configurations, more than one device may operate as a controlling device, while another device acts as the controlling device for transactions conducted via the serial bus. The controlling device can provide control signaling that facilitates clock synchronization and identifies the type of transaction to be conducted via a conventional two-wire serial bus. The receiving device may be referred to as a client device, slave device, dependent device, peripheral device, or another term supported by a standard defining a protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device may be referred to as a master device, and the associated receiving device may be referred to as a dependent device.

[0032] According to certain aspects of this disclosure, serial data links can be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0033] Figure 1 An example of a device 100 comprising multiple devices or circuits coupled via one or more data communication buses is illustrated. The processing circuitry 102 of device 100 includes multiple circuits or devices 104, 106, and / or 108. In some examples, the processing circuitry 102 is implemented using one or more ASICs. In other examples, the processing circuitry 102 is implemented in a SoC. In one example, device 100 may be configured to operate as a communication device, and the processing circuitry 102 includes an ASIC 104, one or more peripheral devices 106, and a transceiver 108 that cooperates to enable the device to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 122.

[0034] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer, enabling one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage devices 118 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage devices 118. ASIC 104 may access its onboard memory 114, processor-readable storage devices 118, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage devices 118 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 122, display 138, operator controls such as switches or buttons 136, 130 and / or integrated or external keyboard 132, and other components. The user interface module may be configured to operate with display 138, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0035] Processing circuitry 102 may provide multiple buses 120 enabling communication between two or more devices 104, 106, and / or 108. In one example, ASIC 104 may include bus interface circuitry 116 coupled to one or more of the buses 120. Each bus interface circuitry 116 may include a combination of circuitry, counters, timers, control logic components, and other configurable circuitry or modules. In one example, some bus interface circuitry 116 may be configured to operate according to a standard-defined communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0036] Figure 2Examples of interface circuitry that may be adopted or adapted according to certain aspects of this disclosure are illustrated. A first interface circuit is configured as a camera subsystem 200, and a second interface circuit is configured as a display subsystem 250. For example, the interface circuitry may be deployed in a mobile communication device. The camera subsystem 200 may include a CSI-2 defined communication link between an image sensor 202 and an application processor 212. The communication link may include a high data rate data transmission link 210 used by the image sensor 202 to transmit image data to the application processor 212 using a transmitter 206. The high data rate data transmission link 210 may be configured and operated according to a C-PHY protocol. In one example, a physical layer interface implemented using C-PHY technology and protocols defined by the MIPI Alliance may be referred to as a C-PHY interface and may be used to connect a camera or display to the application processor. The application processor 212 may include a crystal oscillator (XO 214) or other clock source to generate a clock signal 222 that controls the operation of the transmitter 206. The clock signal 222 may be processed by a phase-locked loop (PLL) 204 in the image sensor 202. In some cases, clock signal 222 may also be used by C-PHY receiver 216 in application processor 212. The communication link may include a camera control interface (CCI), which is essentially similar to an inter-integrated circuit (I2C) interface. The CCI bus may include a serial clock (SCL) line carrying the clock signal and a serial data (SDA) line carrying data. CCI link 220 may be bidirectional and may operate at a lower data rate than the high data rate data transmission link 210. Application processor 212 may use CCI link 220 to exchange control and configuration information with image sensor 202. Application processor 212 may include a CCI bus master device 218, and image sensor 202 may include a CCI slave device 208.

[0037] Display subsystem 250 may include a unidirectional data link 258 that can be configured and operated according to the C-PHY protocol. In application processor 252, a clock source such as PLL 254 may be used to generate a bit clock signal used by C-PHY receiver 256 to control transmissions on data link 258. At display device 260, C-PHY receiver 262 may extract embedded clock information from a sequence of symbols transmitted on the data link or from a clock channel provided in data link 258.

[0038] Some aspects disclosed herein relate to systems, apparatus, and methods that support a wide range of interface protocols and can operate using different physical media. For example... Figure 2As shown, for example, camera subsystem 200 and / or display subsystem 250 may use the C-PHY protocol to convey high data rate information. In some configurations, camera subsystem 200 and / or display subsystem 250 may communicate using a reverse channel (e.g., CCI link 220) used to configure image sensor 202 or other devices. In some cases, a low-power operating mode may be defined for links using either the C-PHY protocol.

[0039] Figure 3 An example of a device 300 employing a data link that can be used to communicatively couple two or more devices, sub-components, or circuits is illustrated. Here, device 300 includes multiple devices 302 and 3220-322 coupled to a two-wire serial bus 320. N Equipment 302 and 3220-322 N It can be implemented in one or more semiconductor IC devices, such as application processors, SoCs, or ASICs. In various specific implementations, devices 302 and 3220-322... N Some of the devices may include, support modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices, or operate as such. In some examples, one or more devices 3220 to 322 N These devices can be used to control, manage, or monitor sensor equipment. (Equipment 302 and 3220-322) N Communication between them via serial bus 320 is controlled by bus master device 302. Some types of buses can support multiple bus masters 302.

[0040] In one example, the bus master device 302 includes an interface controller 304 configured to manage access to the serial bus, configure dynamic addresses for slave devices, and / or generate a clock signal 328 to be transmitted on clock line 318 of the serial bus 320. The bus master device 302 may include a configuration register 306 or other storage device 324 and other control logic components 312 configured to process protocols and / or higher-level functions. The control logic components 312 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. The bus master device 302 includes a transceiver 310 and line drivers / receivers 314a and 314b. The transceiver 310 may include a receiver, a transmitter, and common circuitry, where such common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in the clock signal 328 provided by clock generation circuitry 308. Additional timing clocks 326 may be used by the control logic components 312 and other functions, circuitry, or modules.

[0041] At least one device 3220-322 N The device 3220 can be configured to operate as a slave device on a serial bus 320 and may include circuitry and modules supporting a display, an image sensor, and / or controlling and communicating with one or more sensors that measure environmental conditions. In one example, the device 3220 configured to operate as a slave device may provide control functions, physical layer circuitry 332 including circuitry and modules for supporting a display, an image sensor, and / or controlling and communicating with one or more sensors that measure environmental conditions. In this example, the device 3220 may include a configuration register 334 or other storage device 336, control logic unit 342, transceiver 340, and line drivers / receivers 344a and 344b. The control logic unit 342 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. The transceiver 340 may include a receiver, a transmitter, and common circuitry, wherein these common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 348 provided by clock generation and / or recovery circuitry 346. In some cases, clock signal 348 may be derived from a signal received from clock line 318. Other timing clocks 338 may be used by control logic unit 342 and other functions, circuits, or modules.

[0042] The serial bus 320 can operate according to standard-defined protocols or proprietary protocols. In some cases, two or more devices 302, 3220-322 can operate simultaneously. N It can be configured to operate as a bus master on serial bus 320. In some cases, device 300 includes multiple serial buses 320, 352a and / or 352b, which couple devices 302, 3220-322. N Two or more devices or devices 302, 3220-322 N One of the devices is a display or camera 350, and peripheral devices such as a display or camera 350 or an radio frequency IC (RFIC). In some examples, a slave device 3220 is configured to operate as a display or camera coupled to the display or camera 350. The latter slave device 3220 may include physical layer circuitry 332 configured to operate as a C-PHY interface controller that communicates with the display or camera 350 via a serial bus 352a or 352b operating according to the C-PHY protocol.

[0043] In certain aspects of this disclosure, systems and apparatuses may employ a multiphase data encoding and decoding interface approach to communicate between IC devices. A multiphase encoder may drive multiple conductors (i.e., three conductors). Each conductor may be referred to as a wire, but it may include conductive traces on a circuit board or traces or interconnects within the conductive layer of a semiconductor IC device. In one example, a physical layer interface implemented using C-PHY technology and protocols defined by the MIPI Alliance may be referred to as a C-PHY interface and may be used to connect a camera or display to an application processor. The C-PHY interface employs tri-phase symbol encoding to transmit data symbols on a three-wire channel or “trio,” where each trio includes an embedded clock. A trio may be referred to herein as a channel. Multiple trios can be used to establish multi-channel C-PHY communication channels to carry data exchanged between a pair of devices, where each channel includes a trio carrying a portion of data that may be independently encoded according to the C-PHY protocol.

[0044] The C-PHY interface provides a three-phase encoding scheme for three-wire systems. The three-phase encoding scheme defines three-phase states and two polarities, thus providing six states and five possible transitions from each state. Deterministic voltage and / or current changes can be detected and decoded to extract data from the three conductors.

[0045] Figure 4 Examples are shown that can be used to implement Figure 3 The C-PHY interface for certain aspects of the serial bus 352a or 352b is depicted. The illustrated example may involve a three-wire link configured to carry three-phase polarity encoded data according to the DSI protocol. The use of three-phase polarity encoding provides high-speed data transmission and can consume half or less power than other interfaces at the desired operating frequency because fewer than three drivers are active in the C-PHY link at any given time. The C-PHY interface uses three-phase polarity encoding to encode multiple bits for each sign transition on the three-wire link. In one example, a combination of three-phase encoding and polarity encoding can be used to support a wide video graphics array (WVGA), 80 frames per second LCD driver IC without a frame buffer, delivering pixel data at 810 Mbps for display refresh via three or more wires.

[0046] In the depicted C-PHY interface, three-phase polarity coding is used to control the signaling state of connectors, wires, traces, and other interconnects providing the communication channel. In the illustrated example, a combination of three wires (tri-wire group 440) is used to provide a single unidirectional channel or path. Each wire in tri-wire group 440 can be undriven, positively driven, or negatively driven in any symbol transmission interval. In some cases, the undriven signal line of tri-wire group 440 may be in a high-impedance state. In some cases, the undriven signal line of tri-wire group 440 may be driven or pulled to a voltage level substantially intermediate between the positive and negative voltage levels provided on the driven signal line. In some cases, no current may flow through the undriven signal line of tri-wire group 440. Drivers 408 in the transmitter 400, which control the signal lines coupled to tri-wire group 440, ensure that only one wire of tri-wire group 440 is in each of the three states (represented as +1, -1, or 0) in each symbol interval.

[0047] In one example, driver 408 includes a cell-level current-mode driver. In another example, driver 408 drives opposite polarity voltages on two signals transmitted on two signal lines of three-wire group 440, while a third signal line is at high impedance and / or pulled to ground. For each transmitted symbol interval, at least one signal is in an undriven (0) state, while one signal is driven positive (+1 state) and one signal is driven negative (-1 state), such that the sum of the currents flowing to receiver 420 is zero amperes. For each symbol, the state of at least one signal line of three-wire group 440 changes from the symbol transmitted in the previous transmitted interval.

[0048] In transmitter 400, mapper 402 can receive a 16-bit input data word 418, and mapper 402 can map the input data word 418 to 7 symbols 412 for sequential transmission via the signal lines of three-wire group 440. It is configured for three-wire, three-phase encoding. M Wire, N The phase encoder 406 receives seven symbols 412 generated by the mapper one symbol at a time 414, and calculates the state of each signal line of the three-wire group 440 for each symbol interval based on the preceding state of the signal lines of the three-wire group 440. The seven symbols 412 can be serialized using, for example, a parallel-to-serial converter 404. The encoder 406 provides a control signal 416 to define the output of the driver 408. The encoder 406 selects the state of the signal lines of the three-wire group 440 based on the input symbols 414 and the previous states of the signal lines of the three-wire group 440, and can provide the control signal 416 to cause the driver 408 to generate the desired signaling state on the three-wire group 440.

[0049] The use of three-wire, three-phase coding allows multiple bits to be encoded in multiple symbols, where the number of bits in each symbol is not an integer. In the example of a three-wire, three-phase system, there are 3 available combinations of two wires that can be driven simultaneously, and 2 possible polarity combinations on a pair of wires that can be driven simultaneously, resulting in 6 possible states. Since each transition starts from the current state, 5 of the 6 states are available at each transition. For 5 states, each symbol transition can encode log2(5) ≅ 2.32 bits. Therefore, the mapper can accept a 16-bit word and convert it into a 7-symbol sequence, since 7 symbols with 2.32 bits each can encode 16.24 bits. In other words, the combination of seven symbols encoding five states has 5 7 (78,125) permutations. Therefore, 7 symbols can be used to represent 16-bit 2. 16 Encode 65,536 possible permutations.

[0050] In the illustrated example, receiver 420 includes comparator 422 and decoder 424, which are configured to provide a digital representation of the state of each of the three signal lines of the three-line group 440, and the change in the state of the three signal lines compared to the state transmitted in a previous symbol period. In the illustrated example, seven consecutive states are combined by serial-to-parallel converter 426 to produce a set of seven symbols to be processed by demapping unit 428 to obtain 16 bits of data that can be buffered in first-in-first-out (FIFO) memory device 430, which may be implemented using, for example, registers. In another example, fourteen consecutive states are combined by appropriately configured serial-to-parallel converters to produce a set of 14 symbols to be processed by demapping unit to obtain 32 bits of data that can be buffered in a 32-bit wide FIFO memory device.

[0051] Figure 5An example of signaling 500 employing a 3-phase modulation data encoding scheme based on a cyclic state transition diagram 550 is illustrated. According to the data encoding scheme, the phase of the 3-phase signal can be rotated in two directions and can be transmitted on three wires 514a, 514b, and 514c, identified as connectors A, B, and C. Each of the three signals is driven independently on wires 514a, 514b, and 514c. Each of the three signals comprises a 3-phase signal, wherein each signal is 120 degrees out of phase with respect to the other two signals. At any given time, each of the three wires 514a, 514b, and 514c is in a different state from the other two wires in the 3-wire system. When more than three conductors or wires are used, two or more pairs of wires may be in the same state. The illustrated encoding scheme can also encode information about the polarity of two wires 514a, 514b and / or 514c that are actively driven to +1 and -1 states. For the depicted state sequence, the polarity is indicated at 508.

[0052] In any phase state of the illustrated 3-wire example, exactly two of the wires 514a, 514b, 514c carry signals that are effectively differential signals for that phase state, while the third wire 514a, 514b, or 514c is not driven. The phase state of each wire 514a, 514b, 514c can be determined by the voltage difference between wire 514a, 514b, or 514c and at least one other wire 514a, 514b, and / or 514c, or by the direction of current flow or the absence of current flow in wire 514a, 514b, or 514c. Three phase states (S1, S2, and S3) are defined as shown in the state transition diagram 550. The signal can flow clockwise from phase state S1 to phase state S2, from phase state S2 to phase state S3, and / or from phase state S3 to phase state S1, and the signal can flow counterclockwise from phase state S1 to phase state S3, from phase state S3 to phase state S2, and / or from phase state S2 to phase state S1. For N Other values, N The transitions between states can optionally be defined according to the corresponding state diagram to obtain cyclic phase rotations between state transitions.

[0053] In the example of a 3-wire, 3-phase communication link, clockwise phase rotations (S1 to S2), (S2 to S3), and / or (S3 to S1) at phase transitions 510 (between states) can be used to encode logic 1, while counterclockwise phase rotations (S1 to S3), (S3 to S2), and / or (S2 to S1) at phase transitions 510 can be used to encode logic 0. Therefore, bits can be encoded at each transition by controlling whether the phase of the control signal "rotates" clockwise or counterclockwise. For example, logic 1 can be encoded when the three wires 514a, 514b, and 514c transition from phase state S1 to phase state S2, and logic 0 can be encoded when the three wires 514a, 514b, and 514c transition from phase state S1 to phase state S3. In the depicted 3-wire example, the direction of phase rotation can be easily determined based on which of the three wires 514a, 514b, and 514c was not driven before and after the transition.

[0054] Information can also be encoded in the polarity and / or polarity changes of the state 508 of the driven conductors 514a, 514b, 514c, or in the direction of current flow or changes in the direction of current flow between the two conductors 514a, 514b, 514c. Signals 502, 504, and 506 illustrate the voltage levels applied to conductors 514a, 514b, 514c in each phase state of a 3-wire, 3-phase link, respectively. At any given time, the first conductors 514a, 514b, 514c are coupled to a more positive voltage (e.g., +V), the second conductors 514a, 514b, 514c are coupled to a more negative voltage (e.g., -V), while the third conductors 514a, 514b, 514c can be open circuits. Therefore, a polarity encoding state can be determined by the current flow between the first and second conductors 514a, 514b, 514c, or by the voltage polarity of the first and second conductors 514a, 514b, 514c. In some embodiments, two bits of data 512 can be encoded in each phase transition 510. The decoder can determine the direction of signal phase rotation to obtain the first bit. The second bit can be determined based on the polarity difference between two signals in signals 502, 504, and 506. In some cases, the second bit can be determined based on the change or no change in the polarity of the differential signal transmitted on a pair of conductors 514a, 514b, 514c. The decoder, having determined the direction of phase rotation, can determine the phase state and polarity of the voltage applied between the two active conductors 514a, 514b, and / or 514c, or the direction of the current flowing through the two active conductors 514a, 514b, and / or 514c.

[0055] In the example of the 3-wire, 3-phase link described herein, one bit of data can be encoded during phase rotation or phase change in the 3-wire, 3-phase link, and another bit can be encoded during polarity or polarity change of the two driven lines. In some implementations, more than two bits can be encoded in each transition of the 3-wire, 3-phase encoding system by allowing transitions from the current state to any of the possible states. Given three rotation phases and two polarities for each phase, six states are defined such that five states are available from any current state. Therefore, there can be log2(5) ≅ 2.32 bits per symbol (transition), and the mapper can accept a 16-bit word and convert it into 7 symbols.

[0056] Figure 6 This is a state transition diagram 600 illustrating the possible signaling states 602, 604, 606, 612, 614, and 616 for three wires in a 3-wire, 3-phase interface (e.g., including the MIPI Alliance C-PHY high-speed mode interface). All possible transitions from each signaling state 602, 604, 606, 612, 614, and 616 are illustrated. Transitions in the state transition diagram 600 can be represented by a flip, rotate, polarity (FRP) symbol 626, which has one of the following three-bit binary values: {000, 001, 010, 011, 100}. The rotate bit 622 of the FRP symbol 626 indicates the direction of phase rotation associated with the transition to the next state. When the transition to the next state involves a polarity change, the polarity bit 624 of the FRP symbol 626 is set to a binary value of 1. When the flip bit 620 of the FRP symbol 626 is set to a binary value of 1, rotation and polarity values ​​can be ignored and / or returned to zero. A flip indicates a state transition involving only a change in polarity. Therefore, when a flip occurs, the phase of the three-phase signal is not considered to be rotating, and the polarity bit is redundant when a flip occurs. The FRP symbol 626 corresponds to the linear state change for each transition. The state transition diagram 600 can be divided into an inner circle 608 including positive polarity signaling states 602, 604, and 606 and an outer circle 618 surrounding negative polarity signaling states 612, 614, and 616.

[0057] Figure 7Some aspects of signaling on a data communication link 702 operating according to the C-PHY protocol are illustrated. A high-speed transaction 700 is illustrated, where the C-PHY interface is initially configured for low-power operation mode 712. Starting at a first time 704, a SoT sequence 718 is sent to switch the C-PHY interface to a low-voltage, high-speed operation mode 714 for data transmission. In high-speed operation mode 714, low-voltage differential (3-phase) signaling is used. Starting at a second time 708, an EOT sequence 728 is sent to return the C-PHY interface to low-power operation mode 716. A "post-synchronization code" (POST mode 726) is provided at the end of high-speed data transmission to provide the receiver with reliable notification of the end of the high-speed burst. In some cases, the receiver may determine that the C-PHY interface is configured for low-power operation mode 716 based on the detection of signaling at a higher voltage level associated with the low-power mode.

[0058] The C-PHY interface adapted according to certain aspects of this disclosure transitions from high-speed mode to low-power mode after transmitting POST mode 726 as defined by the C-PHY protocol. According to the C-PHY protocol, POST mode 726 is provided at the end of high-speed data transmission to provide reliable notification of the end of high-speed data transmission. POST mode 726 includes a series of unmapped codewords (e.g., a sequence where all symbols have the value "4"). Unmapped codewords may refer to a sequence of 7 symbols not used to encode data. A SoT sequence 718 is transmitted to initiate high-speed operation mode 714, and in one example, it may be defined as the sequence {LP-111, LP-001, LP-000}. Pauses may be made before and after SoT sequence 718 during transmission. EOT sequence 728 may occur when the LP-111 state is transmitted for a period of time before the minimum duration in the bus idle state.

[0059] High-speed data transmission includes data packets 724, each consisting of one or more 7-symbol sequences, each encoding a data word. Encoding and decoding can be implemented using a mapping table that associates each 16-bit permutation with a combination of 7 symbols. Each symbol can be an FRP symbol that determines the next signaling state of the three-wire group based on the current signaling state of the three-wire group. In the C-PHY encoding scheme, the 7-symbol combinations produce a total of 78,125 permutations (5... 7 ), of which 65,536 (2 16 Each of the 12,589 possible 7-symbol combinations is uniquely associated with one of the 16 possible values ​​used to encode the data word. Therefore, 12,589 possible 7-symbol combinations are nominally available for control use in the control sequence.

[0060] The C-PHY protocol defines certain 7-symbol sequences that can be reserved for training, synchronization, and control purposes. For example, data packet 724 is led during transmission by a preamble 720 and a synchronization word 722, and data transmission is terminated by a POST mode 726. The preamble 720, synchronization word 722, and POST mode 726 each comprise one or more reserved 7-symbol sequences. In the illustrated example, two initial sequences 740 and 750 are shown. Initial sequences 740 and 750 have preambles of different types.

[0061] In the first initial sequence 740, the preamble 742 includes a programmable sequence 746, which can be used to configure, train, or otherwise convey control information to the receiver. The preamble 742 includes a preamble start sequence 744, followed by the programmable sequence 746, and is completed by a preamble end sequence 748.

[0062] In the illustrated example, the preamble start sequence 744 includes a repeating instance of a 7-symbol sequence, where each symbol has the value "3". The number of repetitions can be defined by configuration during protocol, application, or calibration. The programmable sequence 746 includes a number of 7-symbol sequences, which may include reserved symbols or encoded data words. The number, type, and interpretation of the 7-symbol sequences in the programmable sequence 746 are defined by configuration during protocol, application, or calibration. In the illustrated example, the preamble end sequence 748 includes a single 7-symbol sequence, where each symbol has the value "3".

[0063] In the second initial sequence 750, the preamble 752 includes a preamble start sequence 754, followed immediately by a preamble end sequence 756. In the illustrated example, the preamble start sequence 754 includes a repeating instance of a 7-symbol sequence, where each symbol has the value "3". The number of repetitions can be defined by configuration during protocol, application, or calibration. In the illustrated example, the preamble end sequence 756 includes a single 7-symbol sequence, where each symbol has the value "3".

[0064] Both initial sequences 740 and 750 end with a synchronization word 722. In the illustrated example, the preamble-end sequences 748 and 756 comprise a single 7-symbol sequence with a first and last transmitted symbol of value "3" and five intermediate symbols of value "4". Data packet 724 follows the synchronization word 722 during transmission. According to the C-PHY protocol, the receiver is configured to recognize and respond to the synchronization word 722 after receiving the five symbols of value "4" followed by a symbol of value "3". In the illustrated example, POST mode 726 comprises a repeating instance of the 7-symbol sequence, where each symbol has a value "4". The number of repetitions can be defined by configuration during protocol, application, or calibration.

[0065] The transition between operating modes 712 and 714 is managed by a C-PHY protocol defined by certain MIPI alliances. In some cases, the C-PHY protocol defines time windows during which the transition between operating modes 712 and 714 is expected to take place. The C-PHY interface in the receiving device is expected to enable its high-speed physical layer circuitry within the time window defined for the transition from low-power operating mode 712 to high-speed operating mode 714. The C-PHY interface in the receiving device is further expected to disable its high-speed physical layer circuitry within the time window defined for the transition from high-speed operating mode 714 to low-power operating mode 712. In conventional systems, the C-PHY interface uses programmable timers to monitor and track the time windows. These programmable timers are typically managed by software and configured using lookup tables, in which timer values ​​are indexed based on the data rate configured for the C-PHY interface.

[0066] Figure 8 The contents of lookup table 800 are illustrated, which configures a timer to control the shutdown of certain high-speed physical layer circuitry in the C-PHY interface provided in the receiving device. The time window for the transition from high-speed operating mode 714 to low-power operating mode 712 may have a defined duration, configured such that the receiver can flush all decoded data from the buffer of its C-PHY interface before the high-speed physical layer circuitry is disabled. Figure 4 In the illustrated example, symbols derived by decoder 424 from the signaling state of three-wire group 440 are provided to serial-to-parallel converter 426, which produces a set of seven symbols. These symbols are processed by demapper 428 to obtain 16-bit data in a word. Multiple 16-bit data bits in the word are buffered in FIFO storage device 430. To prevent data loss, the contents of serial-to-parallel converter 426 and FIFO storage device 430 must be refreshed before certain high-speed physical layer circuitry is disabled. Disabling the high-speed physical layer circuitry disables the receive clock generation circuitry and deprives the data recovery circuitry of the timing information required to capture and decode symbols already transmitted by the transmitting device.

[0067] The use of programmable timers and lookup tables increases the processing overhead of the C-PHY interface. Furthermore, the clock signal used to increment or decrement the programmable timer provides low-resolution timing at some higher symbol rates (802), and no resolution at others, such as when the time window expires before the first timer tick is recorded. The timer is programmed with values ​​sufficient to ensure that all remaining data is cleared from the receiver's C-PHY interface buffer and the high-speed physical layer circuitry is disabled before the time window expires, regardless of the symbol rate configured for the C-PHY interface. The delay in disabling the high-speed physical layer circuitry after flushing all data can lead to unnecessary power consumption by the C-PHY interface.

[0068] The aspects disclosed herein enable the receiving device to automatically shut down or disable the high-speed physical layer circuitry in the C-PHY interface once the last coded symbol has been decoded and the data buffer controlled by the high-speed physical layer circuitry has been flushed. In one aspect, automatic shutdown of the high-speed physical layer circuitry in the C-PHY interface can be achieved without using programmable timers and associated lookup tables. This reduces processing overhead and software complexity in the C-PHY interface.

[0069] Figure 9 An example of a C-PHY interface 900 is illustrated, which supports automatic shutdown of high-speed physical layer circuitry in a receiving device configured according to certain aspects of this disclosure. In the illustrated example, the high-speed physical layer circuitry can be automatically shut down without loading or monitoring a shutdown timer. The high-speed physical layer circuitry includes a high-speed clock and data recovery circuitry 902 coupled to a three-wire or connector (“three-wire group 920”) of the C-PHY bus. The high-speed clock and data recovery circuitry 902 uses timing information extracted from transitions between signaling states of the three-wire group 920 to generate a receiver clock signal 922. The receiver clock signal 922 can be used to clock decoded data into a FIFO storage device 904, which buffers decoded data received from the high-speed clock and data recovery circuitry 902. Data can be clocked out of the FIFO storage device 904 using a PHY Protocol Interface (PPI) clock signal 918 generated or controlled by protocol layer circuitry. The timing information in the PPI clock signal 918 enables certain PPI interface circuits 906 to process, transmit, and / or provide access to the processed output data 930 for use by various circuits or modules of the receiving device. The PPI interface circuit 906 can be configured to process data decoded from the symbol stream according to the C-PHY protocol. In some implementations, the high-speed clock and data recovery circuit 902 can signal the PPI interface circuit 906 when a control signal is detected in the symbol stream received via the three-wire group 920.

[0070] In the illustrated example, finite state machine 910 can be configured to manage, monitor, and control the operation of C-PHY interface 900. In other examples, other processors or controllers may be used. Finite state machine 910 can assert control in response to the state of certain inputs and / or based on values ​​stored in certain control registers 912. According to certain aspects of this disclosure, PPI interface circuitry 906 can generate a signal indicating that the end of transmission has been detected (PPI EOT signal 924). This occurs when a transaction has been completed according to the applicable C-PHY protocol and / or a valid POST mode 726 (see [link to relevant documentation]) is detected. Figure 7 When the PPI EOT signal 924 is generated, the synchronizer circuit 914 receives and propagates the PPI EOT signal 924 as the PHY EOT signal 926 according to the timing provided by the internally generated clock signal 916 used by the finite state machine 910 and other control circuits.

[0071] Finite state machine 910 can respond to PHY EOT signal 926 by asserting a power-down or shutdown signal 928, which disables or puts the high-speed physical layer circuitry in C-PHY interface 900 into a low-power operating mode. Finite state machine 910 can assert the power-down or shutdown signal 928 according to timing indicated by control register 912. In some cases, finite state machine 910 can suppress the assertion of power-down or shutdown signal 928 based on certain bit settings in control register 912. In one example, bits in one or more of the control registers 912 can be configured by a higher-level application to prevent or delay the disabling of the high-speed physical layer circuitry in C-PHY interface 900. In another example, bits in one or more of the control registers 912 can be configured by a higher-level application to select between a low-power operating mode and a disabled operating mode for the high-speed physical layer circuitry in C-PHY interface 900.

[0072] The high-speed physical layer circuitry in the C-PHY interface 900 can be shut down according to a predefined synchronization scheme. In one example, the synchronization scheme may be defined by the C-PHY protocol. In some implementations, a finite state machine 910 can manage the shutdown process. For example, the finite state machine 910 can initiate steps in the shutdown process by writing certain bits or values ​​into one or more control registers 912. When a POST mode 726 defined by the MIPI Alliance C-PHY protocol is received (see...), the shutdown process can be initiated. Figure 7 When the signal is received, the high-speed physical layer circuitry in the C-PHY interface 900 can be shut down. After the indication that transmission has ended, reception of the symbol mode corresponding to POST mode 726 can continue.

[0073] The use of PPI EOT signal 924 and / or PHY EOT signal 926 enables the C-PHY interface 900 to quickly shut down or disable the high-speed physical layer circuitry after a C-PHY transaction is completed. This rapid disabling of the high-speed physical layer circuitry can result in significant power savings over time.

[0074] Examples of processing circuitry and methods Figure 10 This is a diagram illustrating an example of a hardware implementation of device 1000. In some examples, device 1000 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1002 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1002 may include one or more processors 1004 controlled by some combination of hardware modules and software modules. Examples of processors 1004 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors 1004 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1016. One or more processors 1004 may be configured by a combination of software modules 1016 loaded during initialization and may be further configured by loading or unloading one or more software modules 1016 during operation.

[0075] In the illustrated example, processing circuitry 1002 may be implemented using a bus architecture, typically represented by bus 1010. Bus 1010 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1002 and overall design constraints. Bus 1010 links together various circuits including one or more processors 1004 and storage devices 1006. Storage devices 1006 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1010 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuitry. Bus interface 1008 provides an interface between bus 1010 and one or more transceivers 1012a, 1012b. Transceivers 1012a, 1012b may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1012a, 1012b. Each transceiver 1012a, 1012b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1012a may be used to couple device 1000 to a multi-wire bus. In another example, transceiver 1012b may be used to connect device 1000 to a radio access network. Depending on the nature of device 1000, a user interface 1018 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1010, either directly or via bus interface 1008.

[0076] Processor 1004 may be responsible for managing bus 1010 and for general processing, which may include executing software stored in a computer-readable medium (which may include storage device 1006). In this regard, processing circuitry 1002 (including processor 1004) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1006 may be used to store data manipulated by processor 1004 during software execution, and the software may be configured to implement certain methods disclosed herein.

[0077] One or more processors 1004 in the processing circuitry 1002 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. The software may reside in a computer-readable form in storage device 1006 or on an external computer-readable medium. External computer-readable media and / or storage device 1006 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital multifunction discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1006 may also include, for example, carrier waves, transmission lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1006 may reside in processing circuitry 1002, in processor 1004, outside of processing circuitry 1002, or distributed across multiple entities including processing circuitry 1002. The computer-readable media and / or storage device 1006 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize that the optimal implementation of the functions described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0078] Storage device 1006 can maintain and / or organize software in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1016. Each software module in software module 1016 may include instructions and data that, when installed or loaded on processing circuitry 1002 and executed by one or more processors 1004, contribute to a runtime image 1014 that controls the operation of one or more processors 1004. Some instructions, when executed, cause processing circuitry 1002 to perform functions according to certain methods, algorithms, and processes described herein.

[0079] Some software modules in software module 1016 may be loaded during the initialization of processing circuit 1002, and these software modules 1016 may configure processing circuit 1002 to perform the various functions disclosed herein. For example, some software modules 1016 may configure the internal devices and / or logic circuit 1022 of processor 1004, and may manage access to external devices such as transceivers 1012a, 1012b, bus interface 1008, user interface 1018, timers, math coprocessors, etc. Software module 1016 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuit 1002. Resources may include memory, processing time, access to transceivers 1012a, 1012b, user interface 1018, etc.

[0080] One or more processors 1004 of the processing circuitry 1002 can be multifunctional, whereby some software modules in software module 1016 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1004 may also be adapted to manage background tasks initiated in response to inputs, for example, from user interface 1018, transceivers 1012a, 1012b, and device drivers. To support the execution of multiple functions, one or more processors 1004 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1004 as needed or desired. In one example, the multitasking environment may be implemented using a time-sharing program 1020 that transfers control of processor 1004 between different tasks, whereby each task returns control of one or more processors 1004 to the time-sharing program 1020 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1004, the processing circuitry is effectively dedicated to the purpose addressed by the functions associated with the control task. The time-sharing program 1020 may include an operating system, a main loop for loop-based transfer control, functions for allocating control of one or more processors 1004 according to function priority, and / or an interrupt-driven main loop for providing control of one or more processors 1004 to processing functions in response to external events.

[0081] Figure 11 This is a flowchart 1100 of a method for operating communication interface circuitry configured according to certain aspects of this disclosure. In some cases, the method is implemented using one or more processors in a mobile communication device that includes a display or camera subsystem. The one or more processors may include a finite state machine.

[0082] At block 1102 of the illustrated method, the symbol stream is converted into multiple data words at the data recovery circuit. The symbol stream may be received via three wires of a serial bus according to a high-speed mode defined by the MIPI Alliance C-PHY protocol. At block 1104 of the illustrated method, the multiple data words may be provided to the protocol interface circuit. At block 1106 of the illustrated method, the data recovery circuit may be disabled when the first EOT signal received from the protocol interface circuit indicates the end of transmission.

[0083] In some examples, after indicating the end of transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol can be received at the interface circuitry. After indicating the end of transmission, a continuous symbol mode corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol can be received.

[0084] In some implementations, the transmission ends when the protocol interface circuit has finished processing the data received from the data recovery circuit. In some implementations, a FIFO buffer circuit configured to store multiple data words is used to couple the protocol interface circuit to the output of the data recovery circuit. The transmission ends when the FIFO buffer has been cleared of multiple data words.

[0085] In some examples, a protocol interface clock signal can be generated to control the operation of the protocol interface circuitry. This protocol interface clock signal can be suppressed when the data recovery circuitry is disabled.

[0086] Figure 12 This is a diagram illustrating a first example of a hardware implementation of a device 1200 employing processing circuitry 1202. The processing circuitry typically has one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, and is typically represented by processor 1216. Processing circuitry 1202 may be implemented using a bus architecture, typically represented by bus 1220. Bus 1220 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1202 and overall design constraints. Bus 1220 links together various circuits including multiple processors 1216, modules or circuits 1204, 1206, and 1208, and processor-readable storage medium 1218. Bus interface circuitry and / or modules 1214 may be provided to support communication over multiple serial data links 1212. Bus 1220 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and will therefore not be described further.

[0087] Processor 1216 may be responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1218. Processor-readable storage medium 1218 may include non-transitory storage medium. When executed by processor 1216, the software causes processing circuitry 1202 to perform the various functions described above for any particular device. Processor-readable storage medium may be used to store data manipulated by processor 1216 when executing the software. Processing circuitry 1202 also includes at least one of modules 1204, 1206, and 1208. Modules 1204, 1206, and 1208 may be software modules running in processor 1216, residing in / stored in processor-readable storage medium 1218, one or more hardware modules coupled to processor 1216, or some combination thereof. Modules 1204, 1206, and 1208 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0088] In one configuration, the device 1200 includes: a module and / or circuit 1204 adapted to convert a 3-bit symbol stream into parallel multi-bit data words; a module and / or circuit 1206 adapted to compare symbol sequences; and a module and / or circuit 1208 adapted to detect patterns in the symbol stream, including EOT patterns.

[0089] In one example, apparatus 1200 includes: components for converting a symbol stream into multiple data words at a data recovery circuit; components including protocol interface circuitry for processing the multiple data words; and components for disabling the data recovery circuitry when a first EOT signal received from the protocol interface circuitry indicates the end of transmission. The symbol stream may be received via three wires of a serial bus in a high-speed mode defined by the MIPI Alliance C-PHY protocol.

[0090] In some implementations, after the indication transmission ends, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit. In some implementations, when the indication transmission ends, the reception of symbol modes corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

[0091] In some implementations, the transmission ends when the protocol interface circuit has finished processing the data received from the data recovery circuit. The apparatus 1200 may include a FIFO buffer circuit that couples the protocol interface circuit to the output of the data recovery circuit. The FIFO buffer circuit may be configured to store multiple data words received from the data recovery circuit. The transmission ends when the FIFO buffer has been cleared of multiple data words.

[0092] In some implementations, device 1200 includes a clock generation circuit configured to provide a protocol interface clock signal that controls the operation of the protocol interface circuitry. The protocol interface clock signal can be suppressed when the data recovery circuitry is disabled.

[0093] In some implementations, the device 1200 includes a synchronization circuit configured to propagate the first EOT signal as the second EOT signal according to timing provided by an internally generated clock signal used by a finite state machine.

[0094] The processor-readable storage medium 1218 may include instructions that cause the processing circuitry 1202 to perform the following operations: convert the symbol stream at the data recovery circuitry to provide multiple data words; provide the multiple data words to the protocol interface circuitry; and disable the data recovery circuitry when a first EOT signal received from the protocol interface circuitry indicates the end of transmission. The symbol stream may be received via three wires of a serial bus in a high-speed mode defined by the MIPI Alliance C-PHY protocol.

[0095] In some cases, after the indication of completion of transmission, signaling defined for switching the serial bus to a low-speed mode as defined by the MIPI Alliance C-PHY protocol is received at the interface circuitry. In other cases, when the indication of completion of transmission ends, reception of symbolic modes corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

[0096] In some implementations, the transmission ends when the protocol interface circuit has finished processing the data received from the data recovery circuit. A FIFO buffer circuit, which couples the protocol interface circuit to the output of the data recovery circuit, can be configured to store multiple data words received from the data recovery circuit. The transmission ends when the FIFO buffer is empty of multiple data words.

[0097] In some specific implementations, the code is further configured to cause the processing circuitry to suppress the protocol interface clock signal that controls the operation of the protocol interface circuitry when the data recovery circuitry is disabled.

[0098] The interface circuitry provided according to certain aspects of this disclosure includes: a data recovery circuitry configured to receive a symbol stream via three wires of a serial bus in a high-speed mode defined by the MIPI Alliance C-PHY protocol; a protocol interface circuitry coupled to the output of the data recovery circuitry and configured to receive data from the data recovery circuitry; and a finite state machine configured to disable the data recovery circuitry when a first EOT signal received from the protocol interface circuitry indicates the end of transmission.

[0099] In some cases, after the indication of completion of transmission, signaling defined for switching the serial bus to a low-speed mode as defined by the MIPI Alliance C-PHY protocol is received at the interface circuitry. In other cases, when the indication of completion of transmission ends, reception of symbolic modes corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

[0100] In some implementations, the end of transmission is indicated when the protocol interface circuit has completed processing the data received from the data recovery circuit. The interface circuit may include a FIFO buffer circuit configured to couple the protocol interface circuit to the output of the data recovery circuit. This FIFO buffer circuit may be configured to store multiple data words received from the data recovery circuit. The end of transmission can be indicated when the FIFO buffer has been cleared of multiple data words.

[0101] The clock generation circuit can be configured to provide a protocol interface clock signal that controls the operation of the protocol interface circuitry. The protocol interface clock signal can be suppressed when the data recovery circuit is disabled. The synchronization circuit can be configured to propagate the first EOT signal as the second EOT signal based on timing provided by an internally generated clock signal used by the finite state machine.

[0102] Some specific implementation examples are described in the following numbered clauses: 1. An interface circuit comprising: a data recovery circuit configured to receive a symbol stream via three wires of a serial bus in a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; a protocol interface circuit coupled to an output of the data recovery circuit and configured to receive data from the data recovery circuit; and a finite state machine configured to disable the data recovery circuit when a first End of Transmission (EOT) signal received from the protocol interface circuit indicates the end of transmission.

[0103] 2. The interface circuit according to Clause 1, wherein after indicating the end of the transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

[0104] 3. The interface circuitry according to Clause 1 or Clause 2, wherein when the transmission is indicated to be finished, reception of a symbolic mode corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

[0105] 4. An interface circuit according to any one of Clauses 1 to 3, wherein the transmission is indicated to be complete when the protocol interface circuit has finished processing the data received from the data recovery circuit.

[0106] 5. The interface circuit according to any one of Clauses 1 to 4, further comprising: a first-in-first-out (FIFO) buffer circuit that couples the protocol interface circuit to the output of the data recovery circuit, the FIFO buffer circuit being configured to store a plurality of data words received from the data recovery circuit.

[0107] 6. The interface circuit according to Clause 5, wherein the transmission ends when the FIFO buffer has been cleared of the plurality of data words.

[0108] 7. The interface circuit according to any one of Clauses 1 to 6, further comprising: a clock generation circuit configured to provide a protocol interface clock signal for controlling the operation of the protocol interface circuit, wherein the protocol interface clock signal is suppressed when the data recovery circuit is disabled.

[0109] 8. The interface circuit according to any one of Clauses 1 to 7, the interface circuit further comprising: a synchronization circuit configured to propagate the first EOT signal as a second EOT signal according to timing provided by an internally generated clock signal used by the finite state machine.

[0110] 9. A method for operating a communication interface circuit, the method comprising: converting a symbol stream into a plurality of data words at a data recovery circuit, the symbol stream being received via three wires of a serial bus according to a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; providing the plurality of data words to a protocol interface circuit; and disabling the data recovery circuit when a first End of Transmission (EOT) signal received from the protocol interface circuit indicates the end of transmission.

[0111] 10. The method according to Clause 9, further comprising: after indicating the end of the transmission, receiving at the interface circuitry a signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol.

[0112] 11. The method according to Clause 9 or Clause 10, the method further comprising: after indicating the end of the transmission, receiving a continuous symbol pattern corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol.

[0113] 12. The method according to any one of Clauses 9 to 11, wherein the transmission is indicated to be complete when the protocol interface circuit has finished processing the data received from the data recovery circuit.

[0114] 13. The method according to any one of Clauses 9 to 12, the method further comprising: coupling the protocol interface circuit to the output of the data recovery circuit using a first-in-first-out (FIFO) buffer circuit configured to store the plurality of data words.

[0115] 14. The method according to Clause 13, wherein the transmission is indicated to be complete when the FIFO buffer has been cleared of the plurality of data words.

[0116] 15. The method according to any one of Clauses 9 to 14, the method further comprising: generating a protocol interface clock signal for controlling the operation of the protocol interface circuitry, wherein the protocol interface clock signal is suppressed when the data recovery circuitry is disabled.

[0117] 16. An apparatus comprising: means for converting a symbol stream into a plurality of data words at a data recovery circuit, the symbol stream being received via three wires of a serial bus according to a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; means for processing the plurality of data words including protocol interface circuitry; and means for disabling the data recovery circuitry when a first End of Transmission (EOT) signal received from the protocol interface circuitry indicates the end of transmission.

[0118] 17. The apparatus according to Clause 16, wherein after indicating the end of the transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

[0119] 18. The apparatus according to Clause 16 or Clause 17, wherein when the transmission is indicated to be finished, reception of a symbolic pattern corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

[0120] 19. The apparatus according to any one of Clauses 16 to 18, wherein the transmission is indicated as finished when the protocol interface circuit has completed processing of the data received from the data recovery circuit.

[0121] 20. The apparatus according to any one of Clauses 16 to 19, further comprising: a first-in-first-out (FIFO) buffer circuit that couples the protocol interface circuit to the output of the data recovery circuit, the FIFO buffer circuit being configured to store a plurality of data words received from the data recovery circuit.

[0122] 21. The apparatus according to any one of Clauses 16 to 20, wherein the transmission is indicated to be complete when the FIFO buffer has been cleared of the plurality of data words.

[0123] 22. The apparatus according to any one of Clauses 16 to 21, further comprising: a clock generation circuit configured to provide a protocol interface clock signal for controlling the operation of the protocol interface circuitry, wherein the protocol interface clock signal is suppressed when the data recovery circuitry is disabled.

[0124] 23. The apparatus according to any one of Clauses 16 to 22, further comprising: a synchronization circuit configured to propagate the first EOT signal as a second EOT signal according to timing provided by an internally generated clock signal used by the finite state machine.

[0125] 24. A processor-readable storage medium comprising code configured to cause processing circuitry to perform the following operations: converting a symbol stream at a data recovery circuitry to provide a plurality of data words, the symbol stream being received via three wires of a serial bus according to a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; providing the plurality of data words to protocol interface circuitry; and disabling the data recovery circuitry when a first End of Transmission (EOT) signal received from the protocol interface circuitry indicates the end of transmission.

[0126] 25. The processor-readable storage medium according to Clause 24, wherein, after indicating the end of the transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

[0127] 26. A processor-readable storage medium according to Clause 24 or Clause 25, wherein, when the transmission is indicated to be finished, reception of a symbolic mode corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

[0128] 27. The processor-readable storage medium of claim 24, wherein the transmission is indicated as finished when the protocol interface circuit has completed processing of the data received from the data recovery circuit.

[0129] 28. A processor-readable storage medium according to any one of Clauses 24 to 27, wherein a first-in-first-out (FIFO) buffer circuit couples the protocol interface circuit to the output of the data recovery circuit, the FIFO buffer circuit being configured to store a plurality of data words received from the data recovery circuit.

[0130] 29. The processor-readable storage medium according to Clause 28, wherein the transmission is indicated to be complete when the FIFO buffer has been cleared of the plurality of data words.

[0131] 30. A processor-readable storage medium according to any one of Clauses 24 to 29, wherein the code is further configured to cause the processing circuitry to: suppress a protocol interface clock signal controlling the operation of the protocol interface circuitry when the data recovery circuitry is disabled.

[0132] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0133] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the language of the claims, wherein an element referred to in the singular is not intended to mean “one and only one,” but rather “one or more” unless specifically stated otherwise. Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents of the elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly recited in the claims. No claim element should be construed as a component plus a function unless the element is explicitly stated using the phrase “component for…”.

Claims

1. An interface circuit, the interface circuit comprising: A data recovery circuit configured to receive a symbol stream via three wires of a serial bus in a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; A protocol interface circuit, which is coupled to the output of the data recovery circuit and configured to receive data from the data recovery circuit; and A finite state machine configured to disable the data recovery circuit when a first End of Transmission (EOT) signal received from the protocol interface circuit indicates the end of transmission.

2. The interface circuit of claim 1, wherein after indicating the end of transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

3. The interface circuit of claim 1, wherein when the transmission is indicated to be finished, reception continues to receive a symbolic mode corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol.

4. The interface circuit according to claim 1, wherein the transmission ends when the protocol interface circuit has completed processing the data received from the data recovery circuit.

5. The interface circuit according to claim 1, further comprising: A first-in-first-out (FIFO) buffer circuit, which couples the protocol interface circuit to the output of the data recovery circuit, is configured to store a plurality of data words received from the data recovery circuit.

6. The interface circuit according to claim 5, wherein the transmission ends when the FIFO buffer has been cleared of the plurality of data words.

7. The interface circuit according to claim 1, further comprising: A clock generation circuit is configured to provide a protocol interface clock signal that controls the operation of the protocol interface circuit, wherein the protocol interface clock signal is suppressed when the data recovery circuit is disabled.

8. The interface circuit according to claim 1, further comprising: A synchronization circuit is configured to propagate the first EOT signal as a second EOT signal according to timing provided by an internally generated clock signal used by the finite state machine.

9. A method for operating a communication interface circuit, the method comprising: At the data recovery circuit, the symbol stream is converted into multiple data words, the symbol stream being received via three wires of a serial bus in a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; Provide the plurality of data words to the protocol interface circuit; as well as The data recovery circuit is disabled when the first End of Transmission (EOT) signal received from the protocol interface circuit indicates that transmission has ended.

10. The method according to claim 9, further comprising: After indicating the end of the transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

11. The method according to claim 9, further comprising: After indicating the end of the transmission, receive a continuous symbol pattern corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol.

12. The method of claim 9, wherein the transmission ends when the protocol interface circuit has completed processing the data received from the data recovery circuit.

13. The method according to claim 9, further comprising: The protocol interface circuit is coupled to the output of the data recovery circuit using a first-in-first-out (FIFO) buffer circuit configured to store the plurality of data words.

14. The method of claim 13, wherein the transmission ends when the FIFO buffer has been cleared of the plurality of data words.

15. The method according to claim 9, further comprising: A protocol interface clock signal is generated to control the operation of the protocol interface circuit, wherein the protocol interface clock signal is suppressed when the data recovery circuit is disabled.

16. An apparatus comprising: A component used to convert a symbol stream into multiple data words at the data recovery circuit, the symbol stream being received via three wires of a serial bus in a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol; A component including a protocol interface circuit for processing the plurality of data words; and A component for disabling the data recovery circuit when a first End of Transmission (EOT) signal received from the protocol interface circuit indicates that transmission has ended.

17. The apparatus of claim 16, wherein after indicating the end of transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

18. The apparatus of claim 16, wherein when the transmission is indicated to be finished, reception of a symbolic pattern corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

19. The apparatus of claim 16, wherein the transmission is indicated to be complete when the protocol interface circuit has finished processing the data received from the data recovery circuit.

20. The apparatus of claim 16, further comprising: A first-in-first-out (FIFO) buffer circuit is provided, which couples the protocol interface circuit to the output of the data recovery circuit. The FIFO buffer circuit is configured to store multiple data words received from the data recovery circuit.

21. The apparatus of claim 20, wherein the transmission is indicated to be complete when the FIFO buffer has been cleared of the plurality of data words.

22. The apparatus of claim 16, further comprising: A clock generation circuit is configured to provide a protocol interface clock signal that controls the operation of the protocol interface circuit, wherein the protocol interface clock signal is suppressed when the data recovery circuit is disabled.

23. The apparatus of claim 16, further comprising: A synchronization circuit configured to propagate the first EOT signal as a second EOT signal according to timing provided by an internally generated clock signal used by the component for disabling the data recovery circuit.

24. A processor-readable storage medium comprising code configured to cause processing circuitry to perform the following operations: At the data recovery circuit, the symbol stream is converted to provide multiple data words. The symbol stream is received via three wires of a serial bus in a high-speed mode defined by the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol. Provide the plurality of data words to the protocol interface circuit; as well as The data recovery circuit is disabled when the first End of Transmission (EOT) signal received from the protocol interface circuit indicates that transmission has ended.

25. The processor-readable storage medium of claim 24, wherein after indicating the end of transmission, signaling defined for switching the serial bus to a low-speed mode defined by the MIPI Alliance C-PHY protocol is received at the interface circuit.

26. The processor-readable storage medium of claim 24, wherein when the transmission is indicated to be finished, reception of a symbolic mode corresponding to the POST mode defined by the MIPI Alliance C-PHY protocol continues.

27. The processor-readable storage medium of claim 24, wherein the transmission is indicated as finished when the protocol interface circuit has completed processing of the data received from the data recovery circuit.

28. The processor-readable storage medium of claim 24, wherein a first-in-first-out (FIFO) buffer circuit couples the protocol interface circuit to the output of the data recovery circuit, the FIFO buffer circuit being configured to store a plurality of data words received from the data recovery circuit.

29. The processor-readable storage medium of claim 28, wherein the transmission is indicated to be complete when the FIFO buffer has been cleared of the plurality of data words.

30. The processor-readable storage medium of claim 24, wherein the code is further configured to cause the processing circuitry to: When the data recovery circuit is disabled, the protocol interface clock signal that controls the operation of the protocol interface circuit is suppressed.

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