Communication interface conversion method, device, equipment and readable storage medium
By using a cross-clock domain conversion method with FIFO buffers and ODDR registers, the problem of data loss and errors caused by interface conversion in Ethernet communication systems is solved, ensuring the reliability of system communication.
CN121284128BActive Publication Date: 2026-05-22CYG SUNRI CO LTD
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Patent Information
- Application Number
- CN202511833137.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-08
- Publication Date
- 2026-05-22
- Estimated Expiration
- 2045-12-08
AI Technical Summary
Technical Problem
Existing cross-standard interface conversion schemes are prone to data loss and packet errors in Ethernet communication systems, affecting the reliability of system communication.
Method used
Cross-clock domain data conversion is achieved by using a FIFO buffer and an ODDR register. The specific steps include converting the RGMII receive data signal into the MII receive data signal and the MII transmit data signal into the RGMII transmit data signal, and using the different clock domain isolation mechanism of the FIFO buffer to perform data format conversion.
Benefits of technology
This effectively avoids data loss and errors, ensures the reliability of system communication, and enables stable data transmission between the RGMII interface and the MII interface.
✦ Generated by Eureka AI based on patent content.
Abstract
The application is suitable for the field of communication technology, and provides a communication interface conversion method, device, equipment and readable storage medium. The method comprises the following steps: acquiring an RGMII receiving data signal, the RGMII receiving data signal being output by a PHY layer through an RGMII interface; converting the RGMII receiving data signal into an MII receiving data signal through a first FIFO buffer; acquiring an MII sending data signal, the MII sending data signal being output by a MAC layer through an MII interface; converting the MII sending data signal under an MII clock domain into an MII sending data signal under a system clock domain through a second FIFO buffer; generating an RGMII sending clock based on a system clock through an ODDR, and converting the MII sending data signal under the system clock domain into an RGMII sending data signal based on the RGMII sending clock. Therefore, the application can avoid the occurrence of data loss, data error and the like in the interface conversion process as much as possible.
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