Liquid ejecting apparatus and head unit

Abstract

The invention provides a liquid ejecting apparatus and a head unit, which can reduce the possibility that a drive circuit substrate needs to be replaced when a head fails. The liquid ejecting apparatus includes: a head portion including an ejecting portion that ejects a liquid by a drive signal; and a driving circuit substrate connected to the head portion, the driving circuit substrate including: a driving circuit outputting the driving signal; a first power supply wiring connecting a power supply circuit and the head; and a first overcurrent protection circuit provided on the first power supply wiring, the first overcurrent protection circuit having: a first mode in which the power supply circuit and the head are turned on; and a second mode in which the power supply circuit and the header are brought into a non-conductive state, and when the current flowing through the first power supply wiring is equal to or greater than a predetermined value, the first mode is switched to the second mode, and the second mode can be switched to the first mode.

Description

Technical Field

[0001] This invention relates to a liquid ejection device and a head unit. Background Technology

[0002] In liquid ejection devices such as inkjet printers that eject ink to print images and documents, liquid ejection devices using piezoelectric elements, such as piezoelectric effect elements, are known. The piezoelectric element is disposed in the head corresponding to each of a plurality of nozzles, and each nozzle is driven according to a drive signal. Thus, a predetermined amount of liquid is ejected from the nozzles formed in the head at a predetermined time, forming dots on the printing medium.

[0003] In such liquid ejection devices, a high voltage of 42V is supplied to the head as a power supply to control the supply of the drive signal to the piezoelectric element. In such a power supply voltage transmission path, the liquid ejection device may malfunction in the event of an abnormality such as overvoltage or overcurrent. In contrast, Patent Document 1 proposes a liquid ejection device in which multiple drive circuits monitor the power supply voltage supplied to the head, and a fuse is installed in the power supply voltage transmission wiring path.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2020-116867

[0005] However, if the voltage of the drive signal is higher than the high voltage supplied to the head, excessive current will flow from the drive signal wiring to the head power supply wiring due to the parasitic diodes present in the head, potentially causing the head to malfunction. For example, stabilizing capacitors are connected to ground on both the head power supply wiring and the drive circuit power supply wiring, and the capacitor connected to the drive circuit power supply wiring has a larger capacitance to facilitate the charging and discharging of the piezoelectric element. Therefore, when the power supply stops due to power abnormalities, the voltage of the head power supply wiring sometimes drops faster than that of the drive circuit power supply wiring, temporarily making the drive circuit power supply wiring a higher voltage than the head power supply wiring. Furthermore, the voltage of the drive signal may sometimes be higher than that of the drive circuit power supply wiring due to the inductance of the transmission path. In the liquid ejection device described in Patent Document 1, if the overcurrent protection function of the fuse is activated due to a head malfunction, the fuse will blow, requiring not only the malfunctioning head to be replaced but also the substrate on which the fuse is installed. Summary of the Invention

[0006] One embodiment of the liquid ejection device according to the present invention comprises:

[0007] Conveying section, conveying medium;

[0008] The head includes a drive section driven by a drive signal and an ejection section that ejects liquid from the medium according to the drive section; and

[0009] The drive circuit board is connected to the head.

[0010] The driving circuit substrate includes:

[0011] The driving circuit outputs the driving signal;

[0012] The first power supply wiring connects the power circuit and the head; and

[0013] The first overcurrent protection circuit is installed on the first power supply wiring.

[0014] The first overcurrent protection circuit has:

[0015] In the first mode, the power circuit and the head are in a conductive state; and

[0016] In the second mode, the power supply circuit and the head are in a non-conductive state.

[0017] If the current flowing through the first power supply wiring is above a predetermined value, the system switches from the first mode to the second mode.

[0018] It can switch from the second mode to the first mode.

[0019] One embodiment of the header unit involved in this invention comprises:

[0020] The head includes a drive section driven by a drive signal and has an ejection section that ejects liquid from a medium according to the drive section; and

[0021] The drive circuit board is connected to the head.

[0022] The driving circuit substrate includes:

[0023] The driving circuit outputs the driving signal;

[0024] The first power supply wiring connects the power circuit and the head; and

[0025] The first overcurrent protection circuit is installed on the first power supply wiring.

[0026] The first overcurrent protection circuit has:

[0027] In the first mode, the power circuit and the head are in a conductive state; and

[0028] In the second mode, the power supply circuit and the head are in a non-conductive state.

[0029] If the current flowing through the first power supply wiring is above a predetermined value, the system switches from the first mode to the second mode.

[0030] It can switch from the second mode to the first mode. Attached Figure Description

[0031] Figure 1 This is a perspective view showing the general structure of the liquid ejection device.

[0032] Figure 2 This is a block diagram showing the electrical structure of the liquid ejection device.

[0033] Figure 3 This is a diagram illustrating an example of the drive signal COM.

[0034] Figure 4 This is a block diagram showing the electrical structure of the drive signal selection circuit.

[0035] Figure 5 This is a circuit diagram showing the electrical structure of the selection circuit.

[0036] Figure 6 This is a diagram showing the decoded content in the decoder.

[0037] Figure 7 This is a diagram used to illustrate the operation of the drive signal selection circuit.

[0038] Figure 8 This is a cross-sectional view showing the general structure of the ejector section.

[0039] Figure 9 This is a block diagram showing the circuit structure of the drive circuit board in the first embodiment.

[0040] Figure 10 This is a diagram showing an example of the structure of an overcurrent protection circuit.

[0041] Figure 11 This is a block diagram showing the structure of the drive circuit.

[0042] Figure 12 This is a diagram illustrating an example of the startup sequence of a drive circuit.

[0043] Figure 13 This is a block diagram showing the circuit structure of the drive circuit board in the second embodiment.

[0044] Figure 14 This is a block diagram showing the circuit structure of the drive circuit board in the third embodiment.

[0045] Figure 15 This is a block diagram showing the circuit structure of the drive circuit board in the fourth embodiment.

[0046] Explanation of reference numerals in the attached figures

[0047] 1…Liquid ejection device, 2…Moving body, 3…Moving mechanism, 4…Conveying mechanism, 10…Control unit, 20…Head unit, 21, 21a, 21b, 21c, 21d…Liquid ejection module, 22…Print head, 24…Carriage, 31…Carriage motor, 32…Carriage guide shaft, 33…Synchronous belt, 40…Tablet, 41…Conveyor motor, 42…Conveyor roller, 50…Drive circuit board, 51, 51a, 51b, 51c, 51d…Drive circuit, 52, 53, 54…Resistors, 60, 60a, 60b, 60c, 60d…Piezoelectric element, 70, 70a, 70b, 70c…Overcurrent protection circuit, 71a, 71b, 71c, 71d…Logic circuit, 72… 73, 74… Resistors, 75a, 75b, 75c… Power supply wiring, 76a, 76b, 76c… Capacitors, 77… Fuse, 80… Startup control circuit, 90… Power supply circuit, 91… Oscillator circuit, 100… Control circuit, 190… Cable, 200, 200a, 200b, 200c, 200d… Drive signal selection circuit, 210… Selection control circuit, 212… Shift register, 214… Latch circuit, 216… Decoder, 230… Selection circuit, 232… Inverter, 234… Transmission gate, 235, 236… Transistors, 400… Voltage generation circuit, 410… Oscillator circuit, 420… Clock selection circuit, 430… Anomaly detection circuit, 43… 1…Oscillation Anomaly Detection Unit, 432…Action Anomaly Detection Unit, 433…Power Supply Voltage Anomaly Detection Unit, 440…Registry Control Circuit, 441…Sequence Register, 442…Status Register, 443…Registry Control Unit, 450…Drive Signal Discharge Circuit, 451…Resistor, 452…Transistor, 460…Reference Voltage Signal Output Circuit, 462, 463…Transistors, 464, 465, 466…Resistor, 467…Inverter, 470…VHV Control Signal Output Circuit, 471…Transistor, 480…Status Signal Input / Output Circuit, 481…Transistor, 482…Inverter, 490…Error Signal Input / Output Circuit, 491…Transistor, 492…Inverter, 5 00…Integrated circuit, 501…Drive signal generation circuit, 502…Amplification control signal generation circuit, 510…DAC interface, 520…DAC section, 530…Modulation section, 540…Gate drive section, 550…Drive signal amplification circuit, 551, 552…Transistor, 553…Coil, 554…Capacitor, 555, 556, 576…Resistor, 600, 600a, 600b, 600c, 600d…Ejector section, 601…Piezoelectric element, 611, 612…Electrode, 621…Vibrating plate, 631…Cavity, 632…Nozzle plate, 641…Reservoir, 651…Nozzle, 661…Supply port, 700…Electronic fuse IC, 701, 702…Resistor. Detailed Implementation

[0048] Preferred embodiments of the present invention will now be described using the accompanying drawings. The drawings are provided for ease of explanation. Furthermore, the embodiments described below do not unduly limit the scope of the invention as defined in the claims. Additionally, the structures described below are not necessarily all essential components of the present invention.

[0049] 1. First Implementation Method

[0050] 1-1. Structure of the liquid ejection device

[0051] As an example of the liquid ejection device involved in this embodiment, the printing device is an inkjet printer, which ejects ink according to image data input from an external host computer, thereby forming dots on a printing medium such as paper and printing an image containing text, graphics, etc., corresponding to the image data.

[0052] Figure 1 This is a perspective view showing the schematic structure of the liquid ejection device 1. Figure 1 The diagram illustrates the direction X of the transport medium P, the direction Y intersecting direction X and in which the moving body 2 reciprocates, and the direction Z of ink ejection. In this embodiment, directions X, Y, and Z are described as mutually orthogonal axes, but the arrangement is not limited to various orthogonal configurations of the liquid ejection device 1. Furthermore, in the following description, the direction Y of the moving body 2's movement is sometimes referred to as the main scanning direction.

[0053] like Figure 1 As shown, the liquid ejection device 1 includes a movable body 2 and a moving mechanism 3 that reciprocates the movable body 2 along the direction Y. The moving mechanism 3 includes: a carriage motor 31, which serves as the drive source for the movable body 2; a carriage guide shaft 32, both ends of which are fixed; and a timing belt 33, which extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0054] The carriage 24 included in the moving body 2 is supported by a carriage guide shaft 32 for free reciprocating movement and is fixed to a portion of a timing belt 33. Furthermore, by driving the timing belt 33 via a carriage motor 31, the carriage 24 is guided by the carriage guide shaft 32 to reciprocate along the Y direction. Additionally, a head unit 20 with multiple nozzles is provided in the portion of the moving body 2 opposite to the medium P. Control signals are input to the head unit 20 via a cable 190. Based on the input control signals, the head unit 20 ejects ink, for example a liquid, from the nozzles.

[0055] The liquid ejection device 1 includes a conveying mechanism 4 that conveys the medium P along the direction X on a platform 40. The conveying mechanism 4 includes a conveying motor 41 as a drive source and a conveying roller 42 that is rotated by the conveying motor 41 to convey the medium P along the direction X.

[0056] In the liquid ejection device 1 configured as described above, when the medium P is conveyed by the conveying mechanism 4, the head unit 20 ejects ink, thereby forming an image on the surface of the medium P.

[0057] 1-2. Electrical structure of the liquid ejection device

[0058] Figure 2 This is a block diagram showing the electrical structure of the liquid ejection device 1. (Example) Figure 2 As shown, the liquid ejection device 1 has a control unit 10 and a head unit 20. The control unit 10 and the head unit 20 are electrically connected by a cable 190 such as a flexible flat cable (FFC).

[0059] The control unit 10 includes a control circuit 100, a power supply circuit 90, and an oscillation circuit 91. Furthermore, the control circuit 100 generates multiple control signals for controlling various structures based on image data input from the host computer and outputs them to the head unit 20.

[0060] Specifically, the control circuit 100 outputs clock signal SCK, printing data signals SIa, SIb, SIc, Sid, latch signals LATa, LATb, LATc, LATd, change signals CHA, CHb, CHc, CHd, and drive data signals DATAa, DATAb, DATAc, DATAd to the head unit 20.

[0061] Furthermore, although the diagram is omitted, the control circuit 100 controls the carriage motor 31 and the conveyor motor 41. Thus, the control... Figure 1 The movement of the carriage 24 in the Y direction shown, Figure 1 The movement of medium P in the direction X shown.

[0062] The power supply circuit 90 generates, for example, DC 42V voltages VHV_H, VHV_A1, and VHV_A2. Furthermore, the power supply circuit 90 supplies voltages VHV_H, VHV_A1, and VHV_A2 to the head unit 20.

[0063] The oscillator circuit 91 outputs a clock signal MCK. The clock signal MCK output from the oscillator circuit 91 is input to the head unit 20. Additionally, as... Figure 2 As shown, the oscillation circuit 91 can be constructed independently of the control circuit 100, or it can be constructed inside the control circuit 100.

[0064] The head unit 20 includes a print head 22 and a drive circuit board 50. The drive circuit board 50 is connected to the print head 22.

[0065] The drive circuit board 50 includes drive circuits 51a, 51b, 51c, and 51d. Drive circuits 51a, 51b, 51c, and 51d drive the liquid ejection modules 21a, 21b, 21c, and 21d contained in the printhead 22, respectively.

[0066] Drive circuit 51a generates drive signal COMA and reference voltage signal VBSa based on voltage VHV_A1, drive data signal DATAa, and clock signal MCK, and outputs them to liquid ejection module 21a. Drive circuit 51b generates drive signal COMb and reference voltage signal VBSb based on voltage VHV_A1, drive data signal DATAb, and clock signal MCK, and outputs them to liquid ejection module 21b. Drive circuit 51c generates drive signal COMc and reference voltage signal VBSc based on voltage VHV_A2, drive data signal DATAc, and clock signal MCK, and outputs them to liquid ejection module 21c. Drive circuit 51d generates drive signal COMd ​​and reference voltage signal VBSd based on voltage VHV_A2, drive data signal DATAd, and clock signal MCK, and outputs them to liquid ejection module 21d. Here, reference voltage signals VBSa, VBSb, VBSc, and VBSd are constant voltage signals, such as ground potential, DC 5V, DC 6V, etc.

[0067] In addition, Figure 2 The diagrams are omitted due to their complexity, but the drive circuit board 50 also includes circuits other than drive circuits 51a, 51b, 51c, and 51d. The details of the circuit structure and operation of the drive circuit board 50 will be described later.

[0068] The printhead 22 includes liquid ejection modules 21a, 21b, 21c, and 21d. Each liquid ejection module 21a has a drive signal selection circuit 200a and multiple ejection sections 600a. Furthermore, each ejection section 600a includes a piezoelectric element 60a. A clock signal SCK, a print data signal SIa, a latch signal LATa, a change signal CHa, a drive signal COMA, and a voltage VHV_H are input to the drive signal selection circuit 200a. Based on the clock signal SCK, print data signal SIa, latch signal LATa, change signal CHa, and voltage VHV_H, the drive signal selection circuit 200a selects or deselects the drive signal COMA, thereby generating a drive signal VOUTa.

[0069] A drive signal VOUTa is supplied to one end of a piezoelectric element 60a included in each of the plurality of ejection sections 600a. Furthermore, a reference voltage signal VBSa is supplied to the other end of the piezoelectric element 60a. Moreover, the piezoelectric element 60a is driven by the potential difference between the drive signal VOUTa and the reference voltage signal VBSa, ejecting ink from the ejection section 600a. That is, the liquid ejection module 21a has a piezoelectric element 60a driven by a drive signal COMA and a drive signal selection circuit 200a that controls the supply of the drive signal COMA to the piezoelectric element 60a.

[0070] The liquid ejection module 21b includes a drive signal selection circuit 200b and multiple ejection sections 600b. Each ejection section 600b also includes a piezoelectric element 60b. A clock signal SCK, a print data signal SIb, a latch signal LATb, a change signal CHb, a drive signal COMb, and a voltage VHV_H are input to the drive signal selection circuit 200b. Furthermore, the drive signal selection circuit 200b selects or deselects the drive signal COMb based on the clock signal SCK, print data signal SIb, latch signal LATb, change signal CHb, and voltage VHV_H, thereby generating a drive signal VOUTb.

[0071] A drive signal VOUTb is supplied to one end of a piezoelectric element 60b included in each of the plurality of ejection sections 600b. Furthermore, a reference voltage signal VBSb is supplied to the other end of the piezoelectric element 60b. Moreover, the piezoelectric element 60b is driven by the potential difference between the drive signal VOUTb and the reference voltage signal VBSb, ejecting ink from the ejection section 600b. That is, the liquid ejection module 21b has a piezoelectric element 60b driven by a drive signal COMb and a drive signal selection circuit 200b that controls the supply of the drive signal COMb to the piezoelectric element 60b.

[0072] The liquid ejection module 21c includes a drive signal selection circuit 200c and multiple ejection sections 600c. Each ejection section 600c includes a piezoelectric element 60c. A clock signal SCK, a print data signal SIc, a latch signal LATc, a change signal CHc, a drive signal COMc, and a voltage VHV_H are input to the drive signal selection circuit 200c. Furthermore, the drive signal selection circuit 200c selects or deselects the drive signal COMc based on the clock signal SCK, the print data signal SIc, the latch signal LATc, the change signal CHc, and the voltage VHV_H, thereby generating a drive signal VOUTc.

[0073] A drive signal VOUTc is supplied to one end of a piezoelectric element 60c included in each of the plurality of ejection sections 600c. Furthermore, a reference voltage signal VBSc is supplied to the other end of the piezoelectric element 60c. Moreover, the piezoelectric element 60c is driven by the potential difference between the drive signal VOUTc and the reference voltage signal VBSc, ejecting ink from the ejection section 600c. That is, the liquid ejection module 21c has a piezoelectric element 60c driven by a drive signal COMc and a drive signal selection circuit 200c that controls the supply of the drive signal COMc to the piezoelectric element 60c.

[0074] The liquid ejection module 21d includes a drive signal selection circuit 200d and multiple ejection sections 600d. Each ejection section 600d includes a piezoelectric element 60d. A clock signal SCK, a print data signal SId, a latch signal LATd, a change signal CHd, a drive signal COMd, and a voltage VHV_H are input to the drive signal selection circuit 200d. Furthermore, the drive signal selection circuit 200d selects or deselects the drive signal COMd ​​based on the clock signal SCK, print data signal SId, latch signal LATd, change signal CHd, and voltage VHV_H, thereby generating a drive signal VOUTd.

[0075] A drive signal VOUTd is supplied to one end of a piezoelectric element 60d included in each of the plurality of ejection sections 600d. Furthermore, a reference voltage signal VBSd is supplied to the other end of the piezoelectric element 60d. Moreover, the piezoelectric element 60d is driven by the potential difference between the drive signal VOUTd and the reference voltage signal VBSd, ejecting ink from the ejection section 600d. That is, the liquid ejection module 21d has a piezoelectric element 60d driven by a drive signal COMd ​​and a drive signal selection circuit 200d that controls the supply of the drive signal COMd ​​to the piezoelectric element 60d.

[0076] Furthermore, in the following description, drive circuits 51a, 51b, 51c, and 51d have the same structure and are sometimes referred to as drive circuit 51 unless otherwise specified. The various signals input to drive circuit 51 are referred to as voltage VHV, drive data signal DATA, and clock signal MCK. Additionally, the various signals output from drive circuit 51 are referred to as drive signal COM and reference voltage signal VBS.

[0077] Furthermore, liquid ejection modules 21a, 21b, 21c, and 21d have the same structure and are referred to as liquid ejection module 21 unless otherwise specified. The liquid ejection module 21 will be described as having a drive signal selection circuit 200 and multiple ejection sections 600, each including a piezoelectric element 60. In this case, the various signals input to the liquid ejection module 21 are referred to as clock signal SCK, printing data signal SI, latch signal LAT, change signal CH, drive signal COM, reference voltage signal VBS, and voltage VHV_H. The signal supplied to the piezoelectric element 60 is referred to as drive signal VOUT.

[0078] 1-3. Structure and operation of the liquid ejection module

[0079] Next, the structure and operation of the drive signal selection circuit 200 will be explained. In explaining the structure and operation of the drive signal selection circuit 200, firstly, using... Figure 3 An example of the drive signal COM input to the drive signal selection circuit 200 will be described. Thereafter, using... Figures 4 to 7 The structure and operation of the drive signal selection circuit 200 are explained.

[0080] Figure 3 This is a diagram illustrating an example of the drive signal COM. Figure 3 The diagram shows the period T1 from the rise of the latch signal LAT to the rise of the change signal CH, the period T2 following period T1 to the rise of the change signal CH, and the period T3 following period T2 to the rise of the latch signal LAT. Furthermore, the period T1, T2, and T3 constitutes the period Ta for forming a new point on the medium P. That is, as shown... Figure 3 As shown, the latch signal LAT is a signal that specifies the period for forming a new point on the medium P, and the change signal CH is a signal that specifies the switching timing of the waveform contained in the drive signal COM.

[0081] like Figure 3As shown, the drive circuit 51 generates a trapezoidal waveform Adp during period T1. When the trapezoidal waveform Adp is supplied to the piezoelectric element 60, a predetermined amount, specifically a moderate amount, of ink is ejected from the corresponding ejection section 600. Furthermore, the drive circuit 51 generates a trapezoidal waveform Bdp during period T2. When the trapezoidal waveform Bdp is supplied to the piezoelectric element 60, a small amount of ink, less than the predetermined amount, is ejected from the corresponding ejection section 600. Furthermore, the drive circuit 51 generates a trapezoidal waveform Cdp during period T3. When the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, the piezoelectric element 60 is driven to a point where ink is not ejected from the corresponding ejection section 600. Therefore, when the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, no dots are formed on the medium P. This trapezoidal waveform Cdp is a waveform used to cause micro-vibration of the ink near the nozzle opening of the ejection section 600 to prevent an increase in ink viscosity. In the following description, the situation in which the piezoelectric element 60 is driven to the extent that ink is not ejected from the ejection section 600 in order to prevent the ink viscosity from increasing is referred to as "micro-vibration".

[0082] Here, the start and end timing voltage values ​​of the trapezoidal waveforms Adp, Bdp, and Cdp are all the same, both being voltage Vc. That is, the trapezoidal waveforms Adp, Bdp, and Cdp are waveforms that begin and end with voltage Vc. Therefore, the drive circuit 51 outputs a drive signal COM representing the continuous waveforms of trapezoidal waveforms Adp, Bdp, and Cdp within the period Ta. Furthermore, Figure 3 The waveform of the drive signal COM shown is an example; the waveform of the drive signal COM can also be different. Furthermore, drive circuits 51a and 51b can also generate and output drive signals COM with different waveforms.

[0083] Figure 4 This is a block diagram showing the electrical structure of the drive signal selection circuit 200. In each of periods T1, T2, and T3, the drive signal selection circuit 200, by switching whether to select the trapezoidal waveforms Adp, Bdp, and Cdp contained in the drive signal COM, generates and outputs a drive signal VOUT to the piezoelectric element 60 during period Ta. Figure 4 As shown, the drive signal selection circuit 200 includes a selection control circuit 210 and multiple selection circuits 230.

[0084] The selection control circuit 210 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, and a voltage VHV_H. In the selection control circuit 210, groups of shift registers 212 (S / R), latch circuits 214, and decoders 216 are provided corresponding to each of the ejector sections 600. That is, the head unit 20 is provided with the same number of groups of shift registers 212, latch circuits 214, and decoders 216 as the total number n of ejector sections 600.

[0085] Shift register 212 temporarily holds 2 bits of printing data [SIH, SIL] contained in the printing data signal SI for each corresponding ejector 600. Specifically, shift registers 212 of the corresponding stages to ejector 600 are cascaded together, and the serially supplied printing data signal SI is sequentially transmitted to the next stage according to the clock signal SCK. Furthermore, in Figure 4 In order to distinguish shift registers 212, they are sequentially labeled as level 1, level 2, ..., level n, starting from the upstream side of the supplied printed data signal SI.

[0086] Each of the n latching circuits 214 latches the printed data [SIH, SIL] held by the corresponding shift register 212 on the rising edge of the latch signal LAT. Each of the n decoders 216 decodes the 2-bit printed data [SIH, SIL] latched by the corresponding latching circuit 214, generates a selection signal S, and supplies it to the selection circuit 230.

[0087] The selection circuit 230 is provided corresponding to each of the ejector sections 600. That is, the number of selection circuits 230 in one head unit 20 is the same as the total number n of ejector sections 600 contained in the head unit 20. The selection circuit 230 controls the supply of the drive signal COM to the piezoelectric element 60 based on the selection signal S supplied from the decoder 216.

[0088] Figure 5 This is a circuit diagram showing the electrical structure of a selection circuit 230 corresponding to one of the ejection sections 600. (Example:) Figure 5 As shown, the selection circuit 230 includes an inverter 232 and a transmission gate 234. Furthermore, the transmission gate 234 includes a transistor 235 as an NMOS transistor and a transistor 236 as a PMOS transistor.

[0089] The selection signal S is supplied from the decoder 216 to the gate terminal of transistor 235. Furthermore, the selection signal S is logically inverted by inverter 232 and also supplied to the gate terminal of transistor 236. The drain terminal of transistor 235 and the source terminal of transistor 236 are connected to terminal TG-In, which is one end of the transistor. The drive signal COM is input from terminal TG-In. Moreover, by controlling transistors 235 and 236 to be turned on or off according to the selection signal S, the drive signal VOUT is output from the other end, terminal TG-Out, which is connected to both the source terminal of transistor 235 and the drain terminal of transistor 236. Terminal TG-Out is electrically connected to electrode 611 of piezoelectric element 60, which will be described later. Additionally, in the following description, the state in which transistors 235 and 236 are controlled to be on is sometimes referred to as "on," and the state in which transistors 235 and 236 are controlled to be off is sometimes referred to as "off."

[0090] Next, use Figure 6 The decoding content of decoder 216 is explained. Figure 6 This diagram illustrates the decoded content in decoder 216. Two bits of printed data [SIH, SIL], a latch signal LAT, and a change signal CH are input to decoder 216. Furthermore, for example, if the printed data [SIH, SIL] is defined as [1, 0] with a "midpoint", decoder 216 outputs a selection signal S at levels H, L, L during periods T1, T2, and T3. Here, the logic level of the selection signal S is level-shifted to a high-amplitude logic based on voltage VHV_H by a level shifter (not shown).

[0091] Figure 7 This is a diagram used to illustrate the operation of the drive signal selection circuit 200. For example... Figure 7 As shown, printing data signals SI are serially supplied to the drive signal selection circuit 200 in sync with the clock signal SCK, and are sequentially transmitted in shift registers 212 corresponding to the ejector sections 600. Furthermore, if the supply of the clock signal SCK stops, the printing data [SIH, SIL] corresponding to the ejector sections 600 are held in each of the shift registers 212. Additionally, the printing data signals SI are supplied in the order corresponding to the final n-stage, ..., 2-stage, 1-stage ejector sections 600 in the shift registers 212.

[0092] Here, if the latch signal LAT rises, each of the latch circuits 214 latches together the printed data [SIH, SIL] held in the corresponding shift register 212. Figure 7 The LT1, LT2, ..., LTn shown are printed data [SIH, SIL] latched by latch circuits 214 corresponding to shift registers 212 of level 1, level 2, ..., level n.

[0093] Decoder 216, based on the size of the points specified by the latched print data [SIH, SIL], outputs according to the following in each of periods T1, T2, and T3: Figure 6 The logic level selection signal S for the content shown.

[0094] When the printed data [SIH, SIL] is [1, 1], the selection circuit 230 selects the trapezoidal waveform Adp during period T1, selects the trapezoidal waveform Bdp during period T2, and does not select the trapezoidal waveform Cdp during period T3, according to the selection signal S. As a result, it generates... Figure 7 The large dots shown correspond to the drive signal VOUT. Therefore, a medium amount of ink and a small amount of ink are ejected from the ejector 600. As a result, large dots are formed on the medium P by the ink bonding. Furthermore, when the printing data [SIH, SIL] is [1, 0], the selection circuit 230 selects the trapezoidal waveform Adp during period T1, does not select the trapezoidal waveform Bdp during period T2, and does not select the trapezoidal waveform Cdp during period T3, according to the selection signal S. As a result, a large dot is generated. Figure 7 The drive signal VOUT corresponds to the midpoint shown. Therefore, a moderate amount of ink is ejected from the ejector 600. Thus, a midpoint is formed on the medium P. Furthermore, when the printing data [SIH, SIL] is [0, 1], the selection circuit 230, according to the selection signal S, does not select the trapezoidal waveform Adp during period T1, selects the trapezoidal waveform Bdp during period T2, and does not select the trapezoidal waveform Cdp during period T3. As a result, a midpoint is generated. Figure 7 The small dots shown correspond to the drive signal VOUT. Therefore, a small amount of ink is ejected from the ejector 600. As a result, small dots are formed on the medium P. Furthermore, when the printing data [SIH, SIL] is [0, 0], the selection circuit 230, according to the selection signal S, does not select the trapezoidal waveform Adp during period T1, does not select the trapezoidal waveform Bdp during period T2, and selects the trapezoidal waveform Cdp during period T3. As a result, a dot is generated. Figure 7 The micro-vibration shown corresponds to the drive signal VOUT. Therefore, the micro-vibration is generated without ink being ejected from the ejection section 600.

[0095] Here, use Figure 8 The structure and operation of the ejection section 600, including the piezoelectric element 60, will be described. Figure 8 This is a cross-sectional view showing the schematic structure of the ejector section 600 when the liquid ejection module 21 is cut off in a manner including the ejector section 600.

[0096] like Figure 8As shown, the liquid ejection module 21 includes an ejection section 600 and a reservoir 641. Ink is introduced into the reservoir 641 from the supply port 661. Furthermore, the reservoir 641 is configured for each color of ink.

[0097] The ejection section 600 includes a piezoelectric element 60, a vibrating plate 621, a chamber 631, and a nozzle 651. The vibrating plate 621 is disposed between the chamber 631 and the piezoelectric element 60. Furthermore, the vibrating plate 621 is displaced by the piezoelectric element 60 disposed on its upper surface. That is, the vibrating plate 621 functions as a diaphragm that expands / contracts the internal volume of the chamber 631 through displacement. The chamber 631 is filled with ink. In addition, the chamber 631 functions as a pressure chamber whose internal volume changes by the drive of the piezoelectric element 60. The nozzle 651 is an opening disposed on a nozzle plate 632 and communicating with the chamber 631.

[0098] The piezoelectric element 60 is a structure in which a piezoelectric body 601 is held between a pair of electrodes 611 and 612. A drive signal VOUT is supplied to electrode 611, and a reference voltage signal VBS is supplied to electrode 612. The piezoelectric element 60 with this structure is driven according to the potential difference between electrodes 611 and 612. Moreover, with the drive of the piezoelectric element 60, electrodes 611 and 612 and the central portion of the vibrating plate 621 are displaced in the vertical direction relative to the two end portions. Furthermore, the internal volume of the chamber 631 changes with the displacement of the vibrating plate 621, and the ink filled inside the chamber 631 is ejected from the nozzle 651.

[0099] Here, as described above, the drive signal VOUTa is a signal that selects at least a portion of the waveform of the drive signal COMA. The piezoelectric element 60a is driven by the drive signal COMA, and the ejector unit 600a ejects ink onto the medium P according to the drive of the piezoelectric element 60a. Similarly, the drive signal VOUTb is a signal that selects at least a portion of the waveform of the drive signal COMAb. The piezoelectric element 60b is driven by the drive signal COMAb, and the ejector unit 600b ejects ink onto the medium P according to the drive of the piezoelectric element 60b. Similarly, the drive signal VOUTc is a signal that selects at least a portion of the waveform of the drive signal COMAc. The piezoelectric element 60c is driven by the drive signal COMAc, and the ejector unit 600c ejects ink onto the medium P according to the drive of the piezoelectric element 60c. Similarly, the drive signal VOUTd is a signal that selects at least a portion of the waveform of the drive signal COMAd. The piezoelectric element 60d is driven by the drive signal COMAd, and the ejector unit 600d ejects ink onto the medium P according to the drive of the piezoelectric element 60d.

[0100] 1-4. Circuit structure and operation of the driving circuit board

[0101] Next, the circuit structure and operation of the drive circuit board 50 will be explained. Figure 9 This is a block diagram showing the circuit structure of the drive circuit board 50. (Example) Figure 9 As shown, the drive circuit board 50 includes overcurrent protection circuits 70a, 70b, and 70c, logic circuits 71a, 71b, 71c, and 71d, resistors 72, 73, and 74, power supply wiring 75a, 75b, and 75c, capacitors 76a, 76b, and 76c, and a start-up control circuit 80.

[0102] Power cable 75a is a connection Figure 2 The wiring of the power supply circuit 90 and the print head 22 shown provides voltage VHV_H to the print head 22 via power supply wiring 75a. Power supply wiring 75b connects the power supply circuit 90 to the drive circuits 51a and 51b, providing voltage VHV_A1 to the drive circuits 51a and 51b via power supply wiring 75b. Power supply wiring 75c connects the power supply circuit 90 to the drive circuits 51c and 51d, providing voltage VHV_A1 to the drive circuits 51c and 51d via power supply wiring 75c.

[0103] In this embodiment, the voltage VHV_A1 supplied to the drive circuits 51a and 51b is a different signal from the voltage VHV_H supplied to the print head 22, and is not supplied to the print head 22. Similarly, the voltage VHV_A2 supplied to the drive circuits 51c and 51d is a different signal from the voltage VHV_H supplied to the print head 22, and is not supplied to the print head 22.

[0104] Capacitor 76a is connected between power supply line 75a and ground. Capacitor 76b is connected between power supply line 75b and ground. Capacitor 76c is connected between power supply line 75c and ground. Capacitors 76a, 76b, and 76c are stabilizing capacitors. Since drive circuits 51a, 51b, 51c, and 51d need to charge and discharge multiple piezoelectric elements 60 simultaneously, the capacitance value of capacitor 76b connected to power supply line 75b (which transmits the power supply voltage VHV_A1 for drive circuits 51a and 51b) and capacitor 76c connected to power supply line 75c (which transmits the power supply voltage VHV_A2 for drive circuits 51c and 51d) are greater than the capacitance value of capacitor 76a connected to power supply line 75a (which transmits the power supply voltage VHV_H for the printhead 22).

[0105] An overcurrent protection circuit 70a is provided on the power supply wiring 75a, and has a conduction mode that turns on the power supply circuit 90 and the print head 22, and a non-conducting mode that turns off the power supply circuit 90 and the print head 22. Furthermore, the overcurrent protection circuit 70a outputs an operation mode signal MD_H indicating whether the operation mode is in conduction mode or non-conducting mode. In this embodiment, when the operation mode signal MD_H is at level H, the operation mode is in conduction mode; when the operation mode signal MD_H is at level L, the operation mode is in non-conducting mode.

[0106] When the current flowing through the power supply wiring 75a exceeds a predetermined value in the on-mode, the overcurrent protection circuit 70a switches from the on-mode to the off-mode. If the current flowing through the power supply wiring 75a exceeds a predetermined value, the overcurrent protection circuit 70a switches from the on-mode to the off-mode, thus stopping the supply of voltage VHV_H from the power supply circuit 90 to the print head 22, and the operation mode signal MD_H changes from H level to L level.

[0107] Furthermore, if the voltage VHV_H output from the power supply circuit 90 is below a predetermined value in the on-mode, the overcurrent protection circuit 70a can also switch from the on-mode to the off-mode. If the voltage VHV_H is below the predetermined value, the overcurrent protection circuit 70a switches from the on-mode to the off-mode, thus stopping the supply of voltage VHV_H from the power supply circuit 90 to the printhead 22, and the operation mode signal MD_H changes from H level to L level.

[0108] An overcurrent protection circuit 70b is provided on the power supply wiring 75b, and has a conduction mode that enables the power supply circuit 90 and the drive circuits 51a and 51b to be in a conducting state, and a non-conducting mode that enables the power supply circuit 90 and the drive circuits 51a and 51b to be in a non-conducting state. Furthermore, the overcurrent protection circuit 70b outputs an operation mode signal MD_A1 indicating whether the operation mode is in a conducting or non-conducting state. In this embodiment, when the operation mode signal MD_A1 is at a high level (H), the operation mode is in a conducting mode; when the operation mode signal MD_A1 is at a low level (L), the operation mode is in a non-conducting mode.

[0109] When the current flowing through the power supply wiring 75b in the on-mode is above a predetermined value, the overcurrent protection circuit 70b switches from the on-mode to the non-on-mode. If the current flowing through the power supply wiring 75b is above a predetermined value, the overcurrent protection circuit 70b switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_A1 from the power supply circuit 90 to the drive circuits 51a and 51b, and the operation mode signal MD_A1 changes from H level to L level.

[0110] Furthermore, when the voltage VHV_A1 output from the power supply circuit 90 is below a predetermined value in the on-mode, the overcurrent protection circuit 70b can also switch from the on-mode to the off-mode. If the voltage VHV_A1 is below the predetermined value, the overcurrent protection circuit 70b switches from the on-mode to the off-mode, thus stopping the supply of voltage VHV_A1 from the power supply circuit 90 to the drive circuits 51a and 51b, and the operation mode signal MD_A1 changes from H level to L level.

[0111] Logic circuit 71a receives operating mode signals MD_H and MD_A1 as inputs and outputs a VHV abnormality signal VERa. Specifically, when both operating mode signals MD_H and MD_A1 are at a high level (H), logic circuit 71a outputs a low-level (L) VHV abnormality signal VERa, indicating that both voltages VHV_H and VHV_A1 are normal. When at least one of the operating mode signals MD_H and MD_A1 is at a low level (L), logic circuit 71a outputs a high-level (H) VHV abnormality signal VERa, indicating that at least one of the voltages VHV_H and VHV_A1 is abnormal. That is, logic circuit 71a is implemented by a 2-input NAND circuit. The VHV abnormality signal VERa output from logic circuit 71a is input to driver circuit 51a as an error signal ERRa.

[0112] When the error signal ERa is at level H, the drive circuit 51a stops outputting the drive waveform of the drive signal COMA. Furthermore, when the error signal ERa is at level L, the drive circuit 51a outputs an enable signal ENA to the overcurrent protection circuits 70a and 70b; when the error signal ERa is at level H, it stops outputting the enable signal ENA to the overcurrent protection circuits 70a and 70b. Therefore, when the overcurrent protection circuit 70a switches from the on mode to the off mode, the drive circuit 51a stops outputting the enable signal ENA to both the on and off modes. Similarly, when the overcurrent protection circuit 70b switches from the on mode to the off mode, the drive circuit 51a stops outputting the enable signal ENA to both the on and off modes.

[0113] In this embodiment, the enable signal ENa is a high-level control signal VHV_CNTa output from the drive circuit 51a. The drive circuit 51a stops the output of the enable signal ENa by outputting the low-level control signal VHV_CNTa. When the enable signal ENa is input, the overcurrent protection circuits 70a and 70b become either in a conducting mode or a non-conducting mode depending on the current flowing through the power supply wirings 75a and 75b, respectively. When no enable signal ENa is input, they become non-conducting. Therefore, even if the output of the enable signal ENa from the drive circuit 51a is stopped by the overcurrent protection circuit 70a switching from a conducting mode to a non-conducting mode, the overcurrent protection circuit 70b also switches from a conducting mode to a non-conducting mode. Similarly, even if the output of the enable signal ENa from the drive circuit 51a is stopped by the overcurrent protection circuit 70b switching from a conducting mode to a non-conducting mode, the overcurrent protection circuit 70a also switches from a conducting mode to a non-conducting mode. Furthermore, when the overcurrent protection circuits 70a and 70b are not enabled by the input enable signal ENa, they will not enter the conduction mode even if the current flowing through the power supply wirings 75a and 75b is less than a predetermined value.

[0114] Furthermore, the overcurrent protection circuit 70a can switch from a non-conducting mode to a conducting mode. Specifically, the overcurrent protection circuit 70a switches from a non-conducting mode to a conducting mode by receiving a predetermined signal. For example, the predetermined signal can be the enable signal ENa output from the drive circuit 51a. That is, the overcurrent protection circuit 70a can also switch from a non-conducting mode to a conducting mode by switching the control signal VHV_CNTa output from the drive circuit 51a from an L level to an H level. Alternatively, the drive circuit 51a can also continuously output the L level control signal VHV_CNTa after switching the control signal VHV_CNTa from an H level to an L level, as long as it is not reset, and switch the control signal VHV_CNTa from an L level to an H level when it is reset. In this case, the predetermined signal is a reset signal (not shown).

[0115] The logic circuit 71b receives the operating mode signal MD_A1 as input and outputs a VHV abnormality signal VERb. Specifically, when the operating mode signal MD_A1 is at a high level (H), the logic circuit 71b outputs a VHV abnormality signal VERa (L level), indicating that the voltage VHV_A1 is normal; when the operating mode signal MD_A1 is at a low level (L level), the logic circuit 71b outputs a VHV abnormality signal VERb (H level), indicating that the voltage VHV_A1 is abnormal. That is, the logic circuit 71b is implemented by a NOT circuit. The VHV abnormality signal VERb output from the logic circuit 71b is input to the driver circuit 51b as an error signal ERRb.

[0116] When the error signal ERRb is at level H, the drive circuit 51b stops outputting the drive waveform of the drive signal COMb. Furthermore, when the error signal ERRb is at level L, the drive circuit 51b outputs an enable signal ENb to the overcurrent protection circuit 70b; when the error signal ERRb is at level H, it stops outputting the enable signal ENb to the overcurrent protection circuit 70b. Therefore, when the overcurrent protection circuit 70b switches from the on mode to the off mode, the drive circuit 51b stops outputting the enable signal ENb to the overcurrent protection circuit 70b.

[0117] In this embodiment, the enable signal ENb is a high-level control signal VHV_CNTb output from the drive circuit 51b. The drive circuit 51b stops outputting the enable signal ENb by outputting the low-level control signal VHV_CNTb. When the enable signal ENb is input, the overcurrent protection circuit 70b becomes either in a conducting mode or a non-conducting mode based on the current flowing through the power supply wiring 75b. When the enable signal ENb is not input, it becomes a non-conducting mode. Furthermore, when the enable signal ENb is not input, the overcurrent protection circuit 70b will not become in a conducting mode even if the current flowing through the power supply wiring 75b is less than a predetermined value.

[0118] Furthermore, the overcurrent protection circuit 70b can switch from a non-conducting mode to a conducting mode. Specifically, the overcurrent protection circuit 70b switches from a non-conducting mode to a conducting mode by receiving a predetermined signal. For example, the predetermined signal can be the enable signals ENa and ENb output from the drive circuits 51a and 51b. That is, the overcurrent protection circuit 70b can also switch from a non-conducting mode to a conducting mode by ensuring that the control signals VHV_CNTa and VHV_CNTb output from the drive circuits 51a and 51b are both at high level (H). Alternatively, the drive circuits 51a and 51b can, after switching the control signals VHV_CNTa and VHV_CNTb from high level to low level (L level), continue to output low-level control signals VHV_CNTa and VHV_CNTb as long as they are not reset, and switch the control signals VHV_CNTa and VHV_CNTb from low level to high level when reset. In this case, the predetermined signal is a reset signal (not shown).

[0119] An overcurrent protection circuit 70c is provided on the power supply wiring 75c, and has a conduction mode that enables the power supply circuit 90 and the drive circuits 51c and 51d to be in a conducting state, and a non-conducting mode that enables the power supply circuit 90 and the drive circuits 51c and 51d to be in a non-conducting state. Furthermore, the overcurrent protection circuit 70c outputs an operation mode signal MD_A2 indicating whether the operation mode is in a conducting or non-conducting state. In this embodiment, when the operation mode signal MD_A2 is at a high level (H), the operation mode is in a conducting mode; when the operation mode signal MD_A2 is at a low level (L), the operation mode is in a non-conducting mode.

[0120] When the current flowing through power supply wiring 75c exceeds a predetermined value in the on-mode, the overcurrent protection circuit 70c switches from the on-mode to the off-mode. If the current flowing through power supply wiring 75c exceeds a predetermined value, the overcurrent protection circuit 70c switches from the on-mode to the off-mode, thus stopping the supply of voltage VHV_A2 from power supply circuit 90 to drive circuits 51c and 51d, and the operation mode signal MD_A2 changes from H level to L level.

[0121] Furthermore, even when the voltage VHV_A2 output from the power supply circuit 90 is below a predetermined value in the on-mode, the overcurrent protection circuit 70c can switch from the on-mode to the off-mode. If the voltage VHV_A2 is below the predetermined value, the overcurrent protection circuit 70c switches from the on-mode to the off-mode, thus stopping the supply of voltage VHV_A2 from the power supply circuit 90 to the drive circuits 51c and 51d, and the operation mode signal MD_A2 changes from H level to L level.

[0122] The logic circuit 71c receives the operating mode signal MD_A2 as input and outputs a VHV abnormality signal VERc. Specifically, when the operating mode signal MD_A2 is at a high level (H), the logic circuit 71c outputs a VHV abnormality signal VERc at a low level (L), indicating that the voltage VHV_A2 is normal; when the operating mode signal MD_A2 is at a low level (L), the logic circuit 71c outputs a VHV abnormality signal VERc at a high level (H). That is, the logic circuit 71c is implemented by a NOT circuit. The VHV abnormality signal VERc output from the logic circuit 71c is input to the driver circuit 51c as an error signal ERRc.

[0123] When the error signal ERRc is at level H, the drive circuit 51c stops outputting the drive waveform of the drive signal COMc. Furthermore, when the error signal ERRc is at level L, the drive circuit 51c outputs an enable signal ENc to the overcurrent protection circuit 70c; when the error signal ERRc is at level H, it stops outputting the enable signal ENc to the overcurrent protection circuit 70c. Therefore, when the overcurrent protection circuit 70c switches from the on mode to the off mode, the drive circuit 51c stops outputting the enable signal ENc to the overcurrent protection circuit 70c.

[0124] In this embodiment, the enable signal ENc is a high-level control signal VHV_CNTc output from the drive circuit 51c. The drive circuit 51c stops outputting the enable signal ENc by outputting the low-level control signal VHV_CNTc. When the enable signal ENc is input, the overcurrent protection circuit 70c enters either a conducting or non-conducting mode depending on the current flowing through the power supply wiring 75c. When the enable signal ENc is not input, it enters a non-conducting mode. Furthermore, when the enable signal ENc is not input, the overcurrent protection circuit 70c will not enter a conducting mode even if the current flowing through the power supply wiring 75c is less than a predetermined value.

[0125] The logic circuit 71d receives the operating mode signal MD_A2 as input and outputs a VHV abnormality signal VERd. Specifically, when the operating mode signal MD_A2 is at a high level (H), the logic circuit 71d outputs a VHV abnormality signal VERd at a low level (L), indicating that the voltage VHV_A2 is normal; when the operating mode signal MD_A2 is at a low level (L), the logic circuit 71d outputs a VHV abnormality signal VERd at a high level (H), indicating that the voltage VHV_A2 is abnormal. That is, the logic circuit 71d is implemented using a NOT circuit. The VHV abnormality signal VERd output from the logic circuit 71d is input to the driver circuit 51d as an error signal ERRd.

[0126] When the error signal ERRd is at level H, the drive circuit 51d stops outputting the drive waveform of the drive signal COMd. Furthermore, when the error signal ERRd is at level L, the drive circuit 51d outputs an enable signal ENd to the overcurrent protection circuit 70c; when the error signal ERRd is at level H, it stops outputting the enable signal End to the overcurrent protection circuit 70c. Therefore, when the overcurrent protection circuit 70c switches from the on mode to the off mode, the drive circuit 51d stops outputting the enable signal End to the overcurrent protection circuit 70c.

[0127] In this embodiment, the enable signal End is a high-level control signal VHV_CNTd output from the drive circuit 51d. The drive circuit 51d stops outputting the enable signal ENd by outputting the low-level control signal VHV_CNTd. When the enable signal ENd is input, the overcurrent protection circuit 70c becomes either in a conducting mode or a non-conducting mode based on the current flowing through the power supply wiring 75c. When the enable signal ENd is not input, it becomes a non-conducting mode. Furthermore, when the enable signal ENd is not input, the overcurrent protection circuit 70c will not become in a conducting mode even if the current flowing through the power supply wiring 75c is less than a predetermined value.

[0128] Furthermore, the overcurrent protection circuit 70c can switch from a non-conducting mode to a conducting mode. Specifically, the overcurrent protection circuit 70c switches from a non-conducting mode to a conducting mode by receiving a predetermined signal. For example, the predetermined signal can be the enable signals ENc and End output from the drive circuits 51c and 51d. That is, the overcurrent protection circuit 70c can also switch from a non-conducting mode to a conducting mode when both the control signal VHV_CNTc output from the drive circuit 51c and the control signal VHV_CNTd output from the drive circuit 51d are at the H level. Alternatively, the drive circuits 51c and 51d can, after switching the control signals VHV_CNTc and VHV_CNTd from the H level to the L level, continue to output the L level control signals VHV_CNTc and VHV_CNTd as long as they are not reset, and switch the control signals VHV_CNTc and VHV_CNTd from the L level to the H level when reset. In this case, the predetermined signal is a reset signal, which is not shown.

[0129] In addition, such as Figure 9As shown, in practice, the terminals of the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd output by the drive circuits 51a, 51b, 51c, and 51d are electrically connected to each other. Furthermore, the drive circuits 51a, 51b, 51c, and 51d replace the output low-level control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd by making each terminal a high impedance (Hi-Z), and the pull-down resistor 72 makes the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd a low level. Additionally, if at least one of the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd is a high level, a common enable signal is input to the overcurrent protection circuits 70a, 70b, and 70c. On the other hand, if the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd are all at low level, then the input of the enable signal to the overcurrent protection circuits 70a, 70b, and 70c will be stopped.

[0130] Overcurrent protection circuits 70a, 70b, and 70c have the same structure and are therefore referred to as overcurrent protection circuit 70. An example of its structure will be described below. Furthermore, in the description of the structure of overcurrent protection circuit 70, voltages VHV_H, VHV_A1, and VHV_A2 are referred to as voltages VHV, operating mode signals MD_H, MD_A1, and MD_A2 are referred to as operating mode signals MD, and control signals VHV_CNTa, HV_CNTb, HV_CNTc, and HV_CNTd are referred to as control signals VHV_CNT.

[0131] Figure 10 This is a diagram showing an example of the structure of an overcurrent protection circuit 70. (As shown...) Figure 10 As shown, the overcurrent protection circuit 70 includes an electronic fuse IC700, resistors 701 and 702. The electronic fuse IC700 has a Vin terminal, a Vout terminal, a UVLO terminal, a P-Good terminal, and an EN terminal. The Vin terminal is the voltage input terminal, and the Vout terminal is the voltage output terminal. The UVLO terminal is used to detect a decrease in the input voltage, and the P-Good terminal is the output terminal indicating the state of the input voltage. The EN terminal is the enable terminal.

[0132] The electronic fuse IC700 operates when the EN terminal is at a low (L) level and the control signal VHV_CNT is at a high (H) level. When the current flowing through the Vin terminal is above a predetermined value, the electronic fuse IC700 de-conducts the Vin and Vout terminals and outputs an L-level signal from the P-Good terminal. Furthermore, when the voltage input to the UVLO terminal is below a predetermined value, the electronic fuse IC700 de-conducts the Vin and Vout terminals and outputs an L-level signal from the P-Good terminal. Conversely, when the current flowing through the Vin terminal is less than a predetermined value and the voltage input to the UVLO terminal is higher than a predetermined value, the electronic fuse IC700 conducts the Vin and Vout terminals and outputs an H-level signal from the P-Good terminal.

[0133] A control signal VHV_CNT is input to the EN terminal. The Vin terminal is connected to the power circuit 90 via a power supply line, and the Vout terminal is connected to the print head 22 or the drive circuit 51 via a power supply line. A voltage VHV is input to the Vin terminal. Resistors 701 and 702 are connected in series between the Vin terminal and ground, and the connection point of resistors 701 and 702 is connected to the UVLO terminal. Therefore, the voltage VHV input to the UVLO terminal is the voltage after being divided by resistors 701 and 702. The above function is achieved through the overcurrent protection circuit 70 constructed in this way.

[0134] Return to Figure 9 The drive circuit 51a monitors the voltage VHV_H supplied to the printhead 22 via power supply wiring 75a. Furthermore, when the voltage VHV_H is higher than a predetermined voltage, the drive circuit 51a outputs an L-level error signal ERRa; when the voltage VHV_H is lower than the predetermined voltage, it outputs an H-level error signal ERRa and stops the output of the drive waveform of the drive signal COMi. Additionally, the H-level error signal ERRa is a signal that stops the output of the voltage VHV_H from the power supply circuit 90; the power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRa is H-level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by the drive circuit 51a becomes lower than the predetermined voltage, therefore the drive circuit 51a outputs an H-level error signal ERRa. The drive circuit 51a can also output an H-level error signal ERRa and an L-level control signal VHV_CNTa when the voltage VHV_H is lower than the predetermined voltage.

[0135] Furthermore, the drive circuit 51b monitors the voltage VHV_A1 supplied to the drive circuits 51a and 51b via the power supply wiring 75b. Moreover, when the voltage VHV_A1 is higher than a predetermined voltage, the drive circuit 51b outputs an L-level error signal ERRb; when the voltage VHV_A1 is lower than the predetermined voltage, it outputs an H-level error signal ERRb and stops the output of the drive waveform of the drive signal COMb. Furthermore, the H-level error signal ERRb is a signal that stops the output of the voltage VHV_A1 from the power supply circuit 90; the power supply circuit 90 stops the output of the voltage VHV_A1 when the error signal ERRb is H-level. For example, if the overcurrent protection circuit 70b switches from the on mode to the off mode, the voltage VHV_A1 monitored by the drive circuit 51b becomes lower than the predetermined voltage, therefore the drive circuit 51b outputs the H-level error signal ERRb. The drive circuit 51b can also output an H-level error signal ERRb and an L-level control signal VHV_CNTb when the voltage VHV_A1 is below a predetermined voltage.

[0136] Furthermore, the drive circuit 51c monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d via power supply wiring 75c. When the voltage VHV_A2 is higher than a predetermined voltage, drive circuit 51c outputs an L-level error signal ERRc; when the voltage VHV_A2 is lower than the predetermined voltage, it outputs an H-level error signal ERRc and stops outputting the drive waveform of drive signal COMc. Similarly, drive circuit 51d monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d via power supply wiring 75c. When the voltage VHV_A2 is higher than the predetermined voltage, drive circuit 51d outputs an L-level error signal ERRd; when the voltage VHV_A2 is lower than the predetermined voltage, it outputs an H-level error signal ERRd and stops outputting the drive waveform of drive signal COMd. Furthermore, the H-level error signals ERRc and ERRd are signals that stop the output of voltage VHV_A2 from the power supply circuit 90. The power supply circuit 90 stops the output of voltage VHV_A2 when at least one of the error signals ERRc and ERRd is at the H level. For example, if the overcurrent protection circuit 70c switches from the on mode to the off mode, the voltage VHV_A2 monitored by the drive circuits 51c and 51d becomes below a predetermined voltage, so the drive circuits 51c and 51d output H-level error signals ERRc and ERRd respectively. The drive circuits 51c and 51d can also output H-level error signals ERRc and ERRd respectively when the voltage VHV_A2 is below the predetermined voltage, and output L-level control signals VHV_CNTc and VHV_CNTd respectively.

[0137] In addition, such as Figure 9 As shown, in practice, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output error signals ERRra, ERRb, ERRc, and ERRd are electrically connected to each other. Furthermore, the drive circuits 51a, 51b, 51c, and 51d replace the output of the low-level error signals ERRra, ERRb, ERRc, and ERRd, making each terminal Hi-Z, and using pull-down resistors 73 to make the error signals ERRra, ERRb, ERRc, and ERRd low-level. Additionally, if all error signals ERRra, ERRb, ERRc, and ERRd are low-level, the error signal input to the power supply circuit 90 is low-level. On the other hand, if at least one of the error signals ERRra, ERRb, ERRc, and ERRd is high-level, the error signal input to the power supply circuit 90 is high-level, and the power supply circuit 90 stops outputting voltages VHV_H, VHV_A1, and VHVA2.

[0138] Furthermore, the terminal of the output error signal ERRA of drive circuit 51a is also an input terminal. If the voltage of this terminal switches from L level to H level, drive circuit 51a stops outputting the drive waveform of drive signal COMa and outputs an L level control signal VHV_CNTa. Similarly, the terminal of the output error signal ERRb of drive circuit 51b is also an input terminal. If the voltage of this terminal switches from L level to H level, drive circuit 51b stops outputting the drive waveform of drive signal COMb and outputs an L level control signal VHV_CNTb. Similarly, the terminal of the output error signal ERRc of drive circuit 51c is also an input terminal. If the voltage of this terminal switches from L level to H level, drive circuit 51c stops outputting the drive waveform of drive signal COMc and outputs an L level control signal VHV_CNTc. Similarly, the terminal of the output error signal ERRd of drive circuit 51d is also an input terminal. If the voltage of this terminal switches from L level to H level, drive circuit 51d stops outputting the drive waveform of drive signal COMd ​​and outputs an L level control signal VHV_CNTd. Therefore, when all error signals ERR1, ERR2, ERR3, and ERR4 are at low level, if at least one of these signals switches from low level to high level, the drive waveforms of drive signals COM1, COM2, COM3, and COM4 stop outputting to printhead 22, and control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd all become low level. As a result, overcurrent protection circuits 70a, 70b, and 70c are all in non-conducting mode.

[0139] Furthermore, drive circuit 51a outputs a status signal BUSYa indicating the operating state of drive circuit 51a. Similarly, drive circuit 51b outputs a status signal BUSYb indicating the operating state of drive circuit 51b. Similarly, drive circuit 51c outputs a status signal BUSYc indicating the operating state of drive circuit 51c. Similarly, drive circuit 51d outputs a status signal BUSYd indicating the operating state of drive circuit 51d. When drive circuits 51a, 51b, 51c, and 51d are in a predetermined state, they output H-level status signals BUSYa, BUSYb, BUSYc, and BUSYd, respectively; when they are not in a predetermined state, they output L-level status signals BUSYa, BUSYb, BUSYc, and BUSYd, respectively. The status signals BUSYa, BUSYb, BUSYc, and BUSYd are input to the control circuit 100 of control unit 10, and control circuit 100 determines the state of drive circuits 51a, 51b, 51c, and 51d based on the status signals BUSYa, BUSYb, BUSYc, and BUSYd.

[0140] In addition, such as Figure 9 As shown, in practice, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output status signals BUSYa, BUSYb, BUSYc, and BUSYd are electrically connected to each other. Furthermore, the drive circuits 51a, 51b, 51c, and 51d replace the output low-level status signals BUSYa, BUSYb, BUSYc, and BUSYd, making each terminal Hi-Z, and using pull-down resistors 74 to make the status signals BUSYa, BUSYb, BUSYc, and BUSYd low-level. Moreover, if all status signals BUSYa, BUSYb, BUSYc, and BUSYd are low-level, the status signal input to the control circuit 100 is low-level. On the other hand, if at least one of the status signals BUSYa, BUSYb, BUSYc, and BUSYd is high-level, the status signal input to the control circuit 100 is high-level, and the control circuit 100 determines the state of the drive circuits 51a, 51b, 51c, and 51d based on this status signal.

[0141] Here, assuming that the drive signals COMa, COMb, COMc, and COMd ​​are supplied to the print head 22, if the supply of voltage VHV_H to the print head 22 stops or decreases, then inside the print head 22, due to the parasitic diodes between the drive signal wirings that transmit the drive signals COMa, COMb, COMc, and COMd ​​and the power supply wiring that transmits the voltage VHV_H, excessive current will flow from the drive signal wirings to the power supply wiring, and the print head 22 may malfunction.

[0142] During the monitoring of voltage VHV_H by drive circuit 51a, if voltage VHV_H decreases, an error signal ERa at level H is output. This immediately stops the output of drive waveforms of drive signals COMa, COMb, COMc, and COMd ​​to printhead 22, thus reducing the likelihood of printhead 22 malfunctioning. Conversely, if voltage VHV_H decreases before drive circuit 51a begins monitoring voltage VHV_H, and at least one drive waveform of drive signals COMa, COMb, COMc, and COMd ​​is output to printhead 22, printhead 22 may malfunction. Therefore, in this embodiment, drive circuit board 50 includes a startup control circuit 80 that controls the startup of drive circuits 51a, 51b, 51c, and 51d. When head unit 20 starts, startup control circuit 80 initially starts drive circuit 51a, which monitors voltage VHV_H among drive circuits 51a, 51b, 51c, and 51d. That is, after the start-up sequence of the drive circuit 51a is started, the start-up control circuit 80 starts the start-up sequence of the drive circuits 51b, 51c, and 51d.

[0143] In this embodiment, the start-up control circuit 80 receives the drive data signals DATAa, DATAb, DATAc, and DATAd output by the input control circuit 100, and outputs data signals DATAXa, DATAXb, DATAXc, and DATAXd corresponding to the drive data signals DATAa, DATAb, DATAc, and DATAd, respectively. That is, the start-up control circuit 80 converts the drive data signals DATAa, DATAb, DATAc, and DATAd into data signals DATAXa, DATAXb, DATAXc, and DATAXd in formats matching the input specifications of the drive circuits 51a, 51b, 51c, and 51d, and outputs them. The data signals DATAXa, DATAXb, DATAXc, and DATAXd are then input to the drive circuits 51a, 51b, 51c, and 51d, respectively. As described above, the driving data signals DATAa, DATAb, DATAc, and DATAd are used to generate driving signals COMa, COMb, COMc, and COMd. However, in reality, the driving circuits 51a, 51b, 51c, and 51d generate driving signals COMa, COMb, COMc, and COMd ​​based on the data signals DATAXa, DATAXb, DATAXc, and DATAXd, respectively.

[0144] Furthermore, the drive data signals DATAa, DATAb, DATAc, and DATAd are also used as instructions to indicate the start-up of drive circuits 51a, 51b, 51c, and 51d. For example, the control circuit 100 may output the drive data signal DATAa as an instruction to start drive circuit 51a, and after a predetermined time, output the drive data signals DATAb, DATAc, and DATAd as instructions to start drive circuits 51b, 51c, and 51d. In this case, if the control circuit 100 only transforms the format of the drive data signals DATAa, DATAb, DATAc, and DATAd to output data signals DATAXa, DATAXb, DATAXc, and DATAXd, then the start-up sequence of drive circuit 51a begins before the start-up sequence of drive circuits 51b, 51c, and 51d. Alternatively, if the control circuit 100 receives at least one of the instructions to start the drive circuits 51b, 51c, and 51d as drive data signals DATAb, DATAc, and DATAd before receiving the instruction to start the drive circuit 51a as drive data signal DATAa, the output of data signals DATAXb, DATAXc, and DATAXd may be kept in standby until the instruction to start the drive circuit 51a is received as drive data signal DATAa and data signal DATAXa is output. Thus, the start-up sequence of drive circuit 51a begins before the start-up sequence of drive circuits 51b, 51c, and 51d.

[0145] Alternatively, if the format of the driving data signals DATAa, DATAb, DATAc, and DATAd matches the input specifications of the driving circuits 51a, 51b, 51c, and 51d, the start-up control circuit 80 may output the data signals DATAXa, DATAXb, DATAXc, and DATAXd without format conversion. Alternatively, the driving circuit board 50 may not include the start-up control circuit 80, and the control circuit 100 may function as the start-up control circuit 80.

[0146] 1-5. Structure of the driving circuit

[0147] Next, use Figure 11 The structure of drive circuits 51a, 51b, 51c, and 51d is described. Figure 11 In this description, the driving circuits 51a and 51b are not distinguished, but are described as driving circuit 51. Figure 11 This is a block diagram showing the structure of the drive circuit 51. The drive circuit 51 includes an integrated circuit 500, a drive signal amplifier circuit 550, and resistors 555 and 556.

[0148] Integrated circuit 500 includes an amplification control signal generation circuit 502, a voltage generation circuit 400, an oscillation circuit 410, a clock selection circuit 420, an abnormality detection circuit 430, a register control circuit 440, a drive signal discharge circuit 450, a reference voltage signal output circuit 460, a VHV control signal output circuit 470, a status signal input / output circuit 480, and an error signal input / output circuit 490.

[0149] The voltage generation circuit 400 generates a voltage GVDD based on the voltage VHV. The voltage GVDD is, for example, a 7.5V DC voltage signal, which is input to various structures of the integrated circuit 500, including the gate drive unit 540 described later.

[0150] The amplification control signal generation circuit 502 generates amplification control signals Hgd and Lgd based on the data signal containing the waveform of the drive signal COM included in the drive data signal DATAX input from the DATA-In terminal. The amplification control signal generation circuit 502 includes a DAC interface (DAC_I / F: Digital to Analog Converter Interface) 510, a DAC section 520, a modulation section 530, and a gate drive section 540.

[0151] The DAC interface 510 receives a drive data signal DATAX from the DATA-In terminal and a clock signal MCK from the MCK-In terminal. The DAC interface 510 accumulates the drive data signal DATAX based on the clock signal MCK, generating, for example, 10-bit drive data dA with a defined waveform for the drive signal COM. The drive data dA is then input to the DAC section 520. The DAC section 520 converts the input drive data dA into a basic analog drive signal aA. This basic drive signal aA is the target signal before amplification of the drive signal COM. The basic drive signal aA is input to the modulation section 530. The modulation section 530 outputs a modulation signal Ms that performs pulse width modulation on the basic drive signal aA. Voltages VHV and GVDD, along with the modulation signal Ms, are input to the gate drive section 540. The gate driving unit 540 generates an amplification control signal Hgd and an amplification control signal Lgd. The Hgd amplifies the input modulation signal Ms based on the voltage GVDD and shifts it to high-amplitude logic based on the voltage VHV. The Lgd inverts the logic level of the input modulation signal Ms and amplifies it based on the voltage GVDD. That is, the Hgd and Lgd are mutually exclusive H-level signals. The Hgd is output from the integrated circuit 500 via the terminal Hg-Out and input to the drive signal amplification circuit 550. Similarly, the Lgd is output from the integrated circuit 500 via the terminal Lg-Out and input to the drive signal amplification circuit 550.

[0152] The drive signal amplifier circuit 550 operates based on amplified control signals Hgd and Lgd to output a drive signal COM. The drive signal amplifier circuit 550 includes transistors 551 and 552, a coil 553, and a capacitor 554. Furthermore, transistors 551 and 552 are, for example, N-channel FETs (Field Effect Transistors).

[0153] A voltage VHV is supplied to the drain terminal of transistor 551. An amplification control signal Hgd is supplied to the gate terminal of transistor 551 via terminal Hg-Out. The source terminal of transistor 551 is electrically connected to the drain terminal of transistor 552. Furthermore, an amplification control signal Lgd is supplied to the gate terminal of transistor 552 via terminal Lg-Out. The source electrode of transistor 552 is connected to ground. Transistor 551, connected in the above manner, operates according to the amplification control signal Hgd, and transistor 552 operates according to the amplification control signal Lgd. That is, transistors 551 and 552 are exclusively turned on. Thus, an amplified modulation signal based on voltage VHV, amplifying the modulation signal Ms, is generated at the connection point between the source terminal of transistor 551 and the drain terminal of transistor 552.

[0154] One end of coil 553 is connected to both the source terminal of transistor 551 and the drain terminal of transistor 552. The other end of coil 553 is connected to one end of capacitor 554. The other end of capacitor 554 is connected to ground. That is, coil 553 and capacitor 554 constitute a low-pass filter. Furthermore, by supplying an amplified modulation signal to this low-pass filter, the amplified modulation signal is demodulated to generate a drive signal COM. Moreover, drive circuit 51 outputs the drive signal COM generated in the above manner.

[0155] In the following description, the structure including the amplified control signal generation circuit 502 and the drive signal amplification circuit 550 contained in the integrated circuit 500 is sometimes referred to as the drive signal generation circuit 501 that generates the drive signal COM based on the drive data signal DATAX.

[0156] The oscillation circuit 410 generates and outputs a clock signal LCK that specifies the timing of the operation of the integrated circuit 500. The clock signal LCK is input to the clock selection circuit 420 and the abnormality detection circuit 430.

[0157] Clock signals MCK, LCK, and a clock selection signal CSW are input to the clock selection circuit 420. Based on the logic level of the clock selection signal CSW, the clock selection circuit 420 switches between outputting the clock signal MCK as the clock signal RCK to the register control circuit 440 and outputting the clock signal LCK as the clock signal RCK to the register control circuit 440. Furthermore, in this embodiment, it is explained that the clock selection circuit 420 outputs the clock signal MCK as the clock signal RCK to the register control circuit 440 when the clock selection signal CSW is at a high level (H), and outputs the clock signal LCK as the clock signal RCK to the register control circuit 440 when the clock selection signal CSW is at a low level (L).

[0158] The abnormality detection circuit 430 includes an oscillation abnormality detection unit 431, an action abnormality detection unit 432, and a power supply voltage abnormality detection unit 433.

[0159] The clock signal LCK output by the oscillation circuit 410 is input to the oscillation anomaly detection unit 431. The oscillation anomaly detection unit 431 detects whether the input clock signal LCK is normal and outputs a clock selection signal CSW and an error signal NES based on the detection result and a logic level. For example, the oscillation anomaly detection unit 431 detects at least one of the frequency and voltage level of the clock signal LCK. Moreover, if at least one of the frequency and voltage level of the clock signal LCK is abnormal, the oscillation anomaly detection unit 431 outputs the H-level clock selection signal CSW to the clock selection circuit 420 and the H-level error signal NES to the register control circuit 440. Furthermore, if both the frequency and voltage level of the clock signal LCK are normal, the oscillation anomaly detection unit 431 outputs the L-level clock selection signal CSW to the clock selection circuit 420 and the L-level error signal NES to the register control circuit 440.

[0160] An operation status signal ASS, representing the operation status of various structures of the drive circuit 51, is input to the operation anomaly detection unit 432. Based on the logic level of the input operation status signal ASS, the operation anomaly detection unit 432 detects whether the various structures of the drive circuit 51 are operating normally. In this embodiment, if any of the various structures of the drive circuit 51 is abnormal, a high-level operation status signal ASS is input to the operation anomaly detection unit 432. Furthermore, when a high-level operation status signal ASS is input, the operation anomaly detection unit 432 outputs a high-level error signal NES to the register control circuit 440.

[0161] A voltage VHV is input to the power supply voltage anomaly detection unit 433. Then, the power supply voltage anomaly detection unit 433 detects the voltage value of VHV. Based on the voltage value of VHV, the power supply voltage anomaly detection unit 433 checks whether the voltage level of the voltage VHV supplied to the liquid ejection module 21 is normal. In this embodiment, if it is determined that the voltage level of VHV supplied to the liquid ejection module 21 is abnormal, the power supply voltage anomaly detection unit 433 outputs an H-level error signal FES to the register control circuit 440.

[0162] The register control circuit 440 includes a sequence register 441, a status register 442, and a register control unit 443. The sequence register 441 and status register 442 hold operation information input as a drive data signal DATAX, synchronized with the clock signal MCK. Furthermore, the register control unit 443, synchronized with the clock signal RCK, generates and outputs control signals CNT1 to CNT6 based on the information held in the sequence register 441 and status register 442. This controls the operation of the drive circuit 51.

[0163] The control signal CNT1 is input to the drive signal discharge circuit 450. The drive signal discharge circuit 450 controls the output of the drive signal COM from the drive circuit 51. When the low-level control signal CNT1 is input to the drive signal discharge circuit 450, the drive signal discharge circuit 450 releases the charge accumulated at the terminal Com-Dis. On the other hand, when the high-level control signal CNT1 is input to the drive signal discharge circuit 450, the drive signal discharge circuit 450 does not release the charge accumulated at the terminal Com-Dis.

[0164] The control signal CNT2 is input to the reference voltage signal output circuit 460. The reference voltage signal output circuit 460 generates and outputs a reference voltage signal VBS supplied to the piezoelectric element 60. The reference voltage signal VBS is a signal with a constant voltage value based on the voltage GVDD. When the H-level control signal CNT2 is input to the reference voltage signal output circuit 460, the reference voltage signal VBS with a constant voltage value is output from the VBS-Out terminal. On the other hand, when the L-level control signal CNT2 is input to the reference voltage signal output circuit 460, the reference voltage signal VBS at ground potential is output. In other words, when the L-level control signal CNT2 is input to the reference voltage signal output circuit 460, the output of the reference voltage signal VBS stops.

[0165] The control signal CNT3 is input to the VHV control signal output circuit 470. The VHV control signal output circuit 470 outputs the control signal VHV_CNT. When the low-level control signal CNT3 is input to the VHV control signal output circuit 470, a voltage GVDD is supplied to the terminal VHV_CNT-Out. That is, the high-level control signal VHV_CNT is output. On the other hand, when the high-level control signal CNT3 is input to the VHV control signal output circuit 470, the terminal VHV_CNT-Out becomes Hi-Z.

[0166] The control signal CNT4 is input to the status signal input / output circuit 480. The status signal input / output circuit 480 outputs a status signal BUSY indicating the operating state of the drive circuit 51. Based on the control signal CNT4 output from the register control circuit 440, the status signal input / output circuit 480 outputs the status signal BUSY from the terminal BUSY-Out and inputs the signal input to the terminal BUSY-Out to the register control circuit 440. When a low-level control signal CNT4 is input to the status signal input / output circuit 480, a voltage GVDD is supplied to the terminal BUSY-Out. That is, a high-level status signal BUSY is output. On the other hand, when a high-level control signal CNT4 is input to the status signal input / output circuit 480, the terminal BUSY-Out becomes Hi-Z.

[0167] The control signal CNT5 is input to the error signal input / output circuit 490. The error signal input / output circuit 490 outputs an error signal ERR indicating whether an abnormality has occurred in the drive circuit 51. Based on the control signal CNT5 output from the register control circuit 440, the error signal input / output circuit 490 outputs the error signal ERR from the terminal ERR-Out and inputs the signal to the terminal ERR-Out to the register control circuit 440. When a low-level control signal CNT5 is input to the error signal input / output circuit 490, a voltage GVDD is supplied to the terminal ERR-Out. That is, a high-level error signal ERR is output. On the other hand, when a high-level control signal CNT5 is input to the error signal input / output circuit 490, the terminal ERR-Out becomes Hi-Z.

[0168] The control signal CNT6 is input to the amplified control signal generation circuit 502. When the control signal CNT6 is input to the amplified control signal generation circuit 502, the waveform of the drive signal COM generated by the drive signal generation circuit 501 is independent of the drive data signal DATAX, but is defined by the control signal CNT6. Specifically, the drive signal generation circuit 501 generates a drive signal COM that is constant at a predetermined voltage value based on the control signal CNT6. Alternatively, the drive signal generation circuit 501 can also generate a drive signal COM that is constant at a ground potential based on the control signal CNT6.

[0169] In the drive circuit 51 configured as described above, operation information, input as a drive data signal DATAX synchronously with the clock signal MCK, is stored in the sequence register 441. This operation information includes information corresponding to the instruction indicating the start of the drive circuit 51. Furthermore, the register control unit 443 executes sequential control of the drive circuit 51 based on the operation information stored in the sequence register 441. Moreover, by executing various sequential controls, including the control of the start sequence described above, information indicating the operation mode accompanying the execution of this sequential control is stored in the status register 442. The register control circuit 440 controls the output of control signals CNT1 to CNT6 based on the information indicating the operation mode stored in the status register 442. Thus, various signals output from the drive circuit 51 are controlled. For example, the register control circuit 440 may also control the output of control signals CNT1, CNT2, CNT3, and CNT5 based on signals input to the error signal FES and the ERR-Out terminal.

[0170] 1-6. Start-up sequence of the drive circuit

[0171] Next, use Figure 12 The startup sequence of drive circuits 51a, 51b, 51c, and 51d is explained in detail. Figure 12 This diagram illustrates an example of the startup sequence of drive circuits 51a, 51b, 51c, and 51d. Figure 12 As shown, drive circuit 51a initially executes the startup sequence in drive circuits 51a, 51b, 51c, and 51d.

[0172] Before starting the startup sequence, the drive circuit 51a sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMA. First, at time t1, the drive circuit 51a receives a startup command as a data signal DATAXa from the startup control circuit 80 and begins the startup sequence (step S11). Next, the drive circuit 51a outputs a control signal VHV_CNTa at level H, starting the output of a constant voltage as the drive signal COMA (step S12). Then, the drive circuit 51a waits for charging to complete until the voltage VHV_H reaches the desired voltage (step S13), and at time t2, begins monitoring the voltage VHV_H (step S14). Next, the drive circuit 51a ends the output of the constant voltage as the drive signal COMA (step S15). Finally, the drive circuit 51a begins outputting the drive waveform of the drive signal COMA, ending the startup sequence (step S16).

[0173] Before starting the startup sequence, the drive circuit 51b sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMb. First, at time t3 after time t2, the drive circuit 51b receives a startup command as a data signal DATAXb from the startup control circuit 80 and begins the startup sequence (step S21). Next, the drive circuit 51b outputs a control signal VHV_CNTb at level H, starting the output of a constant voltage as the drive signal COMb (step S22). Next, the drive circuit 51b begins monitoring the voltage VHV_A1 (step S24). Next, the drive circuit 51b ends the output of the constant voltage as the drive signal COMb (step S25). Finally, the drive circuit 51b begins outputting the drive waveform of the drive signal COMb, ending the startup sequence (step S26).

[0174] Before starting the startup sequence, the drive circuit 51c sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMc. First, at time t4 after time t3, the drive circuit 51c receives a startup command as a data signal DATAXc from the startup control circuit 80 and begins the startup sequence (step S31). Next, the drive circuit 51c outputs a control signal VHV_CNTc at level H, starting the output of a constant voltage as the drive signal COMc (step S32). Next, the drive circuit 51c begins monitoring the voltage VHV_A2 (step S34). Next, the drive circuit 51c ends the output of the constant voltage as the drive signal COMc (step S35). Finally, the drive circuit 51c begins outputting the drive waveform of the drive signal COMc, ending the startup sequence (step S36).

[0175] Before starting the startup sequence, the drive circuit 51d sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMd. First, at time t5 after time t4, the drive circuit 51d receives a startup command as a data signal DATAXd from the startup control circuit 80 and begins the startup sequence (step S41). Next, the drive circuit 51d outputs a control signal VHV_CNTd at level H, starting the output of a constant voltage as the drive signal COMd ​​(step S42). Next, the drive circuit 51d begins monitoring the voltage VHV_A2 (step S44). Next, the drive circuit 51d ends the output of the constant voltage as the drive signal COMd ​​(step S45). Finally, the drive circuit 51d begins outputting the drive waveform of the drive signal COMd, ending the startup sequence (step S46).

[0176] In addition, the start times t3, t4, and t5 of the drive circuits 51b, 51c, and 51d can be after the start time t1 of the drive circuit 51a, but preferably after the start time t2 of the drive circuit 51a.

[0177] Furthermore, the conveying mechanism 4 is an example of a "conveyor section". Additionally, the printhead 22 is an example of a "head". Furthermore, the power supply wiring 75a is an example of a "first power supply wiring", and the power supply wiring 75b is an example of a "second power supply wiring". Furthermore, the overcurrent protection circuit 70a is an example of a "first overcurrent protection circuit", and the overcurrent protection circuit 70b is an example of a "second overcurrent protection circuit". Furthermore, the conduction mode of the overcurrent protection circuit 70a is an example of a "first mode", and the non-conducting mode of the overcurrent protection circuit 70a is an example of a "second mode". Furthermore, the conduction mode of the overcurrent protection circuit 70b is an example of a "third mode", and the non-conducting mode of the overcurrent protection circuit 70b is an example of a "fourth mode". The capacitor 76 is an example of a "first capacitor", and the capacitor 77a is an example of a "second capacitor".

[0178] 1-7. Effects

[0179] As explained above, in the liquid ejection device 1 of the first embodiment, the drive circuit 51a that monitors the voltage VHV_H supplied to the print head 22 starts up before the drive circuit 51b that monitors the voltage VHV_A1 supplied to the drive circuits 51a and 51b, and the drive circuits 51c and 51d that monitor the voltage VHV_A2 supplied to the drive circuits 51c and 51d. Therefore, the drive circuit 51a starts monitoring the voltage VHV_H before the drive circuits 51b, 51c, and 51d start outputting drive signals COMb, COMc, and COMd ​​to the print head 22, respectively. Furthermore, the drive circuit 51a starts monitoring the voltage VHV_H before starting outputting drive signal COMa to the print head 22. Moreover, if the drive circuit 51a detects a decrease in the voltage VHV_H, the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, the liquid ejection device 1 according to the first embodiment can reduce the possibility that the drive signals COMa, COMb, COMc, and COMd ​​are higher than the voltage VHV_H, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, thus reducing the possibility of head failure.

[0180] However, when the supply of voltages VHV_H, VHV_A1, and VHV_A2 to the printhead 22 stops, the capacitance values ​​of the stabilizing capacitors 76b and 76c are larger than that of capacitor 76a. Therefore, voltage VHV_H drops faster than voltages VHV_A1 and VHV_A2, and sometimes the voltages of the drive signals COMa, COMb, COMc, and COMd ​​are higher than voltage VHV_H. Furthermore, sometimes overshoot occurs in the drive signals COMa, COMb, COMc, and COMd ​​due to the inductance of the transmission path, resulting in voltages higher than VHV_H. As a result, due to the parasitic diodes inside the printhead 22, excessive current flows from the drive signal wirings of COMa, COMb, COMc, and COMd ​​to the power supply wiring 75a that transmits voltage VHV_H, making a printhead 22 malfunction highly probable.

[0181] Assuming that the current flowing through the power supply wiring 75a exceeds a predetermined value due to a printhead 22 malfunction, the overcurrent protection circuits 70a, 70b, and 70c switch from an on-mode to a non-on-mode, thus protecting various circuits and electronic components, such as the drive circuits 51a, 51b, 51c, and 51d, contained in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and since they can switch from a non-on-mode to an on-mode, they can be reused. Therefore, according to the liquid ejection device 1 of the first embodiment, in the head unit 20, in the event of a printhead 22 malfunction, it is not necessary to replace the drive circuit board 50, thereby reducing repair labor and costs.

[0182] Furthermore, according to the liquid ejection device 1 of the first embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop the input of the enable signal when switching from the conducting mode to the non-conducting mode, thus maintaining the non-conducting mode. If no predetermined signal is input, the switch from the non-conducting mode to the conducting mode will not be made, thus reducing the possibility of accidentally returning to the conducting mode.

[0183] 2. Second Implementation Method

[0184] Hereinafter, regarding the second embodiment, the same reference numerals will be used to mark the same constituent elements as in the first embodiment, and descriptions that are repeated in the first embodiment will be omitted or simplified. The description will mainly focus on the contents that are different from the first embodiment.

[0185] The circuit structure and operation of the drive circuit board 50 of the liquid ejection device 1 in the second embodiment are different from those of the liquid ejection device 1 in the first embodiment. Figure 13 This is a block diagram showing the circuit structure of the drive circuit board 50 in the second embodiment.

[0186] like Figure 13 As shown, in the second embodiment, the drive circuit 51c monitors the voltage VHV_H instead of VHV_A2. Furthermore, when the voltage VHV_H is higher than a predetermined voltage, the drive circuit 51c outputs an L-level error signal ERRc; when the voltage VHV_H is lower than the predetermined voltage, it outputs an H-level error signal ERRc and stops the output of the drive waveform of the drive signal COMc. Moreover, the H-level error signal ERRc is a signal that stops the output of the voltage VHV_H from the power supply circuit 90. The power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRc is H-level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by the drive circuit 51c becomes lower than the predetermined voltage, therefore the drive circuit 51c outputs an H-level error signal ERRc. The drive circuit 51c may also output an H-level error signal ERRc and an L-level control signal VHV_CNTc when the voltage VHV_H is lower than the predetermined voltage. Thus, drive circuit 51c operates in the same way as drive circuit 51a. That is, in the second embodiment, the two drive circuits 51a and 51c monitor the voltage VHV_H.

[0187] Furthermore, when the head unit 20 is started, the start-up control circuit 80 initially starts at least one of the drive circuits 51a and 51c that monitor the voltage VHV_H in the drive circuits 51a, 51b, 51c, and 51d. That is, the start-up control circuit 80 starts the start-up sequence of drive circuits 51b and 51d after starting the start-up sequence of at least one of the drive circuits 51a and 51c. For example, the start-up control circuit 80 may start the start-up sequence of drive circuits 51b, 51c, and 51d after starting the start-up sequence of drive circuit 51a, or it may start the start-up sequence of drive circuits 51a, 51b, and 51d after starting the start-up sequence of drive circuit 51c, or it may start the start-up sequence of drive circuits 51b and 51d after starting the start-up sequences of drive circuits 51a and 51c simultaneously. Furthermore, the start-up sequence of drive circuits 51b and 51d is preferably after at least one of drive circuits 51a and 51c begins monitoring of voltage VHV_H.

[0188] The other circuit structures of the driving circuit board 50 in the second embodiment are the same as those in the second embodiment. Figure 9 The drive circuit board 50 shown in the first embodiment is the same, so its description is omitted. Furthermore, the other structures and functions of the liquid ejection device 1 in the second embodiment are the same as those in the first embodiment, so their description is omitted.

[0189] In the liquid ejection device 1 of the second embodiment described above, at least one of the drive circuits 51a and 51c that monitors the voltage VHV_H supplied to the print head 22 starts up before drive circuit 51b that monitors the voltage VHV_A1 supplied to drive circuits 51a and 51b, and drive circuit 51d that monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d. Therefore, at least one of the drive circuits 51a and 51c starts monitoring the voltage VHV_H before drive circuits 51b and 51d respectively start outputting drive signals COMb and COMd ​​to the print head 22. Furthermore, drive circuits 51a and 51c start monitoring the voltage VHV_H before starting outputting drive signals COMa and COMc to the print head 22. Furthermore, if at least one of the drive circuits 51a and 51b detects a decrease in voltage VHV_H, the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the printhead 22, respectively. Therefore, according to the liquid ejection device 1 of the second embodiment, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, the possibility that drive signals COMa, COMb, COMc, and COMd ​​are higher than voltage VHV_H can be reduced, thereby reducing the possibility of printhead malfunction.

[0190] Assuming that the current flowing through the power supply wiring 75a exceeds a predetermined value due to a printhead 22 malfunction, the overcurrent protection circuits 70a, 70b, and 70c switch from an on-mode to a non-on-mode, thus protecting various circuits and electronic components, such as the drive circuits 51a, 51b, 51c, and 51d, contained in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and since they can switch from a non-on-mode to an on-mode, they can be reused. Therefore, according to the liquid ejection device 1 of the second embodiment, in the head unit 20, it is not necessary to replace the drive circuit board 50 in the event of a printhead 22 malfunction, thereby reducing repair labor and costs.

[0191] Furthermore, according to the liquid ejection device 1 of the second embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop the input of the enable signal when switching from the conducting mode to the non-conducting mode, thus maintaining the non-conducting mode. If no predetermined signal is input, the device will not switch from the non-conducting mode to the conducting mode, thereby reducing the possibility of accidentally returning to the conducting mode.

[0192] 3. Third Implementation Method

[0193] Hereinafter, regarding the third embodiment, the same reference numerals are used to mark the same constituent elements as in the first or second embodiment, and descriptions that are repeated in the first or second embodiment are omitted or simplified. The description mainly focuses on the contents that are different from the first and second embodiments.

[0194] The circuit structure and operation of the drive circuit board 50 of the liquid ejection device 1 in the third embodiment are different from those of the liquid ejection device 1 in the first or second embodiment. Figure 14 This is a block diagram showing the circuit structure of the drive circuit board 50 in the third embodiment.

[0195] like Figure 14 As shown, in the third embodiment, the drive circuit board 50 includes a fuse 77. The fuse 77 is disposed on the power supply wiring 75a that supplies voltage VHV_H to the print head 22. Specifically, one end of the fuse 77 is connected to the output terminal of the overcurrent protection circuit 70a, and the other end is connected to the print head 22. Therefore, voltage VHV_H is supplied to the print head 22 from the other end of the fuse 77.

[0196] The drive circuit 51a monitors the voltage VHV_H transmitted between the fuse 77 and the printhead 22 in the power supply wiring 75a. When the voltage VHV_H is below a predetermined voltage, it outputs an H-level error signal ERRa and stops the output of the drive waveform of the drive signal COMA. Furthermore, the H-level error signal ERRa is a signal that stops the output of the voltage VHV_H from the power supply circuit 90. The power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRa is at an H level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by the drive circuit 51a becomes below a predetermined voltage, therefore the drive circuit 51a outputs an H-level error signal ERRa. The drive circuit 51a can also output an H-level error signal ERRa and an L-level control signal VHV_CNTa when the voltage VHV_H is below a predetermined voltage.

[0197] Furthermore, when the head unit 20 is started, the start-up control circuit 80 initially starts drive circuit 51a, which monitors the voltage VHV_H among drive circuits 51a, 51b, 51c, and 51d. That is, the start-up control circuit 80 starts drive circuits 51b, 51c, and 51d in sequence after drive circuit 51a starts. Additionally, the timing at which drive circuits 51b, 51c, and 51d begin their start-up sequence is preferably after the time when drive circuit 51a begins monitoring the voltage VHV_H.

[0198] Other circuit structures of the driving circuit board 50 in the third embodiment are the same as those in the third embodiment. Figure 9The drive circuit board 50 shown in the first embodiment is the same, so its description is omitted. Furthermore, the other structures and functions of the liquid ejection device 1 in the third embodiment are the same as those in the first embodiment, so their description is omitted.

[0199] Additionally, in the third embodiment, it can also be combined with... Figure 13 The drive circuit board 50 shown in the second embodiment is the same, and the drive circuits 51a and 51c monitor the voltage VHV_H transmitted between the fuse 77 of the power supply wiring 75a and the printhead 22. In this case, when the head unit 20 is started, the start-up control circuit 80 initially starts at least one of the drive circuits 51a and 51c that monitors the voltage VHV_H. That is, the start-up control circuit 80 starts the start-up sequence of drive circuits 51b and 51d after starting the start-up sequence of at least one of the drive circuits 51a and 51c. For example, the start-up control circuit 80 can start the start-up sequence of drive circuits 51b, 51c, and 51d after the start-up sequence of drive circuit 51a has started; it can also start the start-up sequence of drive circuits 51a, 51b, and 51d after the start-up sequence of drive circuit 51c has started; or it can start the start-up sequence of drive circuits 51b and 51d after the start-up sequence of drive circuits 51a and 51c has started simultaneously. Furthermore, the time when the start-up sequence of drive circuits 51b and 51d begins is preferably after the time when at least one of drive circuits 51a and 51c begins monitoring the voltage VHV_H.

[0200] Alternatively, the drive circuit board 50 can replace the fuse 77 and include other components such as ferrite beads as components for the power cut-off circuit 90 and the print head 22.

[0201] In the liquid ejection device 1 of the third embodiment described above, similarly to the liquid ejection device 1 of the first embodiment, the drive circuit 51a begins monitoring the voltage VHV_H before the drive circuits 51b, 51c, and 51d start outputting drive signals COMb, COMc, and COMd ​​to the printhead 22, respectively. Therefore, according to the liquid ejection device 1 of the third embodiment, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, the possibility that the drive signals COMa, COMb, COMc, and COMd ​​are higher than the voltage VHV_H can be reduced, thus reducing the possibility of printhead malfunction.

[0202] Furthermore, according to the liquid ejection device 1 of the third embodiment, when an overcurrent flows in the power wiring 75a supplied to the print head 22 at voltage VHV_H, the fuse 77 blows, thus further reducing the possibility of print head 22 malfunctioning.

[0203] Furthermore, according to the liquid ejection device 1 of the first embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop inputting the enable signal when switching from the conducting mode to the non-conducting mode, thus maintaining the non-conducting mode. If no predetermined signal is input, the device will not switch from the non-conducting mode to the conducting mode, thereby reducing the possibility of accidentally returning to the conducting mode.

[0204] 4. Fourth Implementation Method

[0205] Hereinafter, regarding the fourth embodiment, the same reference numerals will be used to mark the same constituent elements as in any of the first to third embodiments, and descriptions that are repeated in any of the first to third embodiments will be omitted or simplified. The description will mainly focus on the contents that are different from any of the first to third embodiments.

[0206] The circuit structure and operation of the drive circuit board 50 of the liquid ejection device 1 in the fourth embodiment are different from those of the liquid ejection device 1 in the first to third embodiments. Figure 15 This is a block diagram showing the circuit structure of the drive circuit board 50 in the fourth embodiment.

[0207] like Figure 15 As shown, in the fourth embodiment, the voltage VHV_H supplied to the print head 22 and the voltage VHV_A1 supplied to the drive circuits 51a and 51b are common voltages.

[0208] Drive circuits 51a and 51b monitor the voltage VHV_H. Furthermore, when the voltage VHV_H is higher than a predetermined voltage, drive circuits 51a and 51b output low-level error signals ERa and ERRb, respectively; when the voltage VHV_H is lower than the predetermined voltage, they output high-level error signals ERa and ERRb, respectively, and stop the output of the drive waveforms of drive signals COMa and COMb, respectively. Moreover, the high-level error signals ERa and ERRb are signals that stop the output of the voltage VHV_H from the power supply circuit 90. The power supply circuit 90 stops the output of the voltage VHV_H when at least one of the error signals ERa and ERRb is at a high level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by drive circuits 51a and 51b becomes lower than the predetermined voltage, therefore drive circuits 51a and 51b output high-level error signals ERa and ERRb, respectively. The drive circuits 51a and 51b can also output H-level error signals ERRra and ERRb respectively, and L-level control signals VHV_CNTa and VHV_CNTb respectively, when the voltage VHV_H is below a predetermined voltage.

[0209] Furthermore, when the head unit 20 is started, the start-up control circuit 80 initially starts at least one of the drive circuits 51a and 51b that monitor the voltage VHV_H in the drive circuits 51a, 51b, 51c, and 51d. That is, the start-up control circuit 80 starts the start-up sequence of drive circuits 51c and 51d after starting the start-up sequence of at least one of the drive circuits 51a and 51b. For example, the start-up control circuit 80 may start the start-up sequence of drive circuits 51b, 51c, and 51d after starting the start-up sequence of drive circuit 51a, or it may start the start-up sequence of drive circuits 51a, 51c, and 51d after starting the start-up sequence of drive circuit 51b, or it may start the start-up sequence of drive circuits 51c and 51d after starting the start-up sequences of drive circuits 51a and 51b simultaneously. Furthermore, the start-up sequence of drive circuits 51c and 51d is preferably after at least one of drive circuits 51a and 51b begins monitoring of voltage VHV_H.

[0210] The other circuit structures of the drive circuit board 50 in the fourth embodiment are the same as those in the fourth embodiment. Figure 9 The drive circuit board 50 shown in the first embodiment is the same, so its description is omitted. Furthermore, the other structures and functions of the liquid ejection device 1 in the fourth embodiment are the same as those in the first embodiment, so their description is omitted.

[0211] Additionally, in the fourth embodiment, it can also be combined with... Figure 14Similarly, the drive circuit board 50 of the third embodiment shown includes a fuse 77 disposed on the power supply wiring 75a to which voltage VHV_H is supplied to the print head 22, and drive circuits 51a and 51b monitor the voltage VHV_H transmitted between the fuse 77 and the print head 22 in the power supply wiring 75a.

[0212] In the liquid ejection device 1 of the fourth embodiment described above, at least one of the drive circuits 51a and 51b that monitors the voltage VHV_H (VHV_A1) supplied to the printhead 22 and the drive circuits 51a and 51b starts its startup sequence before monitoring the voltage VHV_A2 supplied to the drive circuits 51c and 51d. Therefore, at least one of the drive circuits 51a and 51b starts monitoring the voltage VHV_H (VHV_A1) before the drive circuits 51c and 51d start outputting drive signals COMc and COMd ​​to the printhead 22, respectively. Furthermore, the drive circuits 51a and 51b start monitoring the voltage VHV_H (VHV_A1) before starting outputting drive signals COMa and COMb to the printhead 22. Furthermore, if at least one of the drive circuits 51a and 51b detects a decrease in voltage VHV_H (VHV_A1), the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, the liquid ejection device 1 according to the fourth embodiment can reduce the likelihood that drive signals COMa, COMb, COMc, and COMd ​​are higher than voltage VHV_H (VHV_A1) not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, thus reducing the possibility of print head malfunction.

[0213] Assuming that the current flowing through the power supply wiring 75a exceeds a predetermined value due to a printhead 22 malfunction, the overcurrent protection circuits 70a, 70b, and 70c switch from an on-mode to a non-on-mode, thus protecting various circuits and electronic components, such as the drive circuits 51a, 51b, 51c, and 51d, contained in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and since they can switch from a non-on-mode to an on-mode, they can be reused. Therefore, according to the liquid ejection device 1 of the fourth embodiment, in the head unit 20, it is not necessary to replace the drive circuit board 50 in the event of a printhead 22 malfunction, thereby reducing repair labor and costs.

[0214] Furthermore, according to the liquid ejection device 1 of the fourth embodiment, the overcurrent protection circuits 70a, 70b, and 70c stop the input of the enable signal when switching from the conducting mode to the non-conducting mode, thus maintaining the non-conducting mode. If no predetermined signal is input, the device will not switch from the non-conducting mode to the conducting mode, thereby reducing the possibility of accidentally returning to the conducting mode.

[0215] 5. Variations

[0216] This invention is not limited to this embodiment, and various modifications can be made within the scope of the spirit of this invention.

[0217] For example, in the above embodiments, the drive circuit substrate 50 includes four drive circuits 51, but the number of drive circuits 51 included in the drive circuit substrate 50 may also be two, three, or more than five. Similarly, the drive circuit substrate 50 includes four overcurrent protection circuits 70, but the number of overcurrent protection circuits 70 included in the drive circuit substrate 50 may also be two, three, or more than five.

[0218] Furthermore, in the above embodiments, the VHV abnormal signals VERa, VERb, VERc, and VERd output from logic circuits 71a, 71b, 71c, and 71d are input to drive circuits 51a, 51b, 51c, and 51d as error signals ERRa, ERRb, ERRc, and ERRd, respectively. However, the VHV abnormal signal VERa output from logic circuit 71a as error signals ERRa, ERRb, ERRc, and ERRd can also be input to drive circuits 51a, 51b, 51c, and 51d together.

[0219] Furthermore, in the above embodiments, it is described that the liquid ejection device 1 is a so-called serial inkjet printer in which a liquid ejection module 21 for ejecting ink is mounted on a carriage 24 and the carriage 24 reciprocates on the medium P to perform printing. However, it can also be a so-called line inkjet printer in which the liquid ejection modules 21 are arranged side by side in the width direction of the medium P and printing is performed by conveying the medium P.

[0220] The embodiments have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from its spirit. For example, the above embodiments can also be appropriately combined.

[0221] This invention includes structures that are substantially the same as those described in the embodiments, such as structures with the same function, method, and result, or structures with the same purpose and effect. Furthermore, this invention includes structures that replace non-essential parts of the structures described in the embodiments. Additionally, this invention includes structures that have the same function or effect as those described in the embodiments, or structures that can achieve the same purpose. Furthermore, this invention includes structures incorporating known technology into the structures described in the embodiments.

[0222] The following content is derived from the above implementation method.

[0223] One method of liquid ejection device includes:

[0224] Conveying section, conveying medium;

[0225] The head includes a drive section driven by a drive signal and an ejection section that ejects liquid from the medium according to the drive section; and

[0226] The drive circuit board is connected to the head.

[0227] The driving circuit substrate includes:

[0228] The driving circuit outputs the driving signal;

[0229] The first power supply wiring connects the power circuit and the head; and

[0230] The first overcurrent protection circuit is installed on the first power supply wiring.

[0231] The first overcurrent protection circuit has:

[0232] In the first mode, the power circuit and the head are in a conductive state; and

[0233] In the second mode, the power supply circuit and the head are in a non-conductive state.

[0234] If the current flowing through the first power supply wiring is above a predetermined value, the system switches from the first mode to the second mode.

[0235] It can switch from the second mode to the first mode.

[0236] In this liquid ejection device, if the head malfunctions and the current flowing through the first power supply wiring exceeds a predetermined value, the first overcurrent protection circuit switches from a first mode that turns on the power supply circuit and the head to a second mode that turns off the power supply circuit and the head. This protects various circuits and electronic components, including the drive circuit, contained in the drive circuit board. Furthermore, the first overcurrent protection circuit can switch back from the second mode to the first mode, allowing for reuse. Therefore, according to this liquid ejection device, in the event of a head malfunction, it is not necessary to replace the drive circuit board, thus reducing repair time and costs.

[0237] In one embodiment of the liquid ejection device, it may be:

[0238] When the first overcurrent protection circuit switches from the first mode to the second mode, the drive circuit stops outputting the enable signal to the first overcurrent protection circuit.

[0239] According to the liquid ejection device, after the first overcurrent protection circuit switches from the first mode to the second mode, it can maintain the second mode.

[0240] In one embodiment of the liquid ejection device, it may be:

[0241] The first overcurrent protection circuit switches from the second mode to the first mode by receiving a predetermined signal.

[0242] According to the liquid ejection device, if the first overcurrent protection circuit is not input with a predetermined signal, it will not switch from the second mode to the first mode, thus reducing the possibility of accidentally returning from the second mode to the first mode.

[0243] In one embodiment of the liquid ejection device, it may be:

[0244] The predetermined signal is an enable signal output from the drive circuit.

[0245] According to the liquid ejection device, if no enable signal is input to the first overcurrent protection circuit, it will not switch from the second mode to the first mode, thus reducing the possibility of accidentally returning from the second mode to the first mode.

[0246] In one embodiment of the liquid ejection device, it may be:

[0247] The driving circuit substrate includes:

[0248] A second power supply wiring connects the power supply circuit and the drive circuit; and

[0249] The second overcurrent protection circuit is installed on the second power supply wiring.

[0250] The second overcurrent protection circuit has:

[0251] The third mode enables the power supply circuit and the drive circuit to be in a conducting state; and

[0252] In the fourth mode, the power supply circuit and the drive circuit are in a non-conducting state.

[0253] If the current flowing through the second power supply wiring is above a predetermined value, the system switches from the third mode to the fourth mode.

[0254] It can switch from the fourth mode to the third mode.

[0255] In this liquid ejection device, when the current flowing through the second power supply wiring exceeds a predetermined value, the second overcurrent protection circuit switches from a third mode (turning on the power supply circuit and drive circuit) to a fourth mode (turning off the power supply circuit and drive circuit), thus protecting the drive circuit. Furthermore, the second overcurrent protection circuit can switch from the fourth mode back to the third mode, allowing for reuse. Therefore, according to this liquid ejection device, in the event of a head failure, it is not necessary to replace the drive circuit board, thereby reducing repair time and costs.

[0256] In one embodiment of the liquid ejection device, it may be:

[0257] When the output of the enable signal from the drive circuit stops, the second overcurrent protection circuit switches from the third mode to the fourth mode.

[0258] According to the liquid ejection device, when the first overcurrent protection circuit switches from a first mode that turns on the power supply circuit and the head to a second mode that turns off the power supply circuit and the head, the second overcurrent circuit switches from a third mode that turns on the power supply circuit and the drive circuit to a fourth mode that turns off the power supply circuit and the drive circuit. Therefore, even if the head fails, the drive circuit can be protected.

[0259] In one embodiment of the liquid ejection device, it may be:

[0260] The second overcurrent protection circuit switches from the fourth mode to the third mode by receiving a predetermined signal.

[0261] According to the liquid ejection device, if the second overcurrent protection circuit is not input with a predetermined signal, it will not switch from the fourth mode to the third mode, thus reducing the possibility of accidentally returning from the fourth mode to the third mode.

[0262] In one embodiment of the liquid ejection device, it may be:

[0263] The driving circuit substrate includes:

[0264] The second power supply wiring connects the power supply circuit and the drive circuit;

[0265] A first capacitor is connected between the first power supply wiring and ground; and

[0266] The second capacitor is connected between the second power supply wiring and the ground.

[0267] The capacitance value of the second capacitor is greater than that of the first capacitor.

[0268] In this liquid ejection device, the capacitance of the second stabilizing capacitor connected to the second power supply wiring connecting the power supply circuit and the drive circuit is greater than the capacitance of the first stabilizing capacitor connected to the first power supply wiring connecting the power supply circuit and the printhead. Therefore, when the power supply voltage from the power supply circuit stops, the printhead's power supply voltage drops faster than the drive circuit's power supply voltage. As a result, there is a possibility of printhead failure due to a large current flowing from the drive signal transmission wiring to the first power supply wiring caused by parasitic diodes inside the printhead. However, this liquid ejection device reduces the likelihood of needing to replace the drive circuit board in the event of a printhead failure, thus reducing repair time and costs.

[0269] One type of header unit is a header unit that has:

[0270] The head includes a drive section driven by a drive signal and has an ejection section that ejects liquid from a medium according to the drive section; and

[0271] The drive circuit board is connected to the head.

[0272] The driving circuit substrate includes:

[0273] The driving circuit outputs the driving signal;

[0274] The first power supply wiring connects the power circuit and the head; and

[0275] The first overcurrent protection circuit is installed on the first power supply wiring.

[0276] The first overcurrent protection circuit has:

[0277] In the first mode, the power circuit and the head are in a conductive state; and

[0278] In the second mode, the power supply circuit and the head are in a non-conductive state.

[0279] If the current flowing through the first power supply wiring is above a predetermined value, the system switches from the first mode to the second mode.

[0280] It can switch from the second mode to the first mode.

[0281] In this head unit, if a head malfunction occurs and the current flowing through the first power supply wiring exceeds a predetermined value, the first overcurrent protection circuit switches from a first mode that turns on the power supply circuit and the head to a second mode that turns off the power supply circuit and the head. This protects various circuits and electronic components, including the drive circuit, contained in the drive circuit board. Furthermore, the first overcurrent protection circuit can switch back from the second mode to the first mode, allowing for reuse. Therefore, according to this head unit, in the event of a head malfunction, it is not necessary to replace the drive circuit board, thus reducing repair time and costs.

[0282] In one embodiment of the head unit, it may be:

[0283] When the first overcurrent protection circuit switches from the first mode to the second mode, the drive circuit stops outputting the enable signal to the first overcurrent protection circuit.

[0284] According to this head unit, after the first overcurrent protection circuit switches from the first mode to the second mode, it can maintain the second mode.

[0285] In one embodiment of the head unit, it may be:

[0286] The first overcurrent protection circuit switches from the second mode to the first mode by receiving a predetermined signal.

[0287] According to this head unit, if the first overcurrent protection circuit is not input with a predetermined signal, it will not switch from the second mode to the first mode, thus reducing the possibility of accidentally returning from the second mode to the first mode.

[0288] In one embodiment of the head unit, it may be:

[0289] The predetermined signal is an enable signal output from the drive circuit.

[0290] According to this head unit, if no enable signal is input to the first overcurrent protection circuit, it will not switch from the second mode to the first mode, thus reducing the possibility of accidentally returning from the second mode to the first mode.

[0291] In one embodiment of the head unit, it may be:

[0292] The driving circuit substrate includes:

[0293] A second power supply wiring connects the power supply circuit and the drive circuit; and

[0294] The second overcurrent protection circuit is installed on the second power supply wiring.

[0295] The second overcurrent protection circuit has:

[0296] The third mode enables the power supply circuit and the drive circuit to be in a conducting state; and

[0297] In the fourth mode, the power supply circuit and the drive circuit are in a non-conducting state.

[0298] If the current flowing through the second power supply wiring is above a predetermined value, the system switches from the third mode to the fourth mode.

[0299] It can switch from the fourth mode to the third mode.

[0300] In this head unit, when the current flowing through the second power supply wiring exceeds a predetermined value, the second overcurrent protection circuit switches from a third mode, which turns on the power supply circuit and drive circuit, to a fourth mode, which turns off the power supply circuit and drive circuit, thus protecting the drive circuit. Furthermore, the second overcurrent protection circuit can switch from the fourth mode back to the third mode, allowing for reuse. Therefore, according to this head unit, in the event of a head failure, it is not necessary to replace the drive circuit board, thereby reducing the time and cost required for repairs.

[0301] In one embodiment of the head unit, it may be:

[0302] When the output of the enable signal from the drive circuit stops, the second overcurrent protection circuit switches from the third mode to the fourth mode.

[0303] According to this head unit, when the first overcurrent protection circuit switches from a first mode that turns on the power supply circuit and the head to a second mode that turns off the power supply circuit and the head, the second overcurrent circuit switches from a third mode that turns on the power supply circuit and the drive circuit to a fourth mode that turns off the power supply circuit and the drive circuit. Therefore, even if the head fails, the drive circuit can be protected.

[0304] In one embodiment of the head unit, it may be:

[0305] The second overcurrent protection circuit switches from the fourth mode to the third mode by receiving a predetermined signal.

[0306] According to this head unit, if the second overcurrent protection circuit is not input with a predetermined signal, it will not switch from the fourth mode to the third mode, thus reducing the possibility of accidentally returning from the fourth mode to the third mode.

[0307] In one embodiment of the head unit, it may be:

[0308] The driving circuit substrate includes:

[0309] The second power supply wiring connects the power supply circuit and the drive circuit;

[0310] A first capacitor is connected between the first power supply wiring and ground; and

[0311] The second capacitor is connected between the second power supply wiring and the ground.

[0312] The capacitance value of the second capacitor is greater than that of the first capacitor.

[0313] In this printhead unit, the capacitance of the second stabilizing capacitor connected to the second power supply wiring connecting the power supply circuit and the drive circuit is greater than the capacitance of the first stabilizing capacitor connected to the first power supply wiring connecting the power supply circuit and the printhead. Therefore, when the power supply voltage from the power supply circuit stops, the printhead's power supply voltage drops faster than the drive circuit's power supply voltage. As a result, there is a possibility of printhead failure due to a large current flowing from the drive signal transmission wiring to the first power supply wiring caused by parasitic diodes inside the printhead. However, this printhead unit reduces the likelihood of needing to replace the drive circuit board in the event of a printhead failure, thus reducing repair time and costs.

Claims

1. A liquid ejection device, characterized in that, have: Conveying section, conveying medium; The head includes a drive unit driven by a drive signal and has an ejection unit that ejects liquid from the medium according to the drive unit. as well as The drive circuit board is connected to the head. The driving circuit substrate includes: The driving circuit outputs the driving signal; The first power supply wiring connects the power circuit and the head; and The first overcurrent protection circuit is installed on the first power supply wiring. The first overcurrent protection circuit has: In the first mode, the power circuit and the head are in a conductive state; and In the second mode, the power supply circuit and the head are in a non-conductive state. If the current flowing through the first power supply wiring is above a predetermined value, the system switches from the first mode to the second mode. It can switch from the second mode to the first mode.

2. The liquid ejection device according to claim 1, characterized in that, When the first overcurrent protection circuit switches from the first mode to the second mode, the drive circuit stops outputting the enable signal to the first overcurrent protection circuit.

3. The liquid ejection device according to claim 1, characterized in that, The first overcurrent protection circuit switches from the second mode to the first mode by receiving a predetermined signal.

4. The liquid ejection device according to claim 3, characterized in that, The predetermined signal is an enable signal output from the drive circuit.

5. The liquid ejection device according to claim 1, characterized in that, The driving circuit substrate includes: A second power supply wiring connects the power supply circuit and the drive circuit; and The second overcurrent protection circuit is installed on the second power supply wiring. The second overcurrent protection circuit has: The third mode enables the power supply circuit and the drive circuit to be in a conducting state; and In the fourth mode, the power supply circuit and the drive circuit are in a non-conducting state. If the current flowing through the second power supply wiring is above a predetermined value, the system switches from the third mode to the fourth mode. It can switch from the fourth mode to the third mode.

6. The liquid ejection device according to claim 5, characterized in that, When the output of the enable signal from the drive circuit stops, the second overcurrent protection circuit switches from the third mode to the fourth mode.

7. The liquid ejection device according to claim 5, characterized in that, The second overcurrent protection circuit switches from the fourth mode to the third mode by receiving a predetermined signal.

8. The liquid ejection device according to claim 1, characterized in that, The driving circuit substrate includes: The second power supply wiring connects the power supply circuit and the drive circuit; A first capacitor is connected between the first power supply wiring and ground; and The second capacitor is connected between the second power supply wiring and the ground. The capacitance value of the second capacitor is greater than that of the first capacitor.

9. A head unit, characterized in that, have: The head includes a drive unit driven by a drive signal and has an ejection unit that ejects liquid from the medium according to the drive unit. as well as The drive circuit board is connected to the head. The driving circuit substrate includes: The driving circuit outputs the driving signal; The first power supply wiring connects the power circuit and the head; and The first overcurrent protection circuit is installed on the first power supply wiring. The first overcurrent protection circuit has: In the first mode, the power circuit and the head are in a conductive state; and In the second mode, the power supply circuit and the head are in a non-conductive state. If the current flowing through the first power supply wiring is above a predetermined value, the system switches from the first mode to the second mode. It can switch from the second mode to the first mode.

10. The head unit according to claim 9, characterized in that, When the first overcurrent protection circuit switches from the first mode to the second mode, the drive circuit stops outputting the enable signal to the first overcurrent protection circuit.

11. The head unit according to claim 9, characterized in that, The first overcurrent protection circuit switches from the second mode to the first mode by receiving a predetermined signal.

12. The head unit according to claim 11, characterized in that, The predetermined signal is an enable signal output from the drive circuit.

13. The head unit according to claim 9, characterized in that, The driving circuit substrate includes: A second power supply wiring connects the power supply circuit and the drive circuit; and The second overcurrent protection circuit is installed on the second power supply wiring. The second overcurrent protection circuit has: The third mode enables the power supply circuit and the drive circuit to be in a conducting state; and In the fourth mode, the power supply circuit and the drive circuit are in a non-conducting state. If the current flowing through the second power supply wiring is above a predetermined value, the system switches from the third mode to the fourth mode. It can switch from the fourth mode to the third mode.

14. The head unit according to claim 13, characterized in that, When the output of the enable signal from the drive circuit stops, the second overcurrent protection circuit switches from the third mode to the fourth mode.

15. The head unit according to claim 13 or 14, characterized in that, The second overcurrent protection circuit switches from the fourth mode to the third mode by receiving a predetermined signal.

16. The head unit according to claim 9, characterized in that, The driving circuit substrate includes: The second power supply wiring connects the power supply circuit and the drive circuit; A first capacitor is connected between the first power supply wiring and ground; and The second capacitor is connected between the second power supply wiring and the ground. The capacitance value of the second capacitor is greater than that of the first capacitor.

Images