Resource-constrained network-oriented distributed random pulse chip control method

Abstract

The invention relates to the technical field of edge AI chips, in particular to a distributed random pulse chip control method for a resource-constrained network. Comprising a heterogeneous neural computing core which is composed of a random computing neural convolution feature extractor and a miniature binary calibration coprocessor and is configured in an edge AI chip. The statistical confidence coefficient of random pulse calculation is monitored in real time through the random pulse flow analyzer, when the confidence coefficient reaches a preset threshold value, an early decision termination mechanism is triggered, calculation of the random calculation neural convolution feature extractor is stopped in advance, and a calculation result is transferred to the miniature binary calibration coprocessor for decision calibration. According to the method, the inherent contradiction between the random calculation precision and the delay is effectively relieved, the energy efficiency ratio and the response speed of the edge AI chip are remarkably improved, and the service life of a battery of resource-limited network equipment is prolonged.

Description

Technical Field

[0001] This invention relates to the field of edge AI chip technology, specifically a chip control method for distributed random pulses in resource-constrained networks. Background Technology

[0002] With the rapid development of the Internet of Things (IoT) and edge computing, the demand for edge AI processing capabilities, especially for the deployment of deep learning models, is rising sharply in resource-constrained networks such as wireless sensor networks and wearable devices. This has brought about stringent power consumption and chip area limitations.

[0003] Most existing AI chips based on the von Neumann architecture employ deterministic binary computation. While quantized models such as binary neural networks (BNNs) have been introduced to accelerate deep learning inference, their hardware implementation still requires a large number of high-precision multipliers and adders. This traditional approach still faces significant power consumption and chip area constraints when handling the massive multiplication and addition operations of convolutional layers. Furthermore, nanoscale chips are susceptible to variations in process technology, voltage, and temperature (PVT), as well as noise, severely impacting the reliability of neural network models. In addition, traditional methods typically require fixed computation cycles, making it difficult to achieve real-time, dynamic resource allocation based on the statistical convergence of inference results.

[0004] How to leverage impulse mechanisms and the principle of randomness to achieve adaptive control based on computational confidence under strict resource constraints while maintaining the robustness of edge AI inference models is a technical problem that urgently needs to be solved.

[0005] To address this, a chip control method for distributed random pulses in resource-constrained networks is proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a chip control method for distributed random pulses in resource-constrained networks. By configuring a heterogeneous neural computing core consisting of a random computation neural convolution feature extractor and a micro binary calibration coprocessor, and introducing a random pulse stream analyzer to monitor the statistical confidence of the computation in real time, early decision termination based on confidence can be achieved.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A chip control method for distributed random pulses in resource-constrained networks includes: A heterogeneous neural computing core is configured within the edge AI chip. The heterogeneous neural computing core includes a random computation neural convolution feature extractor and a micro binary calibration coprocessor. A binary neural network model is loaded into the heterogeneous neural computing core by the edge AI inference engine. The random computation neural convolution feature extractor is used to perform random pulse calculation on the input data and generate a random pulse stream; the random pulse stream analyzer is started to monitor the statistical confidence of the random pulse stream in real time; When the random pulse stream analyzer determines that the statistical confidence level is less than or equal to a preset threshold, it triggers an early decision termination mechanism to stop the calculation of the random computation neural convolution feature extractor in advance and transfers the calculation result to the micro binary calibration coprocessor for decision calibration.

[0008] Preferably, the random computation neural convolution feature extractor specifically includes a random bitstream generator and a pulse computation array: A random bit stream generator is used to convert input data into a corresponding random pulse stream; The pulse computing array consists of n logic gate arrays, which are used to replace traditional binary multipliers. The multiplication-accumulation operation is implemented through a logic AND gate, and the output density of the pulse stream is accumulated through an adder and / or a counter to perform the convolution operation in the binary neural network model. The input data includes the input feature map and the weight parameters in the binary neural network model.

[0009] Preferably, the micro binary calibration coprocessor specifically includes a high-precision arithmetic logic unit, a binary input / output interface, and a decision unit: The high-precision arithmetic logic unit is used to perform traditional deterministic binary operations and to handle application tasks that require a classification accuracy of no less than 95%. The binary input / output interface is used to receive the pulse calculation results output in advance by the random computation neural convolution feature extractor through the early decision termination mechanism, and output the final calibration decision results in standard binary form; The decision unit is used to execute the final decision layer of the binary neural network model and the classification confidence calibration algorithm.

[0010] Preferably, the edge AI inference engine is a software control core deployed on the edge AI chip, specifically: loading the binary neural network model from memory into the heterogeneous neural computing core, and mapping different level operations to the random computation neural convolution feature extractor and the micro binary calibration coprocessor; Receive input data from the sensor and format the input data into an input format suitable for processing by the random computation neural convolution feature extractor; During the execution of the edge AI chip control method, the edge AI inference engine acts as a high-level controller, responsible for starting the random pulse stream analyzer and coordinating the switching of data and control flow between the random computation neural convolution feature extractor and the micro binary calibration coprocessor upon receiving an early decision termination signal.

[0011] Preferably, the binarized neural network model includes a binarized convolutional layer and a binarized fully connected layer. The binarized convolutional layer is used to perform feature extraction on the input data, and the binarized fully connected layer is used to perform classification on the extracted features.

[0012] Preferably, the specific method for generating the random pulse stream includes: Within the random computation neural convolution feature extractor, a random number generator is configured to generate a random bit sequence with a uniform distribution; the input data of the binary neural network model is normalized to obtain an input value between 0 and 1; a digital comparator is used to compare the input value with the random bit sequence output by the random number generator bit by bit. The output pulse is 1 only when the random value is less than or equal to the input value; otherwise, the output non-pulse is 0. By repeating the above comparison process, a random pulse stream with a pulse density proportional to the input value is generated, and the random pulse stream is used as the computational input of the random computational neural convolution feature extractor.

[0013] Preferably, the specific steps for starting the random pulse stream analyzer and monitoring the statistical confidence level of the random pulse stream in real time include: During the computation process, the random pulse stream analyzer continuously accumulates the current results of the random pulse stream output by the random computation neural convolution feature extractor to obtain a cumulative result; it tracks the total number of pulses processed since the start of the computation in real time; based on the cumulative result and the total number of pulses, it calculates the current statistical confidence level. The calculated statistical confidence level is compared with a preset confidence level threshold; when the statistical confidence level ≤ the preset threshold, the random pulse stream analyzer sends an early decision termination signal to the chip controller.

[0014] Preferably, the specific execution steps of the early decision termination mechanism include: the chip controller receiving an early decision termination signal sent from the random pulse stream analyzer; and immediately sending an interrupt command to the random computation neural convolution feature extractor to stop all pulse calculations and pulse stream generation that it is currently performing; The pulse counting unit is activated to quickly convert the pulse results accumulated by the random computation neural convolution feature extractor during the interruption into standard fixed-point binary values; the fixed-point binary values ​​are used as intermediate results and routed to the input interface of the micro binary calibration coprocessor through the edge AI inference engine. The micro binary calibration coprocessor is activated to perform classification confidence calibration.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention employs pulse-based random computation hardware implementation, replacing the traditional binary multiplier with ultra-low-power logic AND gates and pulse density accumulator counters. After tape-out verification, this design, at the same process node (e.g., 28nm), reduces the power consumption of the MAC (multiply-accumulate) unit from 500uW in the traditional design to 30uW, and reduces the area to 15% of the original. For typical edge AI applications (e.g., an 8-layer BNN convolutional model with 2 fully connected layers), the power consumption of the entire inference process is reduced by 60%–70%, and while maintaining a classification accuracy no less than 95% of the reference implementation, the energy efficiency ratio is improved from 100 MOPS / mW in the traditional implementation to 600 MOPS / mW.

[0016] 2. This invention cleverly resolves the contradiction between high parallelism, low power consumption, and high precision in random computation by configuring a heterogeneous neural computing core consisting of a random computation neural convolutional feature extractor and a micro binary calibration coprocessor. The random computation core is responsible for low-power, highly robust feature extraction, while the micro binary calibration coprocessor takes over the results after early termination, performing high-precision binary operations to complete the final classification confidence calibration or decision. This division of labor ensures that the accuracy and reliability of the final decision result are effectively guaranteed while maintaining overall low power consumption and small area.

[0017] 3. The stochastic computing paradigm inherently possesses tolerance to variations in process technology, voltage, temperature, and random noise. By encoding the computation results into the statistical density of the pulse flow, the impact of a single pulse error (soft error or leakage) on the final result is negligible. This invention leverages this robustness to enable edge AI chips to stably execute inference tasks of binary neural network models even under the harsh physical environments and noise interference commonly faced by nanoscale chips, thereby significantly improving the operational reliability of distributed neural computing systems. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart of a chip control method for distributed random pulses in resource-constrained networks proposed in this invention. Figure 2 This is a schematic diagram illustrating the steps of a chip control method for distributed random pulses in resource-constrained networks proposed in this invention. Figure 3 This is a flowchart illustrating the random pulse flow analyzer proposed in this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1 Please see Figures 1 to 3 This invention provides a chip control method for distributed random pulses in resource-constrained networks, the technical solution of which is as follows: A chip control method for distributed random pulses in resource-constrained networks, such as... Figure 1 and Figure 2 As shown, it includes: A heterogeneous neural computing core is configured within the edge AI chip. The heterogeneous neural computing core includes a random computation neural convolution feature extractor and a micro binary calibration coprocessor. A binary neural network model is loaded into the heterogeneous neural computing core by the edge AI inference engine. The random computation neural convolution feature extractor is used to perform random pulse calculation on the input data and generate a random pulse stream; the random pulse stream analyzer is started to monitor the statistical confidence of the random pulse stream in real time; When the random pulse stream analyzer determines that the statistical confidence level is less than or equal to a preset threshold, it triggers an early decision termination mechanism to stop the calculation of the random computation neural convolution feature extractor in advance and transfers the calculation result to the micro binary calibration coprocessor for decision calibration.

[0021] Furthermore, the random computation neural convolution feature extractor specifically includes a random bitstream generator and a pulse computation array: A random bit stream generator is used to convert input data into a corresponding random pulse stream; The pulse computing array consists of n logic gate arrays, which are used to replace traditional binary multipliers. The multiplication-accumulation operation is implemented through a logic AND gate, and the output density of the pulse stream is accumulated through an adder or a counter to perform the convolution operation in the binary neural network model. The input data includes the input feature map and the weight parameters in the binary neural network model.

[0022] The value of n represents the parallelism of the pulse computation array. Its value is not arbitrary but determined based on the number of channels in the largest feature map of the loaded binary neural network model, the number of convolutional kernels, or the minimum inference speed required by the system. The value of n should be optimized to minimize chip area and resource consumption while meeting performance requirements.

[0023] The random bit stream generator preferably employs a low-overhead linear feedback shift register to implement a pseudo-random number generator to ensure high pulse throughput. The maximum length L of the random pulse stream determines the theoretical accuracy limit of the random calculation. The value of L should be dynamically or predetermined according to the minimum classification confidence requirement required by the edge AI chip to ensure the reliability of the results.

[0024] The accumulation function of the multiply-accumulate operation is implemented through the adder and / or counter, specifically a low-power pulse density accumulator counter or pulse counting circuit. The structure of the accumulation hardware is optimized to avoid using traditional high-precision binary adders, thereby minimizing power consumption and hardware complexity in the accumulation stage.

[0025] The stochastic computation neural convolution feature extractor utilizes a stochastic computation paradigm to exhibit inherent robustness against process, voltage, and temperature variations, as well as soft errors and leakage current. The edge AI chip incorporates an on-chip noise characterization module that collects real-time PVT variations and noise statistics. When calculating statistical confidence, the stochastic pulse current analyzer dynamically adjusts the confidence threshold by incorporating data from the on-chip noise characterization module, ensuring the reliability of inference results even under harsh physical conditions.

[0026] This invention leverages the inherent robustness of random computation to PVT variations and collects noise data in real time through an on-chip noise characterization module. This enables the random pulse flow analyzer to dynamically adjust the confidence threshold, ensuring the inference reliability and system stability of the edge AI chip in harsh physical environments.

[0027] This invention significantly simplifies the hardware structure and reduces chip area and power consumption by replacing the binary multiplier of the traditional MAC with an AND gate in the random computation neural convolution feature extractor. Simultaneously, the optimized random bitstream generator and low-power counter ensure high throughput, efficiently meeting the energy efficiency requirements of edge AI chips.

[0028] Furthermore, the micro binary calibration coprocessor specifically includes a high-precision arithmetic logic unit, a binary input / output interface, and a decision unit: The high-precision arithmetic logic unit is used to perform traditional deterministic binary operations and to handle application tasks that require a classification accuracy of no less than 95%. The binary input / output interface is used to receive the pulse calculation results output in advance by the random computation neural convolution feature extractor through the early decision termination mechanism, and output the final calibration decision results in standard binary form; The decision unit is used to execute the final decision layer of the binary neural network model and the classification confidence calibration algorithm.

[0029] The high-precision arithmetic logic unit employs 16-bit or 32-bit fixed-point or half-precision floating-point arithmetic precision to provide a final accuracy that random computation neural convolution feature extractors cannot guarantee. The precision selection of the high-precision arithmetic logic unit is based on the final layer error analysis results of the binary neural network model, ensuring that hardware area and power consumption are minimized while guaranteeing system accuracy.

[0030] The binary input / output interface includes a pulse count-to-binary conversion module, which converts the pulse count result (i.e., the accumulated value) output by the random computation neural convolution feature extractor at the early decision termination into a 16-bit or 32-bit fixed-point binary value as input data for the high-precision arithmetic logic unit.

[0031] The decision unit employs a calibration lookup table or a statistically based calibration model to execute a classification confidence calibration algorithm to handle statistical errors introduced by random calculations. After the high-precision arithmetic logic unit completes the final calculation, the decision unit is responsible for outputting a corrected, highly reliable classification decision result.

[0032] This invention effectively addresses the shortcomings of random computation in high-precision decision-making by incorporating a miniature binary calibration coprocessor. The miniature binary calibration coprocessor provides 16-bit or 32-bit fixed-point / half-precision floating-point arithmetic capabilities to ensure the high reliability of the final decision made by the binary neural network model. Simultaneously, the integrated pulse counting-to-binary conversion module and decision unit (including a calibration lookup table) enable it to quickly and efficiently take over the intermediate results of random computation after the termination of early decisions, completing classification confidence calibration and achieving a perfect heterogeneous fusion of accuracy and energy efficiency.

[0033] Furthermore, the edge AI inference engine is a software control core deployed on the edge AI chip, specifically: loading the binary neural network model from memory into the heterogeneous neural computing core, and mapping different level operations to the random computation neural convolution feature extractor and the micro binary calibration coprocessor; Receive input data from the sensor and format the input data into an input format suitable for processing by the random computation neural convolution feature extractor; During the execution of the edge AI chip control method, the edge AI inference engine acts as a high-level controller, responsible for starting the random pulse stream analyzer and coordinating the switching of data and control flow between the random computation neural convolution feature extractor and the micro binary calibration coprocessor upon receiving an early decision termination signal.

[0034] During the process of loading the binary neural network model from memory to the heterogeneous core, the edge AI inference engine will use a heterogeneous task allocation algorithm for hierarchical mapping. Specifically, binary convolutional layers with high computational cost and relatively low accuracy requirements (such as feature extraction layers) are mapped to randomized neural convolutional feature extractors; while binary fully connected layers with low computational cost and high accuracy requirements (such as final decision layers) are mapped to micro binary calibration coprocessors.

[0035] After receiving input data, the edge AI inference engine performs data preprocessing steps, including: normalizing the original input data (e.g., scaling it to the (0, 1) range) and performing bit-width quantization to ensure that the input data format matches the input standard of the random bit stream generator.

[0036] During the execution of the edge AI chip control method, the edge AI inference engine acts as a high-level controller, and the coordination mechanism is implemented by responding to hardware interrupt signals issued by the chip controller. When an early decision termination signal is received, the edge AI inference engine performs a context switching operation, immediately suspends the software task scheduling of the random computing core, and synchronously starts the task of the binary computing coprocessor, thereby ensuring real-time, low-latency switching of data and control flow.

[0037] Furthermore, the edge AI chip control method has the architectural features of distributed random pulses: The distributed random pulse architecture is characterized by the collaborative work and task partitioning between two heterogeneous cores—a random computation neural convolutional feature extractor and a micro binary calibration coprocessor—within a single chip. Specifically, the edge AI chip control method divides a binary neural network model into subtasks, which are processed in parallel by the random computation neural convolutional feature extractor cores of multiple edge AI chips within the network. A pulse mechanism is used to achieve data transmission and aggregation of computation results between nodes. This distributed pulse mechanism inherently possesses advantages in fault tolerance and low bandwidth requirements, further enhancing the robustness and scalability of the entire edge computing system.

[0038] This invention utilizes an edge AI inference engine as the advanced software control core to achieve efficient and intelligent management of heterogeneous hardware resources. Based on a heterogeneous task allocation algorithm, this engine optimally maps BNN model tasks (such as computationally intensive convolutional layers to random computing cores, and high-precision fully connected layers to micro binary calibration coprocessors), ensuring overall computational efficiency. Simultaneously, it performs data preprocessing (normalization / quantization) to adapt to the random computing cores and achieves real-time, low-latency context switching between random computing and binary cores by responding to hardware interrupt signals, significantly improving the real-time responsiveness and control precision of the heterogeneous computing system.

[0039] Furthermore, the binary neural network model includes a binary convolutional layer and a binary fully connected layer. The binary convolutional layer is used to perform feature extraction on the input data, and the binary fully connected layer is used to perform classification on the extracted features.

[0040] The binary neural network model employs a binary quantization technique, restricting both the weight parameters and activation values ​​in the model to binary values. Specifically, the weight parameters and activation values ​​are quantized using a sign function, taking values ​​of either positive 1 or negative 1, to ensure that the model can be efficiently deployed on a stochastic computation neural convolutional feature extractor and a miniature binary calibration coprocessor.

[0041] The output of the binarized convolutional layer is a feature map in the form of pulse counts. This count result is then converted and used as the input to the binarized fully connected layer. The bit width of the input data of the binarized fully connected layer (i.e., the feature map precision) must match the bit width of the high-precision arithmetic logic unit used by the micro binary calibration coprocessor to ensure the accuracy of the classification process.

[0042] The binarized convolutional layer is mainly used to extract low-level and mid-level statistical features of the original input data; the binarized fully connected layer is used to combine and weight these features, and finally output the classification or regression decision results.

[0043] The training process of the binary neural network model incorporates real physical noise features collected by the on-chip noise representation module as a regularization term into the model's loss function. This PVT-aware model training enables the binary neural network model deployed on the edge AI chip to adapt to and "utilize" the non-ideal physical characteristics prevalent in nanoscale SoCs. The training result optimizes the binary boundaries of model weights and activation values, enhancing the model's inference reliability and generalization ability under harsh real-world operating environments.

[0044] This invention employs a binary neural network model (BNN), which rigorously quantizes weights and activation values ​​using a sign function. This significantly simplifies model complexity, ensuring minimal storage and deployment of the model on edge AI chips. Simultaneously, the characteristics of BNNs are highly compatible with stochastic computation neural convolutional feature extractors, enabling computationally intensive convolutional layers to be efficiently implemented using low-power logic AND gates. This model-hardware co-design ensures that the system can minimize memory footprint and hardware multiplier requirements while maintaining high-accuracy classification.

[0045] A binary neural network model is loaded into the heterogeneous neural computing core by an edge AI inference engine. The edge AI inference engine executes a static mapping task allocation algorithm: mapping all binary convolutional layers to a randomly computed neural convolutional feature extractor; mapping all binary fully connected layers and the final classification decision layer to a micro binary calibration coprocessor. This mapping process is implemented by modifying the control flow instruction set of the inference engine.

[0046] Furthermore, the specific method for generating the random pulse stream includes: Within the random computation neural convolution feature extractor, a random number generator is configured to generate a random bit sequence with a uniform distribution; the input data of the binary neural network model is normalized to obtain an input value between 0 and 1; a digital comparator is used to compare the input value with the random bit sequence output by the random number generator bit by bit. The output pulse is 1 only when the random value is less than or equal to the input value; otherwise, the output non-pulse is 0. By repeating the above comparison process, a random pulse stream with a pulse density proportional to the input value is generated, and the random pulse stream is used as the computational input of the random computational neural convolution feature extractor.

[0047] After the input data of the binary neural network model is normalized, the resulting input value, which is between 0 and 1, must have a bit width (e.g., 8 bits, 12 bits, or 16 bits) that matches the bit width of the random bit sequence output by the random number generator. This ensures that the bit-by-bit comparison of the digital comparator can be performed accurately. The choice of bit width is based on the trade-off between chip area and accuracy in resource-constrained networks.

[0048] The digital comparator preferably employs a low-power bit-by-bit comparison circuit or a pulse-width-based comparator to simplify hardware complexity. The digital comparator is responsible for rapidly comparing the input deterministic binary value with a random sequence and outputting a random pulse (1) or a non-pulse (0) in each clock cycle based on the comparison result.

[0049] The random number generator generates a random bit sequence whose randomness meets the low correlation requirement, that is, the absolute value of the cross-correlation coefficient between adjacent random bit sequences should be less than a preset 0.1. The structural parameters of the random number generator (e.g., feedback polynomial, register length) need to be specifically designed according to the bit width of the input data to ensure that low correlation can be maintained under different bit widths.

[0050] This invention achieves a balance between low power consumption and high precision through an optimized random pulse stream generation method. By normalizing and bit-width quantizing the input data, and employing a low-power bit-by-bit comparison circuit to compare the random number with the input value, the power consumption of traditional high-precision multipliers is avoided. Simultaneously, by constraining the low correlation of the random bit sequence and the consistency between the input data bit width and the random number bit width, the statistical density of the generated random pulse stream is ensured to accurately and reliably reflect the input value, providing a stable and efficient computational input for a random computation neural convolution feature extractor.

[0051] Furthermore, such as Figure 3 As shown, the steps for starting the random pulse stream analyzer and monitoring the statistical confidence level of the random pulse stream in real time include: During the computation process, the random pulse stream analyzer continuously accumulates the current results of the random pulse stream output by the random computation neural convolution feature extractor to obtain a cumulative result; it tracks the total number of pulses processed since the start of the computation in real time; based on the cumulative result and the total number of pulses, it calculates the current statistical confidence level. The calculated statistical confidence level is compared with a preset confidence threshold; when the statistical confidence level is less than or equal to the preset threshold, the random pulse stream analyzer sends an early decision termination signal to the chip controller.

[0052] The statistical confidence level is calculated based on the statistical properties of Bernoulli trials, by calculating the error margin of the current cumulative results. To characterize. The error margin The calculation is based on the statistical properties of the binomial distribution, and its approximate value is... Compared with the total number of pulses processed It is inversely proportional to the square root. The random pulse flow analyzer uses a hardware lookup table to quickly calculate the error margin. Approximate value.

[0053] The statistical confidence level is calculated based on the following method: During the pulse counting process of the random pulse stream, the output of each pulse follows a Bernoulli distribution, and its expected value is the input value p (between 0 and 1). When the total number of processed pulses is... In this case, the cumulative results follow a binomial distribution. .

[0054] According to the central limit theorem, when Large enough (usually) When the binomial distribution is such that it approximates a normal distribution, its mean is 1 / 2. .

[0055] The random pulse flow analyzer uses a hardware approximation circuit or a lookup table to calculate the error margin in real time. The error margin It decreases as the total number of pulses L processed increases.

[0056] The confidence threshold This is directly related to the minimum acceptable classification accuracy of the binary neural network model. This is a pre-defined maximum permissible error value, determined through system-level performance analysis before chip deployment and stored in the chip control register. When the calculated error margin... Less than or equal to the When the calculation results have converged to an acceptable level of accuracy, the random pulse stream analyzer sends an early decision termination signal.

[0057] The confidence threshold The correspondence between the minimum acceptable classification accuracy of the binary neural network model and the target classification accuracy is as follows: if the target classification accuracy is... (e.g., 0.95), then according to the offline performance evaluation of the present invention (verified by Monte Carlo simulation or test set), it is determined that the inference accuracy is not lower than Maximum allowable error margin . Set as 80% is allocated to provide a safety margin. For example, for a typical BNN model, if... =0.95, then after offline evaluation, we get =0.08, therefore =0.064.

[0058] To ensure real-time performance, the cumulative sum calculation logic of the random pulse stream analyzer is designed to be synchronized with the pulse calculation of the random computation neural convolution feature extractor to avoid introducing additional control delays.

[0059] This invention innovatively introduces a random pulse flow analyzer, achieving intelligent and adaptive control of the computation process. It utilizes real-time error margin based on the statistical characteristics of Bernoulli's tests. The analyzer can accurately determine the convergence state of the inference results of the binary neural network model. When the error margin... When the value falls below a preset threshold, an early decision termination is immediately triggered, dynamically reducing the computational latency to the theoretically shortest time required to achieve minimum accuracy. This real-time synchronous monitoring and hardware approximation calculation minimizes redundant computations and significantly improves the energy efficiency of edge AI chips, which is a key guarantee for achieving high efficiency and energy saving in resource-constrained networks.

[0060] Furthermore, the specific execution steps of the early decision termination mechanism include: the chip controller receiving an early decision termination signal sent from the random pulse stream analyzer; and immediately sending an interrupt command to the random computation neural convolution feature extractor to stop all pulse computations and pulse stream generation that it is currently performing; The pulse counting unit is activated to quickly convert the pulse results accumulated by the random computation neural convolution feature extractor during the interruption into standard fixed-point binary values; the fixed-point binary values ​​are used as intermediate results and routed to the input interface of the micro binary calibration coprocessor through the edge AI inference engine. The micro binary calibration coprocessor is activated to perform classification confidence calibration.

[0061] The random pulse stream analyzer uses a dedicated hardware state machine to manage confidence level determination and signal transmission. When the calculated error margin... Less than or equal to At this time, the state machine generates a single-pulse early decision termination signal, which is connected to the interrupt input port of the chip controller.

[0062] After receiving the early decision termination signal, the chip controller will, on the next common clock edge ( Upon arrival, a clock gating instruction `gating_cmd` is immediately sent to the pulse calculation array and the random bit stream generator. This instruction is ANDed with the operating clock of the pulse calculation array via an AND gate. AND, completely shut down within one clock cycle. This immediately stops all pulse calculations.

[0063] Simultaneously, the chip controller activates the snapshot circuit of the pulse counting unit. This snapshot circuit latches the accumulated pulse results of the pulse calculation array at the moment the gating takes effect into a 16-bit snapshot register. This snapshot process is executed atomically at the hardware level, ensuring the consistency of the read values, and its execution time does not exceed two clock cycles.

[0064] The 16-bit fixed-point value in the snapshot register is directly connected to the input interface of the micro binary calibration coprocessor via the on-chip hardware interconnect bus. This bus uses a synchronous handshake protocol, has a bus width of 16 bits, and a data transmission delay of one clock cycle.

[0065] When snapshot data arrives at the input interface of the micro binary calibration coprocessor via the interconnect bus, the input buffer of the micro binary calibration coprocessor is automatically filled, and a data_ready signal is sent to its core logic. Upon receiving data_ready, the micro binary calibration coprocessor, in the next operating clock cycle (… The high-precision fully connected layer calculation is executed at the start of the cycle.

[0066] The total latency from the early decision termination signal to the start of computation by the micro binary calibration coprocessor is controlled to within 5 seconds. During the period, assuming =2×max( frequency, The frequency corresponds to a switching time of approximately 50 nanoseconds at a 100MHz operating frequency for resource-constrained devices (such as wearable devices). This switching latency is negligible compared to the fully connected layer computation time of a micro binary calibration coprocessor, which is typically on the order of microseconds.

[0067] If the inference engine needs to detect early decision termination events at the software layer, the chip controller achieves this by writing a flag (early_stop_flag) to the inference engine's status register. The inference engine detects this flag through polling or interrupts, and performs corresponding statistical counting or logging. However, this subsequent software-level processing does not block the hardware-level data flow; that is, the micro binary calibration coprocessor can still perform computations in parallel.

[0068] This invention achieves microsecond-level real-time control and maximum dynamic power saving through an optimized early decision termination mechanism. The chip controller utilizes clock-gated interrupt instructions to instantly stop the random computation core, avoiding redundant power consumption. Simultaneously, by integrating the pulse counting unit with the internal counter and directly routing data using the hardware interconnect bus, zero-latency data reading and rapid hardware-level switching are guaranteed, successfully translating the energy efficiency advantages of the random computation core into significant performance improvements in real-time responsiveness and overall latency for the entire heterogeneous system.

[0069] This invention combines a randomized neural convolution feature extractor with a miniature binary calibration coprocessor to realize a heterogeneous neural computing core, ensuring low-power feature extraction while maintaining final decision accuracy. The core innovation lies in introducing a random pulse stream analyzer to monitor the statistical confidence level of the computation in real time, triggering an early decision termination mechanism based on this confidence level, enabling the system to dynamically stop redundant computations. This significantly reduces overall computational latency and dynamic power consumption, resolving the inherent contradiction between energy efficiency and real-time responsiveness in resource-constrained networks.

[0070] Example 2 This embodiment describes in detail the implementation of the present invention on a wearable heart rate monitoring device (belonging to a resource-constrained network) in conjunction with a specific application scenario, highlighting the real-time control process of early decision termination and heterogeneous data switching.

[0071] Wearable devices collect users' electrocardiogram (ECG) data in real time and use a lightweight binary neural network (BNN) model for real-time classification of heart rate abnormalities. Due to battery capacity limitations, the system has extremely high requirements for power consumption and response speed.

[0072] The edge AI inference engine loads a pre-trained BNN model, which contains 4 binarized convolutional layers and 2 binarized fully connected layers.

[0073] The heterogeneous task allocation algorithm maps the four most computationally intensive binary convolutional layers to a randomized neural convolutional feature extractor to perform feature extraction, because this task is highly robust to randomness and requires extremely low power consumption.

[0074] The last two binarized fully connected layers are mapped to a micro binary calibration coprocessor to ensure the accuracy of the final classification result.

[0075] After receiving the input data, the edge AI inference engine normalizes it (scales it to...). (Interval) and 8-bit quantization. A random bitstream generator (implemented using LFSR) within the core of the random computation neural convolution feature extractor generates an 8-bit random sequence. A digital comparator compares the normalized input value bit by bit with the random sequence, generating a random pulse stream with a pulse density proportional to the input value. This pulse stream drives the pulse computation array.

[0076] The random pulse stream analyzer monitors the computation of the core of the random computation neural convolution feature extractor in real time. Its internal hardware approximation circuit continuously tracks the total number of pulses processed. And calculate the current error margin. Preset confidence threshold Configured in the chip control register, this threshold corresponds to the minimum acceptable accuracy of 95% for the heart rate classification task. When this occurs, it indicates that the classification features have converged. The random pulse stream analyzer immediately sends an early decision termination signal to the chip controller.

[0077] The chip controller responds to the signal within microseconds and immediately sends a clock gating signal to the pulse computing array and random bitstream generator of the random computation neural convolution feature extractor core, instantly stopping their operation and thus achieving dynamic power saving.

[0078] The chip controller directly reads the accumulated pulse results (i.e. feature maps) in the low-power counter inside the core of the random computation neural convolution feature extractor via a fast hardware bus, and converts them into 16-bit fixed-point binary values.

[0079] This 16-bit fixed-point value serves as an intermediate result, bypassing the software layer of the edge AI inference engine. It is directly routed to the input interface of the micro binary calibration coprocessor via the chip's internal hardware interconnect bus, ensuring zero-latency switching.

[0080] The miniature binary calibration coprocessor is activated, and its high-precision arithmetic logic unit performs the final fully connected layer calculation. The decision unit uses a calibration lookup table to complete the final classification confidence calibration and outputs a highly reliable heart rate abnormality classification result.

[0081] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A chip control method for a distributed random pulse for a resource-constrained network, characterized by, Comprise: A heterogeneous neural computing core is configured in the edge AI chip, and the heterogeneous neural computing core comprises a stochastic computing neural convolution feature extractor and a micro binary calibration coprocessor; A binary neural network model is loaded by an edge AI inference engine to the heterogeneous neural computing core; The stochastic computing neural convolution feature extractor is used for stochastic pulse computing on input data, and a stochastic pulse stream is generated; A stochastic pulse stream analyzer is started to monitor statistical confidence of the stochastic pulse stream in real time; When the stochastic pulse stream analyzer determines that the statistical confidence is less than or equal to a preset threshold, an early decision termination mechanism is triggered, the calculation of the stochastic computing neural convolution feature extractor is stopped in advance, and the calculation result is transferred to the micro binary calibration coprocessor for decision calibration.

2. The method of claim 1, wherein, The stochastic computing neural convolution feature extractor specifically comprises a stochastic bit stream generator and a pulse computing array: The stochastic bit stream generator is used for converting input data into a corresponding stochastic pulse stream; The pulse computing array is composed of n logic gate arrays, and the logic gate arrays are used to replace traditional binary multipliers, wherein product accumulation operation is implemented by logical AND gate multiplication, and the output density of the pulse stream is accumulated by an adder and / or a counter to perform convolution operation in the binary neural network model; The input data comprises input feature maps and weight parameters in the binary neural network model.

3. The method of claim 1, wherein, The micro binary calibration coprocessor specifically comprises a high-precision arithmetic logic unit, a binary input / output interface and a decision unit: The high-precision arithmetic logic unit is used to perform traditional deterministic binary operation, and is used to process application tasks with classification accuracy requirement not less than 95%; The binary input / output interface is used to receive the pulse computing result output in advance by the stochastic computing neural convolution feature extractor through the early decision termination mechanism, and output the final calibration decision result in the form of standard binary; The decision unit is used to execute the final decision layer of the binary neural network model and the classification confidence calibration algorithm.

4. The method of claim 1, wherein, The edge AI inference engine is a software control core deployed on the edge AI chip, specifically: The binary neural network model is loaded from a memory to the heterogeneous neural computing core, and different level operations are mapped to the stochastic computing neural convolution feature extractor and the micro binary calibration coprocessor; Input data from a sensor is received, and the input data is formatted into an input format suitable for processing by the stochastic computing neural convolution feature extractor; During execution of the edge AI chip control method, the edge AI inference engine acts as a high-level controller, is responsible for starting the stochastic pulse stream analyzer, and is responsible for coordinating switching of data and control flow of the stochastic computing neural convolution feature extractor and the micro binary calibration coprocessor when receiving an early decision termination signal.

5. The method of claim 1, wherein: The binary neural network model comprises a binary convolution layer and a binary fully connected layer, the binary convolution layer is used to perform feature extraction on input data, and the binary fully connected layer is used to perform classification on the extracted features.

6. The method of claim 1, wherein, The generation method of the stochastic pulse stream comprises: In the random computing neural convolution feature extractor, a random number generator is configured to generate a random bit sequence with uniform distribution; the input data of the binary neural network model is normalized to obtain an input value between 0 and 1; a digital comparator is used to compare the input value with the random bit sequence output by the random number generator bit by bit; Only when the random number value ≤ the input value, the output pulse is 1, otherwise the output non-pulse is 0; by repeating the above comparison process, a random pulse stream with pulse density proportional to the input value is generated, which is used as the calculation input of the random computing neural convolution feature extractor.

7. The method of claim 1, wherein, The operation steps of starting the random pulse stream analyzer to monitor the statistical confidence of the random pulse stream in real time include: During the calculation process, the random pulse stream analyzer continuously accumulates the current results of the random pulse stream output by the random computing neural convolution feature extractor to obtain accumulated results; it real-time tracks the total number of pulses processed since the start of the calculation; based on the accumulated results and the total number of pulses, the current statistical confidence is calculated; the calculated statistical confidence is compared with the pre-set confidence threshold; when the statistical confidence ≤ the pre-set threshold, the random pulse stream analyzer sends an early decision termination signal to the chip controller.

8. The method of claim 7, wherein, The specific execution steps of the early decision termination mechanism include: the chip controller receives the early decision termination signal sent by the random pulse stream analyzer; and immediately sends an interrupt instruction to the random computing neural convolution feature extractor to stop all pulse calculations and pulse stream generation currently being performed; Start the pulse counting unit to quickly convert the accumulated pulse results of the random computing neural convolution feature extractor at the time of interruption into standard fixed-point binary values; the fixed-point binary values are used as intermediate results, which are routed to the input interface of the micro binary calibration coprocessor through the edge AI inference engine; Activate the micro binary calibration coprocessor to calibrate the classification confidence.

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