Display control method, time schedule controller and display panel
By acquiring voltage values during the power-on and power-off cycles of the display panel and adjusting the clock drive signal and data output timing, synchronous short-circuiting of the data signal output terminal and the common voltage output terminal is achieved, thus solving the screen flickering problem during power-on and power-off and improving the adaptability and stability of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-30
- Publication Date
- 2026-03-27
AI Technical Summary
The screen flickering phenomenon caused by the voltage difference between the reference voltage and the data signal voltage during power-on and power-off cannot fully adapt to the needs of different machine modules, resulting in occasional abnormal phenomena.
By acquiring the voltage value output by the power management circuit, the target time difference is determined, and the clock drive signal and data output timing are adjusted according to the time difference to ensure that the data signal output waveform is synchronized with the common voltage, thereby achieving a short circuit between the data signal output terminal and the common voltage output terminal and eliminating the voltage difference.
It effectively reduces screen flickering when the display panel is turned on and off, improves the adaptability of the display panel, and reduces abnormal phenomena caused by differences in the overall machine core.
Smart Images
Figure CN121747484A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, specifically relating to a display control method, a timing controller, and a display panel. Background Technology
[0002] With the development of display technology, the application range of display panels is becoming increasingly wide, and the types of terminal devices they are equipped with are also different. However, due to the differences in the overall mechanism of different devices, the debugging of display panel products may not be able to fully adapt to the requirements of various mechanisms, and there may be a probability of abnormal phenomena when the same display panel is paired with different overall devices.
[0003] When the display panel is powered on or off, the front-end system-on-chip (SOC) outputs a differential data signal, triggering the integrated chip of the display panel to enter the working state and output a reference voltage. When the voltage difference between the reference voltage and the data signal voltage exceeds a certain threshold, the liquid crystal molecules will deflect, and the light emitted by the backlight module will penetrate the liquid crystal layer, resulting in screen flickering.
[0004] Therefore, how to effectively improve the screen flickering phenomenon during power-on and power-off is a problem that this application urgently needs to solve. Summary of the Invention
[0005] This application provides a display control method, a timing controller, and a display panel, which effectively improves the screen flickering phenomenon during power-on and power-off of the display panel.
[0006] In a first aspect, this application provides a display control method applied to a timing controller of a display panel. The display panel further includes a data driving circuit, a gate driving circuit, and a power management circuit. The control method includes:
[0007] During the power-on or power-off process of the display panel, the current startup voltage value and the current common voltage value output by the power management circuit are obtained; When the current startup voltage is an effective voltage and the current common voltage is an invalid voltage, obtain the target time difference between the current common voltage value and the effective voltage value. Adjust the clock drive signal according to the target time difference, so that the gate drive circuit opens the pixel row in the display panel with a delay according to the clock drive signal; or / and adjust the data output timing according to the target time difference, so that the data drive circuit outputs the data signal with a delay according to the data output timing.
[0008] Optionally, effective voltage refers to a high-level state, and ineffective voltage refers to a low-level state; When the current startup voltage is an effective voltage and the current common voltage is an invalid voltage, obtain the target time difference between the current common voltage value and the effective voltage, including: Acquire detection signals and frame period signals; wherein, the detection signals include high-level states and low-level states; The first target time difference is determined based on the detected signal, the frame period signal, and the preset time threshold; Based on the first target time difference, the preset time length table is called to obtain the target time difference.
[0009] Optionally, the frame period signal refers to one frame period of the display panel; Based on the detected signal, frame period signal, and preset time threshold, the first target time difference is determined, including: When the detected signal is in a low-level state, the first time difference is obtained; where the first time difference refers to the time difference between when the frame period signal is in a high-level state and when the detected signal is in a low-level state. When the first time difference is less than a preset time threshold, the first time difference is determined as the first target time difference.
[0010] Optionally, determining the first target time difference based on the detected signal, the frame period signal, and a preset time threshold further includes: When the first time difference is greater than a preset time threshold, the next frame period signal is acquired; The time difference between when the frame period signal is at a high level and when the frame period signal of the next frame is at a high level is defined as the first target time difference.
[0011] Optionally, based on the first target time difference, a preset time length table is called to obtain the target time difference, including: The target time difference corresponding to the first target time difference is determined by using a preset time length table; Adjust the clock drive signal and / or data output timing according to the target time difference.
[0012] Optionally, adjusting the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of pixel rows in the display panel according to the clock drive signal, includes: When the time difference is the first time difference and both the detection signal and the frame period signal are in a high-level state, the clock drive signal is set to the target state; the target state refers to the clock drive signal being in a low-level state. Until the detected signal is in a low-level state.
[0013] Optionally, adjusting the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of pixel rows in the display panel according to the clock drive signal, further includes: When the detection signal is at a high level and the frame period signal is at a high level, the clock drive signal is set to the target state; Until the next frame period signal is in a high-level state.
[0014] Optionally, the method further includes: Adjust the clock drive signal according to the target time difference, and / or adjust the data output timing according to the target time difference. Then, short-circuit the common voltage output terminal and the data signal output terminal.
[0015] Secondly, this application provides a timing controller, which includes: The detection module is used to acquire the current startup voltage value and the current common voltage value output by the power management circuit during the power-on or power-off process of the display panel. The algorithm control module is used to obtain the target time difference between the current starting voltage value and the current common voltage value when the current starting voltage value is an effective voltage and the current common voltage value is an invalid voltage. The timing control module is used to adjust the clock drive signal according to the target time difference, so that the gate drive circuit opens the pixel row in the display panel with a delay according to the clock drive signal; or / and, to adjust the data output timing according to the target time difference, so that the data drive circuit outputs the data signal with a delay according to the data output timing.
[0016] Thirdly, this application also provides a display panel, the display panel comprising: The invention includes a data driving circuit, a gate driving circuit, a power management circuit, and a timing controller as described in the second aspect. The data drive circuit and the timing controller are connected in communication. The timing controller is used to send data output timing to the data drive circuit so that the data drive circuit outputs data signals. The gate drive circuit is communicatively connected to the timing controller, which sends a clock drive signal to the gate drive circuit to open the pixel row. The power management circuit is communicatively connected to the timing controller and is used to provide the timing controller with startup voltage and common voltage.
[0017] Fourthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor; The memory stores the instructions that the computer executes; When the processor executes the computer execution instructions stored in the memory, it is used to implement a display control method for the first aspect of the invention.
[0018] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement a display control method according to the first aspect of the invention.
[0019] In a sixth aspect, this application provides a computer program product, including a computer program, which, when executed by a processor, is used to implement a display control method according to the first aspect of the invention.
[0020] This application obtains the output voltage value of the display panel when it is powered on and off, and determines the required delay timing based on the voltage value. This facilitates the synchronization of the data signal output waveform with the common voltage during power-on and power-off, making the short-circuit timing more accurate and effectively reducing screen flicker. After the system-on-a-chip outputs the signal, the target time difference is determined based on the effective and ineffective states of the startup voltage and the common voltage. This allows for accurate comparison of signal timing and facilitates subsequent adjustment of the short-circuit. The target time difference allows for adjustment of the clock drive signal and data output timing, providing two timing adjustment methods: adjusting a single timing sequence or adjusting both timing sequences simultaneously, which helps improve the screen flickering phenomenon during power-on and power-off. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0022] Figure 1 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 1 ; Figure 2 This application provides a schematic diagram of the power-on timing of a display product. Figure 3 This is a schematic diagram of the power-on waveform without short circuit provided in an embodiment of this application; Figure 4 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 2 ; Figure 5 This is a schematic diagram of the original clock output timing of the timing controller provided in an embodiment of this application; Figure 6 This is a timing diagram of the delayed clock output of the timing controller provided in an embodiment of this application; Figure 7 This is a schematic diagram of the signal width provided in an embodiment of this application; Figure 8 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 3 ; Figure 9 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 4 ; Figure 10 This is a schematic diagram of the system architecture of the timing controller provided in the embodiments of this application; Figure 11 This is a schematic diagram of the system architecture of the display panel provided in the embodiments of this application; Figure 12 This is a schematic diagram of the structure of the electronic device hardware provided in the embodiments of this application.
[0023] Explanation of reference numerals in the attached figures: 210. Vin voltage; 220. Common voltage; 230. Gate high level; 240. Gate low level; 250. Start-up voltage; 510, STV signal; 520, Clock drive signal (CK signal); 530, Detection signal; 710. Data signal; 720. Data output timing; 730. CK signal; 1000, Timing Controller; 1010, Detection Module; 1020, Algorithm Control Module; 1030, Timing Control Module; 1040, Built-in Register; 1110. Data drive circuit; 1120. Gate drive circuit; 1130. Power supply integrated circuit; 1131. Start-up voltage divider module; 1132. Common voltage divider module; 1133. First resistor; 1134. Second resistor; 1135. Third resistor; 1136. Fourth resistor; 1210. Processor; 1220. Memory; 1230. Communication components; 1240. Bus. Detailed Implementation
[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.
[0025] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.
[0026] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.
[0027] Front-end system-on-a-chip (SoC): A front-end SoC is a highly integrated dedicated chip used to perform the core functions of preliminary processing such as signal reception and format conversion in a display system.
[0028] Detection signal: In this application, the detection signal refers to the signal indicating whether the common voltage output terminal and the data signal output terminal are shorted. When the common voltage output terminal and the data signal output terminal are shorted, the detection signal is at a low level; when the common voltage output terminal and the data signal output terminal are not shorted, the detection signal is at a high level.
[0029] As display technology and industrial technology continue to iterate and upgrade, the application scope of display products is becoming wider and wider, and the corresponding terminal device types are also different, with different display product requirements for each type of terminal device.
[0030] Given that different terminal devices are equipped with different integrated circuits, the debugging of display products cannot fully meet the requirements of every integrated circuit. There is a possibility that the same display panel may exhibit occasional abnormal phenomena when paired with different integrated circuits.
[0031] When the display panel is powered on or off, the front-end SOC inputs differential data signals to the display panel, the power management circuit outputs a reference voltage as required, and the drive circuit also outputs data signals. When the voltage difference between the reference voltage and the data signal output by the drive circuit exceeds a certain threshold, the liquid crystal molecules will deflect accordingly, and the light source emitted by the backlight module will pass through the liquid crystal layer, resulting in screen flickering.
[0032] To avoid this phenomenon, the POF (Panel Orientation Function) is used to force a short circuit between the data signal output terminal and the common voltage output terminal, eliminating the instantaneous voltage difference between them, preventing abnormal liquid crystal reversal or residual charge in the pixels, thereby avoiding screen flicker.
[0033] When the timing of the data signal output is consistent with the power-on timing of the common voltage, a forced short circuit is necessary to eliminate the voltage difference between them and reduce screen flickering. However, when the timing of the differential data signal and power signal output from the front-end SOC changes, the timing of the signal received by its timing controller is inconsistent with the original setting, which may result in a time difference and voltage difference between the common voltage and the data signal output, causing screen flickering. Furthermore, the PCBA (Printed Circuit Board Assembly) generates heat, with temperatures consistently maintained between 50 and 85°C. Prolonged exposure to high temperatures will cause aging and impedance changes in the circuitry. Even if the voltage timing remains unchanged, the actual time received by the drive circuit will be delayed, leading to screen flickering.
[0034] Therefore, how to effectively improve the screen flickering phenomenon during power-on and power-off is a problem that this application urgently needs to solve.
[0035] Since POF functionality is a commonly used technology, this application provides a display control method, a timing controller, and a display panel based on POF functionality, which can be used in the field of display technology and are intended to address the above-mentioned technical problems.
[0036] This application provides a display control method, specifically including the following embodiments: Figure 1 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 1 ,like Figure 1 As shown, the display control method is applied to the timing controller of the display panel. The display panel also includes a data driving circuit, a gate driving circuit, and a power management circuit. Therefore, the display control method specifically includes: S101. During the power-on or power-off process of the display panel, obtain the current startup voltage value and the current common voltage value output by the power management circuit.
[0037] Specifically, in this application, the common voltage is the reference voltage.
[0038] During the power-on sequence of the display panel, the front-end SOC provides power to the display panel. Upon receiving the input power voltage, the power management circuit begins operation and outputs a common voltage and various other voltages according to the settings. These various voltages output by the power management circuit include the voltage supplied to the drive circuit.
[0039] Figure 2 This application provides a schematic diagram of the power-on timing of a display product, such as... Figure 2As shown, the front-end SOC inputs are Vin voltage 210 (Input Voltage), the power management circuit outputs common voltage 220Vcom (Common Voltage), gate high level 230VGH (Gate High Voltage), gate low level 240VGL (Gate Low Voltage), and startup voltage 250VDD (Device Drain Voltage).
[0040] The front-end SOC inputs differential data signals and power signals to the timing controller of the display panel. The timing controller then sends the differential data signals to the drive circuit in a specific timing sequence, and the drive circuit outputs the data signals. The time interval from power-on to data signal output is typically 50ms.
[0041] However, when the data signal begins to be output, the timing controller and power management circuits both undergo a reset action, resetting to their original states. Therefore, when the data signal begins to be output, a black screen will be displayed.
[0042] Figure 3 This is a schematic diagram of the power-on unshort-circuited waveform provided in an embodiment of this application. Figure 3 As shown, the data signal is output first, followed by the common voltage. After the front-end SOC provides Vin voltage to the display panel, the data signal begins to be output. There is a time difference between the common voltage Vcom output by the power management circuit and the data signal, and it is not shorted during power-on.
[0043] During this period, when the voltage difference between the common voltage and the data signal voltage exceeds the voltage value, the liquid crystal will deflect, the light source will shine through, and a flickering phenomenon will occur.
[0044] During the power-on or power-off process of the display panel, the current startup voltage and current common voltage value output by the power management circuit under the current environment are obtained.
[0045] Since the power-on and power-off processes are both part of a single workflow, this application will use power-on as an example for explanation.
[0046] S102. When the current starting voltage value is an effective voltage and the current common voltage value is an invalid voltage, obtain the target time difference between the current common voltage value and the invalid voltage value.
[0047] Specifically, effective voltage refers to a voltage that is in a high voltage state, while ineffective voltage refers to a voltage that is in a low voltage state.
[0048] When the current startup voltage is at a high level and the current common voltage is at a low level, the target time difference corresponding to the change from a low level to a high level of the current common voltage will be obtained.
[0049] The target time difference needs to be determined by a preset time length table.
[0050] Furthermore, when the current startup voltage value is at a high level, the current common voltage value is also at a high level, meaning that the common voltage is being output normally. This indicates that the drive circuit has enabled the POF function, shorting the data signal output terminal and the common voltage output terminal to avoid screen flickering.
[0051] S103. Adjust the clock drive signal according to the target time difference, so that the gate drive circuit opens the pixel row in the display panel with a delay according to the clock drive signal; or / and, adjust the data output timing according to the target time difference, so that the data drive circuit outputs the data signal with a delay according to the data output timing.
[0052] Specifically, the clock drive signal is the signal that drives the gate drive circuit. The data output timing signal is the signal that drives the data drive circuit.
[0053] The timing controller adjusts the clock drive signal according to the target time difference, so that the drive circuit opens the pixel row in the display panel with a delay according to the clock drive signal, and the drive circuit outputs a data signal.
[0054] Alternatively, the timing controller adjusts the data output timing according to the target time difference, so that the data drive circuit outputs data signals according to the data output timing.
[0055] Alternatively, the clock drive signal and data output timing can be adjusted simultaneously, so that the gate drive circuit opens the pixel row according to the clock drive circuit; at the same time, the data drive circuit outputs the data signal according to the data output timing under the opened pixel row.
[0056] At this time, the drive circuit will enable the POF function, short-circuiting the data signal output terminal and the common voltage output terminal to avoid screen flickering.
[0057] This application obtains the output voltage value of the display panel when it is powered on and off, and determines the required delay timing based on the voltage value. This facilitates the synchronization of the data signal output waveform with the common voltage during power-on and power-off, making the short-circuit timing more accurate and effectively reducing screen flicker. After the system-on-a-chip outputs the signal, the target time difference is determined based on the effective and ineffective states of the startup voltage and the common voltage. This allows for accurate comparison of signal timing and facilitates subsequent adjustment of the short-circuit. The target time difference allows for adjustment of the clock drive signal and data output timing, providing two timing adjustment methods: adjusting a single timing sequence or adjusting both timing sequences simultaneously, which helps improve the screen flickering phenomenon during power-on and power-off.
[0058] Figure 4 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 2 This embodiment is... Figure 1 Based on the embodiments, the display control method will be described in detail, such as... Figure 4 As shown, this embodiment provides a display control method, including: S401. During the power-on or power-off process of the display panel, obtain the current startup voltage value and the current common voltage value output by the power management circuit.
[0059] The principles of S401 and S101 are the same, so they will not be described again here.
[0060] S402, Acquire detection signals and frame period signals.
[0061] The detection signal includes a high-level state and a low-level state.
[0062] Specifically, effective voltage refers to a high-level state, and invalid voltage refers to a low-level state. When the current startup voltage is effective and the current common voltage is invalid, the target time difference between the current common voltage value and the invalid voltage value is obtained.
[0063] In this application, the detection signal is a signal indicating whether the data signal output terminal and the common voltage output terminal are short-circuited. When the current start-up voltage is an effective voltage and the common voltage value is an effective voltage, the detection signal is in an invalid state, i.e., in a low-level state, indicating that the data signal output terminal and the common voltage output terminal are short-circuited and no timing adjustment is required; when the current start-up voltage is an effective voltage and the common voltage value is an invalid voltage, the detection signal is in an effective state, i.e., in a high-level state, indicating that the data signal output terminal and the common voltage output terminal are not short-circuited and timing adjustment is required.
[0064] The frame period signal refers to one frame cycle of the display panel. When the frame period signal is active, it indicates the start of a frame cycle.
[0065] Figure 5 This is a schematic diagram of the original clock output timing of the timing controller provided in the embodiments of this application, as shown below. Figure 5 As shown, the frame period signal STV (Start Vertical Signal) 510 is in a high-level state, indicating the start of a frame period. At this time, the clock scan signal CK (Clock Signal) 520 is output according to the original setting. The detection signal 530 below remains in a low-level state because it is not detected.
[0066] Therefore, when timing adjustments are required, the detection signal and frame period signal in the current environment can be obtained.
[0067] It should be noted that when the detection signal is in a high-level state, it indicates that there is no short circuit, so the timing needs to be adjusted.
[0068] S403. When the detected signal is in a low-level state, obtain the first time difference.
[0069] The first time difference refers to the time difference between when the frame period signal is at a high level and when the detection signal is at a low level.
[0070] Specifically, the time difference of the first target is determined based on the detected signal, the frame period signal, and the preset time threshold.
[0071] When the detection signal changes from a high level to a low level, the time difference between the frame period signal changing from a high level to the detection signal changing to a low level is obtained.
[0072] When the first target time difference is less than the preset time threshold, execute S404; when the first target time difference is greater than the preset time threshold, execute S405 and S406.
[0073] S404. When the first time difference is less than the preset time threshold, the first time difference is determined as the first target time difference.
[0074] Specifically, the preset time threshold is usually 100%. .in, The calculation method is as follows
[0075] in, The number of complete frames displayed per second. This represents the total number of scan lines contained in a single frame.
[0076] When the first time difference is less than the preset time threshold, the first time difference obtained at this time is determined as the first target time difference.
[0077] Figure 6 A timing diagram of the delayed clock output of the timing controller provided in the embodiments of this application is shown below. Figure 6 As shown, the frame period signal STV (Start Vertical Signal) 510 is in a high-level state, indicating the start of a frame period. At this time, the clock drive signal CK (Clock Signal) 520 is output according to the original setting. The detection signal 530 below is pulled high because it detects that the data signal data terminal and the common voltage output terminal are not short-circuited, making it a high-level state. Figure 6 It is only shown that the time difference between the frame period signal STV signal 510 from a high level state to the detection signal 530 from a low level state is a preset time threshold. In the case of the above, other cases are not shown one by one, but the waveform diagram should be modified accordingly based on the text description.
[0078] like Figure 6 As shown, the time difference represented by the dashed line is a preset time threshold. If this threshold is determined, then the target time difference is determined accordingly. Figure 6 As shown, the clock drive signal CK signal 520 will be suppressed within the target time difference, causing it to be in a low-level state.
[0079] S405. When the first time difference is greater than the preset time threshold, acquire the next frame period signal.
[0080] Specifically, in the first time difference greater than At that time, the next frame period signal is obtained.
[0081] Until the next frame cycle signal is in a high-level state.
[0082] S406. The time difference between when the frame period signal is at a high level and when the frame period signal of the next frame is at a high level is determined as the first target time difference.
[0083] Specifically, the time difference between when the frame period signal is in a high-level state and when a positive period signal of a frame is in a high-level state is determined as the first target time difference.
[0084] S407. Determine the target time difference corresponding to the first target time difference by using a preset time length table.
[0085] Specifically, based on the first target time difference, a preset time length table is called to obtain the target time difference.
[0086] The preset time length table refers to the time during the experimental phase when controlling the common voltage output to create a time difference between the start-up voltage and the common voltage output, with corresponding time differences of 5ms, 10ms, 15ms, 20ms, up to 100ms. Based on each time difference, the target time difference *m* for the clock drive signal delay and the target time difference *n* for the data output timing delay are adjusted. This is then used to create a table, which is written to the internal register of the timing controller.
[0087] Table 1 shows the preset time lengths, as shown in Table 1 below:
[0088] Table 1 only shows the target time differences corresponding to several time differences, but it should not only include the target time differences mentioned above.
[0089] Based on the first target time difference, the preset time length table is called to determine the closest target time difference corresponding to the first target time difference.
[0090] It is important to note that since the timing of the delayed clock drive signal or delayed data output is determined based on the duration of its high-level signal, it cannot directly determine the delay time. Specifically, the high-level state of the CK signal has a longer duration than the high-level state of the data timing sequence. Figure 7 This is a schematic diagram of the signal width provided in the embodiments of this application, such as... Figure 7 As shown, data signal 710 is the bottom waveform; data output timing 720 is the middle waveform; and CK signal 730 is the top waveform.
[0091] like Figure 7 As shown, when the CK signal 730 is high, the timing controller can output multiple data output timings 720. The area indicated by the dashed line in the figure represents the time width of the CK signal 730 high level and the data output timing 720 high level.
[0092] However, only when the CK signal 730 is in a high-level state, the data output timing 720 is the actual data charging time from the falling edge of the last high-level state to the falling edge of the CK signal.
[0093] S408. Adjust the clock drive signal and / or data output timing according to the target time difference.
[0094] Specifically, based on the target time difference, the clock drive signal is delayed to the target time difference; or / and the data output timing is adjusted to the target time difference.
[0095] S409. Adjust the clock drive signal according to the target time difference, so that the gate drive circuit opens the pixel row in the display panel with a delay according to the clock drive signal; or / and, adjust the data output timing according to the target time difference, so that the data drive circuit outputs the data signal with a delay according to the data output timing.
[0096] Specifically, in coarse adjustment, that is, when only the clock drive signal is adjusted, the target time difference is m.
[0097] Based on the target time difference, the clock drive signal is delayed by the target time difference, so that after receiving the clock drive signal, the gate drive circuit opens the pixel row in the display panel according to the delay of the clock drive signal, and the data drive circuit outputs the data signal.
[0098] When fine-tuning is required, i.e. when the timing of data output needs to be adjusted, the target time difference is n.
[0099] Based on the target time difference, the data output timing is adjusted to delay the data output timing by the target time difference, so that the data driving circuit outputs the data signal after receiving the data output timing.
[0100] It should be noted that if the common voltage output terminal and the data signal output terminal are still not short-circuited after adjusting the clock drive signal, the data output timing needs to be adjusted again.
[0101] Based on the target timetable, adjust the clock drive signal and data output timing to enable the POF function of the drive circuit.
[0102] S410. Adjust the clock drive signal according to the target time difference, or / and adjust the data output timing according to the target time difference. Then, short-circuit the common voltage output terminal and the data signal output terminal.
[0103] Specifically, based on the target time difference, after delaying the timing of the clock drive signal and data output to the target time difference, the drive circuit will enable the POF function and short-circuit the common voltage output terminal and the data signal output terminal.
[0104] This application embodiment determines the target time difference by combining a preset time length table and time difference, making the timing delay time of the clock drive signal and data output more reasonable, effectively ensuring the timing consistency during short circuits, and effectively improving the screen flickering phenomenon during power-on and power-off; according to the combined control of the clock drive signal and data output timing, the timing during short circuits is made more stringent, facilitating subsequent short circuit processing.
[0105] Figure 8 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 3 , Figure 9 The diagram shown is a flowchart of a display control method provided in an embodiment of this application. Figure 4 This embodiment is... Figure 1 and Figure 4 Based on the embodiment, the step S409, which adjusts the clock drive signal according to the target time difference so that the gate drive circuit opens the pixel rows in the display panel with a delay according to the clock drive signal, will be described in detail, such as... Figure 4 As shown, it includes: After determining the target time difference, there are two methods for adjusting the clock drive signal: The first adjustment method: when the time difference does not exceed the preset time threshold.
[0106] S801, when the first target time difference is the first time difference and both the detection signal and the frame period signal are in a high-level state, the clock drive signal is set to the target state.
[0107] The target state refers to the state where the clock drive signal is low.
[0108] For reference Figure 6The clock drive signal CK signal 530 is in a low level state beyond the dotted line area when the first target time difference is the first time difference, that is, the first target time difference has not exceeded the preset time threshold.
[0109] When the detection signal is at a high level, the data signal output terminal and the common voltage output terminal are not short-circuited. The clock drive signal CK signal 530 is delayed to the target time difference. That is, within the target time difference, the clock drive signal CK signal 530 is suppressed and kept at a low level, so that the gate drive circuit does not open the pixel row of the display panel during the target time difference.
[0110] S802, until the detection signal is low.
[0111] The CK signal will no longer be suppressed until the detection signal is low, allowing it to be output according to the original settings.
[0112] The second adjustment method: when the time difference exceeds the preset time threshold.
[0113] S901. When the detection signal is at a high level and the frame period signal is at a high level, the clock drive signal is set to the target state.
[0114] Specifically, when the first time difference exceeds a preset time threshold, refer to Figure 6 The clock drive signal CK signal 530 in the circuit is suppressed and kept at a low level, that is, the gate drive circuit does not open the pixel row of the display panel.
[0115] S902, until the next frame period signal is in a high-level state.
[0116] Until the next frame cycle signal is at a high level, the clock drive signal CK is output normally according to the original setting.
[0117] In this application, the timing sequence is made more reasonable by classifying the first target time difference into two cases: one is greater than a preset time threshold, and the other is less than a preset time threshold. This effectively improves the screen flickering phenomenon during power-on and power-off.
[0118] Figure 10 This is a schematic diagram of the system architecture of the timing controller provided in an embodiment of this application. It should be noted that... Figure 10 The examples shown are merely examples of system architectures that can be applied to the embodiments of this application, in order to help those skilled in the art understand the technical content of this application, but do not mean that the embodiments of this application cannot be used in other devices, systems, environments or scenarios.
[0119] The timing controller 1000 includes a detection module 1010, an algorithm control module 1020, and a timing control module 1030.
[0120] The detection module 1010 is used to acquire the current startup voltage value and the current common voltage value output by the power management circuit during the power-on or power-off process of the display panel, and to detect whether the data terminal of the data signal and the common voltage output terminal are short-circuited based on the current startup voltage value and the current common voltage value.
[0121] The algorithm control module 1020 is used to call a preset time length table to obtain the target time difference between the current common voltage value and the current invalid voltage value when the current starting voltage value is an effective voltage and the current common voltage value is an invalid voltage.
[0122] The timing control module 1030, also known as the built-in crystal oscillator, is used to adjust the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of the pixel row in the display panel according to the clock drive signal; or / and, to adjust the data output timing according to the target time difference, so that the data drive circuit delays the output of the data signal according to the data output timing.
[0123] The timing controller 1000 also includes a built-in register 1040. The built-in register 1040 is a high-speed storage unit of the timing controller 1010, storing corresponding data. Among them, the preset time length table is stored here.
[0124] Figure 11 This is a schematic diagram of the system architecture of the display panel provided in an embodiment of this application. It should be noted that... Figure 11 The examples shown are merely examples of system architectures that can be applied to the embodiments of this application, in order to help those skilled in the art understand the technical content of this application, but do not mean that the embodiments of this application cannot be used in other devices, systems, environments or scenarios.
[0125] The display panel 1100 includes a timing controller 1000, a data driving circuit 1110, a gate driving circuit 1120, and a power supply integrated circuit 1130.
[0126] The data driver circuit 1110 is communicatively connected to the timing controller 1000. The timing controller 1000 is used to send data output timing to the data driver circuit 1110 so that the data driver circuit 1110 outputs data signals.
[0127] The gate driving circuit 1120 is communicatively connected to the timing controller 1000. The timing controller 100 is used to send a clock driving signal to the gate driving circuit 1120 so that the gate driving circuit 1120 opens the pixel row.
[0128] The power management circuit 1130 is communicatively connected to the timing controller 1000. The power management circuit 1130 is used to provide the timing controller with startup voltage and common voltage.
[0129] The power management circuit 1130 includes a startup voltage divider module 1131 and a common voltage divider module 1132.
[0130] The start-up voltage divider module 1131 includes a first resistor 1133 and a second resistor 1134. The first end of the first resistor 1133 and the first end of the second resistor 1134 are connected. The first end of the first resistor 1133 is communicatively connected to the timing controller 1000 and sends the current start-up voltage to the timing controller 1000.
[0131] The common voltage divider module 1132 includes a third resistor 1135 and a fourth resistor 1136. The first end of the third resistor 1135 and the first end of the fourth resistor 1136 are connected. The first end of the third resistor 1135 is communicatively connected to the timing controller and sends the current common voltage to the timing controller 1000.
[0132] In a specific implementation of the aforementioned display control method, each module can be implemented as a processor. The processor can execute computer execution instructions stored in the memory, thereby enabling the processor to execute the aforementioned display control method.
[0133] Figure 12 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application. For example... Figure 12 As shown, the electronic device includes at least one processor 1210 and a memory 1220. The electronic device also includes a communication component 1230. The processor 1210, memory 1220, and communication component 1230 are connected via a bus 1240.
[0134] In a specific implementation, at least one processor 1210 executes computer execution instructions stored in memory 1220, causing at least one processor 1210 to execute a display control method as described above on the electronic device side.
[0135] The specific implementation process of processor 1210 can be found in the above method embodiments. Its implementation principle and technical effect are similar and will not be repeated here.
[0136] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.
[0137] The memory may include high-speed RAM, and may also include non-volatile memory (NWM), such as at least one disk storage device.
[0138] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0139] The above description of the functions implemented by electronic devices and main control devices has introduced the solutions provided by the embodiments of the present invention. It is understood that, in order to implement the above functions, the electronic device or main control device includes hardware structures or software modules corresponding to the execution of each function. By combining the units and algorithm steps of the various examples described in the embodiments of the present invention, the embodiments of the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the technical solutions of the embodiments of the present invention.
[0140] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the display control method described above.
[0141] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0142] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIO). Alternatively, the processor and the readable storage medium can exist as discrete components in an electronic device or a host device.
[0143] This application also provides a computer program product, which includes: a computer program stored in a readable storage medium, at least one processor of an electronic device being able to read the computer program from the readable storage medium, and when the computer program is executed by the processor, it is used to implement the display control method described above.
[0144] Furthermore, the terms "first," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0145] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0146] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.
Claims
1. A display control method, characterized in that, The method is applied to a timing controller of a display panel, the display panel further comprising a data driving circuit, a gate driving circuit, and a power management circuit, and the control method includes: During the power-on or power-off process of the display panel, the current startup voltage value and the current common voltage value output by the power management circuit are obtained; When the current startup voltage value is an effective voltage and the current common voltage value is an invalid voltage, the target time difference between the current common voltage value and the effective voltage is obtained. Adjust the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of the pixel row in the display panel according to the clock drive signal; or / and adjust the data output timing according to the target time difference, so that the data drive circuit delays the output of the data signal according to the data output timing.
2. The display control method according to claim 1, characterized in that, The effective voltage refers to a high-level state, and the invalid voltage refers to a low-level state. When the current startup voltage value is an effective voltage and the current common voltage value is an invalid voltage, the target time difference between the current common voltage value and the effective voltage is obtained, including: Acquire detection signals and frame period signals; wherein the detection signals include high-level states and low-level states; The first target time difference is determined based on the detected signal, the frame period signal, and the preset time threshold. Based on the first target time difference, a preset time length table is invoked to obtain the target time difference.
3. The display control method according to claim 2, characterized in that, The frame period signal refers to one frame period of the display panel; Determining the first target time difference based on the detected signal, the frame period signal, and the preset time threshold includes: When the detected signal is in a low-level state, a first time difference is acquired; wherein, the first time difference refers to the time difference between when the frame period signal is in a high-level state and when the detected signal is in a low-level state; When the first time difference is less than the preset time threshold, the first time difference is determined as the first target time difference.
4. The display control method according to claim 3, characterized in that, The step of determining the first target time difference based on the detected signal, the frame period signal, and the preset time threshold further includes: When the first time difference is greater than the preset time threshold, the next frame period signal is obtained; The time difference between when the frame period signal is at a high level and when the next frame period signal is at a high level is determined as the first target time difference.
5. The display control method according to any one of claims 3 to 4, characterized in that, The step of calling a preset time length table based on the first target time difference to obtain the target time difference includes: The target time difference corresponding to the first target time difference is determined by using a preset time length table; Adjust the clock drive signal and / or the data output timing according to the target time difference.
6. The display control method according to claim 3, characterized in that, The step of adjusting the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of the pixel row in the display panel according to the clock drive signal, includes: When the time difference is a first time difference, and both the detection signal and the frame period signal are in a high-level state, the clock drive signal is set to the target state; the target state refers to the clock drive signal being in a low-level state. Until the detected signal is in a low-level state.
7. The display control method according to claim 6, characterized in that, The step of adjusting the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of the pixel rows in the display panel according to the clock drive signal, further includes: When the detection signal is at a high level and the frame period signal is at a high level, the clock drive signal is set to the target state; Until the next frame period signal is in a high-level state.
8. The display control method according to claim 1, characterized in that, The method further includes: The clock drive signal is adjusted according to the target time difference, and / or the data output timing is adjusted according to the target time difference. After that, the common voltage output terminal and the data signal output terminal are short-circuited.
9. A timing controller, characterized in that, The timing controller includes: The detection module is used to acquire the current startup voltage value and the current common voltage value output by the power management circuit during the power-on or power-off process of the display panel. The algorithm control module is used to obtain the target time difference between the current starting voltage value and the current common voltage value when the current starting voltage value is an effective voltage and the current common voltage value is an invalid voltage. The timing control module is used to adjust the clock drive signal according to the target time difference, so that the gate drive circuit delays the opening of the pixel row in the display panel according to the clock drive signal; and / or adjust the data output timing according to the target time difference, so that the data drive circuit delays the output of the data signal according to the data output timing.
10. A display panel, characterized in that, The display panel includes: The data driving circuit, the gate driving circuit, the power management circuit, and the timing controller as described in claim 9; The data driving circuit and the timing controller are communicatively connected. The timing controller is used to send data output timing to the data driving circuit so that the data driving circuit outputs data signals. The gate driving circuit is communicatively connected to the timing controller, and the timing controller is used to send a clock driving signal to the gate driving circuit so that the gate driving circuit opens the pixel row; The power management circuit is communicatively connected to the timing controller, and the power management circuit is used to provide the timing controller with startup voltage and common voltage.