Analog-to-digital conversion method, circuit, chip, device and laser radar

Abstract

The present disclosure relates to the technical field of analog-to-digital conversion, and particularly relates to an analog-to-digital conversion method, circuit, chip, device and laser radar, which is used to improve the signal-to-noise ratio and accuracy of a SAR ADC without increasing much power consumption and chip area. The analog-to-digital conversion method provided by the present disclosure comprises: determining an initial digital code and a first residual voltage corresponding to an input analog signal. The first residual voltage is determined multiple times to determine a first probability of a determination result being a first result. According to the first probability and the first residual voltage, a second residual voltage is determined. The second residual voltage is determined multiple times to determine a second probability of a determination result being the first result. According to the first probability, the second probability and the initial digital code, an output digital code is determined.

Description

Technical Field

[0001] This disclosure relates to the field of analog-to-digital conversion technology, and in particular to an analog-to-digital conversion method, circuit, chip, device, and lidar. Background Technology

[0002] In some lidar systems, an analog-to-digital converter (ADC) is used to sample and quantize the analog electrical signal output by the detector to obtain the time and amplitude information of the echo signal, thereby enabling the measurement of object distance and reflectivity. Since lidar systems require precise acquisition of weak echo signals with a large dynamic range, the performance of the ADC has a significant impact on the system's ranging accuracy and detection capability.

[0003] Analog-to-digital converters (ADCs) can convert input analog signals into digital representations (such as digital codes or digital signals). Successive approximation register (SAR) ADCs, as a type of ADC, quantize analog signals into digital signals by performing a series of bit determinations in order from the most significant bit (MSB) to the least significant bit (LSB).

[0004] In some cases, quantization errors may be introduced during the above conversion process. For example, after determining the least significant bit, the comparator may still have a residual error voltage, which can affect the signal-to-noise ratio of the ADC. Some existing technologies improve accuracy by increasing power consumption and chip area, which is costly.

[0005] Therefore, how to suppress the impact of SAR ADC quantization error on signal-to-noise ratio and accuracy while meeting the requirements of high-speed sampling, and how to achieve high-precision analog-to-digital conversion without significantly increasing power consumption and chip area, remains a technical problem that needs to be solved. Summary of the Invention

[0006] This disclosure provides an analog-to-digital conversion method, apparatus, circuit, and chip to improve the signal-to-noise ratio and accuracy of a SAR ADC without significantly increasing power consumption and chip area.

[0007] According to a first aspect of this disclosure, an analog-to-digital conversion (ADC) method is provided. The ADC method includes: determining an initial digital code corresponding to an input analog signal and a first residual voltage; performing multiple determinations on the first residual voltage to determine a first probability that the determination result is a first result; determining a second residual voltage based on the first probability and the first residual voltage; performing multiple determinations on the second residual voltage to determine a second probability that the determination result is the first result; and determining an output digital code based on the first probability, the second probability, and the initial digital code.

[0008] Optionally, the step of performing multiple determinations on the first residual voltage to determine a first probability that the determination result is the first result includes: configuring a first output voltage of the digital-to-analog converter based on the first residual voltage; and performing multiple determinations on the first output voltage to determine a first probability that the determination result is the first result.

[0009] Optionally, determining a second probability that the determination result is the first result by performing multiple determinations on the second residual voltage includes: configuring a second output voltage of the digital-to-analog converter based on the second residual voltage. This involves performing multiple determinations on the second output voltage to determine a second probability that the determination result is the first result.

[0010] Optionally, the first residual voltage is determined multiple times, including: performing a first comparison determination on the first residual voltage based on a comparator threshold.

[0011] Optionally, the second residual voltage is determined multiple times, including: performing a second comparison determination on the second residual voltage based on a comparator threshold.

[0012] Optionally, determining the second residual voltage based on the first probability and the first residual voltage includes at least one of the following: when the first probability is greater than a target threshold, subtracting a reference voltage from the first residual voltage to determine the second residual voltage; or when the first probability is less than or equal to the target threshold, adding a reference voltage to the first residual voltage to determine the second residual voltage.

[0013] Optionally, determining the output digital code based on the first probability, the second probability, and the initial digital code includes: determining a third residual voltage based on the first probability and the second probability; and determining the output digital code based on the third residual voltage and the initial digital code.

[0014] Optionally, determining the third residual voltage based on the first probability and the second probability includes: determining a first functional relationship between the first probability and the third residual voltage and comparator noise, and a second functional relationship between the second probability and the fourth residual voltage and comparator noise; the adjustment amount of the fourth residual voltage compared to the third residual voltage is equal to the adjustment amount of the second residual voltage compared to the first residual voltage. The third residual voltage is determined based on the first functional relationship and the second functional relationship.

[0015] Optionally, determining the third residual voltage based on the first functional relationship and the second functional relationship includes: determining a third functional relationship after removing comparator noise based on the first functional relationship and the second functional relationship; and determining the third residual voltage based on the third functional relationship and the adjustment amount of the fourth residual voltage compared to the third residual voltage.

[0016] Optionally, determining the initial digital code and the first residual voltage corresponding to the input analog signal includes: performing multiple least significant bit comparisons on the input analog signal, and when it is determined that the results of the two most recent least significant bit comparisons are inconsistent, outputting the initial digital code and the first residual voltage.

[0017] According to a second aspect of this disclosure, an analog-to-digital conversion circuit is provided, comprising: a logic controller configured to determine an initial digital code corresponding to an input analog signal and a first residual voltage; a comparator configured to make multiple determinations on the first residual voltage and to make multiple determinations on a second residual voltage; a noise estimation circuit configured to determine a first probability that the determination result corresponding to the first residual voltage is a first result and to determine a second probability that the determination result corresponding to the second residual voltage is the first result; a residual voltage adjustment circuit configured to adjust the first residual voltage according to the first probability and determine the second residual voltage; and a digital arithmetic circuit configured to determine an output digital code according to the first probability, the second probability, and the initial digital code.

[0018] According to a third aspect of this disclosure, a chip is provided, comprising the analog-to-digital conversion circuit described in any of the above embodiments.

[0019] According to a fourth aspect of this disclosure, an analog-to-digital conversion apparatus is provided, comprising: an initial conversion module configured to determine an initial digital code corresponding to an input analog signal and a first residual voltage; a first probability determination module configured to perform multiple determinations on the first residual voltage to determine a first probability that the determination result is a first result; a voltage adjustment module configured to adjust the first residual voltage according to the first probability to determine a second residual voltage; a second probability determination module configured to perform multiple determinations on the second residual voltage to determine a second probability that the determination result is the first result; and a digital code output module configured to determine an output digital code based on the first probability, the second probability, and the initial digital code.

[0020] According to a fifth aspect of this disclosure, a lidar is provided, comprising: a detector. The detector is connected to a signal conversion device configured to perform an analog-to-digital conversion method according to any of the above embodiments, or the signal conversion device includes an analog-to-digital conversion circuit according to any of the above embodiments, or the signal conversion device includes an analog-to-digital conversion apparatus according to any of the above embodiments. The detector is configured to output an input analog signal in response to a received optical signal. The signal conversion device is configured to determine an output digital code based on the input analog signal. The lidar is configured to determine characteristics of the optical signal based on the output digital code.

[0021] The analog-to-digital conversion method, apparatus, circuit, chip, and lidar provided in this disclosure, by determining a first residual voltage corresponding to the input analog signal and performing multiple determinations on the first residual voltage to determine a first probability that the determination result is a first result, can effectively smooth out the random influence of comparator circuit noise, obtaining a more stable statistic (first probability) that reflects the relationship between the true value of the residual voltage and the comparator threshold. A second residual voltage can be generated based on the first probability and the first residual voltage. Then, by performing multiple determinations on the second residual voltage to determine a second probability that the determination result is a first result, another statistic (second probability) reflecting the relationship between the true value of the residual voltage and the comparator threshold can be obtained. Finally, by combining the first probability, the second probability, and the initial digital code, a high-precision final output digital code can be obtained.

[0022] Compared to suppressing noise by increasing capacitor size or power consumption, the embodiments of this disclosure estimate and compensate for the error introduced by comparator noise more accurately by repeatedly comparing the first residual voltage and the second residual voltage and performing probability calculations, thereby extracting a more realistic residual voltage and achieving higher conversion accuracy without significantly increasing chip area and power consumption. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the following description of the embodiments will be provided as examples. The drawings described below are merely embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. The drawings are used to provide a further understanding of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain this disclosure and do not constitute a limitation of this disclosure.

[0024] Figure 1 A flowchart of an exemplary analog-to-digital conversion method consistent with some embodiments of this disclosure is shown.

[0025] Figure 2 A schematic diagram of an exemplary search phase consistent with some embodiments of this disclosure is shown.

[0026] Figure 3 A schematic diagram of an exemplary analog-to-digital converter circuit consistent with some embodiments of this disclosure is shown.

[0027] Figure 4 A schematic diagram of an exemplary analog-to-digital converter consistent with some embodiments of the present disclosure is shown. Detailed Implementation

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the specific implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0029] To keep the drawings simple, each figure only schematically shows the parts related to the corresponding embodiment, and they do not represent the actual structure of the product. In addition, for the sake of simplicity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0030] Unless otherwise defined, the technical or scientific terms used in the claims and description shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar words used in this patent application description and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “an” or “a” and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar words mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected,” “coupled,” or “linked” and similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0031] Unless otherwise specified, all embodiments mentioned herein can be combined to form new technical solutions. Similarly, unless otherwise specified, all technical features mentioned herein can be combined to form new technical solutions.

[0032] In this disclosure, the terms "or" and "and / or" describe the relationship between related objects and indicate a non-exclusive inclusion. For example, "A and / or B" and "A or B" can include: the presence of only "A", the presence of only "B", and the presence of both "A" and "B", where "A" and "B" can be singular or plural. As another example, "A, B, and / or C" and "A, B, or C" can include: the presence of only "A", the presence of only "B", the presence of only "C", the presence of both "A" and "B", the presence of both "A" and "C", the presence of both "B" and "C", and the presence of both "A", "B", and "C", where "A", "B", and "C" can be singular or plural. Furthermore, the symbol " / " in this disclosure indicates an "or" relationship between the related objects before and after the symbol. In this disclosure, the term "at least one A or B" has the same meaning as "A or B" described above. The term "at least one A, B, or C" has the same meaning as "A, B, or C" above. "One or more" of multiple objects refers to any one or any combination of multiple objects, such as "one or more of A, B, and C" including: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B, and C".

[0033] Analog-to-digital converters (ADCs) may introduce conversion errors, including quantization distortion and circuit noise (such as sampling noise and DAC noise), during the conversion of input analog signals into digital signals. Quantization error is related to the number of bits in the ADC, while circuit noise becomes increasingly difficult to suppress with increasing resolution; for example, power consumption quadruples for every 1-bit increase in resolution, leading to a significant increase in power consumption and chip area cost in high-precision scenarios. Therefore, this disclosure provides a solution to improve the signal-to-noise ratio and accuracy of a SAR ADC without significantly increasing power consumption and chip area.

[0034] like Figure 1 The diagram illustrates an exemplary analog-to-digital conversion method flowchart consistent with some embodiments of this disclosure. The analog-to-digital conversion method can be implemented using an analog-to-digital converter (ADC). For example, the ADC may include an analog-to-digital conversion circuit, an analog-to-digital conversion chip, an analog-to-digital conversion device, or a similar apparatus. In some embodiments, the analog-to-digital conversion method includes:

[0035] S101: Determine the initial digital code and the first residual voltage corresponding to the input analog signal.

[0036] For example, an analog-to-digital converter (ADC) may include an input terminal. The input terminal of the ADC may be connected to a detector. The detector may receive an optical signal and output an analog electrical signal in response to the optical signal. The analog electrical signal may be input through the input terminal of the ADC to form an input analog signal. The ADC may perform analog-to-digital conversion on the input analog signal to determine an initial digital code, which can be obtained by converting the input analog signal. The ADC may determine a first residual voltage characterizing the conversion error.

[0037] Figure 2 A schematic diagram illustrating an exemplary search phase consistent with some embodiments of this disclosure is shown. For example... Figure 2 As shown, after the digital-to-analog converter (DAC) 20 samples the input analog signal (Vin) 21, it can output a voltage signal ( 22. During the sampling of Vin, sampling noise signal (Vn_samp)23 and DAC noise signal (Vn_dac)24 may be superimposed. It can be a superimposed signal including Vin, Vn_samp, and Vn_dac. For example... =Vin + Vn_samp + Vn_dac. Where Vn_samp includes interference signals introduced during the sampling process, and Vn_dac includes the noise generated by the DAC itself during operation.

[0038] In output After that, the analog-to-digital converter can... Perform a binary search procedure. For example, following the order from the most significant bit (MSB) to the least significant bit (LSB), comparator 26 will... The value is compared with the comparator threshold 25 (this process may be affected by comparator noise signal 27) to determine whether each bit is 1 or 0. For example, If the value is greater than the comparator threshold, the bit can be determined to be 1. For example, If the value is less than the comparator threshold, the bit can be determined to be 0. For example, the comparator threshold can be 0V or other values. The determination result can be transmitted to the SAR logic control unit (SAR logic) 28. The SAR logic 28 can convert bit by bit according to the comparator's determination result and output the initial digital code (Dout) 29. For example, For the DAC output voltage during the bit-by-bit determination process, the current bit can be determined based on the reference voltage (Vref) and the results of the determined bits. .for example, .in, This can represent the weighting coefficient of all bits that have been determined to be 1, from the MSB to the previous bit (i.e., the current decision bit). The sum of the products of the reference voltage and the bit weighting coefficient. (i represents the weight level of that bit, decreasing sequentially from MSB to LSB. For example, in a 4-bit ADC, i=1 for MSB, and the MSB weight coefficient is...) ; LSB i=4, LSB weight coefficient ).

[0039] The first residual voltage can represent the error voltage remaining at the comparator input after the initial digital code (Dout) is determined. For example, this error voltage can represent... The difference between the analog voltage corresponding to Dout. For example, the first residual voltage. N is the number of bits in the ADC. It can represent the analog voltage corresponding to Dout, or it can be the sum of the products of the weighting coefficients of all bits determined to be 1 and the reference voltage.

[0040] During bit-by-bit comparison in an ADC, if an incorrect decision is made at a high bit due to comparator noise, the error in the overall conversion result will be greater than one LSB voltage. For example, if the decision for bit b2 is incorrect for four bits (b3-b0) of the ADC, the error in the overall conversion result will be greater than the voltage at bit b0. To correct this error, repeated comparisons can be performed at the LSB, allowing the DAC output voltage to continuously approach the comparator threshold.

[0041] In some embodiments, the input analog signal can be compared multiple times for the least significant bit. When it is determined that the results of the two most recent least significant bit comparisons are inconsistent, the initial digital code and the first residual voltage are determined.

[0042] For example, the input analog signal can be compared more than twice to determine the least significant bit (LSB). For example, after entering the LSB repetition decision stage, if the nth and (n+1)th LSB decision results are inconsistent, it indicates that the DAC output voltage is near the comparator threshold and the residual voltage is less than one LSB voltage. At this point, the search can be stopped. The decision results from the binary search stage and the LSB repetition decision stage are merged according to their respective weight levels to generate the initial digital code (Dout). The remaining error voltage at the comparator input that is not represented by this initial digital code (including quantization distortion, sampling noise, DAC noise, etc.) forms the first residual voltage (Vres1). The initial digital code and the first residual voltage can characterize the amplitude information of the input analog signal.

[0043] For example, the residual voltage can be further estimated based on Vres1 to compensate for the initial digital code, outputting a high-precision final digital code. The final digital code can be the precise digital code corresponding to the input analog signal.

[0044] S102: Perform multiple determinations on the first residual voltage to determine the first probability that the determination result is the first result.

[0045] For example, multiple comparator decisions are performed on the first residual voltage Vres1, and the number of times the first result appears in the decision results is recorded, and its proportion is calculated. For example, the first result can be a bit decision result of 1. The first probability can be the proportion of the first result appearing in the multiple decision results. For example, if N1 comparator decisions are performed on the first residual voltage Vres1, the first probability P1 can be the number of first results / N1. Multiple decisions can reduce the influence of random noise, and the determined first probability can preliminarily characterize the relationship between Vres1 and the comparator threshold.

[0046] In some embodiments, determining a first probability that the determination result is a first result by performing multiple determinations on the first residual voltage may include: configuring a first output voltage of the digital-to-analog converter (DAC) based on the first residual voltage; and performing multiple determinations on the first output voltage to determine a first probability that the determination result is a first result.

[0047] For example, after completing the above successive approximation search (including the binary search stage and the LSB repeated decision stage), the DAC output voltage = the voltage corresponding to the initial digital code Dout + the first residual voltage Vres. In the subsequent error estimation stage, in order to statistically measure Vres, the DAC's switching state can be reconfigured to output the first residual voltage. For example, configuring the DAC's switching state can include switching the capacitor switch state, such as switching the capacitor switch originally connected to the reference voltage to ground, and switching the capacitor switch originally grounded to connected to the reference voltage, thereby canceling out the voltage component corresponding to the initial digital code, leaving the first residual voltage.

[0048] In some embodiments, determining the first residual voltage multiple times may include: performing a first comparison determination between the first residual voltage and a comparator threshold.

[0049] For example, the first output voltage of the DAC is input to the positive input of the comparator, and the comparator threshold voltage is input to the negative input. When the first output voltage is greater than the comparator threshold, the comparator determines the result as the first result, for example, outputting the first result "1"; otherwise, it outputs the second result "0". This comparison process is repeated for the first number N1, such as 32 times, 64 times, etc. The number of times the first result is output in the N1 comparisons is counted, and the first probability P1 is determined as: the number of times the first result is output / N1.

[0050] S103: Determine the second residual voltage based on the first probability and the first residual voltage.

[0051] For example, based on the first probability, the adjustment direction of the first residual voltage can be determined, such as adjusting in a decreasing direction or adjusting in a increasing direction. According to the adjustment direction and the reference voltage as the adjustment magnitude, the second residual voltage can be determined.

[0052] In some embodiments, determining the second residual voltage based on the first probability and the first residual voltage may include at least one of the following:

[0053] When the first probability is greater than the target threshold, the first residual voltage is subtracted from the reference voltage to determine the second residual voltage; or, when the first probability is less than or equal to the target threshold, the first residual voltage is added to the reference voltage to determine the second residual voltage.

[0054] For example, the first result indicates that the comparator outputs "1", indicating that the first residual voltage is greater than the comparator threshold. The target threshold is, for example, 0.5. When the probability of the comparator outputting "1" is greater than 0.5, it means that in multiple comparisons, the number of times the first residual voltage is greater than the comparator threshold is greater than the number of times the first residual voltage is less than the comparator threshold. The current first residual voltage is more likely to be higher than the comparator threshold. The residual voltage can be adjusted to decrease, making the adjusted second residual voltage closer to or exceeding the comparator threshold. When the probability of the comparator outputting "1" is less than or equal to 0.5, it means that in multiple comparisons, the number of times the first residual voltage is greater than the comparator threshold is less than the number of times the first residual voltage is less than the comparator threshold. The first residual voltage is more likely to be lower than the comparator threshold. The residual voltage can be adjusted to increase, similarly making the adjusted second residual voltage closer to or exceeding the comparator threshold. The second residual voltage can be further evaluated by comparing its magnitude with the comparator threshold. For example, when adjusting the residual voltage, it can be adjusted according to a reference voltage. For example, the reference voltage can be the voltage corresponding to one LSB, or it can be a voltage less than the voltage corresponding to one LSB, such as 1 / 2 or 1 / 4 of the voltage corresponding to one LSB.

[0055] S104: Perform multiple determinations on the second residual voltage to determine the second probability that the determination result is the first result.

[0056] For example, multiple comparator decisions are performed on the second residual voltage Vres2, the number of times the first result appears in the decision results is recorded, and its proportion is calculated. For instance, N2 comparator decisions are performed on Vres2, the number of times the comparator outputs the first result "1" is counted, and the second probability P2 is determined as the number of times the first result appears / N2.

[0057] In some embodiments, determining a second probability that the determination result is the first result by performing multiple determinations on the second residual voltage may include: configuring a second output voltage of the DAC based on the second residual voltage; and determining a second probability that the determination result is the first result by performing multiple determinations on the second output voltage.

[0058] For example, after configuring the first output voltage of the DAC based on the first residual voltage, some switching states of the DAC can be reconfigured based on the second residual voltage. For instance, if the second residual voltage is one LSB voltage less than the first residual voltage, the state of one LSB capacitor switch is switched, changing the LSB capacitor switch that was originally connected to the reference voltage to ground; or, if the second residual voltage is one LSB voltage more than the first residual voltage, the LSB capacitor switch that was originally grounded is switched to be connected to the reference voltage, thereby configuring the DAC output voltage as the second output voltage.

[0059] In some embodiments, determining the second residual voltage multiple times may include: performing a second comparison determination between the second residual voltage and a comparator threshold.

[0060] For example, the second output voltage of the DAC is input to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the voltage corresponding to the comparator threshold (e.g., 0V). If the second output voltage is greater than the comparator threshold, the comparator determines the result as the first result, for example, outputting the first result "1"; otherwise, it outputs the second result "0". This comparison process is repeated a second time M2, for example, 32 times, 64 times, etc. The number of times the first result is output in N2 comparisons is counted, and the second probability P2 is determined as the number of times the first result is output / N2. M2 can be the same as or different from N1.

[0061] S105: Determine the output digital code based on the first probability, the second probability, and the initial digital code.

[0062] For example, the relatively true residual voltage can be determined based on the statistical probability of two different residual voltages, and then combined with the initial digital code to obtain the final high-precision output digital code.

[0063] In some embodiments, the polarity of the residual voltage can be determined based on the relationship between the first probability and the second probability, and a fixed correction amount can be assigned to the digital code. For example, when P1 > 0.5 and P2 < 0.5, it indicates that after the residual voltage adjustment, the comparator's comparison result flips, and the residual voltage is close to the comparator threshold of 0. In this case, the correction amount of the digital code can be set to 0, and the output digital code is determined to be equal to the initial digital code. For example, when P1 > 0.5 and P2 > 0.5, it indicates that the value of the residual voltage before and after adjustment is more likely to be higher than the comparator threshold, and the correction amount of the digital code can be set to a positive correction amount (e.g., +0.5 LSB). For example, when P1 < 0.5 and P2 < 0.5, it indicates that the value of the residual voltage before and after adjustment is more likely to be lower than the comparator threshold, and the correction amount of the digital code can be set to a negative correction amount (e.g., -0.5 LSB).

[0064] In some embodiments, a lookup table can be pre-established. The lookup table may include the correspondence between (P1, P2) and the final residual voltage. Exemplarily, the lookup table can be established through actual measurement or simulation, or it can be established based on a function calculation using a statistical distribution model of comparator noise. After determining P1 and P2, the final residual voltage can be determined by looking up the table. The found final residual voltage is then fused with the initial digital code to determine the final output digital code.

[0065] In some embodiments, determining the output digital code based on a first probability, a second probability, and an initial digital code may include: determining a third residual voltage based on the first probability and the second probability; and determining the output digital code based on the third residual voltage and the initial digital code.

[0066] For example, the corrected residual voltage estimate (third residual voltage) can be determined based on the first probability and the second probability. The third residual voltage is converted into a corresponding digital quantity, and then digital addition is performed with the initial digital code to determine the final output digital code.

[0067] In some embodiments, when determining the third residual voltage based on the first probability and the second probability, for example, the lookup table method described above can be used to determine the third residual voltage corresponding to (P1, P2) by looking up the table.

[0068] For example, in some embodiments, when the absolute values ​​of Vres3 and ΔV are relatively small (e.g., much smaller than the comparator noise voltage), a linear approximation relationship can be established between the third residual voltage and the first and second probabilities, and the third residual voltage Vres3 can be determined based on this linear approximation relationship. Exemplarily, when establishing this linear approximation relationship, the voltage adjustment ΔV of the second residual voltage compared to the first residual voltage can also be combined with the target threshold Pth used in the probability judgment (e.g., 0.5). For example: β is the correction coefficient; the absolute value of the difference between the first probability P1 and the target threshold reflects the degree of deviation of the first residual voltage from the comparator threshold. For example, the larger P1 is than the target threshold, the larger the actual Vres3 can be considered, and Vres3 can be compared with... Positive correlation. The difference between the first probability and the second probability reflects the amount of voltage adjustment. The degree of influence on probability. For example, the larger the difference between the first probability and the second probability, the higher the voltage adjustment sensitivity. A smaller expected increase in the third residual voltage based on the initial digital code voltage makes it easier to meet the actual situation. Vres3 can be compared with... Negative correlation.

[0069] In some other embodiments, determining the third residual voltage based on a first probability and a second probability may include: determining a first functional relationship between the first probability and the third residual voltage and comparator noise, and a second functional relationship between the second probability and the fourth residual voltage and comparator noise; the third residual voltage can be determined based on the first and second functional relationships. For example, the adjustment amount of the fourth residual voltage relative to the third residual voltage may be equal to the adjustment amount of the second residual voltage relative to the first residual voltage.

[0070] For example, a first functional relationship can be established between the first probability P1 and the third residual voltage Vres3 and the comparator noise Vn_comp, and a second functional relationship can be established between the second probability P2 and the fourth residual voltage Vres4 and the comparator noise Vn_comp. Since the statistical calculations of P1 and P2 are completed in a very short time, the comparator noise Vn_comp can be considered consistent. The first and second functional relationships can reflect the variation of the probability of the comparator outputting "1" with the residual voltage when comparator noise exists. For example, the third residual voltage Vres3 can be considered as the residual voltage to be optimized corresponding to the first residual voltage, and also the actual residual voltage that needs to be solved. For example, the fourth residual voltage Vres4 can be considered as the residual voltage to be optimized corresponding to the second residual voltage. For example, the voltage adjustment of the fourth residual voltage compared to the third residual voltage is equal to the voltage adjustment of the second residual voltage compared to the first residual voltage.

[0071] For example, based on the statistical distribution model of comparator noise, the first functional relationship can be expressed as follows: (Formula 1); the second functional relationship can be expressed as: (Formula 2). The statistical distribution model of comparator noise can be, for example, a Gaussian distribution model.

[0072] In the above functional relationship, It represents the inverse function of the error function, and can perform a nonlinear inverse transform to convert the probability offset into a voltage offset; is the standardization factor for the Gaussian distribution.

[0073] In some embodiments, when determining the third residual voltage based on the first and second functional relationships, the first and second functional relationships can be combined, for example, by subtraction; then, by combining the relationship between the fourth and third residual voltages, a functional relationship between the third residual voltage and the comparator noise, the first probability, and the second probability can be obtained. Based on this functional relationship, the third residual voltage can be determined using the measured comparator noise, the first probability, and the second probability.

[0074] Because comparator noise is affected by factors such as process, voltage, and temperature, the accuracy of the third residual voltage determined based on the comparator noise measured under fixed conditions may be affected to some extent.

[0075] In some embodiments, determining the third residual voltage based on the first functional relationship and the second functional relationship may include: determining the third functional relationship after removing comparator noise based on the first functional relationship and the second functional relationship; and determining the third residual voltage based on the third functional relationship and the adjustment amount of the fourth residual voltage compared to the third residual voltage.

[0076] For example, the first functional relationship and the second functional relationship can be divided to eliminate the comparator noise parameters. Then, by combining the relationship between the fourth residual voltage and the third residual voltage, the third residual voltage after eliminating the influence of comparator noise can be determined, thereby further improving the accuracy of the final residual voltage determination and thus improving the accuracy of the final output digital code.

[0077] For example, dividing the first functional relationship represented by Formula 1 by the second functional relationship represented by Formula 2 yields the third functional relationship:

[0078] ;

[0079] Furthermore, consider the relationship between Vres3 and Vres4. Vres4 can be eliminated, and the final result is:

[0080] .

[0081] That is, .

[0082] In some embodiments, when determining and In some implementations, a function can be called directly for calculation. Alternatively, a lookup table can be used. In this lookup table method, the value corresponding to each quantized probability P (discrete value) can be pre-calculated. The data is stored, and during subsequent table lookups, the pre-stored correspondence is invoked to directly read the data corresponding to P1. Corresponding to P2 For example, P1 and P2 can be determined based on P in the quantization table. Alternatively, nearest-neighbor matching or linear interpolation can be used to determine P1 and P2 based on P in the quantization table.

[0083] The above implementation method performs probabilistic statistical measurements on the residual voltages of two known fixed voltage differences and solves the problem using the functional relationship corresponding to the two measurement results. During the solution process, the unknown and variable parameter of comparator noise is completely canceled out. This eliminates the error introduced by comparator noise in the output result, significantly improving conversion accuracy and overall signal-to-noise ratio.

[0084] Figure 3 A schematic diagram of an exemplary analog-to-digital converter circuit consistent with some embodiments of this disclosure is shown. For example... Figure 3As shown, this disclosure provides an analog-to-digital converter (ADC) circuit. The ADC circuit includes a logic controller 31, a comparator 32, a noise estimation circuit 33, a residual voltage adjustment circuit 34, and a digital arithmetic circuit 35. The logic controller 31 can determine an initial digital code and a first residual voltage corresponding to an input analog signal. The comparator 32 can perform multiple determinations on the first residual voltage and multiple determinations on a second residual voltage. The noise estimation circuit 33 can determine a first probability that the determination result corresponding to the first residual voltage is a first result and a second probability that the determination result corresponding to the second residual voltage is a first result. The residual voltage adjustment circuit 34 can adjust the first residual voltage according to the first probability to determine the second residual voltage. The digital arithmetic circuit 35 can determine an output digital code according to the first probability, the second probability, and the initial digital code.

[0085] In some embodiments, the logic controller 31 may include a successive approximation register logic (SAR Logic) unit in the SAR ADC, which can coordinate the timing and control decisions of the analog-to-digital conversion process. The SAR Logic can control the conversion process bit by bit in the order from MSB to LSB, and output the initial digital code. The unquantized analog voltage remaining at the comparator input (or DAC output) is the first residual voltage. In some embodiments, the comparator 32 may include a voltage comparison unit in the SAR ADC, which compares the DAC output voltage with a reference threshold and outputs a high / low (1 / 0) decision result, driving the SAR Logic to make a bit decision. In some embodiments, the noise estimation circuit 33 may include a counter and a probability calculation module. For example, the counter can count the number of times the decision result is the first result, and the probability calculation module may include a divider responsible for dividing the counter output value by a fixed total number of decisions. The residual voltage adjustment circuit 34 may include a capacitive digital-to-analog converter (CDAC), which can switch the connection state of the capacitor unit corresponding to the LSB in the DAC according to the control signal of the decision logic, thereby adjusting the DAC output voltage. The digital processing circuit 35 can be implemented in any of a variety of ways. For example, it can be implemented using real-time calculation. For instance, when determining the output digital code by solving a functional relationship, the function calculation module can first calculate the inverse function, and then the arithmetic logic unit can calculate the actual residual voltage (such as the formula for calculating the third residual voltage Vres3 mentioned above). , The initial digital code is added to the quantized digital code corresponding to the actual residual voltage using an adder to obtain the output digital code. For example, the arithmetic logic unit may include a multiplier, divider, adder, or similar device. For example, the digital operation circuit 35 can be implemented using a lookup table. For instance, the address generation module can quantize the first probability P1 and the second probability P2 output by the noise estimation circuit 33 into fixed-width index values ​​and concatenate them to form the lookup table address. For example, the address generation module may include a register, multiplexer, or similar device. The lookup table storage unit pre-stores correction values ​​corresponding to different combinations of (P1, P2), which represent the digital code increment corresponding to the actual residual voltage Vres3 obtained based on statistical calculations. For example, the lookup table storage unit may include a memory or similar device. The digital synthesis module can add the correction value read from the lookup table to the initial digital code Dout output by the logic controller 31 to determine the corrected high-precision output digital code. For example, the digital synthesis module may include an adder or similar device.

[0086] This disclosure also provides a chip including an analog-to-digital converter circuit as described above. This chip can be a standalone ADC chip or an analog peripheral within a microcontroller or microprocessor.

[0087] This disclosure also provides an analog-to-digital conversion apparatus, including units or means for performing the steps of any of the above-described analog-to-digital conversion methods. For example, please refer to... Figure 4 This illustrates a schematic diagram of the structure of an analog-to-digital converter provided in some embodiments of this disclosure. For example... Figure 4 As shown, the system includes an initial conversion module 41, a first probability determination module 42, a voltage adjustment module 43, a second probability determination module 44, and a digital code output module 45. The initial conversion module 41 determines an initial digital code and a first residual voltage corresponding to the input analog signal. The first probability determination module 42 performs multiple determinations on the first residual voltage to determine a first probability that the determination result is the first result. The voltage adjustment module 43 adjusts the first residual voltage according to the first probability to determine a second residual voltage. The second probability determination module 44 performs multiple determinations on the second residual voltage to determine a second probability that the determination result is the first result. The digital code output module 45 determines the output digital code based on the first probability, the second probability, and the initial digital code.

[0088] Each of the above modules can be implemented by hardware, software, or a combination of hardware and software, and this disclosure does not limit the implementation.

[0089] For example, the underlying analog hardware of the SAR ADC (such as comparators, CDACs, etc.) can be used as controlled peripherals, while the overall algorithm flow is controlled and calculated by software running on a processor. For example, the processor may include a microcontroller unit (MCU), a digital signal processor (DSP), a central processing unit (CPU), etc. For example, the initial conversion module 41 can initiate and control the hardware SAR ADC to complete one analog-to-digital conversion, and then read its output initial digital code; the first residual voltage itself does not need to be directly read. For example, the first probability determination module 42 / second probability determination module 44 can repeatedly read the output bits of the comparator and accumulate counts in memory to calculate the first and second probabilities. For example, the voltage adjustment module 43 can adjust the voltage by controlling the fine-tuning switch of the CDAC. For example, the digital code output module 45 can implement a lookup table in memory or directly run the calculation code to complete the fusion calculation of the final output digital code.

[0090] For example, parts with high timing and speed requirements can be implemented in hardware, such as the successive approximation comparison logic of the initial conversion module 41, the counting process in the first probability determination module 42 / second probability determination module 44, and the switching control logic of the voltage adjustment module 43. Parts with high complexity but relatively low real-time requirements can be implemented in software; for example, the processor obtains the final analog-to-digital conversion result by looking up tables or performing function calculations.

[0091] The implementation details of the aforementioned analog-to-digital conversion circuit, chip, or analog-to-digital conversion device can be found in the description of the aforementioned method, and will not be repeated here.

[0092] In some embodiments, the analog-to-digital conversion method, circuit, chip, and apparatus provided in this disclosure can be applied to LiDAR (light detection and ranging). For example, a LiDAR emits laser pulses and receives light signals reflected from an object, converting the received light signals into analog electrical signals, which can then be used as the aforementioned input analog signals. Reflected light signals are sometimes weak and may be affected by ambient light, circuit noise, etc., thus requiring high signal-to-noise ratio and accuracy from the signal conversion equipment performing the analog-to-digital conversion. By employing the analog-to-digital conversion method provided in this disclosure, errors introduced by comparator noise can be effectively suppressed, improving conversion accuracy and signal-to-noise ratio.

[0093] Exemplarily, the lidar of this disclosure embodiment may include a detector. The detector may be connected to a signal conversion device. Exemplarily, the signal conversion device may perform the analog-to-digital conversion method described in any of the above embodiments. Exemplarily, the signal conversion device includes the analog-to-digital conversion circuit described in any of the above embodiments. Exemplarily, the signal conversion device includes the analog-to-digital conversion apparatus described in any of the above embodiments. Exemplarily, the signal conversion device may include the chip described above. The detector may respond to the received optical signal and output an input analog signal. The input analog signal is processed by the signal conversion device and converted into an output digital code. The lidar can determine the characteristics of the optical signal based on the output digital code. For example, the characteristics of the optical signal may include quantitative information describing the object or environment, such as time-of-flight information, signal strength or energy information, and distance information indirectly determined based on time of flight, reflectivity information indirectly determined based on signal strength, etc. Exemplarily, the characteristics of the optical signal can be determined by a processing unit based on the output digital code.

[0094] In some embodiments, the signal conversion device and processing unit described above may be integrated into the lidar, or may be independent of the lidar, or may be partially integrated into the lidar and partially independent of the lidar. No restrictions are imposed on the embodiments disclosed herein.

[0095] In some implementations, the detector may include a photodetector circuit, a single-photon avalanche diode (SPAD), an avalanche photodiode (APD), a silicon photomultiplier (SiPM), or a similar device.

[0096] In summary, the embodiments disclosed herein effectively improve the signal-to-noise ratio and conversion accuracy of SAR ADC without significantly increasing power consumption and chip area, making them particularly suitable for applications such as lidar that require high signal detection accuracy and have strict limitations on power consumption and chip area.

[0097] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. An analog-to-digital conversion method, characterized in that, include: The least significant bit of the input analog signal is compared multiple times. When the results of the two most recent least significant bit comparisons are inconsistent, the initial digital code and the first residual voltage corresponding to the input analog signal are determined. The first residual voltage is judged multiple times to determine the first probability that the judgment result is the first result; The second residual voltage is determined based on the first probability and the first residual voltage; The second residual voltage is determined multiple times to determine the second probability that the determination result is the first result; The output digital code is determined based on the first probability, the second probability, and the initial digital code.

2. The method according to claim 1, characterized in that, The step of performing multiple determinations on the first residual voltage to determine the first probability that the determination result is the first result includes: Configure the first output voltage of the digital-to-analog converter based on the first residual voltage; The first output voltage is judged multiple times to determine the first probability that the judgment result is the first result.

3. The method according to claim 1, characterized in that, The step of performing multiple determinations on the second residual voltage to determine the second probability that the determination result is the first result includes: Configure the second output voltage of the digital-to-analog converter based on the second residual voltage; The second output voltage is judged multiple times to determine the second probability that the judgment result is the first result.

4. The method according to claim 1, characterized in that, The first residual voltage is determined multiple times, including: The first residual voltage is compared with the comparator threshold for the first time to determine the value.

5. The method according to claim 1, characterized in that, The second residual voltage is determined multiple times, including: The second residual voltage is compared with the comparator threshold for a second determination.

6. The method according to claim 1, characterized in that, The second residual voltage is determined based on the first probability and the first residual voltage, including at least one of the following: When the first probability is greater than the target threshold, the first residual voltage is subtracted from the reference voltage to determine the second residual voltage; or When the first probability is less than or equal to the target threshold, the first residual voltage is added to the reference voltage to determine the second residual voltage.

7. The method according to claim 1, characterized in that, Determining the output digital code based on the first probability, the second probability, and the initial digital code includes: The third residual voltage is determined based on the first probability and the second probability; The output digital code is determined based on the third residual voltage and the initial digital code.

8. The method according to claim 7, characterized in that, Determining the third residual voltage based on the first probability and the second probability includes: A first functional relationship is determined between the first probability and the third residual voltage and comparator noise, and a second functional relationship is determined between the second probability and the fourth residual voltage and comparator noise; the adjustment amount of the fourth residual voltage compared to the third residual voltage is equal to the adjustment amount of the second residual voltage compared to the first residual voltage; the first functional relationship includes The second functional relationship includes: ;in, This refers to the third residual voltage. This refers to the fourth residual voltage. Indicates comparator noise. Indicates the first probability. Indicates the second probability; Based on the first functional relationship and the second functional relationship, the comparator noise is removed, and the third residual voltage is determined.

9. The method according to claim 8, characterized in that, Determining the third residual voltage based on the first functional relationship and the second functional relationship includes: Based on the first functional relationship and the second functional relationship, a third functional relationship is determined after removing comparator noise; the third functional relationship includes: ; The third residual voltage is determined based on the third functional relationship and the adjustment amount of the fourth residual voltage compared to the third residual voltage.

10. An analog-to-digital converter circuit, characterized in that, include: The logic controller is configured to perform multiple least-bit comparisons on the input analog signal, and when it is determined that the results of the two most recent least-bit comparisons are inconsistent, output an initial digital code corresponding to the input analog signal. The comparator is configured to make multiple determinations on the first residual voltage after the logic controller outputs the initial digital code; In addition, the second residual voltage is determined multiple times; The noise estimation circuit is configured to determine a first probability that the determination result corresponding to the first residual voltage is the first result; And, determine the second probability that the judgment result corresponding to the second residual voltage is the first result; A residual voltage adjustment circuit is configured to adjust the first residual voltage according to the first probability to determine the second residual voltage; A digital processing circuit is configured to determine an output digital code based on the first probability, the second probability, and the initial digital code.

11. A chip, characterized in that, Includes the analog-to-digital converter circuit as described in claim 10.

12. An analog-to-digital converter, characterized in that, include: The initial conversion module is configured to perform multiple least-bit comparisons on the input analog signal. When it is determined that the results of the two most recent least-bit comparisons are inconsistent, the initial digital code and the first residual voltage corresponding to the input analog signal are determined. The first probability determination module is configured to make multiple determinations on the first residual voltage and determine the first probability that the determination result is the first result. A voltage adjustment module is configured to adjust the first residual voltage according to the first probability to determine a second residual voltage; The second probability determination module is configured to make multiple determinations on the second residual voltage and determine a second probability that the determination result is the first result. The digital code output module is configured to determine the output digital code based on the first probability, the second probability, and the initial digital code.

13. A lidar, characterized in that, include: detector; The detector is connected to a signal conversion device, wherein the signal conversion device is configured to perform the analog-to-digital conversion method according to any one of claims 1 to 9, or the signal conversion device includes the analog-to-digital conversion circuit according to claim 10, or the signal conversion device includes the analog-to-digital conversion apparatus according to claim 12; The detector is configured to output an input analog signal in response to a received optical signal; The signal conversion device is configured to output a digital code based on the determined input analog signal; The lidar is configured to determine the characteristics of the optical signal based on the output digital code.

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