Wiring board

Abstract

The invention provides a wiring board, and discloses a technology of a wiring board capable of coping with various kinds of mounting components with different contents required by high integration. A wiring board according to the present invention has a plurality of wiring structures in which a plurality of trunk lines are housed and both end portions of the trunk lines are exposed on the upper surfaces of the plurality of wiring structures as a plurality of connection points, and a cavity in which the plurality of wiring structures are housed, the plurality of wiring structures include two or more wiring structures selected from among a first wiring structure having a silicon layer at the lower part, a second wiring structure having a glass layer at the lower part, and a third wiring structure having a resin layer at the lower part and not including a glass layer and a silicon layer. The planar dimensions of the two or more types of wiring structures and / or the minimum L / S of the plurality of trunk lines differ, L represents the width of the trunk line, and S represents the width of the space between the trunk lines.

Description

Technical Field

[0001] This invention relates to wiring substrates. Background Technology

[0002] As conventional wiring substrates, wiring substrates with embedded wiring structures called patches are known in order to achieve high integration of a portion of the wiring according to the installed electronic components (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-236188 (paragraph

[0044] ) Figure 1 )

[0004] However, depending on the type of electronic component, the required level of integration and the width of the high integration range (i.e., the width of the upper surface of the wiring structure) of the required wiring structure vary. Therefore, this application discloses a technology for wiring boards capable of handling various mounting components with different requirements for high integration. Summary of the Invention

[0005] One aspect of the invention is a wiring substrate having a plurality of wiring structures and cavities housing the plurality of wiring structures. The plurality of wiring structures contain a plurality of relays, and the ends of these relays are exposed on the upper surface of the plurality of wiring structures as multiple connection points. The plurality of wiring structures includes two or more of the following: a first wiring structure with a silicon layer at its lower part; a second wiring structure with a glass layer at its lower part; and a third wiring structure with a resin layer at its lower part and not containing either a glass layer or a silicon layer. At least one of the planar dimensions of the two or more wiring structures or the minimum L / S ratio of the plurality of relays is different, where L represents the width of the relay and S represents the width of the space between the relays. Attached Figure Description

[0006] Figure 1 This is a side sectional view of the wiring substrate according to the first embodiment.

[0007] Figure 2 This is a top view of the wiring board.

[0008] Figure 3A , Figure 3B This is a top view of the electronic components.

[0009] Figure 4A , Figure 4B , Figure 4C This is a top view of the wiring structure.

[0010] Figure 5A , Figure 5B , Figure 5C This is a side sectional view of the wiring structure.

[0011] Figure 6A This is a side sectional view of the wiring substrate before the cavity is formed. Figure 6B This is a side sectional view of a wiring substrate with cavities. Figure 6C This is a side sectional view of a wiring substrate with wiring structures arranged inside the cavity.

[0012] Figure 7A This is a side cross-sectional view of a wiring substrate with vias formed in the outermost insulating layer. Figure 7B This is a side cross-sectional view of a wiring substrate with via conductors formed in the vias. Figure 7C This is a side cross-sectional view of a wiring substrate with metal pillars.

[0013] Figure 8 This is a side sectional view of the wiring substrate according to the second embodiment.

[0014] Figure 9 This is a top view of the wiring substrate according to the second embodiment.

[0015] Figure 10A , Figure 10B , Figure 10C This is a top view of the wiring structure according to the second embodiment.

[0016] Label Explanation

[0017] 10: Wiring substrate; 13: Insulating layer; 14: Conductive layer; 15: Via conductor; 19: Metal pillar; 20X, 20Y, 20Z, 20W: Wiring structure; 21D: Line; 22: Connection point; 23: Repeater; 25: Silicon layer; 26: Glass layer; 30: Cavity; 100X, 100Y, 100Z, 100W: Electronic component; R3: First array area; R4: Second array area. Detailed Implementation

[0018] [First Implementation Method]

[0019] Reference Figures 1-5C The wiring substrate 10 of this embodiment will be described. Figure 1 The wiring substrate 10 shown is a multilayer wiring substrate, having a multilayer portion 12 formed by alternately stacking multiple insulating layers 13 and multiple conductive layers 14 on both sides of the core substrate 11. Furthermore, in Figure 1 The image shows only a portion of the front side of the core substrate 11 in the wiring substrate 10.

[0020] The insulating layer 13 has a plurality of via conductors 15, which connect adjacent conductive layers 14 in the stacked portion 12 separated by the insulating layer 13. The core substrate 11 has a plurality of through conductors 18, through which the innermost conductive layers 14 are connected to each other.

[0021] The outermost layer of insulating layer 13 and conductive layer 14, furthest from core substrate 11, is, for example, conductive layer 14. Additionally, an inner layer 13 of the outermost insulating layer 13 forms a two-layer structure where a lower insulating layer 13A and an upper insulating layer 13B overlap. Furthermore, a portion of the fifth conductive layer 14 from the core substrate 11 side forms a planar layer 14P.

[0022] In the multiple openings 13H formed in the outermost insulating layer 13 Figure 1 The interior of all the openings shown has metal pillars 19, and directly below these metal pillars 19 there are via conductors 15, forming a stacked structure.

[0023] The upper surfaces of the plurality of metal pillars 19 form a plurality of gaskets 19A. The plurality of gaskets 19A are arranged in the same plane, and as... Figure 2 As shown, it is divided into multiple regions, and each of these regions is arranged in a matrix.

[0024] like Figure 2 As shown, the mounting components of the wiring substrate 10 include multiple chip-type electronic components 100X, 100Y, ... with multiple pads 101 arranged in a matrix on the lower surface. These multiple electronic components 100X, 100Y, ... are, for example, semiconductor elements, and are composed of various functions such as CPU elements, memory elements, and sensor elements. Moreover, the multiple pads 101 of the multiple electronic components 100X, 100Y, ... are flip-chip connected to the aforementioned multiple pads 19A. Hereinafter, without distinguishing between the electronic components 100X, 100Y, ..., they will be collectively referred to as electronic components 100.

[0025] In addition, Figure 2 In the diagram, the outline of electronic component 100 and pad 101 are represented by imaginary lines (double-dotted lines), pad 19A is represented by solid lines, and the outline of wiring structure 20 and connection point 22 (described later) are represented by dashed lines. The connection point 22 and the lines representing pads 19A and 101 are difficult to distinguish, therefore... Figure 2 The upper left corner shows a portion of the connection point 22 and pads 19A and 101. Additionally, the connection point 22 and the lines representing pads 19A and 101 are different sizes to avoid overlap, but the planar shapes of the connection point 22 and pads 19A and 101 can be the same or different.

[0026] The planar shape of each electronic component 100 is quadrilateral, and as described above, a plurality of pads 101 are arranged in a matrix on the entire lower surface. Furthermore, the spacing between the plurality of pads 101 (hereinafter referred to as "pad spacing") differs from one another in a portion of each electronic component 100. Specifically, as... Figure 3A as well as Figure 3B As shown, electronic component 100 is provided with a first region R1 positioned adjacent to one of a pair of opposing outer edges and a second region R2 positioned adjacent to the other. The pad spacing of the second region R2 is larger than that of the first region R1. Furthermore, the second region R2 of electronic component 100X and the first region R1 of electronic component 100Y have the same pad spacing. That is, if the pad spacing is listed in ascending order, it is first region R1 of electronic component 100X, then second region R2 of electronic component 100X and first region R1 of electronic component 100Y, then second region R2 of electronic component 100Y.

[0027] like Figure 2 As shown, the aforementioned plurality of electronic components 100 are uniformly oriented, for example, with their outer edges parallel to each other or at right angles, and are symmetrically arranged such that a pair of electronic components 100Y sandwiches a pair of electronic components 100X. Furthermore, adjacent electronic components 100 are arranged such that regions with the same pad spacing are located near each other's close outer edges. Moreover, a plurality of pads 19A on the upper surface of the wiring substrate 10 are located directly below the pads 101 of the plurality of electronic components 100.

[0028] Furthermore, in the wiring substrate 10 of this embodiment, multiple electronic components 100 are symmetrically arranged, but the arrangement of the multiple electronic components 100 is arbitrary; they can be arranged asymmetrically, or their orientations can be inconsistent. Additionally, the aforementioned electronic component 100 can be a single semiconductor chip, or a semiconductor chip package in which the interposer substrate and the semiconductor chip are integrated. That is, any surface-mount semiconductor component is acceptable. Furthermore, as the electronic component 100 of this embodiment, a BGA (Ball Grid Array) type is envisioned, but an LGA (Lard Grid Array) type is also possible.

[0029] In order to Figure 2 The multiple pads 101 of adjacent electronic components 100 shown are connected to each other. Three wiring structures 20X, 20Y, and 20Z, namely the first to the third wiring structures, are embedded in the upper part of the stacked portion 12 on the upper side of the wiring substrate 10. Without distinguishing between these first to third wiring structures 20X, 20Y, and 20Z, they are collectively referred to as wiring structure 20. First, the common structure of all wiring structures 20 will be described.

[0030] like Figure 4A , Figure 4B , Figure 4C As shown, the wiring structure 20 is, for example, a plate with a planar quadrilateral shape. Additionally, as... Figure 5A , Figure 5B , Figure 5C As shown, multiple relay lines 23 are built into the interior of the wiring structure 20. Furthermore, the two ends of the multiple relay lines 23 are exposed on the upper surface of the wiring structure 20 as multiple connection points 22. These multiple connection points 22 are separately arranged in a first array region R3 corresponding to a first region R1 of two adjacent electronic components 100 and a second array region R4 corresponding to a second region R2. Furthermore, the spacing between the connection points 22 in the first array region R3 and the second array region R4 is constant. Additionally, as... Figure 1 As shown, the overlapping connection point 22 in the vertical direction is connected to the pad 101 via the aforementioned metal post 19.

[0031] like Figure 1 As shown, the wiring substrate 10 has a cavity 30 with a lower insulating layer 13A penetrating the outermost insulating layer 13 and the insulating layer 13 below it, and a planar layer 14P as its bottom surface. Furthermore, the cavity 30 is divided into three cavities: one for housing a pair of first wiring structures 20X and a pair of second wiring structures 20Y, and another for housing each of the third wiring structures 20Z. It should be noted that the structure can accommodate all wiring structures 20 together in one cavity 30, or the structure can accommodate each wiring structure 20 individually in the cavity 30.

[0032] Each wiring structure 20 is housed with its lower surface overlapping the bottom surface of the cavity 30. Furthermore, the upper surface of each wiring structure 20 is covered by the upper insulating layer 13B of the outermost insulating layer 13. The resin constituting the upper insulating layer 13B fills the gap between the inner surface of the cavity 30 and the wiring structure 20, thus fixing the wiring structure 20 within the cavity 30. Moreover, metal pillars 19 are connected to the connection points 22 of the wiring structure 20 via through-hole conductors 15 formed on the upper insulating layer 13B and the insulating layer 13 covering the upper insulating layer 13B from above. The upper ends of these multiple metal pillars 19 become the aforementioned pads 19A, connected to the multiple pads 101 of the electronic component 100. That is, the connection points 22 of the overlapping wiring structures 20 in the vertical direction are connected to the pads 101 of the electronic component 100 via metal pillars 19.

[0033] like Figure 1As shown, a plurality of metal pillars 19 are disposed on the side opposite to the second wiring structure 20Y relative to each of the third wiring structures 20Z, and are connected to the third conductive layer 14 from the top in the wiring substrate 10 via via conductors 15. Furthermore, the pads 19A at the upper ends of these plurality of metal pillars 19 are connected to a plurality of pads 101 on the lower surface of the electronic component 100Z located at a portion offset from the third wiring structure 20Z.

[0034] Furthermore, if the insulating layer 13 located on the upper surface at the bottom of the cavity 30 is referred to as the "first insulating layer", and the lower insulating layer 13A is referred to as the "third insulating layer", then the wiring substrate 10 of this embodiment has the following structure: "a multilayer structure having a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer stacked sequentially from bottom to top, and the cavity for receiving the wiring structure is formed to penetrate both the second insulating layer and the third insulating layer."

[0035] The detailed structure of the wiring structure 20 is as follows. The first wiring structure 20X, sometimes referred to as a silicon patch, has a silicon layer 25 as a support layer at its bottom. The second wiring structure 20Y, sometimes referred to as a glass patch, has a glass layer 26 as a support layer at its bottom. The third wiring structure 20Z, sometimes referred to as a resin patch, does not have a support layer and has a structure that does not include a glass layer or a silicon layer. Furthermore, an adhesive layer 28 for fixing the wiring structure 20 to the bottom of the cavity 30 is adhered to the lower surface of each wiring structure.

[0036] In detail, such as Figure 5A As shown, the first wiring structure 20X has conductive layers 21B and insulating layers 21A alternately stacked on the silicon layer 25, with the uppermost layer being the insulating layer 21A. In each conductive layer 21B, for example, multiple lines 21D are arranged in a manner that do not intersect each other (in...). Figure 5A (The topmost wire 21D is omitted). At both ends of each wire 21D below the topmost layer, one or more via conductors 21C penetrating one or more insulating layers 21A are provided. The uppermost via conductor 21C is connected to the uppermost conductive layer 21B. Furthermore, the aforementioned relay line 23 is constituted by individual units of each topmost wire 21D, and the relay line 23 is also constituted by each wire 21D below the topmost layer, the via conductors 21C at both ends, and a portion of the uppermost conductive layer 21B on these via conductors 21C. Moreover, both ends of each relay line 23 are exposed on the first wiring structure 20X through through holes 21K formed in the uppermost insulating layer 21A, becoming the aforementioned connection points 22.

[0037] like Figure 5B as well as Figure 5CAs simplified, the second and third wiring structures 20Y and 20Z are basically the same as the first wiring structure 20X, except that they have a glass layer 26 instead of a silicon layer 25, or neither a silicon layer 25 nor a glass layer 26.

[0038] The planar dimensions of the wiring structures 20 increase in the order of the first wiring structure 20X, the second wiring structure 20Y, and the third wiring structure 20Z. Similarly, the minimum L / S ratio of the line 21D increases in the order of the first wiring structure 20X, the second wiring structure 20Y, and the third wiring structure 20Z. Specifically, regarding the width L of the line 21D, the first wiring structure 20X has a width of 0.5μm to 2μm, the second wiring structure 20Y has a width of 2μm to 3μm, and the third wiring structure 20Z has a width of 3μm to 5μm. Furthermore, regarding the width S of the space between the lines 21D, the first wiring structure 20X has a width of 0.5μm to 2μm, the second wiring structure 20Y has a width of 2μm to 3μm, and the third wiring structure 20Z has a width of 3μm to 5μm.

[0039] Furthermore, in the wiring substrate 10 of this embodiment, the plurality of wiring structures 20 are arranged symmetrically, but they may not be arranged symmetrically, and the orientation of the plurality of wiring structures 20 may not be uniform. Additionally, the wiring substrate 10 has three types of wiring structures 20, but the types of wiring structures 20 disposed on the wiring substrate 10 may be two or more. Furthermore, not all electronic components 100 may be connected through wiring structures 20; for example, a portion of the pad 101 of the electronic component 100 may also be connected to the third conductive layer 14 from the top in the wiring substrate 10 via metal pillars 19 and via conductors 15.

[0040] The above is a description of the wiring board 10 of this embodiment. Next, referring to... Figures 6A-7C The manufacturing method of the wiring substrate is explained. (1) Preparation of core substrate 11. Core substrate 11 is a general substrate on which through-hole conductors 18 and conductive layers 14 are formed on a substrate on which copper foil is laminated on the front and back sides of a glass cloth impregnated with resin. Next, an insulating layer 13 is laminated on the core substrate 11, and a conductive layer 14 is laminated thereon by a known method (e.g., semi-additive method). Next, six layers of each of the insulating layer 13 and conductive layer 14 are laminated by the same method. At this time, a planar layer 14P is formed on the fifth conductive layer 14 from the side of the core substrate 11. In addition, a plurality of through-hole conductors 15 are formed on the plurality of insulating layers 13 respectively (see Figure 6A ).

[0041] (2) Further overlap of insulating layer 13. This insulating layer 13 corresponds to the lower insulating layer 13A in the outermost insulating layer 13. Next, CO2 laser is irradiated onto the portion of the lower insulating layer 13A that overlaps on the planar layer 14P to form a cavity 30 that penetrates the lower insulating layer 13A and the adjacent insulating layer 13 (see reference). Figure 6B ).

[0042] (3) The walls and bottom of the cavity 30 are cleaned by permanganate treatment, and the surface of the planar layer 14P is treated with CZ. Next, wiring structures 20 are arranged inside the cavity 30. These wiring structures 20 are heated and pressurized by a joint (not shown), and the adhesive layer 28 on the bottom surface of the wiring structure 20 is tightly attached to the planar layer 14P (see reference). Figure 6C ).

[0043] (4) When an insulating resin film (e.g., ABF) is superimposed on the upper surface of the wiring structure 20 and the cavity 30 and heated and pressurized, the melted resin enters the gap between the side surface of the wiring structure 20 and the wall surface of the cavity 30, and the upper insulating layer 13B of the outermost insulating layer 13 is stacked. Then, a UV laser is irradiated toward the portion of the outermost insulating layer 13 that overlaps with the plurality of connection points 22 of the wiring structure 20 to form a plurality of vias 15H (refer to...). Figure 7A ).

[0044] (5) When the resist is removed by chemical plating, resist treatment, or electroplating, a conductive layer 14 is stacked on the insulating layer 13, and a via conductor 15 is formed in the via 15H. A via pad 15A is formed at the upper end of the via conductor 15 (refer to...). Figure 7B ).

[0045] (6) Next, an outermost insulating layer 13, serving as a solder resist layer, is stacked on the conductive layer 14. An opening 13H is formed by a known method, such as photolithography, to expose the via pad 15A of the via conductor 15. Then, the outermost insulating layer 13 is sequentially subjected to chemical plating, resist plating, and electroplating. If the resist plating is removed, a metal pillar 19 is formed within the opening 13H, and a pad 19A is formed at the upper end of the metal pillar 19 on its upper surface (see reference). Figure 7C ).

[0046] (7) After placing the electronic component 100 on the metal pillar 19 by a chip assembly machine (not shown), a reflow process is performed to mount the electronic component 100 on the metal pillar 19.

[0047] Furthermore, the metal pillar 19 in this embodiment is formed by plating, but solder can also be formed in the opening 13H instead of the metal pillar 19.

[0048] The manufacturing method of the wiring substrate 10 has been described above. The structure of the wiring substrate 10 according to this embodiment has the following effects. In the current technology, the minimum L / S and the maximum achievable planar size differ among the three wiring structures 20: the first wiring structure 20X containing a silicon layer 25, the second wiring structure 20Y containing a glass layer 26, and the third wiring structure 20Z containing neither a silicon layer nor a glass layer. Furthermore, in the current technology, the minimum achievable L / S increases from small to large, and the maximum achievable planar size increases from small to large, according to the order of the first, second, and third wiring structures 20X, 20Y, and 20Z.

[0049] On the other hand, the requirements for the degree of integration and the size of the planar dimensions of the electronic components 100 mounted on the wiring substrate 10 vary greatly depending on their type. However, even if it is desired to make the wiring of the wiring structure 20 dense to match the densely arranged electronic components 100 with multiple pads, it is sometimes difficult to meet the requirements of high integration in wiring structures with glass layers or wiring structures without support layers. In addition, even if the wiring structure 20 is made large to mount large electronic components 100, it is difficult to make the planar dimensions large in wiring structures with silicon layers formed by cutting from a circular silicon wafer, and even if it can be made large, it is prone to breakage, resulting in durability problems. That is, if a wiring substrate 10 with only one type of wiring structure 20 is mounted for various electronic components 100, problems such as reduced durability may occur.

[0050] In contrast, the wiring substrate 10 of this embodiment has two or more wiring structures 20 with different planar dimensions and minimum L / S, such as the first to third wiring structures 20X, 20Y, and 20Z. Therefore, it is possible to install various electronic components 100 with different contents required for high integration.

[0051] [Second Implementation]

[0052] In the second embodiment described above, each of the plurality of electronic components 100 has a first region R1 and a second region R2 with different pad spacing, and the first region R1 and the second region R2 of adjacent electronic components 100 are connected by a wiring structure 20. Furthermore, in the wiring structure 20, in order to make the connection points 22 correspond to the pads 101, the plurality of connection points 22 arranged in the first array region R3 and the second array region R4 are spaced at the same distance from each other. In this embodiment, the arrangement spacing of the plurality of connection points 22 in the first array region R3 and the second array region R4 is different from that in the above embodiment. Hereinafter, refer to... Figures 8-10C This only illustrates the differences from the first embodiment.

[0053] like Figure 9 As shown, in this embodiment, electronic components 100A, 100B, 100C, and 100D are mounted on the wiring substrate 10. For electronic components 100 other than electronic component 100A, a plurality of pads 101 are arranged in a matrix on the entire lower surface. On the other hand, for example, for electronic component 100A, a plurality of pads 101 are arranged in a matrix on the entire area of ​​the lower surface, excluding the quadrilateral region in the center. Furthermore, the spacing of the pads 101 of the electronic components 100 varies depending on the type of electronic component 100; for example, the spacing increases in the order of electronic components 100D, 100A, 100B, and 100C.

[0054] Furthermore, the planar dimensions of the pad 101 are approximately the same as those of the pads 101 of electronic components 100A, 100B, and 100C other than electronic component 100D, and the planar dimensions of the pad 101 of electronic component 100D are smaller compared to them. In this embodiment, the overall planar dimensions of electronic components 100A, 100B, 100C, and 100D are in the same order as the aforementioned pad spacing. That is, for example, the planar dimensions increase in size in the order of electronic components 100D, 100A, 100B, and 100C.

[0055] like Figure 9 As shown, the pad spacing of adjacent electronic components 100A and 100B, and electronic components 100B and 100C, is different. Therefore, the multiple connection points 22 of the wiring structure 20 connected to the multiple pads 101 of these electronic components 100 are spaced differently in the first array region R3 and the second array region R4, with the arrangement spacing in the second array region R4 being larger than that in the first array region R3.

[0056] Specifically, regarding the spacing of the connection points 22 (hereinafter, appropriately referred to as "connection point spacing"), the second array region R4 of the first wiring structure 20A is the same as the first array region R3 of the second wiring structure 20B (see reference). Figure 10A , Figure 10B The second array region R4 of the second wiring structure 20B is the same as the first array region R3 of the third wiring structure 20C (see reference). Figure 10B , Figure 10CThat is, regarding the spacing between connection points, the first array region R3 of the first wiring structure 20A has the smallest spacing, followed by the second array region R4 of the first wiring structure 20A and the first array region R3 of the second wiring structure 20B. Then, the second array region R4 of the second wiring structure 20B and the first array region R3 of the third wiring structure 20C have the smallest spacing, while the second array region R4 of the third wiring structure 20C has the largest spacing. Furthermore, regarding the planar dimensions of the wiring structures 20, the first wiring structure 20A has the smallest, the second wiring structure 20B has the second smallest, and the third wiring structure 20C has the largest.

[0057] exist Figure 9 In the middle, a pair of second wiring structures 20B are symmetrically arranged on the left and right sides of the central region directly below the portion of the electronic component 100A that does not have a pad 101, and a pair of third wiring structures 20C are arranged on the opposite side of the pair of second wiring structures 20B in the central region (in Figure 9 In the diagram, only one side of the third wiring structure 20C is shown. Additionally, in... Figure 9 A pair of first wiring structures 20A are symmetrically arranged on the upper and lower sides of the central region. That is, a pair of first wiring structures 20A, a pair of second wiring structures 20B, and a pair of third wiring structures 20C are symmetrically arranged with the central region as the center.

[0058] And, as Figure 8 As shown, multiple connection points 22 of the second array region R4 of a pair of first wiring structures 20A and multiple connection points 22 of the first array region R3 of a pair of second wiring structures 20B are arranged directly below multiple pads 101 that become electronic components 100A. Multiple connection points 22 of the second array region R4 of each second wiring structure 20B and multiple connection points 22 of the first array region R3 of the adjacent third wiring structure 20C of each second wiring structure 20B are arranged directly below multiple pads 101 that become electronic components 100B. Moreover, multiple connection points 22 of the second array region R4 of each third wiring structure 20C are arranged directly below multiple pads 101 that become electronic components 100B in each electronic component 100C.

[0059] According to the wiring structure 20 of the second embodiment, the spacing between the connection points 22 is different in the first array region R3 and the second array region R4, so electronic components 100 with different spacing of pads 101 can be connected to each other via the wiring structure 20.

[0060] Furthermore, as with the relationship between the first and second wiring structures 20A and 20B, and the relationship between the second and third wiring structures 20B and 20C, by making the spacing of the connection points 22 the same in the second array region R4 of one wiring structure 20 and the first array region R3 of the other wiring structure 20, electronic components 100 with different spacing of pads 101 can be connected to each other via the wiring structure 20.

[0061] Furthermore, in the wiring substrate 10 of this embodiment, the spacing of the connection points 22 of the first wiring structure 20A, the second wiring structure 20B, and the third wiring structure 20C increases in two stages. That is, regarding the spacing of the connection points 22, the second array region R4 of the first wiring structure 20A is the same as the first array region R3 of the second wiring structure 20B, and the second array region R4 of the second wiring structure 20B is the same as the first array region R3 of the third wiring structure 20C. In this way, by providing a structure in which the spacing of the connection points 22 among three or more wiring structures 20 is relatively large and related across multiple stages, three or more electronic components 100 with different spacing of the pads 101 can be connected to each other via multiple wiring structures 20.

[0062] [Other Implementation Methods]

[0063] (1) In the above embodiment, all of the first, second, and third wiring structures 20X, 20Y, and 20Z are present, but only two of these three may be present. For example, the wiring substrate 10 may only have the first and second wiring structures 20X and 20Y, and the minimum L / S of the relay line 23 increases from small to large according to the order of the first and second wiring structures 20X and 20Y. Alternatively, the wiring substrate 10 may only have the second and third wiring structures 20Y and 20Z, and the minimum L / S of the plurality of relay lines 23 increases from small to large according to the order of the second and third wiring structures 20Y and 20Z. Furthermore, the wiring substrate 10 may only have the first and third wiring structures 20X and 20Z, and the minimum L / S of the plurality of relay lines 23 increases from small to large according to the order of the first and third wiring structures 20X and 20Z.

[0064] (2) Alternatively, all the wiring structures 20X, 20Y, and 20Z with the same spacing of all connection points 22 may coexist with wiring structures 20A, 20B, and 20C with different spacing in the first array region R3 and the second array region R4.

[0065] (3) As described above, in the current technology, the minimum achievable L / S and the maximum achievable planar dimension increase from small to large in the order of the first wiring structure 20X containing a silicon layer 25, the second wiring structure 20Y containing a glass layer 26, and the third wiring structure 20Z containing neither a silicon layer nor a glass layer. However, the minimum L / S and planar dimension of the first, second, and third wiring structures 20X, 20Y, and 20Z provided on the wiring substrate 10 may not follow the achievable order. As long as the minimum L / S or planar dimension of two wiring structures 20 among the various wiring structures 20 provided on the wiring substrate 10 are different from each other, wiring structures 20 of different types may include wiring structures with the same minimum L / S and planar dimension, or wiring structures in the opposite order to the achievable order.

[0066] Specifically, in the wiring structure 20X with silicon layer 25 and the wiring structure 20Y with glass layer 26, the L / S ratio of the trunk line 23 can be the same, and the planar dimensions of the wiring structure 20Y with glass layer 26 and the wiring structure 20Z without either silicon layer 25 or glass layer 26 can also be the same. Furthermore, for example, the minimum L / S ratio of the wiring structure 20Y with glass layer 26 can be made smaller than that of the wiring structure 20X with silicon layer 25, and the planar dimension of the wiring structure 20Z without either silicon layer 25 or glass layer 26 can be made smaller than that of the wiring structure 20Y with glass layer 26. That is, considering the type of electronic component 100 installed, the space available for configuring the wiring structure 20, etc., the most suitable wiring structure 20 can be selected from those with silicon layer 25, those with glass layer 26, those without silicon layer 25, and those without glass layer 26.

[0067] (4) In the above embodiments, such as Figure 2 As shown, electronic component 100X and electronic component 100Y disposed to the right of electronic component 100X, and electronic component 100X and electronic component 100Y disposed to the left of electronic component 100X, are independently connected through two second wiring structures 20Y, but they can also be connected through a single second wiring structure 20Y extending from the right electronic component 100Y to the left electronic component 100Y. Specifically, the trunk line 23 connecting electronic component 100X to the right electronic component 100Y and the trunk line 23 connecting electronic component 100X to the left electronic component 100Y can also be centrally formed within the second wiring structure 20Y.

[0068] (5) In the above-described embodiments, the plurality of relay lines 23 of each wiring structure 20 are configured to relay a portion of all pads 101 of two electronic components 100 to each other. However, for example, they may also be configured to relay all pads 101 of one electronic component 100 to a portion of a plurality of pads 101 of another electronic component 100. In addition, the wiring structure 20 of the previous embodiment is configured to relay two electronic components 100 to each other, but it may also be configured to relay the pads 101 of three or more electronic components 100 to each other.

[0069] (6) On the wiring structure 20, the insulation layer 13 may be stacked in two or more layers, or in only one layer. In addition, adjacent wiring structures 20 may be arranged at different heights in the stacking direction.

[0070] (7) The wiring structure 20 may not be a layered structure. For example, it may be a structure in which the relay line 23 is formed inside glass, silicon or other materials.

[0071] Furthermore, specific examples of the technology included in the claims are disclosed in this specification and the accompanying drawings, but the technology described in the claims is not limited to these specific examples, and also includes examples obtained by various modifications and alterations to the specific examples, as well as examples obtained by taking a part of the specific examples separately.

Claims

1. A wiring substrate having a plurality of wiring structures and cavities for housing the plurality of wiring structures, wherein the plurality of wiring structures have a plurality of relay lines embedded therein, and the two ends of the plurality of relay lines are exposed on the upper surface of the plurality of wiring structures as a plurality of connection points, wherein, The plurality of wiring structures includes two or more of the following: a first wiring structure with a silicon layer at the bottom, a second wiring structure with a glass layer at the bottom, and a third wiring structure with a resin layer at the bottom that does not include a glass layer or a silicon layer. The planar dimensions of the two or more wiring structures or the minimum L / S of the plurality of trunks are different, where L represents the width of the trunk and S represents the width of the space between the trunks.

2. The wiring substrate according to claim 1, wherein, The wiring substrate has a multilayer structure consisting of a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer stacked sequentially from bottom to top. The cavity is formed to penetrate both the second insulating layer and the third insulating layer.

3. The wiring substrate according to claim 1, wherein, The wiring substrate has two types of wiring structures: the first wiring structure and the second wiring structure. In the order of the first wiring structure and the second wiring structure, the minimum L / S of the plurality of trunk lines increases from small to large and the planar dimensions increase from small to large.

4. The wiring substrate according to claim 1, wherein, The wiring substrate has two wiring structures: the second wiring structure and the third wiring structure. In accordance with the order of the second wiring structure and the third wiring structure, the minimum L / S of the plurality of trunk lines increases from small to large and the planar dimensions increase from small to large.

5. The wiring substrate according to claim 1, wherein, The wiring substrate has two wiring structures: the first wiring structure and the third wiring structure. In the order of the first wiring structure and the third wiring structure, the minimum L / S of the plurality of trunk lines increases from small to large and the planar dimensions increase from small to large.

6. The wiring substrate according to claim 1, wherein, The wiring substrate has three wiring structures: the first wiring structure, the second wiring structure, and the third wiring structure. In the order of the first wiring structure, the second wiring structure, and the third wiring structure, the minimum L / S of the plurality of trunk lines increases from small to large, and their planar dimensions also increase from small to large.

7. The wiring substrate according to claim 1, wherein, The wiring substrate has a wiring structure, which is any one of the first wiring structure, the second wiring structure, and the third wiring structure, and... The wiring structure has: A first array region, in which the plurality of connection points are arranged in a matrix and connected to the pads of the first electronic component; as well as In the second array region, the plurality of connection points are arranged in a matrix with the same spacing as in the first array region and are connected to the pads of the second electronic components.

8. The wiring substrate according to claim 1, wherein, The plurality of connection points are arranged in a matrix, and the spacing between the plurality of connection points varies between different types of wiring structures.

9. The wiring substrate according to any one of claims 1 to 8, wherein, The wiring substrate contains electronic components with multiple pads on its lower surface. The plurality of pads of the electronic component are configured and connected to locations that overlap with the plurality of connection points of the two or more wiring structures from above.

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