A low on-resistance schottky diode and a preparation method thereof

Abstract

The application relates to the technical field of diodes, and particularly discloses a low-conduction-resistance Schottky diode and a preparation method thereof. The diode comprises a front metal electrode layer, a Schottky contact layer, a heavily doped barrier weakening layer, a barrier modulation transition layer, an N-type epitaxial layer, an N+ type silicon substrate layer, a back ohmic contact layer and a back metal electrode layer. The heavily doped barrier weakening layer is an N++ type monocrystalline silicon layer arranged between the Schottky contact layer and the barrier modulation transition layer, and is used for reducing the Schottky barrier width and forming a quasi-tunneling type carrier injection path under an ultralow-temperature condition. Through synergic regulation of the barrier height, the barrier width and the doping distribution of the Schottky contact area, the carrier transport mechanism is gradually transitioned from thermal emission to field-assisted injection and quasi-tunneling mode under a low-temperature condition, so that the forward conduction voltage drop and the conduction resistance under the conditions of -40 DEG C and -55 DEG C are effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of diode technology, specifically to a low on-resistance Schottky diode and its fabrication method. Background Technology

[0002] Schottky diodes, also known as hot-carrier diodes, are semiconductor diodes with low forward voltage drop and very fast switching action. Their applications are extremely wide; it's fair to say that almost any scenario involving smart devices relies on this component. However, different environmental parameters in different scenarios place different demands on the performance of Schottky diodes. For example, in low-temperature (-20~-40℃) light-load instantaneous control scenarios at altitudes of 3000-4000 meters, existing Schottky diodes suffer from a relatively high initial on-resistance under low temperature and light load conditions. Furthermore, the device has weak self-heating, and the junction temperature cannot rise quickly enough, preventing the internal resistance from recovering through self-heating, resulting in a high on-voltage drop and affecting the sensitivity and power consumption of the control loop. Specific applications include solenoid valve drives in high-altitude mines and industrial PLC switching outputs. This is clearly a technical problem that needs to be solved. The technical problem this invention aims to solve is how to provide a low-on-resistance Schottky diode for low-temperature scenarios to meet the requirements of low temperatures. Summary of the Invention

[0003] The purpose of this invention is to provide a low on-resistance Schottky diode and its fabrication method to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A low on-resistance Schottky diode and its fabrication method, the diode comprising:

[0006] Front metal electrode layer;

[0007] Schottky contact layer;

[0008] Heavily doped barrier weakening layer;

[0009] Barrier modulation transition layer;

[0010] N-type epitaxial layer;

[0011] N-type silicon substrate;

[0012] Backside ohmic contact layer;

[0013] Backside metal electrode layer;

[0014] The heavily doped barrier weakening layer is an N⁺⁺ type single-crystal silicon layer with a thickness of 20-40 nm and a doping concentration of (1-3) × 10⁻⁶. 19 cm-3 A layer is disposed between the Schottky contact layer and the barrier modulation transition layer to reduce the width of the Schottky barrier and form a quasi-tunneling carrier injection path under ultra-low temperature conditions. The barrier modulation transition layer is an N⁺-type silicon layer with a thickness of 80-150 nm. The doping concentration is distributed in a gradient decreasing distribution from the side near the Schottky contact layer to the side near the N-type epitaxial layer to reduce the metal-semiconductor contact resistance and suppress the rise of reverse leakage current under low temperature conditions.

[0015] As a further aspect of the present invention: the Schottky contact layer includes an intrinsic silicon interface passivation layer disposed between the metal electrode and the semiconductor, the thickness of the intrinsic silicon interface passivation layer being 3-8 nm, and the corresponding equivalent Schottky barrier height being 0.56-0.65 eV.

[0016] As a further aspect of the present invention: the front metal electrode layer is an Au-Ni alloy layer, wherein the mass ratio of Au to Ni is 6:4-7:3, which is used to maintain the structural stability of the metal-silicon interface and reduce the contact resistance under low temperature or ultra-low temperature conditions.

[0017] As a further aspect of the present invention: the thickness of the N-type epitaxial layer is 6.0-7.5 μm, and the doping concentration is (2.5-4.0) × 10⁻⁶. 17 cm -3 It is used to reduce the proportion of volume resistivity under low temperature conditions.

[0018] As a further aspect of the present invention: the N⁺ type silicon substrate layer is <100> Crystalline monocrystalline silicon has a resistivity of 0.001-0.005 Ω·cm.

[0019] As a further aspect of the present invention: the back ohmic contact layer is a Ti / Al alloy layer, wherein the mass ratio of Ti to Al is 1:9, and the back metal electrode layer is a Ni / Au double-layer structure.

[0020] The present invention also provides a method for fabricating a low on-resistance Schottky diode, the method comprising:

[0021] Step S1: Grow an N-type epitaxial layer on an N⁺-type silicon substrate;

[0022] Step S2: Form a barrier modulation transition layer on the surface of the N-type epitaxial layer;

[0023] Step S3: Form a heavily doped barrier weakening layer on the surface of the barrier modulation transition layer;

[0024] Step S4: Form a Schottky contact layer on the surface of the heavily doped barrier weakening layer;

[0025] Step S5: Form a front metal electrode layer on the Schottky contact layer;

[0026] Step S6: A back ohmic contact layer and a back metal electrode layer are sequentially formed on the back side of the silicon substrate;

[0027] Step S7: Perform rapid thermal annealing on the device.

[0028] As a further aspect of the present invention: the heavily doped barrier weakening layer in step S3 is formed by low-energy ion implantation, with an implantation energy of 3-5 keV and an implantation dose of (5-8) × 10⁻⁶. 14 cm -2 It is activated by rapid thermal annealing, wherein the rapid thermal annealing temperature is 440-450℃ and the holding time is 20-40s.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows: By synergistically controlling the barrier height, barrier width and doping distribution of the Schottky contact region, the present invention enables the carrier transport mechanism to gradually transition from thermal emission to field-assisted injection and quasi-tunneling modes under low temperature conditions, thereby effectively reducing the forward conduction voltage drop and conduction resistance under -40℃ and -55℃ conditions, and avoiding the conduction degradation problem caused by barrier control in conventional structures at low temperatures. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention.

[0031] Figure 1 This is a flowchart illustrating the fabrication method of a low on-resistance Schottky diode.

[0032] Figure 2 This is a schematic diagram of a low on-resistance Schottky diode.

[0033] In the figure: 1-front metal electrode layer, 2-Schottky contact layer, 3-heavily doped barrier weakening layer, 4-barrier modulation transition layer, 5-N-type epitaxial layer, 6-N⁺-type silicon substrate layer, 7-back metal electrode layer. Detailed Implementation

[0034] To make the technical problems, solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] Regarding the materials and equipment used in the embodiments, the methods used in this invention are all conventional methods known to those skilled in the art unless otherwise specified. The reagents and other materials used are all commercially available products unless otherwise specified. Some of the materials and equipment involved are described below:

[0036] Material:

[0037] Substrate: <100> The substrate is an N⁺-type single-crystal silicon substrate with a resistivity of 0.001~0.005 Ω·cm and a thickness of 350±10μm. It is polished on both sides and free of lattice defects.

[0038] Dopant sources: phosphine (PH3, 99.999% purity), borane (B2H6, 99.999% purity, for isolation only). PH3 needs to be diluted to 1% before use.

[0039] Metal targets: Au target (99.999%), Ni target (99.999%), Ti target (99.999%), Al target (99.999%), target size Φ50.8mm×3mm (general specification for magnetron sputtering);

[0040] Passivation materials: tetraethoxysilane (TEOS, purity 99.999%), Ar / O2 mixed gas (Ar:O2=95:5, purity 99.999%).

[0041] Etching reagents: BOE etching solution (HF:NH4F=1:6, buffer etching), SF6 / O2 mixed gas for ICP etching (SF6:O2=8:2), Au etching solution (KI / I2 / H2O=10:1:50), Ni etching solution (FeCl3 solution), dilute HF (5%).

[0042] Cleaning reagents: acetone, anhydrous ethanol, deionized water (18.2 MΩ·cm), piranha solution (H2SO4:H2O2=3:1, freshly prepared and used);

[0043] Photolithography consumables: positive photoresist (AZ6130), developer (AZ300MIF), 2 photomasks (Schottky junction photomask and metal electrode photomask, 1μm precision, positive);

[0044] Packaging consumables: 0805 ceramic packaging base, conductive silver paste, gold wire (diameter 25μm), metal cap / epoxy resin encapsulating adhesive.

[0045] equipment:

[0046] Cleaning equipment: Ultrasonic cleaner (300W power, 40kHz frequency), Class 100 clean bench, high-temperature cleaning oven;

[0047] Epitaxial equipment: Low-pressure chemical vapor deposition (LPCVD) equipment (preferred, for good epitaxial layer uniformity), or plasma-enhanced CVD (PECVD).

[0048] Metal deposition equipment: magnetron sputtering system (including RF / DC power supply, capable of simultaneously loading 4 targets to achieve alloy co-sputtering);

[0049] Etching equipment: wet etching stage (with temperature control), inductively coupled plasma etching (ICP) equipment (for dry etching of isolation areas);

[0050] Annealing equipment: Rapid thermal annealing (RTA) equipment (nitrogen atmosphere, temperature control accuracy ±1℃, heating rate ≥100℃ / s), diffusion furnace;

[0051] Photolithography equipment: UV lithography machine (365nm, resolution ≥1μm), spin coater, developer, and drying machine;

[0052] Characterization / testing equipment: High and low temperature test chamber (temperature control range -60~150℃, accuracy ±0.5℃), semiconductor device characteristic tester (measuring IV / CV curves), step meter (measuring film thickness), four-probe tester (measuring sheet resistance), ion implanter (dedicated to Example 3, low energy, 3~5keV).

[0053] Packaging equipment: diamond dicing machine, gold wire ball bonding machine, laser sealing machine / epoxy resin encapsulation machine.

[0054] Example 1

[0055] In this embodiment of the invention, a low on-resistance Schottky diode and its fabrication method are provided, the diode comprising:

[0056] The front metal electrode layer is an Au-Ni alloy (mass ratio 7:3), with a thickness of 320 nm and an electrode area of ​​0.12 mm² (0.3 mm × 0.4 mm).

[0057] The low-barrier Schottky contact layer includes an intrinsic silicon interface passivation layer with an intrinsic silicon layer thickness of 8 nm (uniformity ≤ 1 nm), an equivalent Schottky barrier height φSB = 0.65 eV (room temperature CV method), and an interface state density ≤ 1 × 10⁻⁶. 11 cm -2 Among them, the bottom layer of the low barrier Schottky contact layer is the intrinsic silicon interface passivation layer, which is directly attached to the epitaxial layer below. The top layer is the metal-semiconductor direct contact interface, which is directly superimposed on the intrinsic silicon passivation layer and in close contact with the front metal electrode layer above. It is the core of forming the Schottky barrier and realizing carrier transport.

[0058] A shallow junction, highly doped N-type epitaxial layer, made of N-type single-crystal silicon (phosphorus doped), with a thickness of 7 μm and a doping concentration of 3 × 10⁻⁶. 17 cm -3 Sheet resistance 80Ω (uniformity ≤ ±5%);

[0059] The N-type silicon substrate layer is made of N-type silicon. <100> Monocrystalline silicon, 350 μm thick, doping concentration 5 × 10⁻⁶ 19 cm -3 The resistivity is 0.005 Ω·cm.

[0060] The back ohmic contact layer is made of a Ti / Al alloy with a mass ratio of 1:9, with a thickness of 220nm, an ohmic contact resistance of ≤0.1Ω, and fully covers the back of the substrate.

[0061] The back metal electrode layer is made of a Ni / Au dual-layer structure, with a Ni layer thickness of 100nm (for adhesion enhancement and oxidation prevention) and an Au layer thickness of 200nm (for improved conductivity).

[0062] The preparation method is as follows:

[0063] Step 1: Ultra-clean cleaning of N⁺ substrate:

[0064] 1. Cutting: Take an N⁺ silicon substrate and cut it into 2cm×2cm square pieces using a diamond dicing machine (fitting the laboratory equipment cavity). Use dust-free tweezers to pick them up and place them in an ultrasonic cleaning basket.

[0065] 2. Acetone ultrasonic treatment: 300W power, 40kHz frequency, room temperature, 10min, to remove surface organic contaminants (oil, dust).

[0066] 3. Anhydrous ethanol ultrasonication: 300W power, 40kHz frequency, room temperature, 10min, to remove acetone residue;

[0067] 4. Deionized water ultrasonic cleaning: 300W power, 40kHz frequency, room temperature, 5min, to remove alcohol residue. Shake the cleaning basket to ensure no residue on both sides.

[0068] 5. Piranha immersion: Operate in a fume hood (wearing anti-corrosion gloves / goggles), immerse in freshly prepared piranha solution (H2SO4:H2O2=3:1), at room temperature, for 20 minutes to remove carbon contamination and form a uniform oxide layer;

[0069] 6. Dilute HF immersion: 5% dilute HF, room temperature, 30 seconds, precisely removes the natural oxide layer on the surface, exposing the fresh silicon surface (avoiding excessively long etching time or excessively short etching time leaving oxide layer residue).

[0070] 7. Rinse with deionized water: Rinse with running deionized water (18.2 MΩ·cm) for 5 minutes, gently shake the container to ensure no HF residue remains;

[0071] 8. Drying: Dry the glue in a 120℃ oven for 10 minutes to completely remove surface moisture;

[0072] 9. Transfer: Immediately after cleaning, transfer to the epitaxial process. Exposure time in air should be ≤5 minutes to avoid re-oxidation.

[0073] Step 2: Growth of N⁺ ultrathin shallow junction epitaxial layer:

[0074] 1. Equipment Pretreatment: Turn on the LPCVD equipment and evacuate to 1×10⁻⁶. -3 Pa, introduce N2 carrier gas (200 sccm), purge the chamber for 5 min to remove impurities and oxygen;

[0075] 2. Substrate placement: Place the dried substrate evenly into the LPCVD chamber tray, ensuring good contact and no tilting;

[0076] 3. Degassing: Evacuate to 1×10 -3 Pa, heat to 1050℃ (heating rate 50℃ / min), hold for 10min, remove residual gas inside the substrate;

[0077] 4. Epitaxial growth: Introduce N2 (200 sccm) + SiH4 (50 sccm) + PH3 (5 sccm, diluted to 1%), growth pressure 200 Pa, temperature 1050 ℃, time 45 min (pre-experiment calibration: 1 min ≈ 0.15 μm, ensure thickness 7 μm).

[0078] 5. End of growth: Turn off SiH4 and PH3, maintain N2 flow rate at 200 sccm, and cool to room temperature (cooling rate 30℃ / min to avoid epitaxial layer cracking).

[0079] 6. Sample removal: After the chamber cools to room temperature, introduce N2 at atmospheric pressure and remove the epitaxial wafer.

[0080] Step 3: Etching and passivation of the isolation area:

[0081] 1. Spin coating and baking: The epitaxial wafer is placed in a spin coater and fixed by vacuum adsorption; positive photoresist (AZ6130) is spin-coated at 3000 r / min for 30 s (resin thickness 1.5 μm); pre-baking is carried out at 95℃ for 1 min and post-baking is carried out at 120℃ for 2 min.

[0082] 2. Photolithography exposure: Attach a Schottky junction photomask (0.3mm×0.4mm for a single junction surface, 50μm for the isolation region), and align it precisely; expose using an ultraviolet lithography machine (wavelength 365nm, exposure dose 150mJ / cm²).

[0083] 3. Development and fixing: Develop with developer (AZ300MIF) at room temperature for 45 seconds, fix with deionized water for 1 minute; bake at 150℃ for 5 minutes to form the photoresist mask for the isolation area;

[0084] 4. ICP dry etching: Place the equipment into the ICP etching apparatus, introduce SF6 / O2 mixed gas (8:2) at a flow rate of 50 sccm; etch power of 300 W, bias voltage of 50 W, pressure of 1 Pa, time of 60 s, and etch depth to the substrate layer (approximately 7.5 μm).

[0085] 5. Resin removal and cleaning: Soak in acetone for 10 minutes to remove photoresist; rinse with running deionized water for 5 minutes; dry in a drying oven at 120℃ for 10 minutes;

[0086] 6. Surface passivation: A TEOS passivation layer is deposited using a PECVD equipment at a temperature of 300℃ and a pressure of 50Pa, with SiH4 / O2 = 1:4 and a thickness of 8nm.

[0087] Step 4: Schottky barrier layer fabrication:

[0088] 1. Plasma pretreatment: The passivated epitaxial wafer is placed in the PECVD chamber, and an Ar / O2 mixed gas (95:5) is introduced at a flow rate of 50 sccm, a power of 200 W, a pressure of 10 Pa, and a time of 5 min to activate the junction surface and remove trace contaminants.

[0089] 2. Intrinsic Si barrier layer deposition: magnetron sputtering, DC sputtering of pure Si target (99.999%), Ar gas 30 sccm, pressure 0.5 Pa, power 150 W, time 10 s, deposition thickness 8 nm.

[0090] Step 5: Front-side metal electrode deposition and shaping:

[0091] 1. Equipment pretreatment: Turn on the magnetron sputtering machine and evacuate to 5×10⁻⁶. -4 Pa, introduce Ar gas (30 sccm), and purge the cavity for 5 minutes;

[0092] 2. Sample placement: Place the epitaxial wafer with the barrier layer deposited into the cavity, with the junction surface facing upwards and securely fixed;

[0093] 3. Co-sputtering deposition: Au target power 140W, Ni target power 60W (mass ratio 7:3), Ar gas 30sccm, pressure 0.3Pa, time 120s, deposition thickness 320nm;

[0094] 4. Photolithography and Etching: The process is as follows: Spin-coating AZ6130 photoresist at 3000 r / min for 30 s; pre-baking at 95℃ for 1 min, and post-baking at 120℃ for 2 min; Exposure: Apply metal electrode photomask (front electrode matched with junction surface, lead width 80 μm), and UV exposure (365 nm, 150 mJ / cm²); Development: Develop with AZ300MIF developer at room temperature for 45 s, fix with deionized water for 1 min; harden the film at 150℃ for 5 min; Wet etching: First immerse in Au etching solution (KI / I2 / H2O=10:1:50) at room temperature for 20 s; then immerse in Ni etching solution (FeCl3) at room temperature for 15 s; Remove photoresist: Soak in acetone for 10 min, rinse with deionized water for 5 min, and dry at 120℃ for 10 min.

[0095] Step 6: Deposition of back ohmic contact layer + back metal electrode:

[0096] 1. Sample pretreatment: Turn the epitaxial wafer over so that the back side is facing up; immerse in 5% dilute HF for 10 seconds to remove the oxide layer on the back side; rinse with deionized water for 5 minutes; dry in a drying oven at 120℃ for 10 minutes.

[0097] 2. Ohmic contact layer deposition: magnetron sputtering co-sputtering, Ti target 20W, Al target 180W (mass ratio 1:9), Ar gas 30sccm, pressure 0.3Pa, time 80s, thickness 220nm;

[0098] 3. Backside metal electrode deposition: First, sputter a Ni target (100W, 40s, 100nm thickness), then sputter an Au target (100W, 80s, 200nm thickness) to fully cover the backside.

[0099] Step 7: Rapid thermal annealing:

[0100] 1. Equipment pretreatment: Turn on the RTA equipment, introduce high-purity N2 (99.999%) at a flow rate of 200 sccm, and purge the chamber for 5 minutes;

[0101] 2. Sample placement: Place the sample with deposited front and back electrodes into the cavity, ensuring it is evenly spread and heated uniformly;

[0102] 3. Annealing parameters: heating rate 100℃ / s, heating to 450℃, holding for 30s; cooling rate 80℃ / s, cooling to room temperature; maintaining N2 flow rate of 200sccm throughout the process;

[0103] 4. Sample removal: Remove the sample after it has reached room temperature and observe that there is no oxidation color on the surface (oxidation requires re-annealing).

[0104] The functions of each layer in the above content are explained as follows:

[0105] The Ni layer in the front metal electrode layer enhances the adhesion between the metal film and the underlying layer, preventing Au detachment at low temperatures and ensuring contact stability. A low-barrier Schottky contact layer passivates metal-semiconductor interface defects, reducing contact resistance. Precise control of the barrier height adapts to temperatures as low as -40°C, balancing low on-resistance and low reverse leakage current. A shallow-junction, highly doped N-type epitaxial layer reduces the proportion of semiconductor resistance during the light-load transient conduction phase at low temperatures; the doping concentration balances low resistance and barrier stability, ensuring efficient carrier transport. An N⁺-type silicon substrate layer reduces current transport losses, provides mechanical support, and perfectly matches the epitaxial layer lattice, preventing performance degradation caused by interface stress. The back ohmic contact layer uses low-resistance ohmic contacts to ensure efficient current extraction without additional contact resistance, improving low-temperature conduction efficiency and adapting to light-load transient conditions. The Ni layer in the back metal electrode layer prevents Al oxidation and enhances adhesion to the substrate. The Au layer improves welding performance and conductivity, adapting to industrial welding processes and preventing contact failure at low temperatures.

[0106] Example 2

[0107] In this embodiment of the invention, a low on-resistance Schottky diode and its fabrication method are provided. Based on Example 1, the materials have been optimized, specifically as follows:

[0108] A barrier modulation transition layer was added between the low-barrier Schottky contact layer and the shallow-junction, highly doped N-type epitaxial layer. The barrier modulation transition layer was made of N⁺-type single-crystal silicon (phosphorus-doped), with a thickness of 100 nm and a peak doping concentration of 10 × 10⁻⁶. 17 cm -3 The gradient decays downwards to the concentration in the epitaxial layer; it can form a current-preferential conduction region under low temperature and light load, significantly reducing the initial conduction contact resistance; gradient doping avoids the formation of a high-stress interface with the epitaxial layer and does not increase the reverse leakage current.

[0109] Accordingly, the preparation method of the barrier modulation transition layer is as follows:

[0110] 1. Pretreatment: After the epitaxial wafer has been etched and cleaned in the isolation area (corresponding to step 3 in Example 1), it is immersed in 5% dilute HF for 30 seconds to remove the surface oxide layer; rinsed with deionized water for 5 minutes, and dried in a baking oven at 120℃ for 10 minutes;

[0111] 2. Diffusion preparation: Turn on the diffusion furnace, introduce N2 carrier gas (200 sccm), heat to 850℃ (heating rate 50℃ / min), hold for 5 min, and stabilize the furnace temperature;

[0112] 3. Phosphorus diffusion: Place the epitaxial wafer in a diffusion furnace and introduce N2 carrier gas (200 sccm) + PH3 (1% diluted, flow rate 10 sccm). The diffusion time is 25 s (precise control to ensure a layer thickness of 100 nm).

[0113] 4. Rapid cooling: Turn off PH3, maintain N2 flow rate at 200 sccm, and rapidly cool to room temperature (cooling rate 80℃ / min) to avoid excessive diffusion of doping.

[0114] Example 3:

[0115] Please see Figure 1 and Figure 2 In this embodiment of the invention, a low on-resistance Schottky diode and its fabrication method are provided. Based on Example 2, the materials are optimized by adding an extremely thin, heavily doped barrier weakening layer between the low-barrier Schottky metal contact layer and the barrier modulation transition layer. Simultaneously, the low-barrier Schottky metal contact layer and the barrier modulation transition layer are finely tuned. The overall structure includes: a front metal electrode layer 1; a Schottky contact layer 2; a heavily doped barrier weakening layer 3; a barrier modulation transition layer 4; an N-type epitaxial layer 5; an N⁺-type silicon substrate layer 6; a back ohmic contact layer; and a back metal electrode layer 7. In the figure, the back ohmic contact layer and the back metal electrode layer 7 are actually two layers in a single whole layer.

[0116] The overall preparation method is as follows:

[0117] Step S1: Grow an N-type epitaxial layer on an N⁺-type silicon substrate;

[0118] Step S2: Form a barrier modulation transition layer on the surface of the N-type epitaxial layer;

[0119] Step S3: Form a heavily doped barrier weakening layer on the surface of the barrier modulation transition layer;

[0120] Step S4: Form a Schottky contact layer on the surface of the heavily doped barrier weakening layer;

[0121] Step S5: Form a front metal electrode layer on the Schottky contact layer;

[0122] Step S6: A back ohmic contact layer and a back metal electrode layer are sequentially formed on the back side of the silicon substrate;

[0123] Step S7: Perform rapid thermal annealing on the device;

[0124] The specific differences from Example 2 are as follows:

[0125] The intrinsic silicon layer thickness in the low-barrier Schottky metal contact layer is 4 nm (uniformity ≤ ±1 nm), the equivalent Schottky barrier height φSB = 0.56 eV (room temperature CV method), and the interface state density ≤ 1 × 10⁻⁶. 11 cm -2 The barrier modulation transition layer has a thickness of 120 nm (slightly thicker than in Example 2) and a doping concentration of 7 × 10⁻⁶. 17 cm-2 The gradient decays downwards to the concentration of the epitaxial layer; the former actually lowers the potential barrier in one step, reducing the difficulty for carriers to cross the barrier at ultra-low temperatures; the passivation layer is thinned to reduce the obstruction of carrier transport; the latter adjusts the thickness to buffer the abrupt doping changes between the weakening layer and the epitaxial layer, avoiding stress concentration and a sharp increase in leakage current; it further reduces the contact resistance to ensure the stability of leakage current at ultra-low temperatures.

[0126] For the ultrathin heavily doped barrier weakening layer, the material used is N⁺⁺ type single crystal silicon (phosphorus doped), with a thickness of 30 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 With uniformity ≤±10%, it can form a near-tunneling contact region at -55℃, significantly reducing the barrier width; carrier injection can be triggered by a small current of 1~3mA, solving the problem of hysteresis conduction; the ultra-thin design avoids high-stress interfaces and leakage current. Its fabrication method is as follows:

[0127] After the isolation area etching and cleaning was completed, the epitaxial wafer was immersed in 5% dilute HF for 20 seconds (30 seconds in Example 2) to remove the surface oxide layer; rinsed with deionized water for 5 minutes; and dried in a baking oven at 120°C for 10 minutes.

[0128] Turn on the low-energy ion implanter and evacuate to 1×10⁻⁶. -4 Pa, place the epitaxial wafer into the cavity, fix it firmly, with the junction surface facing upwards;

[0129] Implantation parameters: P⁺ ion implantation was used, with an implantation energy of 4 keV (it is strictly forbidden to exceed 5 keV, otherwise the layer will be too deep), and an implantation dose of 6 × 10⁻⁶. 14 cm -2 The injection rate is uniform; after injection is complete: turn off the ion source, introduce N2 carrier gas (100 sccm), and remove the epitaxial wafer after cooling to room temperature, ensuring that the surface is undamaged.

[0130] RTA-activated annealing:

[0131] Turn on the RTA equipment and introduce high-purity N2 (200 sccm) to purge the chamber for 5 minutes; Annealing parameters: heating rate 100℃ / s, heat to 850℃, hold for 6 seconds (strictly control the time to avoid excessive doping diffusion); cooling rate 80℃ / s, cool to room temperature.

[0132] The fine-tuning process for preparing the barrier modulation transition layer is the same as that in Example 2, and the fine-tuning is as follows:

[0133] The diffusion time was 30 s (25 s in Example 2) to ensure a layer thickness of 120 nm; the peak doping concentration was 7 × 10⁻⁶. 17 cm -3 (Example 2 is 10×10) 17 cm -3);

[0134] During surface passivation, consistent with Example 2, a TEOS passivation layer was deposited by PECVD; however, the deposition thickness was 4 nm to ensure uniformity ≤ ±1 nm.

[0135] Comparative Example 1

[0136] In this embodiment of the invention, a low on-resistance Schottky diode and its fabrication method are provided, the diode comprising:

[0137] The front metal electrode layer is made of pure Au, with a thickness of 300±50nm, an electrode area of ​​0.12mm², and a contact resistance of ≥0.5Ω (room temperature).

[0138] Schottky contact layer, without passivation layer, direct contact between metal and semiconductor, equivalent Schottky barrier height φSB = 0.75 eV (room temperature), interface state density ≥ 5 × 10⁻⁶ 11 cm -2 ;

[0139] The N-type epitaxial layer is made of N-type single-crystal silicon, with a thickness of 12 μm and a doping concentration of 8 × 10⁻⁶. 16 cm -3 The sheet resistance is 200 ohms per square meter;

[0140] The N⁺ type silicon substrate layer is made of N⁺ type material. <100> Monocrystalline silicon, 350 μm thick, doping concentration 2 × 10⁻⁶ 19 cm -3 The resistivity is 0.005 Ω·cm.

[0141] The back ohmic contact layer is made of pure Al, with a thickness of 200 nm and an ohmic contact resistance ≥ 0.3 Ω (room temperature).

[0142] The back metal electrode layer is made of pure Au and has a thickness of 200 nm.

[0143] Its preparation method is as follows:

[0144] Step 1: Simple cleaning of N⁺ substrate:

[0145] 1. Cutting: Take an N⁺ silicon substrate and cut it into 2cm×2cm square pieces using a diamond dicing machine. Use dust-free tweezers to pick them up and place them in an ultrasonic cleaning basket.

[0146] 2. Acetone ultrasound: 300W power, 40kHz frequency, room temperature, 8min, to remove surface organic contaminants;

[0147] 3. Anhydrous ethanol ultrasonication: 300W power, 40kHz frequency, room temperature, 8min, to remove acetone residue;

[0148] 4. Deionized water ultrasonication: 300W power, 40kHz frequency, room temperature, 5min, to remove alcohol residue;

[0149] 5. Immersion in dilute HF: 5% dilute HF, room temperature, 1 min (too long, will over-corrode the surface) to remove the surface oxide layer;

[0150] 6. Rinse with deionized water: Rinse with running deionized water for 3 minutes (rinsing may not be thorough);

[0151] 7. Drying: Dry the glue in a 100℃ oven for 15 minutes to remove surface moisture;

[0152] 8. Transfer: After cleaning, expose to air for 10 minutes (it is prone to secondary oxidation) before transferring to the epitaxial process;

[0153] 9. Inspection: If there are no obvious stains or scratches on the substrate surface when observed with the naked eye, it is considered qualified (no precision inspection is required).

[0154] Step 2: Growth of N-type epitaxial layer:

[0155] 1. Equipment pretreatment: Turn on the LPCVD equipment and evacuate to 5×10⁻⁶. -3 Pa, introduce N2 carrier gas (150 sccm), and purge the chamber for 3 min;

[0156] 2. Substrate placement: Place the dried substrate into the LPCVD chamber tray; precise positioning is not required.

[0157] 3. Degassing: Evacuate to 5×10 -3 Pa, heat to 1000℃ (heating rate uncontrolled), hold for 8 minutes;

[0158] 4. Epitaxial growth: N2 (150 sccm) + SiH4 (40 sccm) + PH3 (3 sccm, diluted to 1%) were introduced, with a growth pressure of 300 Pa, a temperature of 1000 ℃, and a time of 70 min (thickness 12 μm).

[0159] 5. End of growth: Turn off SiH4 and PH3, and allow to cool naturally to room temperature (without temperature control rate, it is easy to cause cracking of the epitaxial layer);

[0160] 6. Sample removal: After the chamber cools to room temperature, remove the epitaxial wafer.

[0161] Step 3: Etching of the isolation area:

[0162] 1. Spin coating and baking: The epitaxial wafer is placed in a spin coater and coated with positive photoresist (AZ6130) at 2500 r / min for 30 s (resist thickness is not uniform); pre-baking is done at 90℃ / 1 min and post-baking is done at 110℃ / 2 min.

[0163] 2. Photolithography exposure: Schottky junction photomask is applied, with no precise alignment requirements; ultraviolet lithography exposure (wavelength 365nm, exposure dose not precisely controlled);

[0164] 3. Development and fixing: Develop with developer (AZ300MIF) at room temperature for 60 seconds (overdevelopment), fix with deionized water for 1 minute; harden the film at 140℃ for 5 minutes in a drying oven;

[0165] 4. ICP dry etching: Place the equipment into the ICP etching apparatus, introduce SF6 gas (single gas, no O2), flow rate 40 sccm; etching power 250W, bias voltage uncontrolled, pressure 2Pa, time 80s (irregular etching depth).

[0166] 5. Resin removal and cleaning: Soak in acetone for 8 minutes to remove photoresist; rinse with running deionized water for 3 minutes; dry in a drying oven at 100℃ for 15 minutes.

[0167] Step 4: Schottky contact layer preparation:

[0168] 1. Sample pretreatment: Rinse the etched epitaxial wafer with deionized water for 2 minutes, then dry it in a baking oven at 100℃ for 5 minutes;

[0169] 2. Direct contact fabrication: No plasma activation or intrinsic Si passivation layer deposition is required; the process proceeds directly to the front metal electrode deposition step (direct contact between metal and semiconductor).

[0170] Step 5: Front-side metal electrode deposition and shaping:

[0171] 1. Equipment pretreatment: Turn on the magnetron sputtering machine and evacuate to 1×10⁻⁶. -3 Pa, introduce Ar gas (25 sccm), purge the cavity for 3 minutes;

[0172] 2. Sample placement: Place the epitaxial wafer into the cavity with the junction surface facing upwards;

[0173] 3. Pure Au deposition: Sputtering pure Au target, power 150W, Ar gas 25sccm, pressure 0.5Pa, time 100s, deposition thickness 300nm;

[0174] 4. Photolithography and etching: The steps of coating, exposure, development and etching are the same as in step 3. The process is rough and lacks precise control.

[0175] Step 6: Deposition of back ohmic contact layer + back metal electrode:

[0176] 1. Sample pretreatment: Turn the epitaxial wafer over so that the back side is facing up; rinse with deionized water for 2 minutes, dry in a glue oven at 100℃ for 5 minutes;

[0177] 2. Ohmic contact layer deposition: sputtering pure Al target, power 180W, Ar gas 25sccm, pressure 0.5Pa, time 70s, thickness 200nm;

[0178] 3. Backside metal electrode deposition: sputtering pure Au target, power 150W, Ar gas 25sccm, pressure 0.5Pa, time 80s, thickness 200nm.

[0179] Step 7: Dicing + Packaging

[0180] 1. Dicing: Diamond dicing machine, speed 8mm / s, depth not precisely controlled, divides along the isolation zone into individual devices (0.8mm×0.5mm, 0805 package); dust-free air gun blows away debris;

[0181] 2. Chip bonding: Apply conductive silver paste to the pads of the 0805 ceramic package base (thickness not controlled); bond the chip to the base, and cure the silver paste in a baking oven at 140℃ for 25 minutes;

[0182] 3. Bonding: Gold wire ball bonding machine, gold wire diameter 25μm, bonding temperature and pressure are not precisely controlled, as long as there are no broken wires visible to the naked eye after bonding;

[0183] 4. Sealing: Epoxy resin encapsulant, cured at room temperature for 2 hours (curing without heating, which may cause bubbles).

[0184] Test objectives and methods:

[0185] 1. Forward conduction voltage drop (Vf):

[0186] The test temperatures were room temperature (25℃), -40℃, and -55℃. The device was placed in the high and low temperature test chamber, the corresponding temperature was set, and the temperature was maintained for 30 minutes. The semiconductor device characteristic tester was adjusted to the "forward conduction test mode", the device was connected (the positive and negative terminals were correctly matched), and the forward current was gradually adjusted to the set value (read the value after stabilizing for 3 seconds). The forward voltage drop Vf at the corresponding current was recorded. Each current point was measured 3 times, and the average value was taken (to reduce the error).

[0187] Forward conduction voltage drop is positively correlated with conduction resistance (at a fixed current, the smaller Vf is, the lower the conduction resistance); at the same temperature and current, the difference in Vf between the example and the comparative example directly reflects the low conduction advantage of the optimized scheme.

[0188] 2. On-resistance (rf):

[0189] The test temperatures were room temperature (25℃), -40℃, and -55℃, and the "four-probe method" was used for measurement: the device was fixed on the probe stage of the high and low temperature test chamber, and the four probes were respectively in contact with the front electrode and the back electrode of the device (to ensure good contact). The test temperature was set and kept at that temperature for 30 minutes. A 1mA forward current was applied, and the voltage drop between the probes was measured. The contact resistance rc was calculated using the formula (rc = voltage drop / test current). The measurement was repeated 3 times, and the average value was taken.

[0190] The test data is as follows:

[0191] Table 1

[0192] Forward conduction voltage drop Vf (mV) On-resistance rf (Ω) Comparative Example 1 230 3.4 Example 1 221 2.8 Example 2 216 2.8 Example 3 213 2.5

[0193] Table 2

[0194] Forward conduction voltage drop Vf (mV) On-resistance rf (Ω) Comparative Example 1 290 13.4 Example 1 231 6.3 Example 2 214 5.3 Example 3 196 4.9

[0195] Table 3

[0196] Forward conduction voltage drop Vf (mV) On-resistance rf (Ω) Comparative Example 1 423 32.0 Example 1 295 12.1 Example 2 257 9.6 Example 3 240 6.0

[0197] Tables 1, 2, and 3 correspond to the specific parameters under normal temperature (25℃), -40℃, and -55℃ conditions, respectively. Based on the data, Example 3 is identified as the optimal example.

[0198] Data Explanation:

[0199] The forward conduction of silicon-based Schottky diodes mainly relies on the carrier transport behavior at the metal-semiconductor interface. Under normal temperature conditions, the forward current is mainly dominated by the "thermal emission mechanism," in which electrons overcome the Schottky barrier and inject into the metal under thermal excitation. When the ambient temperature decreases, especially below −40°C, the thermal energy of the carriers decreases significantly, the thermal energy required for electrons to overcome the barrier height is insufficient, the thermal emission efficiency drops sharply, and the equivalent width of the Schottky barrier increases. In addition, as the depletion layer in the semiconductor widens with temperature, the barrier region's blocking effect on the carriers is enhanced. At this time, in the low current region, the device conduction characteristics are no longer determined by the bulk resistance but by the interface barrier, resulting in an increase in forward voltage drop and conduction hysteresis.

[0200] In the above description, Example 1 primarily improves low-temperature conduction characteristics by reducing the equivalent barrier height at the Schottky contact interface and increasing the doping level of the N-type epitaxial layer. In this structure: reducing the barrier height lowers the energy threshold required for thermionic emission; increasing the doping concentration of the epitaxial layer helps shorten the depletion layer width, thereby reducing the equivalent resistance of the barrier region; within a temperature range of approximately −40°C, thermionic emission remains the dominant conduction mechanism, and this structure can effectively reduce the forward voltage drop in the low-current region. However, as the temperature decreases further, the thermionic emission efficiency drops sharply, and the improvement effect of this structure gradually becomes limited.

[0201] Based on Example 1, Example 2 introduces a barrier modulation transition layer below the Schottky contact interface. This layer employs a gradient doping design. The physical effects of this structure are mainly reflected in: smoothing the electric field distribution in the barrier region; gradient doping avoids high field concentration caused by abrupt junctions, keeping the equivalent width of the barrier region controllable under low-temperature conditions; furthermore, reducing the temperature sensitivity of the contact resistance; by increasing the concentration of free carriers near the interface, the conduction behavior is not entirely dependent on the thermal excitation process, suppressing abnormal fluctuations in low-temperature reverse leakage; and the smooth electric field distribution reduces leakage channels induced by local high fields. Especially in the range of −40℃ to −50℃, the carrier transport mechanism of Example 2 gradually transitions from a single thermal emission to a hybrid thermal emission-tunneling mechanism, enabling the device to maintain a low on-resistance at even lower temperatures.

[0202] Furthermore, when the temperature drops to -55°C, the thermal emission mechanism can hardly maintain stable conduction under milliampere current conditions. In Example 3, the equivalent width of the Schottky barrier is actively shortened by structural means, so that the carrier transport mechanism is transformed into quasi-tunneling dominance. To this end, an extremely thin (20-40 nm), extremely highly doped N⁺⁺ type barrier weakening layer is set directly below the Schottky contact interface. The physical functions of this layer include: significantly compressing the depletion layer width, greatly reducing the thickness of the space charge layer in the barrier region due to extremely high doping, and enhancing the interface electric field strength. Under low temperature conditions, an electric field environment conducive to field-assisted carrier injection is formed, which triggers the quasi-tunneling conduction process. Even if the electron thermal energy is insufficient to cross the barrier, it can enter the metal electrode through tunneling or quasi-tunneling. Therefore, Example 3 can still quickly enter a stable conduction state under the conditions of -55°C and 1-10 mA small current, and the sensitivity of conduction behavior to temperature changes is significantly reduced.

[0203] This invention does not simply reduce the barrier height, but rather engineers and controls the spatial structure of the barrier region; enabling the conduction mechanism to automatically transition from thermal emission to tunneling dominance with temperature changes; and achieving rapid conduction of small currents in low-temperature and ultra-low-temperature environments while ensuring controlled reverse leakage.

[0204] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low on-resistance Schottky diode, characterized in that, The diode includes: Front metal electrode layer; Schottky contact layer; Heavily doped barrier weakening layer; Barrier modulation transition layer; N-type epitaxial layer; N-type silicon substrate; Backside ohmic contact layer; Backside metal electrode layer; The heavily doped barrier weakening layer is an N⁺⁺ type single-crystal silicon layer with a thickness of 20-40 nm and a doping concentration of (1-3) × 10⁻⁶. 19 cm -3 A layer is disposed between the Schottky contact layer and the barrier modulation transition layer to reduce the width of the Schottky barrier and form a quasi-tunneling carrier injection path under ultra-low temperature conditions. The barrier modulation transition layer is an N⁺-type silicon layer with a thickness of 80-150 nm. The doping concentration is distributed in a gradient decreasing distribution from the side near the Schottky contact layer to the side near the N-type epitaxial layer to reduce the metal-semiconductor contact resistance and suppress the rise of reverse leakage current under low temperature conditions.

2. The low on-resistance Schottky diode according to claim 1, characterized in that, The Schottky contact layer includes an intrinsic silicon interface passivation layer disposed between the metal electrode and the semiconductor. The thickness of the intrinsic silicon interface passivation layer is 3-8 nm, and the corresponding equivalent Schottky barrier height is 0.56-0.65 eV.

3. The low on-resistance Schottky diode according to claim 1, characterized in that, The front metal electrode layer is an Au-Ni alloy layer, wherein the mass ratio of Au to Ni is 6:4-7:3, which is used to maintain the structural stability of the metal-silicon interface and reduce the contact resistance under low temperature or ultra-low temperature conditions.

4. The low on-resistance Schottky diode according to claim 1, characterized in that, The thickness of the N-type epitaxial layer is 6.0-7.5 μm, and the doping concentration is (2.5-4.0) × 10⁻⁶. 17 cm -3 It is used to reduce the proportion of volume resistivity under low temperature conditions.

5. The low on-resistance Schottky diode according to claim 1, characterized in that, The N⁺-type silicon substrate layer is <100> Crystalline monocrystalline silicon has a resistivity of 0.001-0.005 Ω·cm.

6. The low on-resistance Schottky diode according to claim 1, characterized in that, The back ohmic contact layer is a Ti / Al alloy layer, wherein the mass ratio of Ti to Al is 1:9, and the back metal electrode layer is a Ni / Au double-layer structure.

7. A method for fabricating a low on-resistance Schottky diode as described in any one of claims 1 to 6, characterized in that, The preparation method includes: Step S1: Grow an N-type epitaxial layer on an N⁺-type silicon substrate; Step S2: Form a barrier modulation transition layer on the surface of the N-type epitaxial layer; Step S3: Form a heavily doped barrier weakening layer on the surface of the barrier modulation transition layer; Step S4: Form a Schottky contact layer on the surface of the heavily doped barrier weakening layer; Step S5: Form a front metal electrode layer on the Schottky contact layer; Step S6: A back ohmic contact layer and a back metal electrode layer are sequentially formed on the back side of the silicon substrate; Step S7: Perform rapid thermal annealing on the device.

8. The method for fabricating a low on-resistance Schottky diode according to claim 7, characterized in that, The heavily doped barrier weakening layer in step S3 is formed by low-energy ion implantation, with an implantation energy of 3-5 keV and an implantation dose of (5-8) × 10⁻⁶. 14 cm -2 It is activated by rapid thermal annealing, wherein the rapid thermal annealing temperature is 440-450℃ and the holding time is 20-40s.

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