GaN HEMT preparation method and GaN HEMT

Abstract

The invention discloses a GaN HEMT preparation method and a GaN HEMT, and belongs to the technical field of semiconductors, and the method comprises the steps: forming an epitaxial structure on the surface of a substrate, and forming an isolation region, a source electrode and a drain electrode in the epitaxial structure; forming a first passivation protection layer on the surface, deviating from the substrate, of the epitaxial structure, and forming a gate pin groove in the first passivation protection layer between the source electrode and the drain electrode; forming a mask material film in the gate pin groove, and gathering the mask material film through surface tension to form a micro mask with a nano array structure; after the two-dimensional electron gas in the epitaxial structure which is not covered by the micro-mask is cut off, the micro-mask is removed, and a gate array structure is formed; and forming a gate in the gate pin groove with the gate array structure to obtain the GaN HEMT. According to the invention, the two-dimensional electron gas in the partial region below the gate pin is cut off based on the simple micro-mask, the width of the effective channel region is reduced, the gate voltage swing of the device is increased, and the linearity performance is improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of semiconductors, in particular to a GaN HEMT preparation method and GaN HEMT. BACKGROUND

[0002] Linearity is a core performance index of a radio frequency power amplifier, and nonlinear distortion will limit the performance of a device. A GaN HEMT (High Electron Mobility Transistor) has become a preferred device for a base station radio frequency PA (Power Amplifier) due to advantages of high power density, wide frequency band and high efficiency, but its inherent nonlinear characteristics are still a technical bottleneck. Therefore, how to improve the linearity performance of the GaN HEMT is a technical problem to be solved by the person skilled in the art at present. SUMMARY

[0003] The application aims to provide a GaN HEMT preparation method and GaN HEMT, so as to improve the linearity performance of the GaN HEMT.

[0004] To achieve the above-mentioned purpose, the application provides a GaN HEMT preparation method, which comprises the following steps:

[0005] An epitaxial structure is formed on a substrate surface, and an isolation region, a source electrode and a drain electrode are formed in the epitaxial structure;

[0006] A first passivation protection layer is formed on a surface of the epitaxial structure away from the substrate, and a gate pin recess is formed in the first passivation protection layer between the source electrode and the drain electrode;

[0007] A mask material film is formed in the gate pin recess, and the mask material film is gathered to form a micro mask with a nano array structure through surface tension;

[0008] After two-dimensional electron gas in the epitaxial structure not covered by the micro mask is disconnected, the micro mask is removed, and a gate array structure is formed;

[0009] A gate electrode is formed in the gate pin recess with the gate array structure, and the GaN HEMT is obtained.

[0010] Optionally, the step of forming the gate pin recess in the first passivation protection layer between the source electrode and the drain electrode comprises:

[0011] The gate pin recess is formed in the first passivation protection layer between the source electrode and the drain electrode, and the first passivation protection layer below the gate pin recess is reserved;

[0012] Correspondingly, the breaking of the two-dimensional electron gas in the epitaxial structure not covered by the micro mask further comprises:

[0013] Removing the first passivation protection layer under the gate foot groove.

[0014] Optionally, the forming of the epitaxial structure on the substrate surface, and the forming of the isolation region, the source and the drain in the epitaxial structure comprises:

[0015] Sequentially epitaxially growing a composite buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the substrate surface in a direction away from the substrate to form the epitaxial structure;

[0016] The isolation region is formed on both sides of the laminated structure composed of the channel layer, the insertion layer, the barrier layer and the cap layer along the length direction respectively;

[0017] The source and the drain are formed between the isolation region on the same side and the isolation region on the same side of the laminated structure composed of the barrier layer and the cap layer along the length direction respectively.

[0018] Optionally, the breaking of the two-dimensional electron gas in the epitaxial structure not covered by the micro mask comprises:

[0019] The cap layer, the barrier layer, the insertion layer and part of the thickness of the channel layer not covered by the micro mask are etched by an etching process to break the two-dimensional electron gas in the epitaxial structure.

[0020] Optionally, the breaking of the two-dimensional electron gas in the epitaxial structure not covered by the micro mask comprises:

[0021] The lattices of the cap layer, the barrier layer, the insertion layer and part of the thickness of the channel layer not covered by the micro mask are broken by an ion implantation process to break the two-dimensional electron gas in the epitaxial structure.

[0022] Optionally, the forming of the gate in the gate foot groove with the gate array structure comprises:

[0023] A gate pattern is defined at the position of the gate foot groove with the gate array structure by a photolithography process;

[0024] A gate material is evaporated on the surface of the epitaxial structure with the gate pattern by an electron beam evaporation process;

[0025] The gate material corresponding to the non-gate pattern is stripped by a stripping process;

[0026] After the stripping process is completed, an annealing process is performed to form the gate.

[0027] Optionally, after forming the gate in the gate foot groove with the gate array structure, the method further comprises:

[0028] forming a second passivation protection layer on the epitaxial structure surface with the gate.

[0029] Optionally, the mask material thin film is a metal thin film; and the gathering of the mask material thin film through surface tension to form the micro mask with the nano array structure comprises:

[0030] annealing under a nitrogen atmosphere to gather the mask material thin film through the surface tension to form the micro mask with the nano array structure.

[0031] Optionally, the forming of the mask material thin film in the gate foot groove comprises:

[0032] forming the mask material thin film in the gate foot groove through an electron beam evaporation process or a magnetron sputtering process.

[0033] To achieve the above object, the application further provides a GaN HEMT prepared by the GaN HEMT preparation method.

[0034] Obviously, the GaN HEMT preparation method provided by the application relies on the surface tension of the mask material to gather the micro mask with the nano array structure at the gate foot position; by using the simple micro mask and based on the micro mask to disconnect the two-dimensional electron gas in the part of the area below the gate foot, the effective channel width is effectively reduced, the gate voltage swing of the device is increased, and the linearity performance of the GaN HEMT is optimized and improved. In the process of manufacturing, the method reduces the difficulty of the photolithography process and reduces a layer of high-precision photolithography mask plate; without introducing new equipment, the micro mask with high precision can be made, the device performance is further improved, and the development cost is reduced. The application further provides a GaN HEMT, which has the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only belong to the embodiments of the application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0036] Figure 1 a flow chart of the GaN HEMT preparation method provided by the embodiments of the application;

[0037] Figures 2 to 11A flowchart of a GaN HEMT preparation method provided by an embodiment of the present application.

[0038] 1 - substrate; 2 - composite buffer layer; 21 - nucleation layer; 22 - buffer layer; 3 - channel layer; 4 - insertion layer; 5 - barrier layer; 6 - cap layer; 7 - isolation region; 81 - source electrode; 82 - drain electrode; 9 - first passivation protection layer; 10 - gate foot recess; 11 - mask material film; 12 - micro mask; 13 - gate array structure; 131 - recess; 14 - gate; 15 - second passivation protection layer. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0040] With the evolution of 5G / 6G communication technology towards high frequency bands (millimeter waves), high modulation complexity, and multi-carrier aggregation, the linearity of radio frequency power amplifiers has become a core performance indicator. Nonlinear distortion will directly lead to problems such as modulation signal error vector magnitude (EVM) deterioration, adjacent channel leakage ratio (ACLR) exceeding the standard, and system bit error rate (BER) rising, thereby limiting the spectral efficiency and data transmission rate.

[0041] GaN HEMT has become the preferred device for base station radio frequency PA (Power Amplifier) due to its high power density, wide frequency band, and high efficiency advantages, but its inherent nonlinear characteristics are still a technical bottleneck.

[0042] Current solutions to improve linearity have obvious shortcomings, such as: (1) circuit-level compensation (such as DPD, the full name of English is Digital Pre-Distortion, Chinese is digital pre-distortion): high-precision modeling is required, and the bandwidth is limited, and the algorithm complexity increases sharply in the wideband multi-carrier scenario; (2) extension structure design (such as gradient AlGaN layer) only partially improves the transconductance flatness, and it is difficult to suppress high-frequency capacitance nonlinearity; (3) circuit topology improvement (such as Doherty architecture, Doherty architecture is a commonly used power amplifier structure): high dependence on the linearity of the device itself, and efficiency and bandwidth trade-off; (4) traditional linearization techniques (such as feedback, feedforward) will introduce additional loss and reduce power added efficiency (PAE); (4) device manufacturing process: traditional methods of fin-shaped nanowire channels / planar nanowire channels require an additional photomask, which is complex and requires higher precision photolithography machines.

[0043] Therefore, the present application provides a GaN HEMT preparation method, which improves the linearity performance of GaN HEMT by using a micro-mask with a nanometer array structure and disconnecting the two-dimensional electron gas in the part of the area below the gate pin based on the micro-mask.

[0044] Please refer to Figure 1 , Figure 1 A flowchart of a GaN HEMT preparation method provided by the embodiment of the present application, which can include:

[0045] S101: Form an epitaxial structure on the surface of the substrate, and form an isolation region, a source and a drain in the epitaxial structure.

[0046] The embodiment does not limit the specific type of substrate 1, for example, the material of substrate 1 can be silicon, sapphire or silicon carbide.

[0047] The embodiment does not limit the specific way of forming the epitaxial structure, the isolation region 7, the source 81 and the drain 82, which can be determined according to the specific structure of the epitaxial structure, for example, the following way can be used:

[0048] The composite buffer layer 2, the channel layer 3, the insertion layer 4, the barrier layer 5 and the cap layer 6 are epitaxially grown in sequence on the surface of the substrate 1 in the direction away from the substrate 1, forming an epitaxial structure;

[0049] The isolation region 7 is formed on both sides of the laminated structure composed of the channel layer 3, the insertion layer 4, the barrier layer 5 and the cap layer 6 in the length direction.

[0050] The source 81 and the drain 82 are formed between the isolation region 7 on the same side and the barrier layer 5 and the cap layer 6 on the same side in the laminated structure along the length direction.

[0051] It should be noted that the epitaxial structure in this embodiment is a heterojunction epitaxial structure.

[0052] This embodiment does not limit the specific type of the composite buffer layer 2. For example, the composite buffer layer 2 may include, but is not limited to, a nucleation layer 21 and a buffer layer 22 sequentially disposed along the direction away from the substrate 1. This embodiment does not limit the specific thickness of the composite buffer layer 2. For example, the thickness of the composite buffer layer 2 may be 300 nm to 1.5 μm, including the values ​​at both ends.

[0053] This embodiment does not limit the specific type of nucleation layer 21. The material of nucleation layer 21 can be, but is not limited to, a group III nitride, which can be AlN or GaN. This embodiment does not limit the specific type of buffer layer 22. For example, the material of buffer layer 22 can be, but is not limited to, a group III nitride, which can be AlGaN or GaN. In this embodiment, nucleation layer 21 can be epitaxially grown on the surface of substrate 1 at a low temperature of 500℃-650℃; then, the temperature can be raised to 1000℃-1100℃ to epitaxially grow buffer layer 22 on the surface of nucleation layer opposite to substrate 1.

[0054] This embodiment does not limit the specific type of the channel layer 3. For example, the material of the channel layer 3 can be, but is not limited to, a group III nitride, which can be GaN or InGaN. This embodiment does not limit the specific thickness of the channel layer 3. For example, the thickness of the channel layer 3 can be 100nm-300nm, including the values ​​at both ends. It should be noted that in this embodiment, a two-dimensional electron gas (2DEG) is formed on the side of the channel layer 3 near the insertion layer 4.

[0055] This embodiment does not limit the specific type of the insertion layer 4. For example, the material of the insertion layer 4 can be, but is not limited to, a group III nitride, which can be AlN. This embodiment does not limit the specific thickness of the insertion layer 4. For example, the thickness of the insertion layer 4 can be 0.8 nm to 1 nm, including the values ​​at both ends.

[0056] This embodiment does not limit the specific type of barrier layer 5. The material of barrier layer 5 can be, but is not limited to, a group III nitride, such as AlGaN, AlN, or InAlN. This embodiment does not limit the specific thickness of barrier layer 5. For example, the thickness of barrier layer 5 can be 5nm-25nm, including the values ​​at both ends.

[0057] This embodiment does not limit the specific type of the cap layer 6. The material of the cap layer 6 can be, but is not limited to, a group III nitride, which can be GaN. This embodiment does not limit the specific thickness of the cap layer 6. For example, the thickness of the cap layer 6 can be 1 nm to 3 nm, including the values ​​at both ends.

[0058] The embodiment is not limited to a specific way of epitaxial growth, and can be determined according to specific types of film layers in the epitaxial structure. For example, MOCVD (Metal-Organic Chemical Vapor Deposition) equipment can be used to epitaxially grow III-V nitride as the composite buffer layer 2, the channel layer 3, the insertion layer 4, the barrier layer 5, and the cap layer 6 in sequence on the surface of the substrate 1 in a direction away from the substrate 1, to form the epitaxial structure.

[0059] The embodiment is not limited to a specific way of forming the isolation region 7, as long as it can form electrical isolation on the two side surfaces of the composite buffer layer 2 in the length direction. For example, ion implantation technology or mesa isolation technology can be used to form the isolation region 7 on the two sides of the laminated structure composed of the channel layer 3, the insertion layer 4, the barrier layer 5, and the cap layer 6 in the length direction, respectively. The ion implantation technology can include, but is not limited to, using B, N, Ar ions as implantation ions to break the two-dimensional electron gas in the epitaxial structure; the mesa isolation technology can include, but is not limited to, using ICP (Inductively Coupled Plasma) etching technology to break the two-dimensional electron gas in the epitaxial structure. The ICP etching technology is a low-damage etching method.

[0060] The source electrode 81 and the drain electrode 82 in the embodiment are both ohmic electrodes. The positions of the source electrode 81 and the drain electrode 82 in the embodiment can be interchanged. The embodiment is not limited to a specific type of the source electrode 81 or the drain electrode 82. For example, the source electrode 81 or the drain electrode 82 includes any one of Ti / Al, Ti / Al / Ni / Au, Ta / Al / Ta, and Si / Ti / Al / TiN metal stacks. The embodiment is not limited to a specific thickness of the source electrode 81 or the drain electrode 82. For example, the thickness of the source electrode 81 or the drain electrode 82 can be 100 nm-300 nm, and includes both ends.

[0061] The embodiment is not limited to a specific way of forming the source electrode 81 and the drain electrode 82, as long as it can form the source electrode 81 and the drain electrode 82 on the two side surfaces of the trench layer in the length direction, respectively, and both of them are located inside the isolation region 7. For example, etching technology and photolithography technology can be used to form the source electrode 81 and the drain electrode 82 on the two sides of the laminated structure composed of the barrier layer 5 and the cap layer 6 in the length direction, respectively, between the same side isolation region 7.

[0062] S102: Form a first passivation protection layer on the surface of the epitaxial structure away from the substrate, and form a gate pin recess in the first passivation protection layer between the source electrode and the drain electrode.

[0063] The embodiment is not limited to the specific type of the first passivation protection layer 9. For example, the first passivation protection layer 9 can be, but is not limited to, a dielectric layer. The dielectric layer can include a single dielectric layer or a composite dielectric layer of at least one of SiN, SiO2, Al2O3, and AlN. The embodiment is not limited to the specific thickness of the first passivation protection layer 9. For example, the specific thickness of the first passivation protection layer 9 can be 100 nm-200 nm, and the values at both ends are included.

[0064] The embodiment is not limited to the specific way of forming the first passivation layer. For example, as long as the first passivation protection layer 9 can cover the entire surface of the epitaxial structure away from the substrate 1 after forming the isolation region 7, the source electrode 81, and the drain electrode 82, the PECVD (Plasma-Enhanced Chemical Vapor Deposition), ICPCVD (Ion-Beam Assisted Chemical Vapor Deposition), or LPCVD (Low-Pressure Chemical Vapor Deposition) method can be used to form the first passivation protection layer 9 on the surface of the epitaxial structure away from the substrate 1.

[0065] The embodiment is not limited to the specific way of forming the gate leg recess 10. For example, as long as the gate leg recess 10 can be formed in the first passivation protection layer 9 between the source electrode 81 and the drain electrode 82, the gate leg recess 10 can be formed in the first passivation protection layer 9 between the source electrode 81 and the drain electrode 82, and the first passivation protection layer 9 under the gate leg recess 10 can be reserved.

[0066] Further, the step of forming the gate leg recess 10 in the first passivation protection layer 9 between the source electrode 81 and the drain electrode 82 and reserving the first passivation protection layer 9 under the gate leg recess 10 in the embodiment can include, but is not limited to:

[0067] Defining a gate leg recess pattern on the surface of the first passivation protection layer 9 between the source electrode 81 and the drain electrode 82 through a photolithography process;

[0068] Etching the first passivation protection layer 9 with a thickness corresponding to the gate leg recess pattern through an etching process to form the gate leg recess 10 and reserve the first passivation protection layer 9 under the gate leg recess 10.

[0069] It should be noted that the above-mentioned way of forming the gate leg recess 10 in the embodiment does not completely etch the first passivation protection layer 9 under the gate leg recess 10. The purpose is to separate the mask material and the material of the epitaxial structure, inhibit the gate leakage problem of the gate 14, and facilitate the subsequent peeling of the micro mask 12.

[0070] The embodiment is not limited to the specific thickness of the first passivation protection layer 9 reserved under the gate foot groove 10. For example, the thickness of the first passivation protection layer 9 reserved under the gate foot groove 10 can be 5 nm-20 nm, and the values at both ends are included.

[0071] S103: Form a mask material film in the gate foot groove, and make the mask material film gather to form a micro mask with a nano array structure by surface tension.

[0072] The embodiment is not limited to the specific type of mask material. Any material with high surface tension can be used. For example, the mask material can be metal. The metal can include, but is not limited to, Ni. Correspondingly, the mask material film 11 can be a metal film.

[0073] The embodiment is not limited to the specific way of forming the mask material film 11. The specific type of mask material can be determined. For example, when the mask material is metal, the mask material film 11 can be formed in the gate foot groove 10 by an electron beam evaporation process or a magnetron sputtering process.

[0074] It should be noted that when the embodiment uses a photolithography process and an etching process to form the gate foot groove 10, the mask material film 11 can be formed on the surface of the first passivation protection layer 9 with the gate foot groove 10 by an electron beam evaporation process or a magnetron sputtering process after the gate foot groove 10 is formed. The mask material film 11 outside the gate foot groove 10 is removed by a stripping process, and the mask material film 11 in the gate foot groove 10 is reserved.

[0075] The embodiment is not limited to the specific way of triggering surface tension. The specific type of mask material can be determined. For example, when the mask material is metal, annealing can be performed in a nitrogen atmosphere to make the mask material film 11 gather to form a micro mask 12 with a nano array structure by surface tension. It should be noted that when the mask material is metal, the mask material film 11 will form spherical nanoparticles arranged in an array by surface tension, and the spherical nanoparticles arranged in an array will be used as the micro mask 12.

[0076] The embodiment is not limited to the specific equipment for annealing. For example, annealing can be performed in a nitrogen atmosphere by an RTP (Rapid Thermal Processing) or an oven. The embodiment is not limited to the specific process conditions for annealing. For example, the temperature for annealing can be 400°C-900°C, and the values at both ends are included. The time for annealing can be 30 s-600 s, and the values at both ends are included.

[0077] S104: After the two-dimensional electron gas in the epitaxial structure not covered by the micro mask is disconnected, the micro mask is removed to form a gate array structure.

[0078] The embodiment is not limited to the specific way of breaking the two-dimensional electron gas, and can be determined according to the specific structure of the epitaxial structure. For example, the following two ways can be used:

[0079] The epitaxial structure is etched by an etching process to break the two-dimensional electron gas in the epitaxial structure.

[0080] Alternatively, the lattice of the cap layer 6, the barrier layer 5, the insertion layer 4 and the channel layer 3 with a partial thickness which are not covered by the micro mask 12 is broken by an ion implantation process to break the two-dimensional electron gas in the epitaxial structure.

[0081] The etching process can include, but is not limited to, using an ICP etching process to etch the cap layer 6, the barrier layer 5, the insertion layer 4 and the channel layer 3 with a partial thickness which are not covered by the micro mask 12 to break the two-dimensional electron gas in the epitaxial structure. The ion implantation process can include, but is not limited to, using B, N, Ar ions as implantation ions to break the lattice of the cap layer 6, the barrier layer 5, the insertion layer 4 and the channel layer 3 with a partial thickness which are not covered by the micro mask 12 to break the two-dimensional electron gas in the epitaxial structure.

[0082] It should be noted that when the first passivation protection layer 9 under the gate foot groove 10 is retained in step S102 in the embodiment, after the two-dimensional electron gas in the epitaxial structure which is not covered by the micro mask 12 is broken, the first passivation protection layer 9 under the gate foot groove 10 can also be removed.

[0083] The embodiment is not limited to the specific way of removing the micro mask 12 and the first passivation protection layer 9 under the gate foot groove 10, as long as the micro mask 12 and the first passivation protection layer 9 under the gate foot groove 10 can be peeled off from the surface of the epitaxial structure. For example, the inorganic cleaning solution can be used to remove the micro mask 12 and the first passivation protection layer 9 under the gate foot groove 10. The embodiment is not limited to the specific type of the inorganic cleaning solution, and the acid solution can be used, but is not limited thereto.

[0084] S105: Forming a gate electrode in the gate foot groove 10 with a gate array structure to obtain a GaN HEMT.

[0085] The gate electrode 14 in the embodiment is an ohmic electrode. The embodiment is not limited to the specific type of the gate electrode 14, and for example, the gate electrode 14 can include any one of the metal stacks of Ni / Au, Ni / Pt / Au, Ti / Ni / Pt / Au, Ti / Al and W / Ti / Pt / Au.

[0086] The embodiment is not limited to the specific way of forming the gate 14, as long as it can fill the gate leg groove 10, for example, the following way can be used:

[0087] The gate pattern is defined at the position of the gate leg groove 10 with the gate array structure 13 through a photolithography process;

[0088] The gate material is evaporated on the surface of the epitaxial structure with the gate pattern through an electron beam evaporation process;

[0089] The gate material corresponding to the non-gate pattern is stripped through a stripping process;

[0090] After the stripping process is completed, an annealing process is performed to form the gate 14.

[0091] Further, after the gate 14 is formed in the gate leg groove 10 with the gate array structure 13, the embodiment can further include:

[0092] A second passivation protection layer 15 is formed on the surface of the epitaxial structure with the gate 14.

[0093] The embodiment is not limited to the specific type of the second passivation protection layer 15, for example, the second passivation protection layer 15 can be but is not limited to a dielectric layer; the material of the dielectric layer can be but is not limited to SiN. The embodiment is not limited to the specific thickness of the second passivation protection layer 15, for example, the specific thickness of the second passivation protection layer 15 can be 100 nm-200 nm, and the values at both ends are included.

[0094] The embodiment is not limited to the specific way of forming the second passivation layer, as long as it can cover the second passivation protection layer 15 on the entire surface of the epitaxial structure away from the substrate 1 after the gate 14 is formed, for example, the PECVD way or the ICPCVD way can be used to form the second passivation protection layer 15 on the surface of the epitaxial structure with the gate 14.

[0095] Based on the above embodiment, the application relies on the surface tension of the mask material itself to gather at the gate leg position to form a micro mask with a nano array structure; by using a simple micro mask and based on the micro mask to disconnect the two-dimensional electron gas under the gate leg, the effective channel width is reduced, the gate voltage swing of the device is increased, and the linearity performance of the GaN HEMT is optimized and improved. In terms of process manufacturing, this scheme reduces the difficulty of the photolithography process and reduces a layer of high-precision photomask plate; without introducing new equipment, a micro mask with high precision can be made to further improve the device performance and reduce the development cost.

[0096] The embodiment of the application also provides a GaN HEMT prepared by using the GaN HEMT preparation method.

[0097] Based on the above embodiments, this application is prepared by the above GaN HEMT preparation method, so it also has the above-mentioned beneficial effects.

[0098] The following examples illustrate the GaN HEMT fabrication process. Please refer to them. Figures 2 to 11 , Figures 2 to 11 The following is a flowchart illustrating a GaN HEMT fabrication method provided in an embodiment of this application.

[0099] 1. For example Figure 2 The cross-sectional view shown shows that on the surface of substrate 1, group III nitrides are epitaxially grown sequentially in the direction away from substrate 1 using an MOCVD device as a composite buffer layer 2, a channel layer 3, an insertion layer 4, a barrier layer 5, and a cap layer 6 to form an epitaxial structure.

[0100] 2. For example Figure 3 The cross-sectional view shown illustrates that electrical isolation of the device is fabricated by using ion implantation or mesa isolation processes on both sides of the epitaxial structure along the length direction, and isolation regions 7 are formed on both sides of the composite buffer layer 2 along the length direction.

[0101] 3. For example Figure 4 The cross-sectional view shown shows that, through etching and photolithography processes, source 81 and drain 82 are formed on both sides of the stacked structure composed of barrier layer 5 and cap layer 6 along the length direction, respectively, between the isolation region 7 on the same side, to serve as ohmic electrodes.

[0102] 4. For example Figure 5 The cross-sectional view shown shows that a dielectric layer is deposited as the first passivation protection layer 9 to passivate and protect the material surface;

[0103] 5. For example Figure 6 The cross-sectional view shown shows that the gate foot groove 10 is prepared in the first passivation protection layer 9 between the source electrode 81 and the drain electrode 82 by photolithography and etching processes. At this time, the first passivation protection layer 9 below the gate foot groove 10 is not completely etched through, leaving 5nm-20nm.

[0104] 6. For example Figure 7 (a) shows the cross-sectional view and Figure 7 (b) shows a top view where Ni is evaporated to form a mask material film 11 by electron beam evaporation process, and the mask material film 11 outside the gate foot groove 10 is peeled off, so that only the mask material film 11 in the gate foot groove 10 is left.

[0105] 7. For example Figure 8 (a) Cross-sectional view and Figure 8(b) The top view shows that the mask material film 11 is annealed at 400℃-900℃ in a nitrogen atmosphere for 30s-600s, so that the mask material film 11 is aggregated by surface tension to form a micromask 12 with a nanoarray structure.

[0106] 8. For example Figure 9 (a) Cross-sectional view and Figure 9 (b) shows a top view. The cap layer 6, barrier layer 5, insertion layer 4, and channel layer 3 of partial thickness not covered by micromask 12 are etched by an etching process to disconnect the two-dimensional electron gas in the epitaxial structure. Then, the first passivation protection layer 9 under the micromask 12 and the gate foot groove 10 is removed to form a regular gate array structure 13. The effective channel width under the gate foot is reduced by the above scheme. After the etching process is completed, a groove 131 will be formed in the area not covered by micromask 12. If the lattice of the cap layer 6, barrier layer 5, insertion layer 4, and channel layer 3 of partial thickness not covered by micromask 12 is broken by ion implantation to disconnect the two-dimensional electron gas in the epitaxial structure, a stacked structure implanted with ions will be formed in the area not covered by micromask 12. The stacked structure includes cap layer 6, barrier layer 5, insertion layer 4, and channel layer 3 of partial thickness.

[0107] 9. For example Figure 10 The cross-sectional view shown shows that a stable gate 14 is formed through photolithography, electron beam evaporation, lift-off and annealing processes;

[0108] 10. For example Figure 11 The cross-sectional view shown shows that a dielectric layer is deposited as a second passivation protection layer 15 to passivate and protect the device.

[0109] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0110] It is further noted that the terminology "first", "second" and the like used in the specification are merely used for differentiating one entity or action from another, and do not necessarily imply any actual physical or logical relationship or order between the entities or actions. Moreover, the use of the term "including", "containing" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or even inherent to such process, method, article or apparatus. An element proceeded by "comprises a... " does not, without further restriction, exclude the presence of additional elements of the same type in the process, method, article or apparatus that comprises the element.

Claims

1. A method for preparing GaN HEMT, characterized in that, include: An epitaxial structure is formed on the surface of a substrate (1), and an isolation region (7), a source (81), and a drain (82) are formed in the epitaxial structure. A first passivation protection layer (9) is formed on the surface of the epitaxial structure opposite to the substrate (1), and a gate foot groove (10) is formed in the first passivation protection layer (9) between the source (81) and the drain (82). A mask material film (11) is formed in the gate foot groove (10), and the mask material film (11) is aggregated by surface tension to form a micromask (12) with a nanoarray structure. After the two-dimensional electron gas in the epitaxial structure not covered by the micromask (12) is disconnected, the micromask (12) is removed to form a gate array structure (13). A gate (14) is formed in the gate foot recess (10) having the gate array structure (13) to obtain the GaNHEMT.

2. The GaN HEMT preparation method according to claim 1, characterized in that, The formation of a gate foot recess (10) in the first passivation protection layer (9) between the source (81) and the drain (82) includes: The gate foot groove (10) is formed in the first passivation protection layer (9) between the source (81) and the drain (82), and the first passivation protection layer (9) below the gate foot groove (10) is retained. Accordingly, after disconnecting the two-dimensional electron gas in the epitaxial structure not covered by the micromask (12), the process further includes: Remove the first passivation protective layer (9) below the gate foot groove (10).

3. The GaN HEMT preparation method according to claim 1, characterized in that, The formation of an epitaxial structure on the surface of a substrate (1), and the formation of an isolation region (7), a source (81), and a drain (82) within the epitaxial structure, includes: A composite buffer layer (2), a channel layer (3), an insertion layer (4), a barrier layer (5), and a cap layer (6) are epitaxially grown sequentially on the surface of the substrate (1) in a direction away from the substrate (1) to form the epitaxial structure; The isolation zone (7) is formed on both sides along the length direction of the stacked structure consisting of the channel layer (3), the insertion layer (4), the barrier layer (5) and the cap layer (6). On both sides of the stacked structure formed by the barrier layer (5) and the cap layer (6) along the length direction, the source (81) and the drain (82) are respectively formed between the isolation region (7) on the same side.

4. The GaN HEMT preparation method according to claim 3, characterized in that, The step of disconnecting the two-dimensional electron gas in the epitaxial structure not covered by the micromask (12) includes: The cap layer (6), barrier layer (5), insertion layer (4), and channel layer (3) of a certain thickness that are not covered by the micromask (12) are etched by an etching process to disconnect the two-dimensional electron gas in the epitaxial structure.

5. The GaN HEMT preparation method according to claim 3, characterized in that, The step of disconnecting the two-dimensional electron gas in the epitaxial structure not covered by the micromask (12) includes: The lattice of the cap layer (6), the barrier layer (5), the insertion layer (4), and the channel layer (3) of a certain thickness that are not covered by the micromask (12) is broken by ion implantation, thereby disconnecting the two-dimensional electron gas in the epitaxial structure.

6. The GaN HEMT preparation method according to claim 1, characterized in that, The formation of the gate (14) in the gate foot recess (10) having the gate array structure (13) includes: The gate pattern is defined at the location of the gate foot recess (10) having the gate array structure (13) by photolithography; Gate material is evaporated on the surface of the epitaxial structure having the gate pattern using an electron beam evaporation process; The gate material corresponding to the non-gate pattern is removed by a stripping process; After the stripping process is completed, an annealing process is performed to form the gate (14).

7. The GaN HEMT preparation method according to claim 1, characterized in that, After forming the gate (14) in the gate foot recess (10) having the gate array structure (13), the method further includes: A second passivation protection layer (15) is formed on the surface of the epitaxial structure having the gate (14).

8. The method for preparing GaN HEMT according to any one of claims 1 to 7, characterized in that, The mask material film (11) is a metal film; the process of aggregating the mask material film (11) through surface tension to form a micromask (12) with a nanoarray structure includes: Annealing is performed in a nitrogen atmosphere, causing the mask material film (11) to aggregate through the surface tension to form the micromask (12) having the nanoarray structure.

9. The GaN HEMT preparation method according to claim 8, characterized in that, The formation of a mask material film (11) in the gate foot groove (10) includes: The mask material film (11) is formed in the gate foot groove (10) by electron beam evaporation or magnetron sputtering.

10. A GaN HEMT, characterized in that, include: GaN HEMT prepared by the GaN HEMT preparation method according to any one of claims 1 to 9.

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