Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof. The preparation method comprises the following steps: preparing an anti-reflection layer on a light receiving surface and / or a backlight surface of a silicon wafer; performing film opening on the anti-reflection layer on the metal area of the silicon wafer by adopting a laser process to form a plurality of windows penetrating to the surface of the silicon wafer; carrying out high-temperature sintering on the silicon wafer after the laser process; electrode slurry is printed on the metal area of the silicon wafer and cured at low temperature, and a grid line electrode in electric contact with the silicon wafer is formed. Through the arrangement of the anti-reflection layer, the low-temperature preparation of the base metal electrode in the solar cell can be realized, the cost of the electrode slurry can be reduced to 3-4 min / W, which is basically equal to the electroplating cost, and the electrode slurry is suitable for TOPCon cells, BC cells and the like.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically relating to a solar cell and its preparation method. Background Technology

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international photovoltaic markets are constantly increasing, prompting industry manufacturers to focus on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells are a new type of high-efficiency N-type cell. By sequentially fabricating an ultra-thin tunnel oxide layer and a doped polycrystalline silicon layer on the back of the cell, it can improve the surface passivation performance of the cell, reduce the metal contact recombination current, and effectively improve the open-circuit voltage and short-circuit current of the cell.

[0003] Currently, TOPCon cells have become mainstream products, and given the current market conditions, cost has become the main factor restricting the development of various companies. For crystalline silicon cells such as TOPCon, BC, and HJT, silver paste consumption is the main cost, accounting for approximately 7-8 cents / W for TOPCon cells and 8-10 cents / W for BC cells. However, for high-temperature sintered TOPCon and BC cells, low-temperature silver-coated copper paste cannot be used. Methods to reduce silver consumption include finer wires and copper electroplating. Electroplating is currently a popular method, but its preparation process is complex, investment costs are huge, and wastewater treatment is difficult. Ultimately, the theoretical cost can only be reduced to 3-4 cents / W, thus preventing its industrialization.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a solar cell and a method for its fabrication. Summary of the Invention

[0005] The purpose of this invention is to provide a solar cell and its preparation method, so as to simplify the metallization process and reduce the metallization cost.

[0006] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0007] A method for preparing a solar cell, the method comprising the following steps:

[0008] An antireflection layer is prepared on the light-receiving surface and / or the backlight surface of a silicon wafer;

[0009] Laser technology is used to open the antireflection layer on the metal region of a silicon wafer, forming several windows that extend to the surface of the silicon wafer;

[0010] High-temperature sintering is performed on silicon wafers after laser processing;

[0011] Electrode paste is printed on the metal region of the silicon wafer and cured at low temperature to form gate electrodes that are in electrical contact with the silicon wafer.

[0012] In one embodiment, the antireflection layer comprises SiN X Layer, SiN X O Y Layer, SiO X One or more combinations of layers, wherein X and Y are both greater than zero; and / or,

[0013] The thickness of the antireflection layer is 60nm-90nm or 70nm-80nm.

[0014] In one embodiment, the sintering temperature for high-temperature sintering of the silicon wafer after laser processing is 600°C to 700°C.

[0015] In one embodiment, a fractional laser is used in the laser process, wherein the overlap rate of the fractional laser spot is 0% to 10%, and multiple elongated windows are formed on the antireflection layer, which are distributed throughout the extension direction of the gate electrode; or,

[0016] In the laser process, a dot matrix laser is used. There are gaps between adjacent spots in the dot matrix laser, and multiple sets of windows are formed on the antireflection layer, which are spaced apart along the extension direction of the gate line electrode.

[0017] In one embodiment, the fractional laser is a picosecond laser or a femtosecond laser; and / or,

[0018] The spot of the array laser is a rectangular spot with a size of (5μm~10μm)*(5μm~10μm).

[0019] In one embodiment, printing electrode paste onto a metal region and curing it at a low temperature includes:

[0020] A first electrode paste is printed on the metal region, the first electrode paste comprising base metal and ohmic contact metal;

[0021] The printed first electrode paste was cured at a low temperature of 300℃~400℃;

[0022] The base metal in the first electrode paste includes one or more of copper, silver-plated copper, and tin, with a solid content of 80% to 90%, and the ohmic contact metal includes one or more of aluminum and nickel, with a solid content of 1% to 3%.

[0023] In one embodiment, after printing electrode paste on the metal region and curing it at low temperature, the process further includes:

[0024] The solar cell after the grid line electrodes are formed is sintered at a low temperature of 400℃~500℃.

[0025] In one embodiment, printing electrode paste onto a metal region and curing it at a low temperature includes:

[0026] A transparent conductive layer is prepared on the surface of the antireflection layer, the transparent conductive layer covering the inside of the window and in contact with the silicon wafer;

[0027] A second electrode paste, comprising a base metal, is printed on a metal region.

[0028] The printed second electrode paste is cured at low temperature at 150℃~400℃ or 200℃~230℃.

[0029] The base metal in the second electrode paste includes one or more of copper, silver-plated copper, and tin, with a solid content of 80% to 90%.

[0030] In one embodiment, the thickness of the transparent conductive layer is 2 nm to 10 nm.

[0031] In one embodiment, the linewidth of the gate electrode is greater than or equal to the width of the window, and the height of the gate electrode is 1 μm to 10 μm.

[0032] In one embodiment, the solar cell is a TOPCon cell, and the antireflection layer and grid electrodes are located on the light-receiving surface and the backlight surface of the silicon wafer; or,

[0033] The solar cell is a BC cell, and the antireflection layer and grid electrodes are located on the back surface of the silicon wafer.

[0034] Another embodiment of the present invention provides the following technical solution:

[0035] A solar cell includes a silicon wafer and an antireflection layer located on the light-receiving surface and / or backlighting surface of the silicon wafer, wherein a plurality of windows are formed on the antireflection layer extending to the surface of the silicon wafer, and the solar cell further includes grid electrodes located on the metal region of the silicon wafer and electrically contacting the silicon wafer.

[0036] In one embodiment, the antireflection layer has a plurality of elongated windows that are distributed throughout the extension direction of the gate electrode, or the antireflection layer has a plurality of sets of windows that are spaced apart along the extension direction of the gate electrode.

[0037] In one embodiment, a transparent conductive layer is stacked on the surface of the antireflective layer, the transparent conductive layer covering the inside of the window and in contact with the silicon wafer.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] This invention enables the low-temperature fabrication of base metal electrodes in solar cells by setting an antireflection layer. The cost of electrode paste can be reduced to 3-4 cents / W, which is basically on par with the cost of electroplating. It is applicable to TOPCon cells, BC cells, etc. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of the solar cell in Embodiment 1 of the present invention;

[0042] Figure 2 This is a schematic diagram of the structure of the antireflection layer after laser opening in Embodiment 1 of the present invention;

[0043] Figure 3 This is a planar schematic diagram of the first window in the first anti-reflection layer in Embodiment 1 of the present invention;

[0044] Figure 4 This is a schematic diagram of the planar structure of the solar cell in Embodiment 1 of the present invention;

[0045] Figures 5a-5f This is a flowchart illustrating the fabrication process of the solar cell in Embodiment 1 of the present invention;

[0046] Figure 6 This is a planar schematic diagram of the first window in the first antireflection layer in Embodiment 2 of the present invention;

[0047] Figure 7 This is a schematic diagram of the planar structure of the solar cell in Embodiment 2 of the present invention;

[0048] Figure 8 This is a schematic diagram of the structure of the solar cell in Embodiment 3 of the present invention;

[0049] Figures 9a-9f This is a flowchart of the fabrication process of the solar cell in Embodiment 3 of the present invention. Detailed Implementation

[0050] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature has a lower horizontal height than the second feature.

[0052] The present invention discloses a method for preparing a solar cell, comprising the following steps:

[0053] Prepare an antireflection layer on the light-receiving surface and / or the backlight surface of the silicon wafer;

[0054] Use a laser process to open the antireflection layer on the metal area of the silicon wafer to form a plurality of windows penetrating to the surface of the silicon wafer;

[0055] Perform high-temperature sintering on the silicon wafer after the laser process;

[0056] Print electrode paste on the metal area of the silicon wafer and cure it at low temperature to form grid electrodes in electrical contact with the silicon wafer.

[0057] The present invention also discloses a solar cell, comprising a silicon wafer and an antireflection layer located on the light-receiving surface and / or the backlight surface of the silicon wafer. A plurality of windows penetrating to the surface of the silicon wafer are formed on the antireflection layer. The solar cell further comprises grid electrodes located on the metal area of the silicon wafer and in electrical contact with the silicon wafer.

[0058] Through the setting of the antireflection layer, the present invention can achieve the low-temperature preparation of base metal electrodes in a solar cell, which is applicable to TOPCon cells, BC cells, etc.

[0059] The following further illustrates the present invention with specific examples.

[0060] Example 1:

[0061] See Figure 1 、 Figure 2The diagram shown is a schematic representation of the solar cell in this embodiment. The solar cell is a TOPCon cell and includes a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The first surface S1 is the front side (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlighting surface) of the silicon substrate 10. Exemplarily, the silicon substrate 10 is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0062] Furthermore, a light-trapping structure (not shown) is formed on the first surface S1 of the silicon substrate 10. For example, a pyramid textured structure can be formed on the first surface S1 of the silicon substrate 10 by alkaline texturing. The pyramid size is preferably 0.5 μm to 3 μm.

[0063] A first doped layer 11 (i.e., emitter) is provided on the first surface S1 of the silicon substrate 10. Exemplarily, the first doped layer 11 may be a P-type doped layer (i.e., P+ emitter) formed by a boron doping process, with a doping concentration of 3E18cm⁻¹. -3 ~1E20cm -3 .

[0064] Preferably, in this embodiment, the first doped layer 11 is a selective emitter (SE) structure, and the region directly below the gate electrode is a heavily doped region with a doping concentration of 1E19cm⁻¹. -3 ~1E20cm -3 The depth is 1μm to 2μm, and the remaining region is a lightly doped region with a doping concentration of 3E18cm. -3 ~1E19cm -3 .

[0065] A tunneling layer 12 and a second doped layer 13 are sequentially stacked on the second surface S2 of the silicon substrate. Exemplarily, the tunneling layer 12 is one or a combination of silicon oxide and silicon oxynitride layers, preferably silicon oxide, with a thickness of 0.5 nm to 3 nm, more preferably 1.5 nm to 2.5 nm. The second doped layer 13 is a phosphorus-doped polycrystalline silicon layer with a surface doping concentration of 1E20 cm⁻¹. -3 ~9E20cm -3 The preferred size is 3E20cm. -3 ~5E20cm -3 The thickness ranges from 1 nm to 150 nm.

[0066] In this embodiment, a first antireflection layer 14 is stacked on the first doped layer 11, and a second antireflection layer 15 is stacked on the second doped layer 13. The thickness of the first antireflection layer 14 and the second antireflection layer 15 is 60nm to 90nm, preferably 70nm to 80nm. The first antireflection layer 14 and the second antireflection layer 15 can be SiN.X Layer, SiN X O Y Layer, SiO X One of the layers, or a combination of multiple layers. Exemplarily, the first antireflection layer 14 and the second antireflection layer 15 in this embodiment are both SiN X layers.

[0067] Combined with Figure 3 As shown, on the first antireflection layer 14 in this embodiment, a plurality of longitudinally elongated first windows 141 are formed and distributed through the first antireflection layer 14 along the extending direction of the gate line electrode, and the first windows 141 penetrate through to the first doping layer 11 below it. The width of the first window 141 is 5 μm to 10 μm, and the depth is the thickness of the first antireflection layer 14.

[0068] Similarly, on the second antireflection layer 15, a plurality of longitudinally elongated second windows 151 are formed and distributed through the second antireflection layer 15 along the extending direction of the gate line electrode, and the second windows 151 penetrate through to the second doping layer 13 below it. The width of the second window 151 is 5 μm to 10 μm, and the depth is the thickness of the second antireflection layer 15.

[0069] Preferably, the width of the first window 141 is smaller than the width of the second window 151. For example, the width of the first window 141 is 5 μm, and the width of the second window 151 is 8 μm.

[0070] The solar cell in this embodiment further includes a first gate line electrode 16 on the front side and a second gate line electrode 17 on the back side. The first gate line electrode 16 and the second gate line electrode 17 are both base metal electrodes. The base metal can be any one or more of copper, copper-clad silver, tin, etc. The base metal electrode also includes an ohmic contact metal, such as metal aluminum, nickel, etc.

[0071] Referring to Figure 1 and combined with Figure 4 As shown, taking the first gate line electrode 16 as an example, its line width can be greater than or equal to the width of the first window 141, and the height is 1 μm to 10 μm. The first gate line electrode 16 penetrates through the first window 141 below and contacts the first doping layer 11. The height of the first gate line electrode 16 is greater than the thickness of the first antireflection layer 14, so the upper part of the first gate line electrode 16 protrudes outside the first window 141. The structure of the second gate line electrode 17 is similar to that of the first gate line electrode 16, and will not be elaborated here.

[0072] The preparation method of the solar cell in this embodiment includes the following steps:

[0073] 1. According to the conventional TOPCon process, sequentially perform steps such as double-sided texturing, front boron diffusion, SE process, back etching, LPCVD (tunneling oxide layer and polysilicon layer deposition), annealing activation, etc., to obtain Figure 5aThe silicon wafer 100 shown.

[0074] 2. Reference Figure 5b As shown, a first antireflection layer 14 and a second antireflection layer 15 are respectively fabricated on the light-receiving surface and the backlight surface of the silicon wafer 100.

[0075] The thickness of the first antireflection layer 14 and the second antireflection layer 15 is 60nm to 90nm, preferably 70nm to 80nm, and the first antireflection layer 14 and the second antireflection layer 15 can be SiN. X Layer, SiN X O Y Layer, SiO X The layers can be one type, or a combination of multiple types, where X and Y are both greater than zero. For example, in this embodiment, both the first antireflection layer 14 and the second antireflection layer 15 are SiN. X layer.

[0076] 3. Participate Figure 5c As shown, a laser process is used to open the second antireflection layer 15 on the back metal area to form a second window 151 that extends through the silicon wafer.

[0077] In this process, a fractional laser is used, which is either a picosecond laser or a femtosecond laser. The overlap rate of the laser spot is 0% to 10%. The laser spot is a rectangular spot with a size of (5μm to 10μm)*(5μm to 10μm), preferably (5μm to 8μm)*(5μm to 8μm).

[0078] For example, in this embodiment, the laser spot size is 8μm*8μm, and the overlap rate is 0%. Figure 3 As shown, the light spots are adjacent to each other and do not overlap.

[0079] 4. Participate Figure 5d As shown, a laser process is used to open the first antireflection layer 14 on the front metal area to form a first window 141 that extends through the silicon wafer.

[0080] In this process, a fractional laser is used, which is either a picosecond laser or a femtosecond laser. The overlap rate of the laser spot is 0% to 10%. The laser spot is a rectangular spot with a size of (5μm to 10μm)*(5μm to 10μm), preferably (5μm to 8μm)*(5μm to 8μm).

[0081] In this embodiment, the front metal region is located above the heavily doped region of the first doped layer 11. Since laser damage can affect battery efficiency, in order to reduce laser damage, the spot size of the front laser is 5μm*5μm with an overlap rate of 0%, thus controlling the reduction in battery efficiency to below 0.1%.

[0082] 5. Perform high-temperature sintering on the silicon wafers after laser processing.

[0083] In this step, the sintering temperature for high-temperature sintering is 600℃~700℃, preferably 650℃. High-temperature sintering allows hydrogen (H) in the antireflective film to diffuse into the silicon wafer, passivating the dangling bonds within the silicon wafer, thus achieving H passivation treatment of the silicon wafer.

[0084] 6. Participate Figure 5e As shown, a first electrode paste is printed on the back metal area and cured at low temperature to form a second gate electrode 17 that penetrates the second window 151 and is in electrical contact with the silicon wafer.

[0085] Specifically, it includes:

[0086] First, a first electrode paste is printed on the metal area, the first electrode paste comprising base metal and ohmic contact metal;

[0087] Then, the printed first electrode paste is cured at a low temperature of 300℃~400℃.

[0088] In this embodiment, the base metal in the first electrode paste is a cheap metal with a resistivity close to that of silver. The first electrode paste can be copper paste, silver-coated copper (Ag@Cu) paste, tin-containing paste, etc. The solid content of the base metal is 80% to 90%. Compared with silver paste, this type of paste has the advantage of low price, and it only needs to be cured at a low temperature of 300°C to 400°C, without the need for a high-temperature sintering step.

[0089] In addition, to ensure that the first electrode paste and the silicon wafer can form a good ohmic contact, an ohmic contact metal can be added to the paste to modify it. In this embodiment, the ohmic contact metal added to the first electrode paste includes one or more of aluminum, nickel, etc., with a solid content of 1% to 3%. Metals such as aluminum and nickel can form a good ohmic contact with silicon at low temperatures.

[0090] 7. (Refer to) Figure 5f As shown, a first electrode paste is printed on the front metal area and cured at low temperature to form a first gate electrode 16 that penetrates the first window 141 and is in electrical contact with the silicon wafer.

[0091] Specifically, it includes:

[0092] First, a first electrode paste is printed on the metal area, the first electrode paste comprising base metal and ohmic contact metal;

[0093] Then, the printed first electrode paste is cured at a low temperature of 300℃~400℃;

[0094] Finally, the solar cell is sintered at a low temperature of 400℃ to 500℃ to ensure good ohmic contact between the grid electrode formed by the first electrode paste and the silicon wafer.

[0095] The first gate electrode 16 and the second gate electrode 17 in this step can be main gate lines or fine gate lines. In this embodiment, a fine gate line is used as an example for explanation.

[0096] Example 2:

[0097] The solar cell in this embodiment has a basically the same structure as the solar cell in Embodiment 1. The difference is that in Embodiment 1, multiple elongated first windows 141 or second windows 151 are formed on the antireflection layer, which are distributed along the extension direction of the grid electrodes. Figure 6 , Figure 7 As shown, in this embodiment, a plurality of first windows 141 are formed on the first anti-reflection layer 14 at intervals along the extension direction of the gate electrode, and similarly, a plurality of second windows 151 are formed on the second anti-reflection layer 15 at intervals along the extension direction of the gate electrode.

[0098] Specifically, the size of each first window 141 and second window 151 is (5μm~10μm)*(5μm~10μm), preferably (5μm~8μm)*(5μm~8μm). The size of the window is consistent with the size of the laser spot, and the spacing between two adjacent windows is controlled by the gap between adjacent spots.

[0099] For example, in this embodiment, the size of the first window 141 is 5μm*5μm, and the size of the second window 151 is 8μm*8μm.

[0100] The method for fabricating the solar cell in this embodiment is basically the same as in Embodiment 1, except that adjacent laser spots do not overlap and there is a gap between them in the laser process. In this embodiment, the spacing between adjacent laser spots is less than or equal to 20% of the spot size.

[0101] For example, when the second antireflection layer 15 on the back metal region is opened, the laser spot size is 8μm*8μm, the spacing between adjacent spots is 10% of the spot size, and finally multiple spaced second windows 151 are obtained, each second window 151 is 8μm*8μm in size, and the spacing between adjacent second windows 151 is 0.8μm.

[0102] Similarly, when opening the film on the first anti-reflection layer 14 on the front metal region, the laser spot size is 5μm * 5μm, and the distance between adjacent spots is 10% of the spot size. Eventually, multiple first windows 141 distributed at intervals can be obtained. Each first window 141 has a size of 5μm * 5μm, and the distance between adjacent first windows 141 is 0.5μm.

[0103] Embodiment 3:

[0104] Refer Figure 8 The schematic structural diagram of the solar cell in this embodiment is shown. The silicon wafer 100, the first anti-reflection layer 14, and the second anti-reflection layer 15 in this embodiment are exactly the same as those in Embodiment 1, and will not be elaborated here.

[0105] Different from Embodiment 1, in this embodiment, a first transparent conductive layer (TCO) 18 is laminated on the surface of the first anti-reflection layer 14. The first transparent conductive layer not only covers the inside of the first window 141 and contacts the surface of the silicon wafer, but also covers the external first anti-reflection layer 14.

[0106] The first transparent conductive layer 18 can be any one or more of an ITO (indium tin oxide) layer, an IWO (indium tungsten oxide) layer, an IMO (indium molybdenum oxide) layer, an AZO (aluminum zinc oxide) layer, a GZO (gallium zinc oxide) layer, etc., with a thickness of 2nm - 10nm, preferably 4nm. The first transparent conductive layer 18 can form a good contact with the silicon wafer in the first window 141, and due to its thin thickness, it basically does not cause current loss.

[0107] Correspondingly, in this embodiment, a second transparent conductive layer 19 is laminated on the surface of the second anti-reflection layer 15. The second transparent conductive layer not only covers the inside of the second window 151 and contacts the surface of the silicon wafer, but also covers the external second anti-reflection layer 15. The structure of the second transparent conductive layer 19 is similar to that of the first transparent conductive layer 18, and will not be elaborated here.

[0108] Both the first grid line electrode 16 and the second grid line electrode 17 in this embodiment are base metal electrodes. The base metal can be any one or more of copper, copper-clad silver, tin, etc. The first grid line electrode 16 contacts the first transparent conductive layer 18 in the first window 141, and the second grid line electrode 17 contacts the second transparent conductive layer 19 in the second window 151. Using a transparent conductive layer can improve the contact performance between the base metal electrode and silicon. Therefore, there is no need to add an ohmic contact metal in the base metal electrode, and ordinary base metal materials can be used.

[0109] The preparation method of the solar cell in this embodiment includes the following steps:

[0110] 1. Following the conventional TOPCon process, the following steps are performed sequentially: double-sided texturing, front-side boron diffusion, SE process, back-side etching, LPCVD (tunneling oxide and polysilicon layer deposition), and annealing activation, to obtain... Figure 9a The silicon wafer 100 shown.

[0111] 2. Reference Figure 9b As shown, a first antireflection layer 14 and a second antireflection layer 15 are respectively fabricated on the light-receiving surface and the backlight surface of the silicon wafer 100.

[0112] The thickness of the first antireflection layer 14 and the second antireflection layer 15 is 60nm to 90nm, preferably 70nm to 80nm, and the first antireflection layer 14 and the second antireflection layer 15 can be SiN. X Layer, SiN X O Y Layer, SiO X The antireflection layer can be one of several layers, or a combination of several layers. For example, in this embodiment, both the first antireflection layer 14 and the second antireflection layer 15 are SiN. X layer.

[0113] 3. Participate Figure 9c As shown, a laser process is used to open the second antireflection layer 15 on the back metal area to form a second window 151 that extends through the silicon wafer.

[0114] In this process, a fractional laser is used, which is either a picosecond laser or a femtosecond laser. The overlap rate of the laser spot is 0% to 10%. The laser spot is a rectangular spot with a size of (5μm to 10μm)*(5μm to 10μm), preferably (5μm to 8μm)*(5μm to 8μm).

[0115] For example, in this embodiment, the laser spot size is 8μm*8μm, and the overlap rate is 0%. Figure 3 As shown, the light spots are adjacent to each other and do not overlap.

[0116] 4. Participate Figure 9d As shown, a laser process is used to open the first antireflection layer 14 on the front metal area to form a first window 141 that extends through the silicon wafer.

[0117] In this process, a fractional laser is used, which is either a picosecond laser or a femtosecond laser. The overlap rate of the laser spot is 0% to 10%. The laser spot is a rectangular spot with a size of (5μm to 10μm)*(5μm to 10μm), preferably (5μm to 8μm)*(5μm to 8μm).

[0118] In this embodiment, the front metal region is located above the heavily doped region of the first doped layer 11. Since laser damage can affect battery efficiency, in order to reduce laser damage, the spot size of the front laser is 5μm*5μm with an overlap rate of 0%, thus controlling the reduction in battery efficiency to below 0.1%.

[0119] 5. Perform high-temperature sintering on the silicon wafers after laser processing.

[0120] In this step, the sintering temperature for high-temperature sintering is 600℃~700℃, preferably 650℃. High-temperature sintering enables H passivation treatment of the silicon wafer.

[0121] 6. Participate Figure 9e As shown, a first transparent conductive layer 18 and a second transparent conductive layer 19 are respectively prepared on the surfaces of the first antireflection layer 14 and the second antireflection layer 15. The first transparent conductive layer 18 and the second transparent conductive layer 19 penetrate through the first window 141 and the second window 151 and are in contact with the silicon wafer.

[0122] In this embodiment, the thickness of both the first transparent conductive layer 18 and the second transparent conductive layer 19 is 4 nm.

[0123] 7. (Refer to) Figure 9f As shown, a second electrode paste is printed on the front and back metal areas respectively and cured at low temperature to form a first gate electrode 16 and a second gate electrode 17 on the front and back respectively.

[0124] Specifically, it includes:

[0125] First, the second electrode paste is printed on the front and back metal areas respectively;

[0126] Then, the printed second electrode paste is cured at a low temperature of 150℃ to 400℃.

[0127] In this embodiment, the metal used in the second electrode paste is an inexpensive metal with a resistivity close to that of silver. The second electrode paste can be copper paste, silver-coated copper (Ag@Cu) paste, silver-copper mixed paste, tin-containing paste, etc., with a solid content of 80% to 90%. Such pastes are cheaper than silver pastes and only need to be cured at a low temperature of 150°C to 400°C. There is no need to go through a high-temperature sintering step. The curing temperature is preferably 200°C to 230°C.

[0128] When the second electrode paste is made of copper paste, the low-temperature curing step is carried out in a nitrogen atmosphere.

[0129] Example 4:

[0130] The solar cell in this embodiment has a basically the same structure as the solar cell in Embodiment 3. The difference is that in Embodiment 3, the antireflection layer has multiple elongated first windows 141 or second windows 151 that are distributed along the extension direction of the grid electrodes. In this embodiment, the first antireflection layer 14 has multiple sets of first windows 141 that are spaced apart along the extension direction of the grid electrodes. Similarly, the second antireflection layer 15 has multiple sets of second windows 151 that are spaced apart along the extension direction of the grid electrodes. The structure of the first window 141 and the second window 151 is exactly the same as in Embodiment 2, and will not be described again here.

[0131] In the above embodiments 1 to 4, a square laser spot is preferably used for film opening. In other embodiments, the shape of the laser spot is not limited to a square, but can also be a rectangle, a circle, etc. The present invention does not specifically limit the shape of the laser spot. All schemes that use laser technology to open the antireflection layer are within the scope of protection of the present invention.

[0132] In Examples 1-4, the TOPCon battery employs an antireflection layer and a base metal electrode structure on both the front and back sides. In other examples, the antireflection layer and base metal electrode structure may be used only on the front side of the TOPCon battery, or only on the back side of the TOPCon battery. These will not be illustrated here.

[0133] Furthermore, this invention is also applicable to BC (Back Contact) batteries, in which all grid electrodes are located on the back side of the battery. Therefore, only an antireflection layer and base metal electrodes are needed on the back side. For example, TBC batteries, which combine TOPCon and BC technologies, can also have an antireflection layer and grid electrodes fabricated on the back side using the method described in the above embodiments.

[0134] It is worth noting that in TBC cells, since both the P-type doped layer and the N-type doped layer are formed on the back side of the silicon wafer, it is necessary to isolate the P-type doped region and the N-type doped region, as well as the anti-reflection layer and the gate electrode above them, for example, by using laser isolation or other processes. The specific metallization process is similar to that in Examples 1 to 4, and will not be described in detail here.

[0135] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0136] This invention enables the low-temperature fabrication of base metal electrodes in solar cells by setting an antireflection layer. The cost of electrode paste can be reduced to 3-4 cents / W, which is basically on par with the cost of electroplating. It is applicable to TOPCon cells, BC cells, etc.

[0137] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0138] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that, The preparation method includes the following steps: An antireflection layer is prepared on the light-receiving surface and / or the backlight surface of a silicon wafer; Laser technology is used to open the antireflection layer on the metal region of a silicon wafer, forming several windows that extend to the surface of the silicon wafer; High-temperature sintering is performed on silicon wafers after laser processing; Electrode paste is printed on the metal region of the silicon wafer and cured at low temperature to form gate electrodes that are in electrical contact with the silicon wafer.

2. The preparation method according to claim 1, characterized in that, The antireflection layer includes SiN X Layer, SiN X O Y Layer, SiO X One or more combinations of layers, wherein X and Y are both greater than zero; and / or, The thickness of the antireflection layer is 60nm-90nm or 70nm-80nm.

3. The preparation method according to claim 1, characterized in that, The sintering temperature for high-temperature sintering of silicon wafers after laser processing is 600℃~700℃.

4. The preparation method according to claim 1, characterized in that, The laser process uses a dot matrix laser with a spot overlap rate of 0% to 10%, and the antireflection layer has multiple elongated windows that are distributed throughout the extension direction of the gate electrode. or, In the laser process, a dot matrix laser is used. There are gaps between adjacent spots in the dot matrix laser, and multiple sets of windows are formed on the antireflection layer, which are spaced apart along the extension direction of the gate line electrode.

5. The preparation method according to claim 4, characterized in that, The fractional laser is a picosecond laser or a femtosecond laser; and / or The spot of the array laser is a rectangular spot with a size of (5μm~10μm)*(5μm~10μm).

6. The preparation method according to claim 1, characterized in that, Printing electrode paste onto a metallic region and curing it at low temperature includes: A first electrode paste is printed on the metal region, the first electrode paste comprising base metal and ohmic contact metal; The printed first electrode paste was cured at a low temperature of 300℃~400℃; The base metal in the first electrode paste includes one or more of copper, silver-plated copper, and tin, with a solid content of 80% to 90%, and the ohmic contact metal includes one or more of aluminum and nickel, with a solid content of 1% to 3%.

7. The preparation method according to claim 6, characterized in that, The process of printing electrode paste onto the metal region and curing it at low temperature also includes: The solar cell after the grid line electrodes are formed is sintered at a low temperature of 400℃~500℃.

8. The preparation method according to claim 1, characterized in that, Printing electrode paste onto a metallic region and curing it at low temperature includes: A transparent conductive layer is prepared on the surface of the antireflection layer, the transparent conductive layer covering the inside of the window and in contact with the silicon wafer; A second electrode paste, comprising a base metal, is printed on a metal region. The printed second electrode paste is cured at low temperature at 150℃~400℃ or 200℃~230℃. The base metal in the second electrode paste includes one or more of copper, silver-plated copper, and tin, with a solid content of 80% to 90%.

9. The preparation method according to claim 8, characterized in that, The thickness of the transparent conductive layer is 2nm to 10nm.

10. The preparation method according to claim 1, characterized in that, The linewidth of the gate electrode is greater than or equal to the width of the window, and the height of the gate electrode is 1 μm to 10 μm.

11. The preparation method according to claim 1, characterized in that, The solar cell is a TOPCon cell, and the antireflection layer and grid electrodes are located on the light-receiving surface and the backlight surface of the silicon wafer; or, The solar cell is a BC cell, and the antireflection layer and grid electrodes are located on the back surface of the silicon wafer.

12. A solar cell, characterized in that, The solar cell includes a silicon wafer and an antireflection layer located on the light-receiving surface and / or backlighting surface of the silicon wafer. The antireflection layer has a plurality of windows extending through to the surface of the silicon wafer. The solar cell also includes grid electrodes located on the metal region of the silicon wafer and in electrical contact with the silicon wafer.

13. The solar cell according to claim 12, characterized in that, The antireflection layer has multiple elongated windows that extend through the gate electrode along its extension direction, or the antireflection layer has multiple sets of windows that are spaced apart along the gate electrode extension direction.

14. The solar cell according to claim 12, characterized in that, A transparent conductive layer is stacked on the surface of the antireflective layer, and the transparent conductive layer covers the inside of the window and is in contact with the silicon wafer.

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