Display device

Abstract

A display device according to one embodiment includes: a substrate including a display area and a non-display area surrounding the display area; the first light shielding layer is arranged on the substrate; an active layer including a semiconductor region of the first transistor and disposed on the first light shielding layer; a gate layer including a gate of the first transistor and disposed on the active layer; a source metal layer disposed on the gate layer and including an anode connection electrode directly connected to the active layer and receiving the driving current flowing in the first transistor; a pixel electrode disposed on the source metal layer and directly connected to the anode connection electrode; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device. BACKGROUND

[0002] As the information society develops, various demands for display devices for displaying images are increasing, and various types of display devices, such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices, are used.

[0003] An image displayed on a display device can be a still image or a dynamic image, and the dynamic image can include various types, such as a moving image, a game image, and a movie. The display device can include a plurality of pixels and a plurality of switching elements for driving the pixels. SUMMARY

[0004] The disclosure aims to provide a display device by which the number of masks of a manufacturing process can be reduced and manufacturing costs can be reduced.

[0005] The object of the disclosure is not limited to the above-mentioned object, and other technical objects can be inferred from the following embodiments.

[0006] According to one embodiment, a display device is provided, including: a substrate including a display area and a non-display area surrounding the display area; a first light-blocking layer disposed on the substrate; an active layer including a semiconductor area of a first transistor and disposed on the first light-blocking layer; a gate layer including a gate of the first transistor and disposed on the active layer; a source metal layer disposed on the gate layer and including an anode connection electrode directly connected to the active layer and receiving a driving current flowing in the first transistor; a pixel electrode disposed on the source metal layer and directly connected to the anode connection electrode; an emission layer disposed on the pixel electrode; and a common electrode disposed on the emission layer.

[0007] According to another embodiment, a display device is provided, including: a substrate including a display area and a non-display area surrounding the display area; an emission element including a pixel electrode and emitting light; a first transistor supplying a driving current to the pixel electrode; an active layer disposed on the substrate and including a semiconductor area of the first transistor; a second transistor supplying a data voltage to a gate of the first transistor based on a first scan signal; a third transistor supplying a reference voltage to the gate of the first transistor based on a second scan signal; a fourth transistor supplying a driving voltage to a drain of the first transistor based on a first emission signal; a fifth transistor including a drain and a source, the drain and the source of the fifth transistor being disposed in the active layer and electrically connecting a source of the first transistor to the pixel electrode based on a second emission signal; and an anode connection electrode directly connecting the source of the fifth transistor to the pixel electrode.

[0008] Details of other embodiments are included in the detailed description and the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a display device according to one embodiment.

[0010] Figure 2 This is a plan view showing a display device according to one embodiment.

[0011] Figure 3 This is a circuit diagram illustrating the circuitry of a display device according to one embodiment.

[0012] Figure 4 This is a cross-sectional view showing the circuitry of a display device according to one embodiment.

[0013] Figure 5 This is a plan view showing voltage lines in a display device according to one embodiment.

[0014] Figure 6 It is along Figure 5 The cross-sectional view taken by line I-I' in the diagram.

[0015] Figure 7 It is along Figure 5 The cross-sectional view taken from line II-II' in the diagram.

[0016] Figure 8 It is along Figure 5 The cross-sectional view taken from line III-III' in the diagram.

[0017] Figures 9 to 13 This is a cross-sectional view of the manufacturing process of a display device according to one embodiment. Detailed Implementation

[0018] In the following description, embodiments will be referenced to the accompanying drawings. In this disclosure, when a first component (or region, layer, portion, etc.) is described as being "on," "connected to," or "attached to" a second component, it means that the first component may be directly connected to / attached to the second component, or that a third component may be disposed therebetween.

[0019] The same reference numerals denote the same parts. Furthermore, in the drawings, the thickness, scale, and dimensions of the parts are exaggerated for the purpose of effectively describing the technical content. The term "and / or" includes all one or more combinations that can be defined by the associated configuration.

[0020] Terms such as "first" and "second" can be used to describe various components, but these components are not limited by the terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the embodiments, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly specifies otherwise, the singular includes the plural.

[0021] Terms such as “below,” “on the lower side,” “above,” and “on the upper side” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated by the markings in the drawings.

[0022] It should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the existence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0023] Figure 1 This is a block diagram illustrating a display device according to one embodiment.

[0024] Reference Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 can be applied to televisions, laptops, monitors, billboards, or display units in the Internet of Things (IoT). As another example, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, and head-mounted displays (HMDs).

[0025] The display device 10 may include a display panel 100, a controller 200, a gate driver 300 that supplies gate signals to a plurality of pixels PX, a data driver 400 that supplies data voltage to a plurality of pixels PX, and a power supply unit 500 that supplies power to a plurality of pixels PX.

[0026] The display panel 100 may include a display area DA (see...) Figure 2 ) and non-display area NDA (see Figure 2 The display area DA may include multiple pixels PX. The non-display area NDA may surround the display area DA and include a gate driver 300 and a data driver 400.

[0027] Multiple gate lines GL and multiple data lines DL can intersect each other in the display panel 100 and can be electrically connected to each pixel PX. For example, a pixel PX can receive gate signals from the gate driver 300 via the gate line GL, receive data signals from the data driver 400 via the data line DL, and receive drive voltage EVDD and low potential voltage EVSS from the power supply unit 500.

[0028] The gate line GL may include a scan line SCL and a light emission control line EML. The scan line SCL supplies a scan signal SC to the pixel PX, and the light emission control line EML supplies a light emission control signal EM to the pixel PX. The data line DL supplies a data voltage Vdata to the pixel PX, and the power supply line VL supplies a power supply voltage. Here, the power supply voltage may include, but is not limited to, a drive voltage EVDD, a low-level voltage EVSS, an initialization voltage Vint, a reference voltage Vref, and a bias voltage Vbias.

[0029] Display panel 100 may include a non-transmissive display panel or a transmissive display panel. A transmissive display panel can display images on a screen and can be applied to transparent display devices in which the actual background is visible. For example, display panel 100 may be implemented as a flexible display panel comprising a plastic substrate.

[0030] A touch sensor can be disposed on the display panel 100. Touch input can be sensed using a separate touch sensor or by means of pixels (PX). The touch sensor can be an on-chip touch sensor or an external touch sensor, and can be implemented as an in-chip touch sensor disposed on the screen of the display panel 100 or embedded in the display panel 100.

[0031] The controller 200 can process image data RGB input from a host system (not shown) to fit the size and resolution of the display panel 100, and supply the processed image data RGB to the data driver 400. Here, the host system can be one of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system. The controller 200 can generate a gate control signal GCS and a data control signal DCS based on a synchronization signal input from the host system. Here, the synchronization signal can include, but is not limited to, a clock signal CLK, a data enable signal DEN, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The gate control signal GCS can be supplied to the gate driver 300 to control the operating timing of the gate driver 300, and the data control signal DCS can be supplied to the data driver 400 to control the operating timing of the data driver 400. For example, the controller 200 can be configured to be integrated with a microprocessor, mobile processor, application processor, etc.

[0032] The controller 200 can drive the pixel PX at various refresh rates. The controller 200 can drive the pixel PX in a variable refresh rate (VRR) mode, or switch between a first refresh rate and a second refresh rate. For example, the controller 200 can drive the pixel PX at various refresh rates by simply changing the rate of the clock signal, generating a synchronization signal to generate horizontal or vertical blanks, or driving the gate driver 300 in a mask manner.

[0033] The gate control signal GCS can be converted into gate high voltage VGH and gate low voltage VGL by a level shifter (not shown) and supplied to the gate driver 300. A level shifter can convert the high level voltage of the gate control signal GCS to gate high voltage VGH and the low level voltage of the gate control signal GCS to gate low voltage VGL. The gate control signal GCS may include a start pulse and a shift clock.

[0034] Gate driver 300 can supply gate signals to gate line GL based on gate control signal GCS supplied from controller 200. Gate driver 300 may include scan driver 310 and light emission control driver 320. Gate line GL may include scan line SCL and light emission control line EML. Scan driver 310 can supply scan signal SC to scan line SCL, and light emission control driver 320 can supply light emission control signal EM to light emission control line EML. Each of scan signal SC and light emission control signal EM may include a pulse that oscillates between gate high voltage VGH and gate low voltage VGL. Scan signal SC can select pixel PX of a line that is written with data synchronously with data voltage Vdata, and light emission control signal EM can define the light emission time of pixel PX. Gate driver 300 may be disposed on one or both sides of display panel 100 in a gate-in-panel (GIP) manner. Gate driver 300 may use a shift register to shift gate signals and sequentially supply the shifted gate signals to gate line GL.

[0035] The data driver 400 can convert image data RGB into data voltage Vdata according to the data control signal DCS supplied from the controller 200, and supply the converted data voltage Vdata to the data line DL. The number and arrangement of the data drivers 400 are not limited to... Figure 1 The quantity and arrangement positions are shown. For example, the data driver 400 may consist of multiple integrated circuits (ICs) and be individually arranged on one side of the display panel 100 as multiple data drivers.

[0036] The power supply unit 500 can use a DC-DC converter to generate the DC power required to drive the display panel 100. For example, the DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply unit 500 can receive a DC input voltage applied from the host system and generate DC voltages, such as gate high voltage VGH, gate low voltage VGL, drive voltage EVDD, low potential voltage EVSS, initialization voltage Vint, reference voltage Vref, and bias voltage Vbias. The gate high voltage VGH and gate low voltage VGL can be supplied to the level shifter and gate driver 300. The drive voltage EVDD, low potential voltage EVSS, initialization voltage Vint, and reference voltage Vref can be supplied to the pixel PX.

[0037] Figure 2 This is a plan view showing a display device according to one embodiment.

[0038] Reference Figure 2 The display panel 100 may include a display area DA and a non-display area NDA. The flat surface shape of the display area DA may be rectangular. The display area DA may be a rectangular shape with rounded corners, but is not limited thereto. As another example, the flat surface shape of the display area DA may be a square, a circle, an ellipse, or other polygonal shapes.

[0039] In the following text, the first direction DR1 and the second direction DR2 are intersecting directions, and are shown as perpendicularly intersecting directions in the plan view. The first direction DR1 may be substantially the same as the extension direction of the short side of the display panel 100, and the second direction DR2 may be the same as the extension direction of the long side of the display panel 100. However, the directions described in the embodiments should be understood as indicating relative directions, and the embodiments are not limited to the described directions.

[0040] The display area DA may include a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The non-display area NDA may surround the display area DA. The non-display area NDA may include a first side disposed in the first direction DR1 of the display area DA, a second side disposed in the direction opposite to the first direction DR1, a third side disposed in the second direction DR2, and a fourth side disposed in the direction opposite to the second direction DR2. Here, in the non-display area NDA, the first side may be the right side, the second side may be the left side, the third side may be the top side, and the fourth side may be the bottom side.

[0041] Scan lines SCL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2. Scan lines SCL can sequentially supply scan signals SC to multiple pixels PX.

[0042] The emission control lines EML can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The emission control lines EML can sequentially supply emission signals EM to multiple pixels PX.

[0043] The data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The data lines DL supply data voltage to the pixels PX. The data voltage determines the brightness of each pixel PX.

[0044] The power lines VL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The power lines VL can supply power voltage to the pixel PX. Here, the power voltage may include, but is not limited to, the drive voltage EVDD, the low-level voltage EVSS, the initialization voltage Vint, the reference voltage Vref, and the bias voltage Vbias.

[0045] The gate driver 300 can be disposed on each of the first and second sides of the non-display area NDA. A low-potential line VSL can be disposed in the non-display area NDA and surround the gate driver 300 and the display area DA. For example, the low-potential line VSL can extend from the flexible film FPCB and pass through the sub-region SR and the curved region BR, and can be disposed on the first to fourth sides of the non-display area NDA, surrounding the gate driver 300 and the display area DA.

[0046] The display panel 100 may include a main region MR, a curved region BR, and a sub-region SR. The main region MR may include a display region DA and a non-display region NDA. The curved region BR may be disposed between the main region MR and the sub-region SR. The curved region BR may extend from the fourth side of the non-display region NDA in a direction opposite to the second direction DR2. The sub-region SR may extend from the curved region BR in a direction opposite to the second direction DR2.

[0047] The sub-region SR may include a first pad region PA1 and a second pad region PA2. The first pad region PA1 may be located at the center of the sub-region SR and connected to the data driver 400. The second pad region PA2 may be located at an end of the sub-region SR and connected to the flexible film FPCB.

[0048] The data driver 400 can be formed in the form of an integrated circuit (IC). For example, the data driver 400 can be configured as a chip-on-plastic (CIP), in which the data driver 400 is directly mounted on the display panel 100. As another example, the data driver 400 can be configured as a chip-on-glass or a chip-on-film.

[0049] The display panel 100 may also include a crack sensing pattern CRP surrounding the low-potential line VSL. The crack sensing pattern CRP may be positioned on the first to fourth sides of the non-display area NDA and completely surround the display area DA. As another example, the crack sensing pattern CRP may not be positioned on a portion of the non-display area NDA.

[0050] Figure 3 This is a circuit diagram illustrating the circuitry of a display device according to one embodiment.

[0051] Reference Figure 3 Each of the multiple pixels PX can be connected to the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first light emission control line EML1, the second light emission control line EML2, the data line DL, the reference voltage line VRL, the drive voltage line VDL, the initialization voltage line VIL, and the low voltage line VSL.

[0052] A pixel PX may include a pixel circuit and a light-emitting element ED. The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0053] The first transistor T1 may include a gate, a drain, and a source. The first transistor T1 can control the drain-source current (Ids) (or drive current) based on the data voltage applied to the gate. The drive current (Ids) flowing through the channel of the first transistor T1 is proportional to the square of the difference between the voltage between the gate and source of the first transistor T1 (Vgs) and the threshold voltage (Vth) of the first transistor T1 (Ids = k × (Vgs - Vth)). 2 Here, k represents a scaling factor determined by the structure and physical characteristics of the first transistor T1, Vgs represents the gate-source voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1. The gate of the first transistor T1 can be electrically connected to the first node N1, the drain can be connected to the source of the fourth transistor T4, and the source can be electrically connected to the second node N2.

[0054] An OLED can receive a driving current (Ids) and emit light. The amount of light emitted, or the brightness of the OLED, can be proportional to the magnitude of the driving current (Ids). An OLED can be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes, but the type of OLED is not limited to this.

[0055] The first electrode of the light-emitting element (ED) can be electrically connected to the third node N3. The first electrode of the ED can be connected via the third node N3 to the source of the fifth transistor T5 and the drain of the sixth transistor T6. Here, the first electrode of the ED can be an anode or a pixel electrode. The second electrode of the ED can be electrically connected to the low-potential line VSL and can receive a low-potential voltage EVSS from the low-potential line VSL. Here, the second electrode of the ED can be a cathode or a common electrode.

[0056] The second transistor T2 can be turned on by a first scan signal from the first scan line SCL1 to electrically connect the data line DL to the first node N1, which is connected to the gate of the first transistor T1. The second transistor T2 can be turned on based on the first scan signal to supply a data voltage to the first node N1. In the second transistor T2, the gate can be electrically connected to the first scan line SCL1, the drain can be electrically connected to the data line DL, and the source can be electrically connected to the first node N1.

[0057] The third transistor T3 can be turned on by the second scan signal of the second scan line SCL2 to electrically connect the reference voltage line VRL to the first node N1, which is connected to the gate of the first transistor T1. The third transistor T3 can be turned on based on the second scan signal to supply the reference voltage Vref to the first node N1. In the third transistor T3, the gate can be electrically connected to the second scan line SCL2, the drain can be electrically connected to the reference voltage line VRL, and the source can be electrically connected to the first node N1.

[0058] The fourth transistor T4 can be turned on by the first light emission signal of the first light emission control line EML1 to electrically connect the drive voltage line VDL to the drain of the first transistor T1. In the fourth transistor T4, the gate can be electrically connected to the first light emission control line EML1, the drain can be electrically connected to the drive voltage line VDL, and the source can be electrically connected to the drain of the first transistor T1.

[0059] The fifth transistor T5 can be turned on by the second light emission signal of the second light emission control line EML2 to electrically connect the second node N2 to the third node N3. In the fifth transistor T5, the gate can be electrically connected to the second light emission control line EML2, the drain can be electrically connected to the second node N2, and the source can be electrically connected to the third node N3.

[0060] The sixth transistor T6 can be turned on by the third scan signal of the third scan line SCL3 to electrically connect the third node N3, which is connected to the first electrode of the light-emitting element ED, to the initialization voltage line VIL. The sixth transistor T6 can be turned on based on the third scan signal to initialize the first electrode of the light-emitting element ED with an initialization voltage. In the sixth transistor T6, the gate can be electrically connected to the third scan line SCL3, the drain can be electrically connected to the third node N3, and the source can be electrically connected to the initialization voltage line VIL.

[0061] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an oxide-based active layer. These transistors may correspond to n-type transistors and output current flowing into the drain to the source based on a high gate voltage VGH applied to the gate. The oxide-based active layer can have a relatively small S-factor, increasing the constant current drive region in low grayscale areas and improving low grayscale performance.

[0062] As another example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an active layer formed of low-temperature polycrystalline silicon (LTPS). At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may correspond to a p-type transistor, and output the current flowing into the source to the drain based on a low gate voltage VGL applied to the gate.

[0063] The first capacitor C1 can be electrically connected between a first node N1 connected to the gate of the first transistor T1 and a second node N2 connected to the source of the first transistor T1. For example, the first capacitor electrode of the first capacitor C1 can be electrically connected to the first node N1, and the second capacitor electrode of the first capacitor C1 can be electrically connected to the second node N2, thereby maintaining the potential difference between the gate and source of the first transistor T1.

[0064] The second capacitor C2 can be electrically connected between the driving voltage line VDL and the second node N2, which is connected to the source of the first transistor T1. For example, the first capacitor electrode of the second capacitor C2 can be electrically connected to the driving voltage line VDL, and the second capacitor electrode of the second capacitor C2 can be electrically connected to the second node N2, thereby maintaining the potential difference between the driving voltage line VDL and the source of the first transistor T1.

[0065] Figure 4This is a cross-sectional view showing the circuitry of a display device according to one embodiment.

[0066] Reference Figure 4 The display panel 100 may include a substrate SUB, a first light-shielding layer LS1, a first buffer layer BF1, a second light-shielding layer LS2, a second buffer layer BF2, an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first protective layer PLN1, a source metal layer SDL, a second protective layer PLN2, a light-emitting element ED, a pixel defining layer PDL, a packaging layer TFEL, a first insulating layer IL1, a bridging electrode BRE, a second insulating layer IL2, a first touch electrode TE1, a second touch electrode TE2, and a planarization layer OC.

[0067] The substrate SUB can be a base substrate or a base component. The substrate SUB can include at least one plastic material. For example, the substrate SUB can be a multi-substrate comprising multiple plastic materials (e.g., polyimide), but the constituent materials of the substrate SUB are not limited to this.

[0068] A first light-shielding layer LS1 can be disposed on a substrate SUB. The first light-shielding layer LS1 may include a first capacitor electrode CPE1 of a first capacitor C1 and a first scan line SCL1. The first capacitor electrode CPE1 can be disposed below a first transistor T1 to block light incident on the first transistor T1. The first capacitor electrode CPE1 can overlap with a second capacitor electrode CPE2 to form the first capacitor C1. The first scan line SCL1 can supply a first scan signal to... Figure 3 The second transistor T2 is shown. The first light-shielding layer LS1 can be formed of a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, but is not limited thereto.

[0069] The first buffer layer BF1 may be disposed on the first light-shielding layer LS1. The first buffer layer BF1 may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include multiple inorganic membranes stacked alternately.

[0070] A second light-shielding layer LS2 may be disposed on the first buffer layer BF1. The second light-shielding layer LS2 may include a second capacitor electrode CPE2 of the first capacitor C1. The second capacitor electrode CPE2 may be disposed below the first transistor T1 to block light incident on the first transistor T1. The second capacitor electrode CPE2 may overlap with the first capacitor electrode CPE1 to form the first capacitor C1. The second light-shielding layer LS2 may contain, but is not limited to, the materials exemplified in the first light-shielding layer LS1.

[0071] The second buffer layer BF2 may be disposed on the second light-shielding layer LS2. The second buffer layer BF2 may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include multiple inorganic membranes stacked alternately.

[0072] The active layer ACTL can be disposed on the second buffer layer BF2. The active layer ACTL can contain oxide-based materials, but is not limited thereto. The active layer ACTL can include the semiconductor region ACT1, drain DE1, and source SE1 of the first transistor T1, and the semiconductor region ACT5, drain DE5, and source SE5 of the fifth transistor T5.

[0073] The gate insulating layer GI can be disposed on the active layer ACTL. The gate insulating layer GI can isolate the active layer ACTL1 and the gate layer GTL.

[0074] The gate layer GTL can be disposed on the gate insulating layer GI. The gate layer GTL may include the gate GE1 of the first transistor T1 and the gate GE5 of the fifth transistor T5. The gate GE5 of the fifth transistor T5 may be... Figure 3 A portion of the second light-emitting control line EML2 shown.

[0075] An interlayer insulating layer (ILD) can be disposed on the gate layer (GTL). The ILD can insulate the gate layer (GTL) from the source metal layer (SDL).

[0076] The first protective layer PLN1 can be disposed on the interlayer insulating layer (ILD). The first protective layer PLN1 can planarize the top of the transistor and protect the transistor. The first protective layer PLN1 can contain organic materials. For example, the first protective layer PLN1 can contain acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0077] A source metal layer (SDL) may be disposed on the first protective layer (PLN1). The source metal layer (SDL) may include a first connection electrode (CE1) and an anode connection electrode (ANE). The first connection electrode (CE1) may electrically connect the gate (GE1) of the first transistor (T1) and the first capacitor electrode (CPE1) of the first capacitor (C1). The first connection electrode (CE1) may be inserted into a second contact hole (CNT2) passing through the first protective layer (PLN1) and the interlayer insulating layer (ILD) to contact the gate (GE1) of the first transistor (T1). The first connection electrode (CE1) may be inserted into a third contact hole (CNT3) passing through the first protective layer (PLN1), the interlayer insulating layer (ILD), the gate insulating layer (GI), the second buffer layer (BF2), and the first buffer layer (BF1) to contact the first capacitor electrode (CPE1).

[0078] The anode connection electrode ANE can electrically connect the source SE5 to the pixel electrode AE ​​of the fifth transistor T5. The anode connection electrode ANE can be inserted into the first contact hole CNT1 that passes through the first protective layer PLN1, the interlayer insulating layer ILD, and the gate insulating layer GI to contact the source SE5 of the fifth transistor T5.

[0079] The second protective layer PLN2 can be disposed on the source metal layer SDL. The second protective layer PLN2 can planarize the upper part of the source metal layer SDL and protect the source metal layer SDL. The second protective layer PLN2 can contain organic materials. For example, the second protective layer PLN2 can contain the materials exemplified in the first protective layer PLN1, but is not limited thereto.

[0080] A pixel defining layer (PDL) can be disposed on the second protective layer (PLN2). The PDL can define a light-emitting area or an opening area. The PDL can contain materials including black pigments, such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymers, etc., but is not limited to these. When the PDL contains materials including black pigments, black dyes, etc., the PDL can be a black barrier. The PDL can contain black pigments or black dyes, thereby blocking external light and increasing the brightness of the display device 10.

[0081] Optionally, spacers (not shown) may be disposed on the pixel defining layer (PDL). The spacers may contain the same material as the pixel defining layer (PDL), but are not limited thereto.

[0082] The light-emitting element (ED) may include a pixel electrode AE, a light-emitting layer EL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on a second protective layer PLN2. The pixel electrode AE ​​may overlap with one of a plurality of light-emitting regions defined by a pixel defining layer PDL. The pixel electrode AE ​​may receive driving current from the pixel circuitry of the pixel PX. Figure 3 The first electrode of the light-emitting element ED.

[0083] The light-emitting layer EL can be disposed on the pixel electrode AE. For example, the light-emitting layer EL can be an organic light-emitting layer formed of organic materials, but is not limited to this.

[0084] The common electrode CAT can be disposed on the light-emitting layer EL. For example, the common electrode CAT can be implemented as an electrode shared by all pixels PX without being distinguished based on individual pixels PX. The common electrode CAT can be a transparent electrode and can transmit light. The common electrode CAT can be electrically connected to the low-potential line VSL and can receive low-potential voltage, common voltage, or cathode voltage. The common electrode CAT can be... Figure 3 The second electrode of the light-emitting element ED.

[0085] When the light-emitting layer EL corresponds to the organic light-emitting layer, when the pixel circuit of pixel PX applies a predetermined voltage to the pixel electrode AE ​​and the common electrode CAT receives the common voltage or the cathode voltage, holes can move to the light-emitting layer EL through the hole transport layer, electrons can move to the light-emitting layer EL through the electron transport layer, and holes and electrons can combine in the light-emitting layer EL to emit light.

[0086] The encapsulation layer TFEL can be disposed on the light-emitting element ED. The encapsulation layer TFEL can be disposed on the common electrode CAT to cover multiple light-emitting elements ED. The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 sequentially stacked on the common electrode CAT.

[0087] The first encapsulation layer TFE1 can be disposed on the common electrode CAT. The first encapsulation layer TFE1 can contain inorganic materials to prevent oxygen or moisture from penetrating the light-emitting element ED. For example, the first encapsulation layer TFE1 can include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0088] A second encapsulation layer TFE2 can be disposed on the first encapsulation layer TFE1 to planarize the upper part of the multiple light-emitting elements (EDs). The second encapsulation layer TFE2 can contain organic materials to protect the light-emitting elements (EDs) from foreign matter (such as dust). For example, the second encapsulation layer TFE2 can include organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The second encapsulation layer TFE2 can be formed by curing monomers or coating polymers.

[0089] A third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may contain inorganic materials to prevent oxygen or moisture from penetrating the light-emitting element ED. For example, the third encapsulation layer TFE3 may contain the materials exemplified in the first encapsulation layer TFE1, but is not limited thereto.

[0090] The first insulating layer IL1 may be disposed on the encapsulation layer TFEL. The first insulating layer IL1 may have both insulating and optical functions. The first insulating layer IL1 may include at least one inorganic film.

[0091] The bridging electrode BRE can be disposed on the first insulating layer IL1. The bridging electrode BRE can be disposed on a different layer from the first touch electrode TE1 and the second touch electrode TE2 to electrically connect the first touch electrode TE1 which is spaced apart from each other (the second touch electrode TE2 is inserted therebetween).

[0092] The second insulating layer IL2 can be disposed on the bridging electrode BRE. The second insulating layer IL2 can insulate the bridging electrode BRE from the first touch electrode TE1 and the second touch electrode TE2. The second insulating layer IL2 may include at least one inorganic film.

[0093] The first touch electrode TE1 and the second touch electrode TE2 can be disposed on the second insulating layer IL2. The first touch electrode TE1 and the second touch electrode TE2 can be formed from a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) and indium tin oxide (ITO), or formed from a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0094] A planarization layer OC can be disposed on the first touch electrode TE1 and the second touch electrode TE2. The planarization layer OC can planarize the upper parts of the first touch electrode TE1 and the second touch electrode TE2, and protect the first touch electrode TE1 and the second touch electrode TE2. The planarization layer OC can contain an organic insulating material.

[0095] The display device 10 can include only one source metal layer SDL between the transistor of the pixel circuit and the pixel electrode AE ​​of the light-emitting element ED, thereby reducing the number of masks and manufacturing costs in the manufacturing process. The display device 10 can reduce the number of conductive layers, thereby optimizing the process and shortening the manufacturing cycle.

[0096] Figure 5 This is a plan view showing voltage lines in a display device according to one embodiment. Figure 6 It is along Figure 5 A cross-sectional view of line I-I' in the diagram. Figure 7 It is along Figure 5 A cross-sectional view of line II-II' in the middle. Figure 8 It is along Figure 5 A cross-sectional view of line III-III' in the diagram. Figures 6 to 8 In the description of the cross-sectional view, the above will be briefly described or omitted. Figure 4 The configuration is described in the cross-sectional view.

[0097] Reference Figures 5 to 8 Flexible film FPCB can be passed through Figure 2 The second pad area PA2 shown is electrically connected to the display panel 100. The flexible film FPCB can supply a drive voltage EVDD to the drive voltage line VDL, a reference voltage Vref to the reference voltage line VRL, and an initialization voltage Vint to the initialization voltage line VIL.

[0098] The driving voltage line VDL may include a first driving voltage line VDL1, a second driving voltage line VDL2, a third driving voltage line VDL3, and a fourth driving voltage line VDL4. Figure 5 and Figure 7 In this configuration, the first driving voltage line VDL1 can extend from the source metal layer SDL along the second direction DR2. The first driving voltage line VDL1 can extend from the lower side of the non-display area NDA to the upper side of the display area DA. The first driving voltage line VDL1 can supply the driving voltage EVDD received from the flexible film FPCB to the display area DA. The first driving voltage line VDL1 can overlap with the fan-out line FOL on the lower side of the non-display area NDA and intersect with the third driving voltage line VDL3, the third reference voltage line VRL3, and the first low-potential line VSL1. The first driving voltage line VDL1 can intersect with the second driving voltage line VDL2 and the second reference voltage line VRL2 in the display area DA. The first driving voltage line VDL1 can intersect with the third driving voltage line VDL3 and the third reference voltage line VRL3 on the upper side of the non-display area NDA.

[0099] exist Figure 5 and Figure 7 In this configuration, the second driving voltage line VDL2 can extend from the first light-shielding layer LS1 along the first direction DR1. The second driving voltage line VDL2 can extend from the left side to the right side of the display area DA. The second driving voltage line VDL2 can be connected to the first driving voltage line VDL1 to receive the driving voltage EVDD and supply the driving voltage EVDD to the pixel PX.

[0100] exist Figure 5 and Figure 8 In this configuration, the third driving voltage line VDL3 can extend from the gate layer GTL along the first direction DR1. The third driving voltage line VDL3 can be positioned on each of the upper and lower sides of the non-display area NDA. The third driving voltage line VDL3 can intersect the fan-out line FOL, the first driving voltage line VDL1, the first reference voltage line VRL1, and the initialization voltage line VIL on the lower side of the non-display area NDA. The third driving voltage line VDL3 can be connected to the first driving voltage line VDL1 to receive the driving voltage EVDD and supply the driving voltage EVDD to the fourth driving voltage line VDL4.

[0101] The fourth driving voltage line VDL4 can extend along the second direction DR2 from each of the left and right sides of the non-display area NDA. The fourth driving voltage line VDL4 can be disposed between the gate driver 300 and the display area DA. Although not shown, the fourth driving voltage line VDL4 can be disposed in the source metal layer SDL. The fourth driving voltage line VDL4 can be electrically connected to the third driving voltage line VDL3 disposed above and below the non-display area NDA.

[0102] The reference voltage line VRL may include a first reference voltage line VRL1, a second reference voltage line VRL2, a third reference voltage line VRL3, and a fourth reference voltage line VRL4. Figure 5 and Figure 8 In this configuration, the first reference voltage line VRL1 can extend from the source metal layer SDL along the second direction DR2. The first reference voltage line VRL1 can extend from the lower side of the non-display area NDA to the upper side of the display area DA. The first reference voltage line VRL1 can supply the reference voltage Vref received from the flexible film FPCB to the display area DA. The first reference voltage line VRL1 can overlap with the fan-out line FOL on the lower side of the non-display area NDA and intersect with the third drive voltage line VDL3, the third reference voltage line VRL3, and the first low potential line VSL1. The first reference voltage line VRL1 can intersect with the second drive voltage line VDL2 and the second reference voltage line VRL2 in the display area DA. The first reference voltage line VRL1 can intersect with the third reference voltage line VRL3 on the upper side of the non-display area NDA.

[0103] exist Figure 5 and Figure 7 In this configuration, the second reference voltage line VRL2 can extend from the first light-shielding layer LS1 along the first direction DR1. The second reference voltage line VRL2 can extend from the left side to the right side of the display area DA. The second reference voltage line VRL2 can be connected to the first reference voltage line VRL1 to receive the reference voltage Vref and supply the reference voltage Vref to the pixel PX.

[0104] exist Figure 5 and Figure 8 In this configuration, the third reference voltage line VRL3 can extend from the gate layer GTL along the first direction DR1. The third reference voltage line VRL3 can be located on each of the upper and lower sides of the non-display area NDA. The third reference voltage line VRL3 can intersect the fan-out line FOL, the first drive voltage line VDL1, the first reference voltage line VRL1, and the initialization voltage line VIL on the lower side of the non-display area NDA. The third reference voltage line VRL3 can be connected to the first reference voltage line VRL1 to receive the reference voltage Vref and supply the reference voltage Vref to the fourth reference voltage line VRL4.

[0105] A fourth reference voltage line VRL4 may extend along the second direction DR2 from each of the left and right sides of the non-display area NDA. The fourth reference voltage line VRL4 may be disposed between the gate driver 300 and the display area DA. Although not shown, the fourth reference voltage line VRL4 may be disposed on the source metal layer SDL. The fourth reference voltage line VRL4 may be electrically connected to the third reference voltage line VRL3 disposed above and below the non-display area NDA.

[0106] exist Figure 5 and Figure 8 In this configuration, the initialization voltage line VIL can extend from the source metal layer SDL along the second direction DR2. The initialization voltage line VIL can extend from the underside of the non-display area NDA to the topside of the display area DA. The initialization voltage line VIL can supply the initialization voltage Vint received from the flexible film FPCB to the display area DA. The initialization voltage line VIL can overlap with the fan-out line FOL on the underside of the non-display area NDA and intersect with the third drive voltage line VDL3, the third reference voltage line VRL3, and the first low-potential line VSL1. The initialization voltage line VIL can intersect with the second drive voltage line VDL2 and the second reference voltage line VRL2 in the display area DA.

[0107] The low-potential line VSL may include a first low-potential line VSL1 and a second low-potential line VSL2. Although not shown, the first low-potential line VSL1 may extend from the gate layer GTL in the first direction DR1. The first low-potential line VSL1 may be located on each of the upper and lower sides of the non-display area NDA. The first low-potential line VSL1 may intersect with the fan-out line FOL, the first drive voltage line VDL1, the first reference voltage line VRL1, and the initialization voltage line VIL on the lower side of the non-display area NDA.

[0108] The second low-potential line VSL2 may extend along the second direction DR2 from each of the left and right sides of the non-display area NDA. The second low-potential line VSL2 may be disposed outside the gate driver 300. Although not shown, the second low-potential line VSL2 may be disposed in the source metal layer SDL. The second low-potential line VSL2 may be electrically connected to the first low-potential line VSL1 disposed above and below the non-display area NDA.

[0109] exist Figure 6 In this design, the flexible film FPCB may include lead electrodes (LDEs). The lead electrodes (LDEs) of the flexible film FPCB can be electrically connected to the pad portion (PAD) via the connecting film (ACF). The pad portion (PAD) can be... Figure 2The second pad region PA2 shown is disposed within the first light-shielding layer LS1. The flexible film FPCB can supply signals and voltages received from the controller 200, power supply unit 500, and host system to the display panel 100. The pad portion PAD can contact the initialization voltage line VIL inserted into the contact hole passing through the first protective layer PLN1, the interlayer insulating layer ILD, the gate insulating layer GI, the second buffer layer BF2, and the first buffer layer BF1.

[0110] exist Figure 7 In this configuration, the scan line SCL can extend from the first light-shielding layer LS1 along the first direction DR1. The scan line SCL can be... Figure 3 The first scan line SCL1 or the second scan line SCL2 shown in the figure.

[0111] The emission control line EML can extend from the first light-shielding layer LS1 along the first direction DR1. The emission control line EML can be... Figure 3 The first light emission control line EML1 or the second light emission control line EML2 shown in the figure.

[0112] exist Figure 8 In this configuration, the fan-out line FOL can be located within the first light-shielding layer LS1. The fan-out line FOL can supply the data voltage received from the data driver 400 to the data line DL of the display area DA.

[0113] Figures 9 to 13 This is a cross-sectional view of the manufacturing process of a display device according to one embodiment.

[0114] exist Figure 9 In this context, the substrate SUB can be a base substrate or a base component. The substrate SUB may include at least one plastic material. For example, the substrate SUB may be a multi-substrate comprising multiple plastic materials (e.g., polyimide), but the constituent materials of the substrate SUB are not limited to this.

[0115] The first light-shielding layer LS1 may be disposed on the substrate SUB. The first light-shielding layer LS1 may include the first capacitor electrode CPE1 of the first capacitor C1 and the first scan line SCL1. The first light-shielding layer LS1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, but is not limited thereto.

[0116] The first buffer layer BF1 may be disposed on the first light-shielding layer LS1. The first buffer layer BF1 may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include multiple inorganic membranes stacked alternately.

[0117] A second light-shielding layer LS2 may be disposed on the first buffer layer BF1. The second light-shielding layer LS2 may include a second capacitor electrode CPE2 of the first capacitor C1. The second capacitor electrode CPE2 may overlap with the first capacitor electrode CPE1 to form the first capacitor C1. The second light-shielding layer LS2 may contain, but is not limited to, the materials exemplified in the first light-shielding layer LS1.

[0118] The second buffer layer BF2 may be disposed on the second light-shielding layer LS2. The second buffer layer BF2 may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include multiple inorganic membranes stacked alternately.

[0119] The active layer ACTL can be disposed on the second buffer layer BF2. The active layer ACTL can include, but is not limited to, an oxide-based material. The active layer ACTL can include the semiconductor region ACT1, drain DE1, and source SE1 of the first transistor T1, and the semiconductor region ACT5, drain DE5, and source SE5 of the fifth transistor T5.

[0120] The gate insulating layer GI can be disposed on the active layer ACTL. The gate insulating layer GI can isolate the active layer ACTL1 from the gate layer GTL.

[0121] The gate layer GTL can be disposed on the gate insulating layer GI. The gate layer GTL may include the gate GE1 of the first transistor T1 and the gate GE5 of the fifth transistor T5.

[0122] exist Figure 10 In this configuration, the interlayer insulating layer (ILD) can be disposed on the gate layer (GTL). The ILD can insulate the gate layer (GTL) from the source metal layer (SDL).

[0123] The first protective layer PLN1 can be disposed on the interlayer insulating layer (ILD). The first protective layer PLN1 can planarize the top of the transistor and protect the transistor. The first protective layer PLN1 can contain organic materials. For example, the first protective layer PLN1 can contain acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0124] The first contact hole CNT1 can be etched from the upper surface of the first protective layer PLN1 and can penetrate the lower surface of the gate insulating layer GI. The first contact hole CNT1 can expose a portion of the upper surface of the source SE5 of the fifth transistor T5.

[0125] The second contact hole CNT2 can be etched from the upper surface of the first protective layer PLN1 and can penetrate the lower surface of the interlayer insulating layer ILD. The second contact hole CNT2 can expose a portion of the upper surface of the gate GE1 of the first transistor T1.

[0126] The third contact hole CNT3 can be etched from the upper surface of the first protective layer PLN1 and can penetrate the lower surface of the first buffer layer BF1. The third contact hole CNT3 can expose a portion of the upper surface of the first capacitor electrode CPE1.

[0127] The upper surface of the first protective layer PLN1 can be etched using at least one of dry etching, plasma etching, and laser etching processes. A mask formed on the first protective layer PLN1 can be used to form the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3. Therefore, the display device 10 can include only one source metal layer SDL between the transistor of the pixel circuit and the pixel electrode AE ​​of the light-emitting element ED, thereby reducing the number of masks and manufacturing costs in the manufacturing process. The display device 10 can reduce the number of conductive layers, thereby optimizing the process and shortening the manufacturing cycle.

[0128] exist Figure 11 In this configuration, the source metal layer SDL can be disposed on the first protective layer PLN1. The source metal layer SDL may include a first connection electrode CE1 and an anode connection electrode ANE. The first connection electrode CE1 can electrically connect the gate GE1 of the first transistor T1 and the first capacitor electrode CPE1 of the first capacitor C1. The first connection electrode CE1 can be inserted into the second contact hole CNT2 to contact the gate GE1 of the first transistor T1. The first connection electrode CE1 can be inserted into the third contact hole CNT3 to contact the first capacitor electrode CPE1.

[0129] The anode connection electrode ANE can electrically connect the source SE5 of the fifth transistor T5 to the pixel electrode AE. The anode connection electrode ANE can be inserted into the first contact hole CNT1 to contact the gate SE5 of the first transistor T5.

[0130] The second protective layer PLN2 can be disposed on the source metal layer SDL. The second protective layer PLN2 can planarize the upper part of the source metal layer SDL and protect the source metal layer SDL. The second protective layer PLN2 can contain organic materials. For example, the second protective layer PLN2 can contain the materials exemplified in the first protective layer PLN1, but is not limited thereto.

[0131] The fourth contact hole CNT4 can be etched from the upper surface of the second protective layer PLN2 and can penetrate the lower surface of the second buffer layer PLN2. The fourth contact hole CNT4 can expose a portion of the upper surface of the anode connection electrode ANE.

[0132] exist Figure 12 In this configuration, the pixel electrode AE ​​can be disposed on the second protective layer PLN2. The pixel electrode AE ​​can be inserted into the fourth contact hole CNT4 to contact the anode connection electrode ANE.

[0133] The pixel defining layer (PDL) can be disposed on the second protective layer (PLN2). The PDL can define a light-emitting region (EA) or an opening region. The light-emitting region (EA) can be disposed on the upper surface of the pixel electrode (AE). The PDL can contain materials including black pigments, and organic materials such as benzocyclobutene resin, polyimide resin, acrylic resin, and photosensitive polymers, but is not limited thereto. When the PDL contains materials including black pigments or black dyes, the PDL can be a black barrier. The PDL can contain black pigments or black dyes to block external light and increase the brightness of the display device 10.

[0134] exist Figure 13 In this process, the light-emitting layer EL can be disposed on the pixel electrode AE. For example, the light-emitting layer EL can be an organic light-emitting layer formed of organic materials, but it is not limited to this.

[0135] The common electrode CAT can be disposed on the light-emitting layer EL. For example, the common electrode CAT can be implemented as an electrode shared by all pixels PX without being differentiated based on individual pixels PX. The common electrode CAT can be a transparent electrode and can transmit light. The common electrode CAT can be electrically connected to the low-potential line VSL and can receive low-potential voltage, common voltage, or cathode voltage.

[0136] The display device 10 according to various embodiments of the present disclosure can be described as follows.

[0137] According to various embodiments of this disclosure, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area; a first light-shielding layer disposed on the substrate; an active layer including a semiconductor region of a first transistor and disposed on the first light-shielding layer; a gate layer including a gate of the first transistor and disposed on the active layer; a source metal layer disposed on the gate layer and including an anode connection electrode directly connected to the active layer and receiving a driving current flowing in the first transistor; a pixel electrode disposed on the source metal layer and directly connected to the anode connection electrode; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer.

[0138] The display device according to various embodiments of the present disclosure may further include: a second light-shielding layer disposed between the first light-shielding layer and the active layer; and a first capacitor formed between the gate and the source of the first transistor, wherein the first capacitor may include: a first capacitor electrode disposed in the first light-shielding layer and electrically connected to the gate of the first transistor; and a second capacitor electrode disposed in the second light-shielding layer and electrically connected to the source of the first transistor.

[0139] In the display device according to various embodiments of the present disclosure, the first capacitor electrode and the second capacitor electrode may overlap with the semiconductor region of the first transistor.

[0140] The display device according to various embodiments of the present disclosure may further include: a first scan line disposed in a first light-shielding layer and supplying a first scan signal; and a second transistor supplying a data voltage to the gate of the first transistor based on the first scan signal.

[0141] The display device according to various embodiments of the present disclosure may further include: a third transistor that supplies a reference voltage to the gate of the first transistor based on a second scan signal; a fourth transistor that supplies a driving voltage to the drain of the first transistor based on a first light emission signal; and a fifth transistor that electrically connects the source of the first transistor to a pixel electrode based on a second light emission signal.

[0142] The display device according to various embodiments of the present disclosure may further include a sixth transistor, which supplies an initialization voltage to the pixel electrode of the light-emitting element based on a third scan signal.

[0143] In the display device according to various embodiments of the present disclosure, the source metal layer may further include a first connection electrode that electrically connects the gate of the first transistor to the first capacitor electrode.

[0144] The display device according to various embodiments of the present disclosure may further include a flexible film disposed on a first side of a non-display area, and a pad portion disposed in a first light-shielding layer and electrically connected to the flexible film.

[0145] The display device according to various embodiments of the present disclosure may further include: a first driving voltage line disposed in a source metal layer and extending in a second direction from a first side of a non-display area to a second side of a non-display area opposite to the first side; a second driving voltage line disposed in a first light-shielding layer and extending in a display area in a first direction intersecting the second direction; and a third driving voltage line disposed in a gate layer and extending in a first direction on both the first and second sides of a non-display area.

[0146] The display device according to various embodiments of the present disclosure may further include: a data driver disposed between the flexible film and the display area and supplying data voltage; and a fan-out line disposed in the first light-shielding layer, extending from the data driver to the display area and overlapping with the first driving voltage line and the third driving voltage line.

[0147] The display device according to various embodiments of the present disclosure may further include: a first low-potential line disposed in a gate layer and extending in a first direction on a first side and a second side of a non-display area; and a second low-potential line disposed in a source metal layer and extending in a second direction on a third side adjacent to the first side and a fourth side opposite to the third side of a non-display area and electrically connected to the first low-potential line.

[0148] The display device according to various embodiments of the present disclosure may further include: a fourth driving voltage line disposed in the source metal layer and extending in a second direction on the third and fourth sides of the non-display area and electrically connected to the third driving voltage line; and a gate driver disposed between the fourth driving voltage line and the second low potential line and supplying a gate signal.

[0149] The display device according to various embodiments of the present disclosure may further include: a first contact hole, through which an anode connection electrode is connected to the source of a fifth transistor; and a fourth contact hole, through which a pixel electrode is connected to the anode connection electrode.

[0150] According to various embodiments of this disclosure, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area; a light-emitting element including a pixel electrode and emitting light; a first transistor supplying a drive current to the pixel electrode; an active layer disposed on the substrate and including a semiconductor region of the first transistor; a second transistor supplying a data voltage to the gate of the first transistor based on a first scan signal; a third transistor supplying a reference voltage to the gate of the first transistor based on a second scan signal; a fourth transistor supplying a drive voltage to the drain of the first transistor based on a first light-emitting signal; a fifth transistor including a drain and a source, the drain and source of the fifth transistor being disposed in the active layer and the source of the first transistor being electrically connected to the pixel electrode based on the second light-emitting signal; and an anode connection electrode directly connecting the source of the fifth transistor to the pixel electrode.

[0151] The display device according to various embodiments of the present disclosure may further include: a first light-shielding layer disposed between a substrate and an active layer; a gate layer including the gate of a first transistor and disposed on the active layer; and a source metal layer disposed on the gate layer and including an anode connection electrode.

[0152] The display device according to various embodiments of the present disclosure may further include: a second light-shielding layer disposed between the first light-shielding layer and the active layer; and a first capacitor including a first capacitor electrode disposed in the first light-shielding layer and electrically connected to the gate of the first transistor and a second capacitor electrode disposed in the second light-shielding layer and electrically connected to the source of the first transistor.

[0153] In the display device according to various embodiments of the present disclosure, the source metal layer may further include a first connection electrode that electrically connects the gate of the first transistor to the first capacitor electrode.

[0154] The display device according to various embodiments of the present disclosure may further include: a first scan line disposed in a first light-shielding layer and supplying a first scan signal to the gate of a second transistor; and a second scan line disposed in the first light-shielding layer and supplying a second scan signal to the gate of a third transistor.

[0155] The display device according to various embodiments of the present disclosure may further include a flexible film disposed on a first side of a non-display area and a pad portion disposed in a first light-shielding layer and electrically connected to the flexible film.

[0156] The display device according to various embodiments of the present disclosure may further include: a first driving voltage line disposed in a source metal layer and extending in a second direction from a first side of a non-display area to a second side of a non-display area opposite to the first side; a second driving voltage line disposed in a first light-shielding layer and extending in a display area in a first direction intersecting the second direction; and a third driving voltage line disposed in a gate layer and extending in a first direction on both the first and second sides of a non-display area.

[0157] The display device according to various embodiments of the present disclosure may further include: a data driver disposed between the flexible film and the display area and supplying data voltage; and a fan-out line disposed in the first light-shielding layer, extending from the data driver to the display area and overlapping with the first driving voltage line and the third driving voltage line.

[0158] The display device according to various embodiments of the present disclosure may further include: a first contact hole, through which an anode connection electrode is connected to the source of a fifth transistor; and a fourth contact hole, through which a pixel electrode is connected to the anode connection electrode.

[0159] In the display device according to embodiments of the present disclosure, by including only one source metal layer between the transistor of the pixel circuit and the pixel electrode of the light-emitting element, the number of masks in the manufacturing process can be reduced and the manufacturing cost can be lowered.

[0160] In the display device according to embodiments of the present disclosure, the process can be optimized by reducing the number of conductive layers.

[0161] However, the effects that can be obtained from this disclosure are not limited to those described above, and based on the following description, those skilled in the art to which this disclosure pertains will be able to clearly understand other effects not mentioned.

[0162] Although one embodiment has been described above with reference to the accompanying drawings, those skilled in the art to which this disclosure pertains will understand that the above-described technical configuration of the invention can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. Furthermore, the scope of the specification is defined by the claims to be described rather than by a detailed description. Moreover, the meaning and scope of the claims, as well as all changes or modifications derived from equivalent concepts, should be interpreted as being included within the scope of this specification.

[0163] Explanation of reference numerals in the attached figures 10: Display device 100: Display panel 200: Controller; 300: Gate Driver 400: Data driver; 500: Power supply unit LS1: First light-shielding layer LS2: Second light-shielding layer ACTL: Active Layer; GTL: Gate Layer SDL: Source Metal Layer; ED: Light Emitting Element

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area surrounding the display area; A first light-shielding layer is disposed on the substrate; An active layer includes a semiconductor region of a first transistor and is disposed on the first light-shielding layer; A gate layer, including the gate of the first transistor and disposed on the active layer; A source metal layer is disposed on the gate layer and includes an anode connection electrode that is directly connected to the active layer and receives a drive current flowing in the first transistor. A pixel electrode is disposed on the source metal layer and directly connected to the anode connection electrode; A light-emitting layer is disposed on the pixel electrode; as well as A common electrode is disposed on the light-emitting layer.

2. The display device according to claim 1, further comprising: A second light-shielding layer is disposed between the first light-shielding layer and the active layer; as well as A first capacitor is formed between the gate and the source of the first transistor. The first capacitor includes: A first capacitor electrode is disposed in the first light-shielding layer and electrically connected to the gate of the first transistor; and The second capacitor electrode is disposed in the second light-shielding layer and electrically connected to the source electrode of the first transistor.

3. The display device according to claim 2, wherein, The first capacitor electrode and the second capacitor electrode overlap with the semiconductor region of the first transistor.

4. The display device according to claim 2, further comprising: A first scan line is disposed in the first light-shielding layer and supplies a first scan signal; as well as The second transistor supplies a data voltage to the gate of the first transistor based on the first scan signal.

5. The display device according to claim 4, further comprising: The third transistor supplies a reference voltage to the gate of the first transistor based on the second scan signal; The fourth transistor supplies a driving voltage to the drain of the first transistor based on the first light-emitting signal; as well as The fifth transistor electrically connects the source of the first transistor to the pixel electrode based on the second light-emitting signal.

6. The display device according to claim 5, further comprising a sixth transistor, the sixth transistor supplying an initialization voltage to the pixel electrode of the light-emitting element based on a third scan signal.

7. The display device according to claim 2, wherein, The source metal layer further includes a first connection electrode that electrically connects the gate of the first transistor to the first capacitor electrode.

8. The display device according to claim 1, further comprising: A flexible film is disposed on the first side of the non-display area; The pad portion is disposed in the first light-shielding layer and electrically connected to the flexible membrane; A first driving voltage line is disposed in the source metal layer and extends in a second direction from the first side of the non-display area to the second side of the non-display area opposite to the first side. A second driving voltage line is disposed in the first light-shielding layer and extends in the display area in a first direction intersecting the second direction; as well as A third driving voltage line is disposed in the gate layer and extends in the first direction on the first side and the second side of the non-display area.

9. The display device according to claim 8, further comprising: A data driver is disposed between the flexible film and the display area and supplies data voltage; as well as A fan-out line is disposed in the first light-shielding layer, extends from the data driver to the display area, and overlaps with the first driving voltage line and the third driving voltage line.

10. The display device according to claim 8, further comprising: A first low-potential line is disposed in the gate layer and extends in the first direction on the first side and the second side of the non-display area; as well as A second low-potential line is disposed in the source metal layer and extends in the second direction on the third side adjacent to the first side and the fourth side opposite to the third side in the non-display area, and is electrically connected to the first low-potential line.

11. The display device according to claim 10, further comprising: A fourth driving voltage line is disposed in the source metal layer and extends in the second direction on the third and fourth sides of the non-display area and is electrically connected to the third driving voltage line; as well as A gate driver is disposed between the fourth drive voltage line and the second low potential line and supplies the gate signal.

12. The display device according to claim 5, further comprising: The anode connection electrode is connected to the source of the fifth transistor through the first contact hole; as well as The fourth contact hole is through which the pixel electrode is connected to the anode connection electrode.

13. A display device, comprising: A substrate, comprising a display area and a non-display area surrounding the display area; Light-emitting elements, including pixel electrodes, emit light; The first transistor supplies driving current to the pixel electrode; An active layer is disposed on the substrate and includes the semiconductor region of the first transistor; The second transistor supplies data voltage to the gate of the first transistor based on the first scan signal; The third transistor supplies a reference voltage to the gate of the first transistor based on the second scan signal; The fourth transistor supplies a driving voltage to the drain of the first transistor based on the first light-emitting signal; A fifth transistor includes a drain and a source, the drain and the source of the fifth transistor are disposed in the active layer and the source of the first transistor is electrically connected to the pixel electrode based on a second light-emitting signal; as well as The anode connection electrode connects the source of the fifth transistor directly to the pixel electrode.

14. The display device according to claim 13, further comprising: A first light-shielding layer is disposed between the substrate and the active layer; A gate layer, including the gate of the first transistor and disposed on the active layer; as well as A source metal layer is disposed on the gate layer and includes the anode connection electrode.

15. The display device according to claim 14, further comprising: A second light-shielding layer is disposed between the first light-shielding layer and the active layer; as well as The first capacitor includes a first capacitor electrode disposed in the first light-shielding layer and electrically connected to the gate of the first transistor, and a second capacitor electrode disposed in the second light-shielding layer and electrically connected to the source of the first transistor.

16. The display device according to claim 15, wherein, The source metal layer further includes a first connection electrode that electrically connects the gate of the first transistor to the first capacitor electrode.

17. The display device according to claim 14, further comprising: A first scan line is disposed in the first light-shielding layer and supplies the first scan signal to the gate of the second transistor; as well as The second scan line is disposed in the first light-shielding layer and supplies the second scan signal to the gate of the third transistor.

18. The display device according to claim 14, further comprising: A flexible film is disposed on the first side of the non-display area; The pad portion is disposed in the first light-shielding layer and electrically connected to the flexible membrane; A first driving voltage line is disposed in the source metal layer and extends in a second direction from the first side of the non-display area to the second side of the non-display area opposite to the first side. A second driving voltage line is disposed in the first light-shielding layer and extends in the display area in a first direction intersecting the second direction; as well as A third driving voltage line is disposed in the gate layer and extends in the first direction on the first side and the second side of the non-display area.

19. The display device according to claim 18, further comprising: A data driver is disposed between the flexible film and the display area and supplies data voltage; as well as A fan-out line is disposed in the first light-shielding layer, extends from the data driver to the display area, and overlaps with the first driving voltage line and the third driving voltage line.

20. The display device according to claim 13, further comprising: The anode connection electrode is connected to the source of the fifth transistor through the first contact hole; as well as The fourth contact hole is through which the pixel electrode is connected to the anode connection electrode.

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