Long codeword LDPC coding and lifting matrix design for next generation WLAN

Abstract

The present disclosure relates to techniques related to low density parity check (LDPC) coding having a longer codeword length and its lifting matrix design in next generation wireless local area network (WLAN) systems. A device (e.g., a station (STA)) encodes a plurality of bits using an extended codeword length that is longer than an existing LDPC parity check matrix. The device then communicates using the encoded plurality of bits in the wireless communication system.

Description

[0001] Cross-references

[0002] This disclosure is part of a non-provisional patent application claiming priority to U.S. Provisional Patent Applications Nos. 63 / 535,825 and 63 / 581,307, filed August 31, 2023 and September 8, 2023, respectively, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to wireless communications, and more specifically, to low-density parity-check (LDPC) coding for next-generation wireless local area network (WLAN) systems in wireless communications, as well as the design of its extended codeword length and lifting matrix. Background Technology

[0004] Unless otherwise stated herein, the methods described in this section are not prior art to the claims listed below, and are not recognized as prior art by virtue of being included in this section.

[0005] In wireless communication, low-density parity-check (LDPC) coding has been used in cellular communications (e.g., fifth-generation (5G) / New Radio (NR)), conforming to the 3GPP (3rd Generation Partnership Project) standards, and in Wi-Fi (or WiFi) and wireless local area network (WLAN) systems conforming to the IEEE 802.11 standard. In IEEE 802.11n / ac / ax / be, the coding rates are R = 1 / 2, 2 / 3, 3 / 4, and 5 / 6, and the codeword lengths are L = 648, 1296 (= 2... 648) and 1944 (= 3) (648). The LDPC parity check matrix is ​​defined by a permutation matrix with a submatrix size of Z = 27, 54, 81. However, to enhance system performance and coverage, higher LDPC coding rates and increased codeword lengths may be required, but these are not yet defined. Therefore, a solution is needed to implement LDPC coding with longer codeword lengths and its boosting matrix design for use in next-generation WLAN systems. Summary of the Invention

[0006] The following summary is provided for purposes of illustration only and is not intended to be limiting in any aspect. That is, the following summary is intended to introduce concepts, highlights, benefits and advantages of the novel and non-obvious technology described herein. The selected embodiments will be further described in the detailed description. Thus, the following summary does not identify key features of the claimed subject matter and is not intended to be used to determine the scope of the claimed subject matter.

[0007] It is an object of the present disclosure to provide schemes, concepts, designs, techniques, methods and apparatuses related to low-density parity-check (LDPC) coding with longer code word length and its lifting matrix design for wireless communication in next generation wireless local area network (WLAN) systems. It is believed that implementation of various schemes presented herein can extend LDPC code word length using L = 2 1296 (= 4 648) and 2 1944 (= 6 648), corresponding to new parity check matrices.

[0008] In one aspect, a method can involve encoding a plurality of bits using an extended code word length, which can be greater than a code word length corresponding to an existing LDPC parity check matrix. The method can also involve communicating the encoded plurality of bits in a wireless communication system.

[0009] In another aspect, an apparatus can include a transceiver configured for wireless communication and a processor coupled with the transceiver. The processor can encode a plurality of bits using an extended code word length, which can be greater than a code word length corresponding to an existing LDPC parity check matrix. The processor can also communicate the encoded plurality of bits in a wireless communication system.

[0010] It is noted that although the description provided herein can be in the context of certain wireless access technologies, networks and network topologies, such as Wi-Fi, the concepts, schemes and any variants / derivatives thereof presented can be implemented in, for and by other types of wireless access technologies, networks and network topologies, such as, but not limited to, Bluetooth, ZigBee, Fifth Generation (5G) / New Radio (NR), Long Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, Internet of Things (IoT), Industrial Internet of Things (IIoT) and Narrow Band-Internet of Things (NB-IoT). Thus, the scope of the present disclosure is not limited to the examples described herein. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. It should be understood that the drawings are not necessarily to scale, as some components can be shown exaggerated or in a schematic manner in the interest of clarity and conciseness, and are intended as illustrative examples of the disclosure.

[0012] Figure 1 FIG. 1 is a diagram of an example network environment, in which various solutions and schemes according to the present disclosure can be implemented.

[0013] Figure 2 FIG. 2 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0014] Figure 3 FIG. 3 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0015] Figure 4 FIG. 4 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0016] Figure 5 FIG. 5 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0017] Figure 6 FIG. 6 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0018] Figure 7 FIG. 7 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0019] Figure 8 FIG. 8 is a diagram of an example scenario, based on suggested schemes of the present disclosure.

[0020] Figure 9 FIG. 9 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0021] Figure 10 FIG. 10 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0022] Figure 11 FIG. 11 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0023] Figure 12 FIG. 12 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0024] Figure 13 FIG. 13 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0025] Figure 14 FIG. 14 is a diagram of an example design, based on suggested schemes of the present disclosure.

[0026] Figure 15 is a diagram of an example design, based on the proposed solution of the present disclosure.

[0027] Figure 16 is a diagram of an example design, based on the proposed solution of the present disclosure.

[0028] Figure 17 is a diagram of an example design, based on the proposed solution of the present disclosure.

[0029] Figure 18 is a block diagram of an example communication system, based on one embodiment of the present disclosure.

[0030] Figure 19 is a flow diagram of an example process, based on one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Detailed embodiments and implementations of the claimed subject matter are disclosed herein. It is understood, however, that the disclosed embodiments and implementations are merely examples of the claimed subject matter and can be embodied in various forms. The disclosure can be implemented in numerous ways, including but not limited to the exemplary embodiments and implementations described herein. Rather, these exemplary embodiments and implementations are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. In the following description, details of well-known features and techniques can be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

[0032] SUMMARY

[0033] Implementations in accordance with the present disclosure relate to various techniques, methods, schemes and / or solutions related to LDPC encoding with longer code word length and its lifting matrix design for wireless communication in next generation wireless local area network systems. In accordance with the present disclosure, many possible solutions can be implemented individually or jointly. That is, although these possible solutions can be described below separately, two or more of these possible solutions can be implemented in one combination or another combination.

[0034] Figure 1 An example network environment 100 in which various solutions and proposed schemes in accordance with the present disclosure can be implemented is shown. Figures 2 to 19 Examples of various proposed schemes implemented in network environment 100 in accordance with the present disclosure are shown. The following description of various proposed schemes is made with reference to Figures 1 to 19 provided.

[0035] Reference is made to Figure 1(A), the network environment 100 can involve at least one station (STA) 110 in wireless communication with a STA 120. Either of the STA 110 and the STA 120 can function as an access point (AP) STA or as a non-AP STA. In some cases, the STA 110 and the STA 120 can be associated with a basic service set (BSS) in compliance with one or more IEEE 802.11 standards (e.g., IEEE 802.11be and future developed standards). Each of the STA 110 and the STA 120 can be configured to communicate by utilizing LDPC encoding with longer codeword length and its lifting matrix design for wireless communication in next generation wireless local area network systems in compliance with various proposed schemes described below. Notably, while various proposed schemes can be described below separately or individually, in actual implementation, some or all of the proposed schemes can be used or implemented jointly. Of course, each of the proposed schemes can be used or implemented separately or individually.

[0036] According to current IEEE 802.11 specifications, e.g., IEEE 802.11n / ac / ax / be, the LDPC code rate R can be 1 / 2, 2 / 3, 3 / 4, or 5 / 6. As for the codeword (K = L R), the codeword length L can be 648, 1296, or 1944. Accordingly, the parity matrix Z can be 27, 54, or 81. With reference to Figure 1 (B), the code rate = k / n, the number of rows can be n – k, the number of columns for information bits can be k, and the number of columns for parity bits can be n – k, corresponding to the following parameters: codeword length = n, information portion = k, parity portion = n – k. For example, for R = 3 / 4 and Z = 81, the codeword length = n = 24 Z, the number of columns for information portion = k = 18 Z, the number of columns for parity portion = n – k = 6 Z.

[0037] According to various proposed schemes of the present disclosure, the parity check of the existing LDPC in IEEE 802.11n / ac / ax / be compliant wireless communication can be defined by a submatrix size Z and a permutation value P ij of a given element (i,j) in the parity check matrix H. Under the proposed schemes, for a codeword length L = 1296, a submatrix size Z = 54, an extended submatrix size Z = 2 1296 LDPC code can be defined. 54 = 108, and in the new LDPC parity check matrix with extended codeword length 2 1296, the permutation value at position (i,j) is 2 P ij + δ ij , where P ij is the value of the LDPC parity check matrix L = 1296 at position (i,j), and δ ij has a value of 0 or 1. Further, for a codeword length L = 1944, a submatrix size Z = 81, the extended submatrix size Z = 2 1944 LDPC code can be defined as 81 = 162, and in the new LDPC parity check matrix with extended codeword length 2 1944, the permutation value at position (i,j) is 2 P ij + δ ij , where P ij is the value of the LDPC parity check matrix L = 1944 at position (i,j), and δ ij has a value of 0 or 1.

[0038] Figure 2 An example design 200 under the proposed scheme of the present disclosure is shown. The design 200 can involve a parity check matrix of a 2 1296 LDPC code. Under the proposed scheme, the coding rate R = ½, a submatrix size Z = 2 54 = 108. In the design 200, “-1” denotes a Z X Z zero matrix, and “0” denotes a Z X Z identity matrix.

[0039] Figure 3 An example design 300 under the proposed scheme of the present disclosure is shown. The design 300 can involve a parity check matrix of a 2 1296 LDPC code. Under the proposed scheme, the coding rate R = 2 / 3, a submatrix size Z = 2 54 = 108. In the design 300, “-1” denotes a Z X Z zero matrix, and “0” denotes a Z X Z identity matrix.

[0040] Figure 4 An example design 400 under the proposed scheme of the present disclosure is shown. The design 400 can involve a parity check matrix of a 2 1296 LDPC code. Under the proposed scheme, the coding rate R = 3 / 4, a submatrix size Z = 2 54 = 108, asFigure 4 of (A). Alternatively, the code rate R = 5 / 6, and the submatrix size Z = 2 54 = 108, as shown in (A) of Figure 4 of (B). In the design 400, "-1" represents a Z X Z zero matrix, and "0" represents a Z X Z identity matrix.

[0041] Figure 5 An example design 500 under the proposed scheme of the present disclosure is shown. The design 500 can involve a 2 1944 LDPC code. Under the proposed scheme, the code rate R = 1 / 2, and Z = 2 81 = 162, as shown in (A) of

[0042] Figure 6 An example design 600 under the proposed scheme of the present disclosure is shown. The design 600 can involve a 2 1944 LDPC code. Under the proposed scheme, the code rate R = 2 / 3, and Z = 2 81 = 162, as shown in (A) of

[0043] Figure 7 An example design 700 under the proposed scheme of the present disclosure is shown. The design 700 can involve a 2 1944 LDPC code. Under the proposed scheme, the code rate R = 3 / 4, and Z = 2 81 = 162, as shown in (A) of Figure 7 of (B). Alternatively, the code rate R = 5 / 6, and Z = 2 81 = 162, as shown in (A) of Figure 7 of (B). In the design 400, "-1" represents a Z X Z zero matrix, and "0" represents a Z X Z identity matrix.

[0044] Figure 8 An example scenario 800 under the proposed scheme of the present disclosure is shown. The scenario 800 can involve extending the LDPC codeword length by using a lifting matrix. As defined in IEEE 802.1 lad, the code rate can be 1 / 2, 5 / 8, 3 / 4, or 13 / 16, and for the parity matrix, Z = 42, H = 336 672, 252 672, 168 672 or 126 672. As defined in IEEE 802.11ay, the code rate can be 1 / 2, 5 / 8, 3 / 4, 13 / 16, 7 / 8, 2 / 3, or 5 / 6, and for the parity matrix, Z = 42, code length = 672, H = 336, respectively. 672, 252 672, 168 672, 126 672, 2Z 2Z, using a lifting matrix, code length = 2 672 = 1344. Under the proposed scheme, the LDPC codeword length can be increased using a lifting matrix similar to that defined in IEEE 802.11ay.

[0045] Reference Figure 8 (A) shows the original code rate R = 3 / 4 LDPC parity check matrix, Z = 42, 168 rows x 672 columns. Figure 8 (B) shows the lifting matrix for code rate 3 / 4. Figure 8 (C) shows the LDPC code matrix for code rate 3 / 4 by applying the lifting matrix of Figure 8 (B) to the original LDPC parity check matrix of Figure 8 (A). The resulting matrix can be double size, with 2 168 rows x 2 672 columns = 336 rows x 1344 columns.

[0046] Figure 9 An example design 900 under the proposed scheme according to the disclosure is shown. The design 900 can involve increasing the LDPC codeword length by one step lifting. Under the proposed scheme, as shown in Figure 9 (A), the non-empty elements "0" in the lifting matrix can act on the Z x Z circulant permutation matrix Pi in the LDPC parity check matrix, resulting in or producing a 2Z x 2Z submatrix to double (2x) the codeword length, where "i" represents the value of the original element of the Z x Z circulant permutation matrix Pi, which is copied and arranged along the diagonal from the top left corner to the bottom right corner of the 2Z x 2Z submatrix, and the value "-1" is copied and arranged along the opposite diagonal from the top right corner to the bottom left corner of the 2Z x 2Z submatrix.

[0047] Under the proposed scheme, as shown in Figure 9As shown in (B), a non-empty element "1" in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix, resulting in or producing a 2Z x 2Z submatrix with twice the (2x) extended codeword length, where "i" represents the value of the original element of the Z x Z cyclic permutation matrix Pi, which is copied and arranged along the diagonal from the upper right corner to the lower left corner of the 2Z x 2Z submatrix, while the value "-1" is copied and arranged along the opposite diagonal from the upper left corner to the lower right corner of the 2Z x 2Z submatrix.

[0048] Under the proposed solution, such as Figure 9 As shown in (C), the non-empty element "-1" in the lifting matrix may act on the Z x Z cyclic permutation matrix Pi in the LDPC parity matrix, resulting in or producing a 2Z x 2Z submatrix with twice the (2x) extended codeword length, where the value "-1" is copied and arranged in the four corners of the 2Z x 2Z submatrix.

[0049] Figure 10 An example design 1000 is shown under the proposed scheme according to this disclosure. Design 1000 may involve L = 2 Example of lifting matrix design in 1944 with R = 1 / 2. Figure 10 (A) shows that the original parity check matrix with L = 1944 may have a coding rate of R = 1 / 2. Figure 10 (B) shows the proposed solution where L = 2 Example of a lifting matrix with 1944 and R = 1 / 2.

[0050] Figure 11 An example design 1100 is shown under the proposed scheme according to this disclosure. Design 1100 may involve L = 2 Example of an LDPC matrix for a longer codeword, R = 1 / 2, in 1944. This matrix could be obtained by... Figure 10 The lifting matrix of (B) is applied to Figure 10 It is obtained from the original parity check matrix of (A).

[0051] Figure 12 An example design 1200 based on the proposed scheme of this disclosure is shown. Design 1200 may involve L = 2 Example of lifting matrix design in 1944 with R = 2 / 3. Figure 12 (A) shows that the original parity check matrix with L = 1944 may have a coding rate of R = 2 / 3. Figure 12 (B) shows L = 2 under the proposed scheme. Example of a lifting matrix with 1944 and R = 2 / 3.

[0052] Figure 13 An example design 1300 according to the proposed scheme of the present disclosure is shown. Design 1300 can involve L = 2 1944, R = 2 / 3 LDPC matrix example for a longer code word, which can be obtained by applying the lifting matrix of Figure 12 (B) to the original parity check matrix of Figure 12 (A).

[0053] Figure 14 An example design 1400 according to the proposed scheme of the present disclosure is shown. Design 1400 can involve L = 2 1944, R = 3 / 4 lifting matrix design example. Figure 14 (A) of shows that the original parity check matrix of L = 1944 can have a code rate of R = 3 / 4. Figure 14 (B) of shows that under the proposed scheme L = 2 1944 and R = 3 / 4 lifting matrix example.

[0054] Figure 15 An example design 1500 according to the proposed scheme of the present disclosure is shown. Design 1500 can involve L = 2 1944, R = 3 / 4 LDPC matrix example for a longer code word, which can be obtained by applying the lifting matrix of Figure 14 (B) to the original parity check matrix of Figure 14 (A).

[0055] Figure 16 An example design 1600 according to the proposed scheme of the present disclosure is shown. Design 1600 can involve L = 2 1944, R = 5 / 6 lifting matrix design example. Figure 16 (A) of shows that the original parity check matrix of L = 1944 can have a code rate of R = 3 / 4. Figure 16 (B) of shows that under the proposed scheme L = 2 1944 and R = 5 / 6 lifting matrix example.

[0056] Figure 17 An example design 1700 according to the proposed scheme of the present disclosure is shown. Design 1700 can involve L = 2 1944, R = 5 / 6 LDPC matrix example for a longer code word, which can be obtained by applying the lifting matrix of Figure 16 (B) to the original parity check matrix of Figure 16 (A).

[0057] Example Implementations

[0058] Figure 18 An example system 1800 is shown that includes at least one example apparatus 1810 and one example apparatus 1820 in accordance with embodiments of the present disclosure. Each of the apparatus 1810 and the apparatus 1820 can perform various functions to implement the schemes, techniques, processes, and methods described herein related to LDPC encoding with longer code word length for wireless communications in next generation WLAN systems and design of its lifting matrix, including the various suggested designs, concepts, schemes, systems, and methods described above and the processes described below. For example, the apparatus 1810 can be implemented in a STA 110 and the apparatus 1820 can be implemented in a STA 120, or vice versa.

[0059] Each of the apparatus 1810 and the apparatus 1820 can be part of an electronic device, which can be a non-AP STA or an AP STA, such as a portable or mobile device, a wearable device, a wireless communication device, or a computing device. When implemented in a STA, each of the apparatus 1810 and the apparatus 1820 can be implemented in a smartphone, a smartwatch, a personal digital assistant, a digital camera, or a computing device such as a tablet, a notebook, or a notebook computer. Each of the apparatus 1810 and the apparatus 1820 can also be part of a machine type device, which can be an IoT device, such as a fixed or stationary device, a home device, a wired communication device, or a computing device. For example, each of the apparatus 1810 and the apparatus 1820 can be implemented in a smart thermostat, a smart refrigerator, a smart door lock, a wireless speaker, or a home control center. When implemented in or as a network device, the apparatus 1810 and / or the apparatus 1820 can be implemented in a network node, such as an AP in a WLAN.

[0060] In some embodiments, each of the apparatus 1810 and the apparatus 1820 can be implemented in the form of one or more integrated circuit (IC) chips, such as but not limited to one or more single-core processors, one or more multi-core processors, one or more reduced instruction set computing (RISC) processors, or one or more complex instruction set computing (CISC) processors. In the various schemes described above, each of the apparatus 1810 and the apparatus 1820 can be implemented in or as a STA or an AP. Each of the apparatus 1810 and the apparatus 1820 can include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), or a combination thereof. Figure 18Some of the components shown, such as processor 1812 and processor 1822. Each of devices 1810 and 1820 may also include one or more other components (e.g., internal power supply, display device, and / or user interface device) unrelated to the proposed solutions disclosed herein; therefore, for simplicity and brevity, these components of devices 1810 and 1820 are not listed in the provided text. Figure 18 The text is not shown below.

[0061] In one aspect, processors 1812 and 1822 may be implemented as one or more single-core processors, one or more multi-core processors, one or more Reduced Instruction Set Computer (RISC) processors, or one or more Complex Instruction Set Computer (CISC) processors. That is, although the singular term "processor" is used herein to refer to processors 1812 and 1822, each of processors 1812 and 1822 may include multiple processors in some implementations of this disclosure, and may include a single processor in other implementations. In another aspect, each of processors 1812 and 1822 may be implemented in hardware (and optionally, firmware) comprising, for example, but not limited to, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors, and / or one or more transformers, these electronic components being configured and arranged to achieve a specific purpose according to this disclosure. In other words, in at least some implementations, each of processors 1812 and 1822 is a dedicated machine specifically designed, arranged, and configured to perform specific tasks, including those related to LDPC encoding of longer codeword lengths for use in next-generation wireless local area network (WLAN) systems in wireless communications and the design of their boosting matrices, according to various implementations disclosed herein.

[0062] In some implementations, device 1810 may further include a transceiver 1816 coupled to processor 1812. Transceiver 1816 may include a transmitter capable of wireless transmission and a receiver capable of wirelessly receiving data. In some implementations, device 1820 may further include a transceiver 1826 coupled to processor 1822. Transceiver 1826 may include a transmitter capable of wireless transmission and a receiver capable of wirelessly receiving data. It is noteworthy that although transceivers 1816 and 1826 are shown as external to and separate from processors 1812 and 1822, respectively, in some implementations, transceiver 1816 may be a component of processor 1812 as a system-on-a-chip (SoC), and transceiver 1826 may be a component of processor 1822 as a SoC.

[0063] In some implementations, device 1810 may further include a memory 1814 coupled to and accessible by processor 1812 for storing data. In some implementations, device 1820 may further include a memory 1824 coupled to and accessible by processor 1822 for storing data. Each of memory 1814 and memory 1824 may include a random access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and / or zero-capacitance RAM (Z-RAM). Alternatively, or additionally, each of memory 1814 and memory 1824 may include a read-only memory (ROM), such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and / or electrically erasable programmable ROM (EEPROM). Alternatively, each of the memories 1814 and 1824 may include a non-volatile random access memory (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), and / or phase-change memory.

[0064] Each of devices 1810 and 1820 can be a communication entity capable of communicating using various proposed schemes according to this disclosure. For illustrative purposes and without limitation, the capabilities of device 1810 as STA 110 and device 1820 as STA 120 are described below in the context of example procedure 1900. It is worth noting that although a detailed description of the capabilities, functions, and / or technical features of device 1820 is provided below, the same applies to device 1810, although its detailed description is not provided only for the sake of brevity. It is also worth noting that although the example implementation described below is provided in the context of WLAN, it can also be implemented in other types of networks.

[0065] Explanatory process

[0066] Figure 19 An example process 1900 implementing the present disclosure is illustrated. Process 1900 may represent one aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1900 may represent one aspect of proposed concepts and schemes related to LDPC coding with longer codeword lengths and its lifting matrix design in wireless communication for next-generation WLAN systems according to the present disclosure. Process 1900 may include one or more operations, actions, or functions, as shown by one or more blocks 1910 and 1920. Although shown as discrete blocks, the individual blocks of process 1900 may be divided into more blocks, merged into fewer blocks, or eliminated, depending on the desired implementation. Furthermore, the blocks / sub-blocks of process 1900 may be arranged in... Figure 19The execution may proceed in the order shown, or in a different order. Furthermore, one or more blocks / subblocks of process 1900 may be executed repeatedly or iteratively. Process 1900 may be implemented by or in devices 1810 and 1820, and any variations thereof. For illustrative purposes only and without limitation, process 1900 is described below in the context of device 1810 being implemented as or as STA 110 as a non-AP STA or AP STA function, and in the context of network environment 100 in a wireless network (e.g., WLAN) where device 1820 is implemented as or as STA 120 as an AP STA or non-AP STA function, according to one or more IEEE 802.11 standards. Process 1900 may begin at block 1910.

[0067] In 1910, process 1900 may involve the processor 1812 of device 1810 encoding multiple bits using an extended codeword length that may be longer than the existing LDPC parity check matrix. Process 1900 can proceed from 1910 to 1920.

[0068] In 1920, process 1900 may involve the processor 1812 of device 1810 communicating with a plurality of encoded bits in a wireless communication system via transceiver 1816 (e.g., by transmitting the encoded bits to device 1820).

[0069] In some implementations, during encoding, process 1900 may involve processor 1812 doubling the codeword length L (2x) such that: (a) for L = 1296, the extended codeword length = 2 1296 = 2592, and (b) for L = 1944, the extended codeword length = 2. 1944 = 3888.

[0070] In some implementations, for L = 1296 and submatrix size Z = 54, during the encoding process, process 1900 may further involve processor 1812 using the extended submatrix size 2. Encoding 54 = 108 corresponds to a codeword length of 2. A new LDPC parity check matrix of 1296. In some implementations, with an extended codeword length of 2... In the new LDPC parity check matrix of 1296, the permutation value at position (i,j) is 2. P ij +δ ij , where P ij Let represent the value at position (i,j) from the existing LDPC parity check matrix L = 1296, and δij The value is 0 or 1.

[0071] In some implementations, for L = 1944 and submatrix size Z = 81, during the encoding process, process 1900 may further involve processor 1812 using the extended submatrix size 2. Encoding 81 = 162 corresponds to a codeword length of 2. The new LDPC parity check matrix of 1944. In some implementations, with an extended codeword length of 2... In the new LDPC parity check matrix of 1944, the permutation value at position (i,j) is 2. P ij +δ ij , where P ij Let represent the value at position (i,j) from the existing LDPC parity check matrix L = 1944, and δ ij The value is 0 or 1.

[0072] In some implementations, in response to the extended codeword length = 2 1296. During the encoding process, process 1900 may involve processor 1812 using a coding rate R = 1 / 2 and a submatrix size Z = 2. 54 = 108 is used for encoding.

[0073] In some implementations, in response to the extended codeword length = 2 1296. During the encoding process, process 1900 may involve processor 1812 using a coding rate R = 2 / 3 and a submatrix size Z = 2. 54 = 108 is used for encoding.

[0074] In some implementations, in response to the extended codeword length = 2 1296. During the encoding process, process 1900 may involve processor 1812 using a coding rate R = 3 / 4 and a submatrix size Z = 2. 54 = 108 is used for encoding.

[0075] In some implementations, in response to the extended codeword length = 2 1296. During the encoding process, process 1900 may involve processor 1812 using a coding rate R = 5 / 6 and a submatrix size Z = 2. 54 = 108 is used for encoding.

[0076] In some implementations, in response to the extended codeword length = 2 In 1944, during the encoding process, procedure 1900 might involve processor 1812 using a coding rate R = 1 / 2 and a submatrix size Z = 2. 81 = 162 is used for encoding.

[0077] In some implementations, in response to the extended codeword length = 2 In 1944, during the encoding process, procedure 1900 might involve processor 1812 using a coding rate R = 2 / 3 and a submatrix size Z = 2. 81 = 162 is used for encoding.

[0078] In some implementations, in response to the extended codeword length = 2 In 1944, during the encoding process, procedure 1900 might involve processor 1812 using a coding rate R = 3 / 4 and a submatrix size Z = 2. 81 = 162 is used for encoding.

[0079] In some implementations, in response to the extended codeword length = 2 In 1944, during the encoding process, procedure 1900 may involve processor 1812 using a coding rate R = 5 / 6 and a submatrix size Z = 2. 81 = 162 is used for encoding.

[0080] In some implementations, in response to the extended codeword length = 2 In 1944, during the encoding process, procedure 1900 may involve processor 1812 using a coding rate R = 1 / 2, 2 / 3, 3 / 4, or 5 / 6 and applying a lifting matrix to an existing LDPC parity matrix, wherein each element in the lifting matrix, when applied to the Z x Z cyclic permutation matrix Pi at the same position in the LDPC parity matrix, creates a submatrix of size 2Z x 2Z such that: (a) when a non-empty element "0" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi at that position, the 2Z x 2Z submatrix is ​​created with values ​​that are the original elements of the Z x Z cyclic permutation matrix arranged along the diagonal from the top left corner to the bottom right corner of the 2Z x 2Z submatrix, while the value "-1" is copied and arranged along the opposite diagonal from the top right corner to the bottom left corner of the 2Z x 2Z submatrix; (b) when a non-empty element "1" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi at that position, the 2Z x 2Z submatrix is ​​created with values ​​that are the original elements of the Z x Z cyclic permutation matrix arranged along the diagonal from the top right corner to the bottom left corner of the 2Z x 2Z submatrix; (c) A 2Z submatrix, whose values ​​are the original elements of the Z x Z cyclic permutation matrix, is arranged along another diagonal from the upper right corner to the lower left corner of the 2Z x 2Z submatrix, while the value "-1" is copied and arranged along the opposite diagonal from the upper left corner to the lower right corner of the 2Z x 2Z submatrix; and (d) when the non-empty element "-1" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi at the same position, the 2Z x 2Z submatrix is ​​created, where the value "-1" is copied and arranged at the four corners of the 2Z x 2Z submatrix.

[0081] Additional notes

[0082] The topics described herein sometimes demonstrate different components contained within or connected to different other components. It should be understood that the architectures depicted are merely examples, and many other architectures can actually be implemented to achieve the same functionality. Conceptually, any arrangement of components to achieve the same functionality is effectively “associated” to achieve the desired function. Therefore, any two components combined in this document to achieve a particular function can be considered “associated” together to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” together to achieve the desired function, and any two components that can be suchly associated can also be considered “operably coupled” together to achieve the desired function. Specific examples of operational coupling include, but are not limited to, physically connectable and / or physically interactive components and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0083] Furthermore, regarding the use of virtually any plural and / or singular terms in this document, a person with technical skills may appropriately translate from plural to singular and / or from singular to plural depending on the context and / or application. For clarity, various singular / plural permutations may be explicitly listed in this document.

[0084] Furthermore, those skilled in the art will understand that terms generally used herein, particularly in appended claims, such as the body of an appended claim, are generally intended as “open” terms. For example, the term “comprising” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “at least having,” and the term “including” should be interpreted as “including but not limited to,” etc. Those skilled in the art will also further understand that if a particular quantity introduced in a claim is intentional, such intention will be explicitly stated in the claim, and where there is no such statement, such intention does not exist. For example, to aid understanding, the following appended claims may contain the use of introductory phrases “at least one” and “one or more” to introduce the claim statement. However, the use of these phrases should not be construed as implying that introducing the claim statement with the indefinite article “a” or “an” would limit any particular claim containing such an introductory claim statement to containing only one such statement, even if the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an,” for example, “a” and / or “an” should be interpreted as “at least one” or “one or more”; the same applies to definite articles used to introduce the claim statement. Furthermore, even when a specific number of claims is explicitly stated, those skilled in the art will recognize that such a statement should be interpreted as at least the stated number; for example, the simple statement "two statements" without any other modifiers means at least two statements, or two or more statements. Additionally, when using conventions such as "at least one A, B, and C, etc.", this structure is generally intended to be interpreted in a manner understood by those skilled in the art. For example, "a system having at least one A, B, and C" will include, but is not limited to, a system having only A, a system having only B, a system having only C, a system with A and B together, a system with A and C together, a system with B and C together, and / or a system with A, B, and C together, etc. Similarly, when using conventions such as "at least one A, B, or C, etc.", this structure is generally intended to be interpreted in a manner understood by those skilled in the art. For example, "a system having at least one A, B, or C" will include, but is not limited to, a system having only A, a system having only B, a system having only C, a system with A and B together, a system with A and C together, a system with B and C together, and / or a system with A, B, and C together, etc. Those skilled in the art will further understand that virtually any extractive word and / or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to include the possibility of containing one, any, or both terms. For example, the phrase “A or B” will be understood to include the possibility of “A” or “B” or “A and B”.

[0085] As can be understood from the foregoing, various embodiments of the present disclosure have been described herein for illustrative purposes, and various modifications may be made without departing from the scope and spirit of the disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the following claims.

Claims

1. A method comprising: The device's processor encodes multiple bits, and the length of the encoded codeword is greater than the length of the codeword corresponding to the existing low-density parity check (LDPC) parity check matrix. as well as The processor uses these encoded bits to communicate in the wireless communication system.

2. The method of claim 1, wherein the encoding includes doubling the codeword length L, such that: For L = 1296, the extended codeword length = 2. 1296 = 2592, and For L = 1944, the extended codeword length is 2. 1944 = 3888.

3. The method as described in claim 2, wherein, For L = 1296 and submatrix size Z = 54, the encoding further includes using the expanded submatrix size 2. Encoding 54 = 108 corresponds to a codeword length of 2 after this extension. A new LDPC parity check matrix of 1296.

4. The method of claim 3, wherein the permutation value at position (i,j) in the new LDPC parity check matrix having the extended codeword length is 2. P ij +δ ij , where P ij Let δ represent the value at position (i,j) from the existing LDPC parity check matrix L=1296, and let δ ij The value is 0 or 1.

5. The method of claim 2, wherein, For L = 1944 and submatrix size Z = 81, the encoding further includes using the expanded submatrix size 2. Encoding 81 = 162 corresponds to a codeword length of 2 after the extension. The new LDPC parity check matrix of 1944.

6. The method of claim 5, wherein the permutation value at position (i,j) in the new LDPC parity check matrix having the extended codeword length is 2. P ij +δ ij , where P ij Let δ represent the value at position (i,j) from the existing LDPC parity check matrix L=1944, and let δ ij The value is 0 or 1.

7. The method of claim 2, wherein, In response to this extended codeword length = 2 1296, this encoding involves using a coding rate R = 1 / 2 and a submatrix size Z = 2. 54 = 108 is used for encoding.

8. The method of claim 2, wherein, In response to this extended codeword length = 2 1296, this encoding involves using a coding rate R = 2 / 3 and a submatrix size Z = 2. 54 = 108 is used for encoding.

9. The method of claim 2, wherein, In response to this extended codeword length = 2 1296, this encoding involves using a coding rate R = 3 / 4 and a submatrix size Z = 2. 54 = 108 is used for encoding.

10. The method of claim 2, wherein, In response to this extended codeword length = 2 1296, this encoding involves using a coding rate R = 5 / 6 and a submatrix size Z = 2. 54 = 108 is used for encoding.

11. The method of claim 2, wherein, In response to this extended codeword length = 2 In 1944, this encoding involved using a coding rate R = 1 / 2 and a submatrix size Z = 2. 81 = 162 is used for encoding.

12. The method of claim 2, wherein, In response to this extended codeword length = 2 In 1944, this encoding involved using a coding rate R = 2 / 3 and a submatrix size Z = 2. 81 = 162 is used for encoding.

13. The method of claim 2, wherein, In response to this extended codeword length = 2 In 1944, this encoding involved using a coding rate R = 3 / 4 and a submatrix size Z = 2. 81 = 162 is used for encoding.

14. The method of claim 2, wherein, In response to this extended codeword length = 2 In 1944, this encoding involved using a coding rate R = 5 / 6 and a submatrix size Z = 2. 81 = 162 is used for encoding.

15. The method of claim 2, wherein, In response to the extended codeword length = 2 In 1944, the encoding involved encoding with a coding rate R = 1 / 2 and applying a lifting matrix to the existing LDPC parity-check matrix, wherein each element of the lifting matrix, when acting on a Z x Z cyclic permutation matrix Pi at the same position in the LDPC parity-check matrix, creates a submatrix of size 2Z x 2Z such that: The non-empty element "0" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi. At the same position, a 2Z x 2Z submatrix is ​​created, whose values ​​are the original elements of the Z x Z cyclic permutation matrix, arranged along the diagonal from the top left to the bottom right corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top right to the bottom left corner of the 2Z x 2Z submatrix. The non-empty element "1" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi at the same position. A 2Z x 2Z submatrix is ​​created with the original elements of the Z x Z cyclic permutation matrix, arranged along the opposite diagonal from the top right to the bottom left corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top left to the bottom right corner of the 2Z x 2Z submatrix. The non-empty element "-1" in the lifting matrix acts on the Z x Z cyclic permutation matrix Pi at the same position, creating the 2Z x 2Z submatrix, whose value "-1" is copied and arranged at the four corners of the 2Z x 2Z submatrix.

16. The method of claim 2, wherein, In response to the extended codeword length = 2 In 1944, the encoding involved encoding with a coding rate R = 2 / 3 and applying a lifting matrix to the existing LDPC parity-check matrix, wherein each element of the lifting matrix, when acting on a Z x Z cyclic permutation matrix Pi at the same position in the LDPC parity-check matrix, creates a submatrix of size 2Z x 2Z such that: The non-empty element "0" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi. At the same position, a 2Z x 2Z submatrix is ​​created, whose values ​​are the original elements of the Z x Z cyclic permutation matrix, arranged along the diagonal from the top left to the bottom right corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top right to the bottom left corner of the 2Z x 2Z submatrix. The non-empty element "1" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi at the same position. A 2Z x 2Z submatrix is ​​created with the original elements of the Z x Z cyclic permutation matrix, arranged along the opposite diagonal from the top right to the bottom left corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top left to the bottom right corner of the 2Z x 2Z submatrix. The non-empty element "-1" in the lifting matrix acts on the Z x Z cyclic permutation matrix Pi at the same position, creating the 2Z x 2Z submatrix, whose value "-1" is copied and arranged at the four corners of the 2Z x 2Z submatrix.

17. The method of claim 2, wherein, In response to the extended codeword length = 2 In 1944, the encoding involved encoding with a coding rate R = 3 / 4 and applying a lifting matrix to the existing LDPC parity-check matrix, wherein each element of the lifting matrix, when acting on a Z x Z cyclic permutation matrix Pi at the same position in the LDPC parity-check matrix, creates a submatrix of size 2Z x 2Z such that: The non-empty element "0" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi. At the same position, a 2Z x 2Z submatrix is ​​created, whose values ​​are the original elements of the Z x Z cyclic permutation matrix, arranged along the diagonal from the top left to the bottom right corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top right to the bottom left corner of the 2Z x 2Z submatrix. The non-empty element "1" in the lifting matrix is ​​applied to the Z x Z cyclic permutation matrix Pi at the same position. A 2Z x 2Z submatrix is ​​created with the original elements of the Z x Z cyclic permutation matrix, arranged along the opposite diagonal from the top right to the bottom left corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top left to the bottom right corner of the 2Z x 2Z submatrix. The non-empty element "-1" in the lifting matrix acts on the Z x Z cyclic permutation matrix Pi at the same position, creating the 2Z x 2Z submatrix, whose value "-1" is copied and arranged at the four corners of the 2Z x 2Z submatrix.

18. The method of claim 2, wherein, In response to the extended codeword length = 2 In 1944, the encoding involved encoding with a coding rate R = 5 / 6 and applying a lifting matrix to the existing LDPC parity matrix, wherein each element of the lifting matrix, when acting on a Z x Z cyclic permutation matrix Pi at the same position in the LDPC parity matrix, creates a submatrix of size 2Z x 2Z such that: The non-empty element "0" is applied in the promotion matrix. When the Z x Z cyclic permutation matrix Pi is in the same position, a 2Z x 2Z submatrix is ​​created, whose values ​​are the original elements of the Z x Z cyclic permutation matrix, arranged along the diagonal from the top left corner to the bottom right corner of the 2Z x 2Z submatrix. The value "-1" is copied and arranged along the opposite diagonal from the top right corner to the bottom left corner. The non-empty element "1" in the promotion matrix acts on the Z x Z cyclic permutation matrix Pi at the same position, creating a 2Z x 2Z submatrix whose values ​​are the original elements of the Z x Z cyclic permutation matrix, arranged along another diagonal from the upper right corner to the lower left corner of the 2Z x 2Z submatrix, while the value "-1" is copied and arranged along the opposite diagonal from the upper left corner to the lower right corner. The non-empty element "-1" is applied in the lifting matrix. When the Z x Z cyclic permutation matrix Pi is in the same position, the 2Z x 2Z submatrix is ​​created, where the value "-1" is copied and arranged at the four corners of the 2Z x 2Z submatrix.

19. An apparatus comprising: A transceiver configured for wireless communication; as well as A processor, coupled to the transceiver and configured to perform operations including: Encoding multiple bits uses an extended codeword length that is longer than the codeword length corresponding to the existing low-density parity-check (LDPC) matrix; and This transceiver enables communication in a wireless communication system using these encoded bits.

20. The apparatus of claim 19, wherein the encoding includes doubling the codeword length L, such that: For L = 1296, the extended codeword length is 2. 1296 = 2592 For L = 1944, the extended codeword length is 2. 1944 = 3888.

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