Display device

Abstract

One embodiment of the present invention provides a display device including: a substrate including a display area and a non-display area outside the display area; and a plurality of light emitting diodes disposed in the display area, in which each of the plurality of light emitting diodes has a dual porous layer structure including a first porous layer defining therein a first hole extending in a direction perpendicular to the substrate and a second porous layer disposed below the first porous layer, the second porous layer defining therein a second hole extending in a direction perpendicular to the substrate, and the second porous layer defines therein second pores extending in a randomly variable direction.

Description

TECHNICAL FIELD

[0001] One or more embodiments relate to a structure of a display apparatus. BACKGROUND

[0002] With the development of display apparatuses that visually display an electrical signal, various display apparatuses having excellent characteristics such as thinness, weight reduction, and low power consumption have been introduced. For example, a flexible display apparatus that can be folded or rolled into a roll shape has been introduced. Recently, research and development of a stretchable display apparatus that can change into various forms are actively in progress. SUMMARY TECHNICAL PROBLEM

[0003] One or more embodiments include a display apparatus having improved light conversion efficiency and light extraction efficiency. Embodiments set forth herein are examples, and the scope of the disclosure is not limited thereto. TECHNICAL SOLUTION

[0004] According to one or more embodiments, a display apparatus includes a substrate including a display area and a non-display area outside the display area, and a plurality of light emitting diodes arranged in the display area, wherein each of the plurality of light emitting diodes has a double porous layer structure including a first porous layer and a second porous layer disposed below the first porous layer, the first porous layer defining first pores extending in a direction perpendicular to a main surface of the substrate therein, and the second porous layer defining second pores extending in a randomly variable direction therein. ADVANTAGEOUS EFFECT OF THE INVENTION

[0005] According to embodiments of the disclosure, a display apparatus that can implement an image having excellent quality by improving light conversion efficiency and light extraction efficiency can be provided. The foregoing effects are exemplary, and the scope of the disclosure is not limited to these effects. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 FIG. 1 is a perspective view schematically illustrating a display apparatus according to an embodiment.

[0007] Figure 2a FIG. 2 is a perspective view schematically illustrating a display apparatus according to an embodiment. Figure 2b FIG. 3 is a perspective view schematically illustrating a display apparatus according to an embodiment. Figure 1 FIG. 4 is a perspective view schematically illustrating a display apparatus according to an embodiment.

[0008] Figure 2c FIG. 5 is a perspective view schematically illustrating a display apparatus according to an embodiment. Figure 1 FIG. 6 is a perspective view schematically illustrating a display apparatus according to an embodiment.

[0009] Figure 2d FIG. 7 is a perspective view schematically illustrating a display apparatus according to an embodiment. Figure 1 FIG. 8 is a perspective view schematically illustrating a display apparatus according to an embodiment. FIG. 9 is a perspective view schematically illustrating a display apparatus according to an embodiment.

[0010] Figure 2e is a perspective view showing Figure 1 the display device being stretched in the third direction.

[0011] Figure 3 is a plan view schematically showing a display device according to an embodiment.

[0012] Figure 4a is a plan view showing a region IV of Figure 3 as part of a display device according to an embodiment.

[0013] Figure 4b is a plan view showing a region IV of Figure 3 as part of a display device according to an embodiment.

[0014] Figure 4c is a plan view showing a region IV of Figure 3 as part of a display device according to an embodiment.

[0015] Figure 5 is a cross-sectional view schematically showing a first island portion and a first bridge portion disposed in a display area of a stretchable display device according to an embodiment.

[0016] Figures 6a to 6c is an equivalent circuit diagram of a sub-pixel of a stretchable display device according to an embodiment.

[0017] Figure 7 is a plan view schematically showing a portion of a display device according to an embodiment.

[0018] Figure 8 is a cross-sectional view schematically showing a portion of a display device according to an embodiment.

[0019] Figures 9a to 9c is a cross-sectional view schematically showing a light emitting diode of a display device according to an embodiment.

[0020] Figure 10a is a plan view schematically showing a hole structure of a display device according to an embodiment.

[0021] Figure 10b is a perspective view schematically showing a hole structure of a display device according to an embodiment.

[0022] Figure 11a is a cross-sectional view schematically showing a light emitting diode of a display device according to another embodiment.

[0023] Figure 11b is a cross-sectional view schematically showing a light emitting diode of a display device according to another embodiment.

[0024] Figure 12 FIG. 1 is a cross-sectional view schematically illustrating a portion of a display device according to an embodiment. DETAILED DESCRIPTION

[0025] The quantum dots can be disposed within the first holes and the second holes.

[0026] The display device can further include a base resin disposed in the first holes and the second holes, wherein the quantum dots are dispersedly disposed in the base resin.

[0027] The display area can include a first sub-pixel for emitting red light, a second sub-pixel for emitting green light, and a third sub-pixel for emitting blue light, the quantum dots can be disposed in light emitting diodes of the first sub-pixel and the second sub-pixel, and the plurality of light emitting diodes can include the light emitting diodes of the first sub-pixel and the second sub-pixel.

[0028] The first holes and the second holes disposed in the third sub-pixel can be filled with the base resin without the quantum dots.

[0029] The first holes and the second holes can extend and connect to each other.

[0030] The first holes can have a cylindrical shape.

[0031] The second holes can have a spiral cylindrical shape.

[0032] A planar diameter of each of the first holes and the second holes can be about 100 nanometers (nm) to about 200 nm.

[0033] In a direction perpendicular to a major surface of the substrate, a thickness of the first porous layer and a thickness of the second porous layer can be equal to each other.

[0034] In a direction perpendicular to a major surface of the substrate, a thickness of the first porous layer can be greater than a thickness of the second porous layer.

[0035] In a direction perpendicular to a major surface of the substrate, a thickness of the second porous layer can be greater than a thickness of the first porous layer.

[0036] Each of the plurality of light emitting diodes can further include a first semiconductor layer doped with a p-type dopant, a second semiconductor layer doped with an n-type dopant, and an intermediate layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the first porous layer and the second porous layer can be included in the second semiconductor layer.

[0037] The first porous layer can have a structure in which the first holes are defined in a material constituting the second semiconductor layer, and the second porous layer can have a structure in which the second holes are defined in the material constituting the second semiconductor layer.

[0038] The material constituting the second semiconductor layer can include a semiconductor material having a composition formula In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, and 0≤x+y≤1).

[0039] The second semiconductor layer can further include a base layer disposed between the intermediate layer and the second porous layer, wherein the base layer can have a non-porous structure.

[0040] Each of the first porous layer and the second porous layer can have a thickness of about 2 micrometers (μm) to about 7 μm.

[0041] The base layer can have a thickness of about 0.3 μm to about 0.5 μm.

[0042] Each of the plurality of light emitting diodes can further include a sub-pixel electrode electrically connected to the first semiconductor layer, and a counter electrode electrically connected to the second semiconductor layer, wherein the sub-pixel electrode can be connected to a pixel circuit arranged in the display area, and the counter electrode can be electrically connected to a voltage line for receiving a low potential voltage.

[0043] The display device can further include a light shielding layer disposed above each of the plurality of light emitting diodes and having a light shielding layer opening defined therein overlapping the light emitting diode, and an overcoat layer disposed on the light shielding layer.

[0044] The overcoat layer can fill the light shielding layer opening.

[0045] The display device can further include a color filter layer filling the light shielding layer opening, wherein the overcoat layer can cover the light shielding layer and the color filter layer.

[0046] The display device can further include an encapsulation layer disposed between the light shielding layer and each of the plurality of light emitting diodes.

[0047] The display device can further include island portions arranged in the display area and spaced apart from each other along rows and columns, and a bridge portion connecting adjacent ones of the island portions to each other, wherein each of the island portions can include at least one light emitting diode of the plurality of light emitting diodes.

[0048] The bridge portions can each have a serpentine shape. Embodiments of the present invention

[0049] The present disclosure is subject to various modifications and can have many embodiments, some of which are exemplified in the accompanying drawings and are further described in the detailed description. The effects and features of the present disclosure will become apparent from the embodiments described below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments described herein and can be implemented in various forms.

[0050] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals and a repeated description thereof will be omitted.

[0051] In the following embodiments, the terms "first", "second", and the like are not intended to be limiting, but are used to distinguish one component from another.

[0052] In the following embodiments, the singular expression includes the plural unless the context clearly indicates otherwise.

[0053] In the following embodiments, the term "include" or "have" and the like is intended to imply the existence of the stated features or components, and does not exclude the possibility of adding one or more other features or components.

[0054] In the following embodiments, when a part of a film, a region, a component, and the like is referred to as being above or over another part, this includes not only the case where it is directly above the other part, but also the case where other films, regions, components, and the like are disposed therebetween.

[0055] In the drawings, components can be exaggerated or reduced in size for ease of illustration. For example, the size and thickness of each configuration shown in the drawings are arbitrary for the purpose of illustration, and the present disclosure is not necessarily limited to those shown.

[0056] In some embodiments, a specific order of processes can be performed in a different order from the described order. For example, two processes described sequentially can be performed substantially simultaneously, or can be performed in an order opposite to the described order.

[0057] In this specification, expressions such as "A and / or B" can include A, B, or A and B. In addition, expressions such as "at least one of A and B" can include A, B, or A and B.

[0058] In the following embodiments, when layers, regions, or components are connected to each other, the layers, regions, or components can be directly connected to each other, or another layer, another region, or another component can be interposed between the layers, regions, or components, and thus the layers, regions, or components can be indirectly connected to each other. For example, in the following embodiments, when layers, regions, or components are electrically connected to each other, the layers, regions, or components can be directly electrically connected to each other, or another layer, another region, or another component can be interposed between the layers, regions, or components, and thus the layers, regions, or components can be indirectly electrically connected to each other.

[0059] In the following embodiments, the terms "x-axis", "y-axis", and "z-axis" are not limited to include three axes in a Cartesian coordinate system, but can be interpreted in a broad sense. For example, the x-axis, the y-axis, and the z-axis can be orthogonal to each other, however, the x-axis, the y-axis, and the z-axis can also refer to different directions that are not orthogonal to each other.

[0060] "About" or "approximately", as used herein, includes the recited value and means within an acceptable range of deviation of a certain value as determined by one of ordinary skill in the art considering the measurement in question and the error associated with the measurement of the particular quantity, i.e., limitations of the measurement system. For example, "about" can mean within one or more standard deviations, or within ± 10%, 5%, or 3% of the recited value.

[0061] Figure 1 is a perspective view schematically showing a display device 1 according to an embodiment. Figure 2a and Figure 2b is a perspective view showing Figure 1 the display device 1 of Figure 2c is a perspective view showing Figure 1 the display device 1 of Figure 2d is a perspective view showing Figure 1 the display device of Figure 2e is a perspective view showing Figure 1 the display device 1 of

[0062] Referring to Figure 1 , the display device 1 can include a display area DA and a non-display area NDA. The display area DA can include a plurality of pixels. The display device 1 can provide a certain image by using light emitted from the plurality of pixels. The non-display area NDA can be placed outside the display area DA. The non-display area NDA can surround the entire display area DA.

[0063] The display device 1 can be a stretchable display device, and can be stretched or contracted in various directions. The display device 1 can be stretched in a first direction (e.g., an x direction and / or an -x direction) by an external force applied by an external object or a user. In an embodiment, as shown in Figure 2a and Figure 2b the display area DA and / or the non-display area NDA of the display device 1 can be stretched in a first direction (e.g., an x direction and / or an -x direction). For example, as shown in Figure 2a the display area DA and / or the non-display area NDA of the display device 1 can be stretched in the x direction and the -x direction. Alternatively, as shown in Figure 2b the display area DA and / or the non-display area NDA of the display device 1 can be stretched in the x direction while one side of the display device 1 is fixed.

[0064] The display device 1 can be stretched in a second direction (e.g., a y direction and / or a -y direction) by an external force applied by an external object or a user. In an embodiment, as shown in Figure 2c the display area DA and / or the non-display area NDA of the display device 1 can be stretched in the y direction and the -y direction. In another embodiment, the display area DA and / or the non-display area NDA of the display device 1 can be stretched in the y direction or the -y direction while one side of the display device 1 is fixed.

[0065] The display device 1 can be stretched in multiple directions (e.g., in a first direction (e.g., an x direction and / or an -x direction) and a second direction (e.g., a y direction and / or a -y direction)) by an external force applied by an external object or a part of a human body. As shown in Figure 2d the display area DA and / or the non-display area NDA of the display device 1 can be stretched in ±x direction and ±y direction.

[0066] The display device 1 can be stretched in a third direction (e.g., a z direction or a -z direction) by an external force applied by an external object or a part of a human body. In an embodiment, Figure 2e a portion of the display device 1 (e.g., a portion of the display area DA) is shown to protrude in the z direction. In another embodiment, a portion of the display device 1 (e.g., a portion of the display area DA) can protrude in the z direction (or be recessed in the -z direction).

[0067] Although Figures 2a to 2e the display device 1 is shown to be stretched in a first direction, a second direction, and / or a third direction, the present disclosure is not limited thereto. In another embodiment, the display device 1 can be deformed into various irregular shapes, such as being bent or twisted along two or more axes.

[0068] Figure 3 is a plan view schematically showing a display device 1 according to an embodiment. As used herein, a "plan view" is a view in the third direction (z direction).

[0069] A plurality of pixels can be arranged in a display region DA of the display device 1. Each pixel can include sub-pixels that emit light of different colors. Light emitting elements corresponding to each sub-pixel can be arranged in the display region DA. Circuits for providing electrical signals to the light emitting elements arranged in the display region DA and transistors electrically connected to the light emitting elements can be located in a non-display region NDA surrounding the display region DA. A gate driver circuit GDC can be arranged in each of a first non-display region NDA1 and a second non-display region NDA2 on opposite sides of the display region DA. The gate driver circuit GDC can include drivers for providing electrical signals to gate electrodes of the transistors electrically connected to the light emitting elements. Although Figure 3 The gate driver circuit GDC is shown as being arranged in each of the first non-display region NDA1 and the second non-display region NDA2, but the present disclosure is not limited thereto. In another embodiment, the gate driver circuit GDC can be arranged in the first non-display region NDA1 or the second non-display region NDA2.

[0070] A data driver circuit DDC can be arranged in a third non-display region NDA3 and / or a fourth non-display region NDA4 connecting the first non-display region NDA1 and the second non-display region NDA2 to each other. In an embodiment, Figure 3 The data driver circuit DDC is shown as being arranged in the fourth non-display region NDA4. In another embodiment, the data driver circuit DDC can be arranged in each of the third non-display region NDA3 and the fourth non-display region NDA4.

[0071] Although Figure 3 The data driver circuit DDC is shown as being arranged in the fourth non-display region NDA4 of the display device 1, but the present disclosure is not limited thereto. In another embodiment, the display device 1 can further include a flexible circuit board (not shown) electrically connected by a terminal portion (not shown) arranged in the fourth non-display region NDA4, and the data driver circuit DDC can be provided on the flexible circuit board.

[0072] In some embodiments, the elongation of the non-display area NDA can be equal to or less than the elongation of the display area DA. In an embodiment, the elongation of the non-display area NDA can be different for each area. For example, the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3 can have substantially the same elongation, but the elongation of the fourth non-display area NDA4 can be less than the elongation of each of the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3.

[0073] Figure 4a is a plan view of the area IV of the display device 1 according to an embodiment. Figure 3

[0074] Referring to Figure 4a The display device 1 is a stretchable display device, and can include first island portions 11 spaced apart from each other in a first direction (e.g., an x direction or an -x direction) and a second direction (e.g., a y direction or a -y direction) in a display area DA, and first bridge portions 12 connecting adjacent first island portions 11 to each other.

[0075] Each of the first island portions 11 can be connected to a plurality of the first bridge portions 12. For example, each of the first island portions 11 can be connected to four first bridge portions 12. Two of the first bridge portions 12 can be disposed on opposite sides of the first island portion 11 in the first direction (e.g., the x direction or the -x direction), and the remaining two of the first bridge portions 12 can be disposed on opposite sides of the first island portion 11 in the second direction (e.g., the y direction or the -y direction). In an embodiment, the four first bridge portions 12 can be connected to four sides of the first island portion 11, respectively. Each of the four first bridge portions 12 can be adjacent to each corner of the first island portion 11.

[0076] The first bridge portions 12 can be spaced apart from each other by first openings CS1 located between the first bridge portions 12. In an embodiment, first openings CS1 having a substantially H shape and first openings CS1 having a substantially I shape obtained by rotating the H shape by 90 degrees can be alternately and repeatedly arranged in the first direction (e.g., the x direction or the -x direction) and the second direction (e.g., the y direction or the -y direction). Both ends of each of the first bridge portions 12 can be connected to each of the adjacent first island portions 11, and one side of each of the first bridge portions 12 can be spaced apart from one side of the adjacent first island portion 11 and / or one side of another first bridge portion 12 by the first opening CS1.

[0077] The display device 1 can include a first non-display area (e.g., a first island portion 11) in which a first bridge portion 12 is not disposed, a second non-display area (e.g., a second island portion 12) in which a first bridge portion 12 is not disposed, and a third non-display area (e.g., a third island portion 13) in which a first bridge portion 12 is not disposed. Figure 4a ​The second island portions 21 and the second bridge portions 22 are arranged in the first non-display area NDA1.

[0078] Each of the second island portions 21 can extend in a first direction (e.g., an x direction or an -x direction). The second island portions 21 can be spaced apart from each other in a second direction (e.g., a y direction or a -y direction) intersecting the first direction (e.g., the x direction or the -x direction). Each of the second island portions 21 can include a reference Figure 3 The driver of the described gate driving circuit GDC (see FIG. 2).

[0079] The second bridge portions 22 can have a serpentine shape. The length of the second bridge portions 22 can be greater than the shortest distance between the adjacent second island portions 21 in the second direction (e.g., the y direction or the -y direction). In an embodiment, the second bridge portions 22 can have a substantially omega (Ω) shape convex toward the first direction (e.g., the x direction or the -x direction). The second bridge portions 22 can be arranged between the adjacent second island portions 21 and can be spaced apart from each other.

[0080] The second bridge portions 22 between the adjacent second island portions 21 can be spaced apart from each other by the second openings CS2. The second openings CS2 and the second bridge portions 22 can be alternately arranged in the first direction (e.g., the x direction or the -x direction) between the adjacent second island portions 21. The second openings CS2 can have the same shape. Both ends of each of the second bridge portions 22 can be connected to each of the adjacent second island portions 21, and one side of each of the second bridge portions 22 can be spaced apart from one side of the adjacent second island portion 21 and / or one side of another second bridge portion 22 by the second opening CS2.

[0081] One of the second island portions 21 arranged in the first non-display area NDA1 can correspond to the plurality of rows of the first island portions 11 arranged in the display area DA1. For example, one of the second island portions 21 arranged in the first non-display area NDA1 can correspond to the first island portions 11 arranged in the i-th row and the first island portions 11 arranged in the (i+1)-th row in the display area DA1 (where i is a positive number greater than 0). Although Figure 4a One second island portion 21 is shown to correspond to two rows of the first island portions 11, but the disclosure is not limited thereto. In another embodiment, one second island portion 21 arranged in the first non-display area NDA1 can correspond to n rows of the first island portions 11 arranged in the display area DA1 (where n is a positive number equal to or greater than 3).

[0082] The non-display area (e.g., the first non-display area NDA1) can include a first sub-non-display area SNDA1 in which the second island portion 21 and the second bridge portion 22 described above are disposed, and a second sub-non-display area SNDA2 between the first sub-non-display area SNDA1 and the display area DA. The third bridge portion 23 can be disposed in the second sub-non-display area SNDA2 to connect the display area DA and the first sub-non-display area SNDA1. One end of the third bridge portion 23 can be connected to the second island portion 21 and / or the second bridge portion 22, and the other end of the third bridge portion 23 can be connected to the first island portion 11 and / or the first bridge portion 12.

[0083] The third bridge portion 23 can have a serpentine shape. In an embodiment, the shape of the third bridge portion 23 can be different from the shape of each of the first bridge portion 12 and the second bridge portion 22. In an embodiment, as shown in FIG. 1B, the third bridge portion 23 can have a substantially Ω shape that is convex toward the second direction (e.g., the y direction or the -y direction). The third bridge portion 23 can have a symmetrical structure in which one of adjacent third bridge portions 23 disposed in the second direction (e.g., the y direction or the -y direction) can be convex in the y direction, and the other can be convex in the -y direction. Between the third bridge portions 23, there can be a structure in which a third opening CS3 and a fourth opening CS4 having different shapes are repeated. The width of the third bridge portion 23 can be different from the width of the first bridge portion 12 and the width of the second bridge portion 22. In an embodiment, the width of the third bridge portion 23 can be greater than the width of the first bridge portion 12 and can be less than the width of the second bridge portion 22. Figure 4a

[0084] Figure 4a It is shown that the second island portion 21 and the second bridge portion 22 in the non-display area (e.g., the first non-display area NDA1) have shapes different from the shape of the first island portion 11 and the shape of the first bridge portion 12 in the display area DA, respectively. In another embodiment of the disclosure, the second island portion 21 and the second bridge portion 22 in the non-display area can have shapes identical to the shape of the first island portion 11 and the shape of the first bridge portion 12 in the display area DA, respectively.

[0085] Figure 4b is a plan view of the area IV of FIG. 1A as a part of the display device 1 according to an embodiment. Figure 3 is a plan view of the area IV of FIG. 1A as a part of the display device 1 according to an embodiment.

[0086] Referring to FIG. 1A, Figure 4b ​The display device 1 is a stretchable display device, and can include first island portions 11 spaced apart from each other in the display area DA and first bridge portions 12 spaced apart from each other by first openings CS1 and connecting adjacent first island portions 11 to each other. Figure 4b The structure of the display area DA in the display device 1 can be the same as the structure of the display area DA previously described with reference to FIG. 1. Figure 4a The structure of the display area DA in the display device 1 can be the same as the structure of the display area DA previously described with reference to FIG. 1.

[0087] The display device 1 can include second island portions 21 and second bridge portions 22 arranged in a non-display area (e.g., the first non-display area NDA1). In an embodiment, the second island portions 21 and the second bridge portions 22 can have substantially the same shapes as the shapes of the first island portions 11 and the shapes of the first bridge portions 12, respectively.

[0088] The second island portions 21 can be spaced apart from each other in a first direction (e.g., an x direction or an -x direction) and a second direction (e.g., a y direction or a -y direction) in a non-display area (e.g., the first non-display area NDA1). Each of the second bridge portions 22 can connect adjacent second island portions 21 to each other. The second bridge portions 22 can be spaced apart from each other by second openings CS2 located between the second bridge portions 22.

[0089] The second openings CS2 can have substantially the same shapes as the shapes of the first openings CS1. For example, second openings CS2 having a substantially H shape and second openings CS2 having a substantially I shape can be alternately and repeatedly arranged in a non-display area (e.g., the first non-display area NDA1). Both ends of each of the second bridge portions 22 can be connected to each of adjacent second island portions 21, and one side of each of the second bridge portions 22 can be spaced apart from one side of an adjacent second island portion 21 and / or one side of another second bridge portion 22 by a second opening CS2.

[0090] Each of the second island portions 21 can be connected to four of the second bridge portions 22. Each of the second island portions 21 can include drivers of the gate driving circuit GDC (see FIG. 2) described with reference to Figure 3

[0091] The second island portions 21 arranged in a row in the first non-display area NDA1 can correspond to the first island portions 11 arranged in a row in the display area DA. For example, the second island portions 21 arranged in an i-th row in the first non-display area NDA1 in a first direction (e.g., an x direction or an -x direction) can correspond to the first island portions 11 arranged in the same row (e.g., an i-th row) in the display area DA (where i is a positive number greater than 0).

[0092] ​The display device 1 can include a third bridge portion 23 disposed in the second sub-non-display area SNDA2 for connecting the display area DA to the first sub-non-display area SNDA1. The non-display area (e.g., the first non-display area NDA1) can include: the first sub-non-display area SNDA1 in which the second island portion 21 and the second bridge portion 22 are disposed; and the second sub-non-display area SNDA2 including the third bridge portion 23 and located between the first sub-non-display area SNDA1 and the display area DA. The third bridge portion 23 can be substantially identical to the first bridge portion 12 and the second bridge portion 22. For example, the width of the third bridge portion 23 can be identical to the width of the first bridge portion 12 and the width of the second bridge portion 22.

[0093] Figure 4c is a part of a display device according to an embodiment Figure 3 is a magnified plan view of the area IV of

[0094] Referring to Figure 4c , the display device 1 is a stretchable display device, and can include first island portions 11 spaced apart from each other in a first direction (e.g., an x direction or an -x direction) and a second direction (e.g., a y direction or a -y direction) in the display area DA, and first bridge portions 12 connecting adjacent first island portions 11 to each other.

[0095] The first bridge portions 12 can be disposed to be spaced apart from each other by first openings CS1 located between the first bridge portions 12. The first bridge portions 12 can have a serpentine shape. For example, as shown in Figure 4c , the first bridge portions 12 can have a substantially 'letter S' shape.

[0096] Each of the first island portions 11 can be connected to a plurality of the first bridge portions 12. For example, each of the first island portions 11 can be connected to four first bridge portions 12. Two of the first bridge portions 12 can be disposed on opposite sides of the first island portion 11 in the first direction (e.g., the x direction or the -x direction), and the remaining two of the first bridge portions 12 can be disposed on opposite sides of the first island portion 11 in the second direction (e.g., the y direction or the -y direction). The four first bridge portions 12 can be connected to four sides of the first island portion 11, respectively. Each of the four first bridge portions 12 can be adjacent to each corner of the first island portion 11.

[0097] The display device 1 can include a second bridge portion 22 disposed in the non-display area (e.g., in the Figure 4cThe first non-display area NDA1 shown in the figure has second island portions 21 spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second bridging portion 22 connecting adjacent second island portions 21 to each other.

[0098] The second bridging portions 22 can be arranged to be spaced apart from each other by a second opening CS2 located between the second bridging portions 22. The second bridging portions 22 can have a serpentine shape. For example, as Figure 4c As shown, the second bridging portion 22 may have an approximate 'letter S' shape. The size and / or width of the second bridging portion 22 may differ from the size and / or width of the first bridging portion 12. For example, the size and / or width of the second bridging portion 22 may be larger than the size and / or width of the first bridging portion 12. The radius of curvature of the arcuate portion of the second bridging portion 22 may differ from the radius of curvature of the arcuate portion of the first bridging portion 12. For example, the radius of curvature of the arcuate portion of the second bridging portion 22 may be larger than the radius of curvature of the arcuate portion of the first bridging portion 12.

[0099] Each of the second island portions 21 may be connected to a plurality of second bridging portions 22. Each of the second island portions 21 may be connected to four second bridging portions 22. Two second bridging portions 22 may be positioned on opposite sides of the second island portion 21 in a first direction (e.g., the x-direction or the -x-direction), and the remaining two second bridging portions 22 may be positioned on opposite sides of the second island portion 21 in a second direction (e.g., the y-direction or the -y-direction). In one embodiment, the four second bridging portions 22 may be connected to the four sides of the second island portion 21 respectively. Each second bridging portion 22 may be connected to the center portion of each side of the second island portion 21.

[0100] The second island portion 21 arranged in a row in the first non-display area NDA1 can correspond to the first island portion 11 arranged in multiple rows in the display area DA. For example, the second island portion 21 arranged in a row in the first non-display area NDA1 can correspond to the first island portion 11 arranged in the i-th row and the first island portion 11 arranged in the (i+1)-th row of the display area DA (where i is a positive number greater than 0). In another embodiment, one row of the second island portion 21 can correspond to n rows of the first island portion 11 (where n is a positive number equal to or greater than 3).

[0101] The non-display area (e.g., the first non-display area NDA1) can include a first sub-non-display area SNDA1 in which the above-described second island portion 21 and the second bridge portion 22 are disposed, and a second sub-non-display area SNDA2 between the first sub-non-display area SNDA1 and the display area DA. The third bridge portion 23 can be disposed in the second sub-non-display area SNDA2 to connect the display area DA and the first sub-non-display area SNDA1. One end of the third bridge portion 23 can be connected to the second island portion 21, and the other end of the third bridge portion 23 can be connected to the first island portion 11. For example, one end of the third bridge portion 23 can be connected to a center portion of one side of the second island portion 21, and the other end of the third bridge portion 23 can be connected to a center portion of one side of the first island portion 11.

[0102] The third bridge portion 23 can have a serpentine shape. In an embodiment, the shape of the third bridge portion 23 can be different from the shape of each of the first bridge portion 12 and the second bridge portion 22. The width of the third bridge portion 23 can be different from the width of the first bridge portion 12 and the width of the second bridge portion 22. The width of the third bridge portion 23 can be greater than the width of the first bridge portion 12, and can be less than the width of the second bridge portion 22. The third openings CS3 and the fourth openings CS4 of different shapes can be alternately disposed between the third bridge portions 23 in the second direction (e.g., the y direction or the -y direction).

[0103] Figure 5 FIG. 1 is a schematic plan view of a stretchable display device 1 according to an embodiment.

[0104] Referring to Figure 5 The first island portion 11 and the first bridge portion 12 disposed in the display area DA can be spaced apart from each other with the first openings CS1 therebetween. The first island portion 11 can include a light emitting element LED and a circuit (e.g., a pixel driving circuit portion (“PC”)) for driving the light emitting element LED electrically connected thereto, and the first bridge portion 12 can include a wiring WL electrically connected to the pixel driving circuit portion PC disposed in each of the adjacent first island portions 11.

[0105] In the first island portion 11, a buffer layer 111 including an inorganic insulating material can be disposed on the substrate 100, and a pixel drive circuit portion PC can be disposed on the buffer layer 111. An insulating layer IL including an inorganic insulating material and / or an organic insulating material can be disposed between the pixel drive circuit portion PC and the light emitting element LED. The light emitting element LED can be disposed on the insulating layer IL and can be electrically connected to the corresponding pixel drive circuit portion PC. The light emitting element LED can emit light of different colors or light of the same color. In an embodiment, each of the light emitting elements LED can emit red light, green light, or blue light. In some embodiments, the light emitting element LED can emit white light. In another embodiment, each of the light emitting elements LED can emit red light, green light, blue light, or white light.

[0106] The substrate 100 can include a polymer resin such as polyether sulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In an embodiment, the substrate 100 can include a single layer including the aforementioned resin. In another embodiment, the substrate 100 can have a multi-layer structure including a base layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material. The substrate 100 including the polymer resin can be flexible, rollable, or bendable.

[0107] In an embodiment, Figure 5 Three pixel drive circuit portions PC are shown to be arranged in each of the first island portions 11, and three light emitting elements LED are connected to each of the pixel drive circuit portions PC. However, the present disclosure is not limited thereto. In another embodiment, the number of the pixel drive circuit portions PC and the light emitting elements LED arranged in the first island portion 11 can be 1, 2, or 4 or more.

[0108] The encapsulation layer 300 can be disposed on the light emitting element LED and can protect the light emitting element LED from external force and / or moisture penetration. The encapsulation layer 300 can include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer 300 can have a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer stack are included. In another embodiment, the encapsulation layer 300 can include an organic material such as a resin. In some embodiments, the encapsulation layer 300 can include urethane epoxy acrylate. The encapsulation layer 300 can include a photosensitive material such as a photoresist.

[0109] In the first bridge portion 12, an insulating layer IL including an organic insulating material can be provided on the substrate 100. Unlike the first island portion 11, in the first bridge portion 12 that deforms relatively greatly, a layer including an inorganic insulating material that is prone to cracking can not exist when the stretchable display device 1 is stretched.

[0110] In an embodiment, the substrate 100 corresponding to the first bridge portion 12 can have the same stack structure as the stack structure of the substrate 100 corresponding to the first island portion 11. In an embodiment, the substrate 100 corresponding to the first bridge portion 12 and the substrate 100 corresponding to the first island portion 11 can be polymer resin layers that are formed together in the same process. In another embodiment, the substrate 100 corresponding to the first bridge portion 12 can have a stack structure different from the stack structure of the substrate 100 corresponding to the first island portion 11. In some embodiments, the substrate 100 corresponding to the first island portion 11 can have a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate 100 corresponding to the first bridge portion 12 can have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0111] As described above, the wiring WL of the first bridge portion 12 can be a signal line (e.g., a gate line and a data line) for supplying an electric signal to a transistor included in the pixel driving circuit portion PC of the first island portion 11, or a voltage line (e.g., a driving voltage line and an initialization voltage line) for supplying a voltage. The encapsulation layer 300 can also be disposed in the first bridge portion 12. In another embodiment, the encapsulation layer 300 can not exist in the first bridge portion 12.

[0112] Reference Figures 4a to 4c and Figure 5 The substrate 100 corresponding to the first island portion 11 and the substrate 100 corresponding to the first bridge portion 12 can be connected to each other. In other words, Figures 4a to 4c The plan view shown in FIG. 1A can be substantially the same as the plan view of the substrate 100 in FIG. 1B. In other words, the substrate 100 can include a region corresponding to the first island portion 11, a region corresponding to the first bridge portion 12, and an opening 100OP1 having the same shape as the shape of the first opening CS1. Figure 5

[0113] Similarly, the encapsulation layer 300 corresponding to the first island portion 11 and the encapsulation layer 300 corresponding to the first bridge portion 12 can be connected to each other. For example, Figures 4a to 4c ​The plan view illustrated in FIG. 1A can be substantially the same as a plan view of the encapsulation layer 300. In other words, the encapsulation layer 300 can include a region corresponding to the first island portion 11, a region corresponding to the first bridge portion 12, and an opening 300OP1 having a shape identical to that of the first opening CS1.

[0114] The circuit light emitting element layer 200 between the substrate 100 and the encapsulation layer 300 can include a buffer layer 111, a pixel driving circuit portion PC, a wiring WL, an insulating layer IL, and a light emitting element LED. Similar to the substrate 100, Figures 4a to 4c The plan view illustrated in FIG. 1A can be substantially the same as a plan view of the circuit light emitting element layer 200. In other words, the circuit light emitting element layer 200 can define therein an opening 200OP1 having a shape identical to that of the first opening CS1.

[0115] Figures 6a to 6c is an equivalent circuit diagram of a sub-pixel of the stretchable display device 1 according to an embodiment.

[0116] Referring to Figure 6a The light emitting element LED corresponding to the sub-pixel can be electrically connected to the pixel driving circuit portion PC, and the pixel driving circuit portion PC can include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel driving circuit portion PC can be electrically connected to a signal line and a voltage line. The signal line can include a gate line such as a first scan line SL1 and a data line DL, and the voltage line can include a first voltage line VDDL.

[0117] The second transistor T2 can be electrically connected to the first scan line SL1 and the data line DL. The first scan line SL1 can supply a first scan signal GW1 to a gate electrode of the second transistor T2. The second transistor T2 can be configured to transfer a data signal Dm input from the data line DL to the first transistor T1 according to the first scan signal GW1 input from the first scan line SL1.

[0118] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first voltage line VDDL, and can store a voltage corresponding to a difference between a voltage received from the second transistor T2 and a first power voltage VDD supplied by the first voltage line VDDL.

[0119] The first transistor T1 can be a driving transistor, and can be configured to control a driving current flowing through the light emitting element LED. The first transistor T1 can be connected to the first voltage line VDDL and the storage capacitor Cst. The first transistor T1 can be configured to control the driving current flowing from the first voltage line VDDL to the light emitting element LED in response to a voltage value stored in the storage capacitor Cst. The light emitting element LED can emit light having a certain brightness through the driving current. A first electrode of the light emitting element LED can be electrically connected to the first transistor T1, and a second electrode of the light emitting element LED can be electrically connected to a second voltage line VSSL supplying a second power voltage VSS, which can be referred to as a "low potential voltage."

[0120] Figure 6a The pixel driving circuit part PC is shown to include two transistors and one storage capacitor. However, in another embodiment, the pixel driving circuit part PC can include three or more transistors.

[0121] Reference Figure 6b The pixel driving circuit part PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0122] The pixel driving circuit part PC is electrically connected to signal lines and voltage lines. The signal lines can include gate lines such as a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EML, and a data line DL. The voltage lines can include a first initialization voltage line VIL1 and a second initialization voltage line VIL2, and a first voltage line VDDL.

[0123] The first voltage line VDDL can transmit a first power voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can transmit a first initialization voltage Vint initializing the first transistor T1 to the pixel driving circuit part PC. The second initialization voltage line VIL2 can transmit a second initialization voltage Vaint initializing a first electrode of the light emitting element LED to the pixel driving circuit part PC.

[0124] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light emitting element LED via the sixth transistor T6. The first transistor T1 can function as a driving transistor, and can be configured to receive a data signal Dm and supply a driving current to the light emitting element LED according to a switching operation of the second transistor T2.

[0125] The second transistor T2 can be a data write transistor, and can be electrically connected to the first scan line SL1 and the data line DL. The second transistor T2 can be electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 can be configured to be turned on according to the first scan signal GW received through the first scan line SL1, and to transmit the data signal Dm transmitted through the data line DL to the first node N1. That is, the second transistor T2 can be configured to perform a switching operation.

[0126] The third transistor T3 can be electrically connected to the first scan line SL1, and electrically connected to the light emitting element LED via the sixth transistor T6. The third transistor T3 can be configured to be turned on according to the first scan signal GW received through the first scan line SL1, to diode-connect the first transistor T1.

[0127] The fourth transistor T4 can be a first initialization transistor, and can be electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. The fourth transistor T4 can be configured to be turned on according to the third scan signal GI received through the third scan line SL3, and to transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, to initialize the voltage of the gate electrode of the first transistor T1. The third scan signal GI can correspond to the first scan signal of another pixel driving circuit portion arranged in a previous row of the corresponding pixel driving circuit portion PC.

[0128] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emission control transistor. The fifth transistor T5 and the sixth transistor T6 can be electrically connected to the emission control line EML, and can be configured to be turned on at the same time according to the emission control signal EM received through the emission control line EML, and to form a current path, so that a driving current can flow from the first voltage line VDDL to the light emitting element LED.

[0129] The seventh transistor T7 can be a second initialization transistor, and can be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be configured to be turned on according to the second scan signal GB received through the second scan line SL2, and to transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light emitting element LED, to initialize the first electrode of the light emitting element LED.

[0130] The storage capacitor Cst can include a first electrode CE1 and a second electrode CE2. The first electrode CE1 can be electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 can be electrically connected to the first voltage line VDDL. The storage capacitor Cst can store and maintain a voltage corresponding to a voltage difference between the first voltage line VDDL and the gate electrode of the first transistor T1, thereby maintaining a voltage applied to the gate electrode of the first transistor T1.

[0131] Referring to Figure 6c The pixel driving circuit portion PC can include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the storage capacitor Cst, and the auxiliary capacitor Ca.

[0132] The pixel driving circuit portion PC can be electrically connected to signal lines and voltage lines. The signal lines can include gate lines (such as a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EML) and a data line DL. The voltage lines can include a first initialization voltage line VIL1 and a second initialization voltage line VIL2, a sustain voltage line VSL, and a first voltage line VDDL.

[0133] The first voltage line VDDL can transmit a first power voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can transmit a first initialization voltage Vint to initialize the first transistor T1 to the pixel driving circuit portion PC. The second initialization voltage line VIL2 can transmit a second initialization voltage Vaint to initialize the first electrode of the light emitting element LED to the pixel driving circuit portion PC. The sustain voltage line VSL can provide a sustain voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) during an initialization period and a data write period.

[0134] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and can be electrically connected to the light emitting element LED via the sixth transistor T6. The first transistor T1 can function as a driving transistor, and can be configured to receive a data signal Dm and supply a driving current to the light emitting element LED according to a switching operation of the second transistor T2.

[0135] The second transistor T2 can be electrically connected to the first scan line SL1 and the data line DL, and can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 can be configured to be turned on according to the first scan signal GW received through the first scan line SL1, and to transmit the data signal Dm transmitted through the data line DL to the first node N1. That is, the second transistor T2 can be configured to perform a switching operation.

[0136] The third transistor T3 can be electrically connected to the first scan line SL1, and electrically connected to the light emitting element LED via the sixth transistor T6. The third transistor T3 can be configured to be turned on according to the first scan signal GW received through the first scan line SL1, to be diode-connected to the first transistor T1, thereby compensating for a threshold voltage of the first transistor T1.

[0137] The fourth transistor T4 can be electrically connected to the third scan line SL3 and the first initialization voltage line VIL1, and can be configured to be turned on according to the third scan signal GI received through the third scan line SL3, and to transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, to initialize the voltage of the gate electrode of the first transistor T1. The third scan signal GI can correspond to the first scan signal of another pixel driving circuit portion arranged in a previous row of the corresponding pixel driving circuit portion PC.

[0138] The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can be electrically connected to the emission control line EML, and can be configured to be turned on at the same time according to the emission control signal EM received through the emission control line EML, and to form a current path, so that a driving current can flow from the first voltage line VDDL to the light emitting element LED.

[0139] The seventh transistor T7 can be a second initialization transistor, and can be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be configured to be turned on according to the second scan signal GB received through the second scan line SL2, and to transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light emitting element LED, to initialize the first electrode of the light emitting element LED.

[0140] The ninth transistor T9 can be electrically connected to the second scan line SL2, the second electrode CE2 of the storage capacitor Cst, and the sustain voltage line VSL. The ninth transistor T9 can be configured to be turned on according to the second scan signal GB received through the second scan line SL2, and to transmit the sustain voltage VSUS to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst) during the initialization period and the data write period.

[0141] The eighth transistor T8 and the ninth transistor T9 can each be electrically connected to the second node N2 (e.g., the second electrode CE2 of the storage capacitor Cst). In some embodiments, in the initialization period and the data write period, the eighth transistor T8 can be turned off, and the ninth transistor T9 can be turned on, and in the emission period, the eighth transistor T8 can be turned on, and the ninth transistor T9 can be turned off. Because the sustain voltage VSUS is transmitted to the second node N2 in the initialization period and the data write period, the uniformity of the brightness of the stretchable display device according to the voltage drop of the first voltage line VDDL (e.g., long range uniformity ("LRU")) can be effectively improved.

[0142] The storage capacitor Cst can include a first electrode CE1 and a second electrode CE2. The first electrode CE1 can be electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 can be electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0143] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustain voltage line VSL, and the first electrode of the light emitting element LED. The auxiliary capacitor Ca can store and maintain a voltage corresponding to a voltage difference between the first electrode of the light emitting element LED and the sustain voltage line VSL while the seventh transistor T7 and the ninth transistor T9 are turned on, and thus can prevent the black state brightness from increasing when the sixth transistor T6 is turned off.

[0144] Figure 7 FIG. 1 is a plan view schematically illustrating a portion of a display device according to an embodiment. Figure 8 FIG. 2 is a cross-sectional view schematically illustrating a portion of the display device according to the embodiment.

[0145] Reference Figure 7 Referring to FIG. 1, the display device 1 is a stretchable display device, and can include first island portions 11 spaced apart from each other in a first direction (e.g., an x direction) and a second direction (e.g., a y direction), and first bridge portions 12 connecting adjacent first island portions 11 to each other. The first bridge portions 12 can have a serpentine shape, for example, a substantially "S" shape. Although Figure 7It is shown that each of the first island portions 11 is a quadrilateral (e.g., a square), but the present disclosure is not limited thereto. In another embodiment, the first island portions 11 can be rectangular, a polygon having five or more sides, or circular.

[0146] The first island portion 11 can be connected to a plurality of first bridge portions 12. For example, the first island portion 11 can be connected to four first bridge portions 12. Two of the first bridge portions 12 can be disposed on opposite sides of the first island portion 11 in a first direction (e.g., an x direction), and the remaining two of the first bridge portions 12 can be disposed on opposite sides of the first island portion 11 in a second direction (e.g., a y direction). The four first bridge portions 12 can be connected to four sides of the first island portion 11, respectively. Each of the first bridge portions 12 can be disposed adjacent to a corner of the first island portion 11.

[0147] A plurality of sub-pixels can be arranged in the first island portion 11. The plurality of sub-pixels can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, and the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can emit different colors of light. For example, the first sub-pixel SP1 can emit red light, the second sub-pixel SP2 can emit green light, and the third sub-pixel SP3 can emit blue light. The red light can be light belonging to a wavelength band of about 580 nanometers (nm) to about 780 nm, the green light can be light belonging to a wavelength band of about 495 nm to about 580 nm, and the blue light can be light belonging to a wavelength band of about 400 nm to about 495 nm.

[0148] Referring to Figure 7 and Figure 8 , each of the plurality of sub-pixels can include a light emitting element LED (see Figure 5 ), for example, a light emitting diode. In an embodiment, the light emitting diode can be an inorganic light emitting diode. Accordingly, a first light emitting diode 1230 emitting red light, a second light emitting diode 2230 emitting green light, and a third light emitting diode 3330 emitting blue light can be arranged in the first island portion 11.

[0149] The first to third pixel driving circuit portions PC1, PC2, and PC3 can be disposed between the substrate 100 and the first to third light emitting diodes 1230, 2230, and 3230. Each of the first to third pixel driving circuit portions PC1, PC2, and PC3 can include transistors and storage capacitors as previously described with reference to Figures 6a to 6c In an embodiment, the first to third pixel driving circuit portions PC1, PC2, and PC3 are shown to have the same configuration as that described with reference to Figure 6aThe pixel driving circuit section PC described has the same structure, and the specific structure is the same as the structure described above.

[0150] refer to Figure 8 The substrate 100 corresponding to the first island portion 11 may include a first sub-substrate 101, a first barrier layer 102, a second sub-substrate 103, and a second barrier layer 104. The first sub-substrate 101 and the second sub-substrate 103 may each comprise a polymer resin, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. The first barrier layer 102 and the second barrier layer 104 may each comprise an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0151] The size or area of ​​the inorganic insulating layer (e.g., the second barrier layer 104) disposed on the uppermost layer of the substrate 100 can be smaller than that of the substrate 100. Figure 7 The dimensions or area of ​​the first island portion 11 shown in the figure. (Reference) Figure 8 The size or area of ​​the inorganic insulating layer (e.g., the second barrier layer 104) disposed on the uppermost layer of the substrate 100 may be smaller than the size or area of ​​the first sub-substrate 101, the first barrier layer 102 and / or the second sub-substrate 103 of the substrate 100 corresponding to the first island portion 11.

[0152] A buffer layer 111 may be disposed on the substrate 100, and the first pixel driving circuit portion to the third pixel driving circuit portions PC1, PC2 and PC3 may be disposed on the buffer layer 111. The buffer layer 111 may contain an inorganic insulating material, such as silicon oxide, silicon nitride or silicon oxynitride.

[0153] Each of the first pixel driving circuit portions PC1, PC2, and PC3 may include a transistor TFT. The transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 8 The illustration shows a top-gate type where the gate electrode GE is disposed on the semiconductor layer Act and the gate insulating layer 113 is located between them. However, according to another embodiment, the transistor TFT can be a bottom-gate type.

[0154] The semiconductor layer Act may comprise polycrystalline silicon. Alternatively, the semiconductor layer Act may comprise amorphous silicon, oxide semiconductor, organic semiconductor, etc. The gate electrode GE may comprise a low-resistance metallic material. The gate electrode GE may comprise conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer comprising the aforementioned materials.

[0155] The gate insulating layer 113 between the semiconductor layer Act and the gate electrode GE may contain an inorganic insulating material, such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer 113 may be a single layer or multiple layers containing the aforementioned materials.

[0156] The source electrode SE and drain electrode DE can be located on the same layer (e.g., the second interlayer insulating layer 117) and can contain the same material. The source electrode SE and drain electrode DE can each contain a material with good conductivity. The source electrode SE and drain electrode DE can each contain a conductive material including Mo, Al, Cu, Ti, etc., and can be formed as a multilayer or a single layer containing the aforementioned materials. In one embodiment, the source electrode SE and drain electrode DE can each have a multilayer structure including a titanium layer, an aluminum layer, and a titanium layer (Ti / Al / Ti). The second interlayer insulating layer 117 can contain an inorganic insulating material, such as silicon oxide, nitric oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and can be a single layer or multiple layers containing the aforementioned materials.

[0157] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2, which overlap each other in a planar view and are separated by a first interlayer insulating layer 115. The storage capacitor Cst may overlap with a transistor TFT in a planar view. In this respect, Figure 8 The gate electrode GE of the transistor TFT is shown as the first electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not overlap with the transistor TFT in a planar view. The storage capacitor Cst may be covered by a second interlayer insulating layer 117. The second electrode CE2 of the storage capacitor Cst may contain a conductive material including Mo, Al, Cu, Ti, etc., and may be formed as a multilayer or a single layer containing the aforementioned materials. A first interlayer insulating layer 115 may be disposed between the gate insulating layer 113 and the second interlayer insulating layer 117. The first interlayer insulating layer 115 may contain an inorganic insulating material, such as silicon oxide, nitric oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or multiple layers containing the aforementioned materials.

[0158] like Figure 7 As shown, the size or area of ​​the inorganic insulating material layer IOL corresponding to the first island portion 11 can be smaller than the size or area of ​​the first island portion 11. (Reference) Figure 8 The size or area of ​​the inorganic insulating material layer IOL disposed on the substrate 100 may be smaller than the size or area of ​​the first sub-substrate 101, the first barrier layer 102 and / or the second sub-substrate 103 of the substrate 100. The inorganic insulating material layer IOL on the substrate 100 may include, for example, a buffer layer 111, a gate insulating layer 113, a first interlayer insulating layer 115 and a second interlayer insulating layer 117.

[0159] In a plan view, the edge of the inorganic insulating material layer IOL and the edge of the second sub-base plate 103 can overlap the organic material layer OL. The organic material layer OL can define an opening corresponding to the center portion of the first island portion 11 therein, and can have a frame-shaped type extending along the edge of the first island portion 11. The organic material layer OL can cover the edge of the inorganic insulating material layer IOL having a step with respect to the upper surface of the second sub-base plate 103 and the edge of the second sub-base plate 103. The organic material layer OL can contain an organic insulating material such as polyimide.

[0160] The first organic insulating layer 119 can be disposed on the second interlayer insulating layer 117, and the second organic insulating layer 121 can be disposed on the first organic insulating layer 119. The first organic insulating layer 119 and the second organic insulating layer 121 can each contain an organic insulating material such as polyimide.

[0161] The second voltage line VSSL can be disposed on the second organic insulating layer 121, and the third organic insulating layer 123 can be disposed on the second organic insulating layer 121. The third organic insulating layer 123 can contain an organic insulating material such as polyimide. The second voltage line VSSL can contain a conductive material including Mo, Al, Cu, Ti, or the like, and can be formed as a single layer or a plurality of layers containing the aforementioned material.

[0162] The first electrode pad 241 and the second electrode pad 242 can be disposed on the third organic insulating layer 123. The first electrode pad 241 can be electrically connected to the transistor TFT through a first connection member CM1 between the first organic insulating layer 119 and the second organic insulating layer 121 and a second connection member CM2 between the second organic insulating layer 121 and the third organic insulating layer 123.

[0163] The light emitting diode 230 can be disposed on the first electrode pad 241 and the second electrode pad 242, and can be electrically connected to the transistor TFT. As described previously, the light emitting diode 230 can be an inorganic light emitting diode, and can include a first light emitting diode 1230 emitting red light, a second light emitting diode 2230 emitting green light, and a third light emitting diode 3230 emitting blue light.

[0164] Each of the light emitting diodes 230 can include a first semiconductor layer 231, a second semiconductor layer 232, an intermediate layer 233 between the first semiconductor layer 231 and the second semiconductor layer 232, a sub-pixel electrode 235 electrically connected to the first semiconductor layer 231, and a counter electrode 238 electrically connected to the second semiconductor layer 232. The sub-pixel electrode 235 of the light emitting diode 230 can be electrically connected to the first electrode pad 241, and the counter electrode 238 can be electrically connected to the second electrode pad 242.

[0165] In addition, the sub-pixel electrode 235 can be electrically connected to the first semiconductor layer 231, and the counter electrode 238 can be electrically connected to the second semiconductor layer 232. In an embodiment, the sub-pixel electrode 235 and the first semiconductor layer 231 can be connected to each other through a first bonding metal layer 236, and the counter electrode 238 and the second semiconductor layer 232 can be connected to each other through a second bonding metal layer 237. The first bonding metal layer 236 and the second bonding metal layer 237 can each include a conductive material including Mo, Al, Cu, Ti, or the like, and can be formed as a single layer or a plurality of layers including the aforementioned material.

[0166] Specifically, the first light emitting diode 1230 can include a first sub-pixel electrode 1235, a first counter electrode 1238, a 1-1 semiconductor layer 1231, a first intermediate layer 1233, and a 2-1 semiconductor layer 1232. The first sub-pixel electrode 1235 can be electrically connected to the first pixel driving circuit portion PC1, and the first counter electrode 1238 can be electrically connected to the second voltage line VSSL. Similarly, the second light emitting diode 2230 can include a second sub-pixel electrode 2235, a second counter electrode 2238, a 1-2 semiconductor layer 2231, a second intermediate layer 2233, and a 2-2 semiconductor layer 2232. The second sub-pixel electrode 2235 can be electrically connected to the second pixel driving circuit portion PC2, and the second counter electrode 2238 can be electrically connected to the second voltage line VSSL. The third light emitting diode 3230 can include a third sub-pixel electrode 3235, a third counter electrode 3238, a 1-3 semiconductor layer 3231, a third intermediate layer 3233, and a 2-3 semiconductor layer 3232. The third sub-pixel electrode 3235 can be electrically connected to the third pixel driving circuit portion PC3, and the third counter electrode 3238 can be electrically connected to the second voltage line VSSL.

[0167] The sub-pixel electrode 235 can be disposed on the first electrode pad 241, and can include a metal or a metal oxide. The counter electrode 238 can be disposed on the second electrode pad 242, and can include a metal or a metal oxide. For example, the sub-pixel electrode 235 and the counter electrode 238 can each include Cu, gold (Au), chromium (Cr), Ti, Al, nickel (Ni), indium tin oxide (ITO), or an oxide or an alloy thereof. The sub-pixel electrode 235 and the counter electrode 238 can be disposed in the same layer and include the same material. However, the disclosure is not limited thereto, and in another embodiment, the sub-pixel electrode 235 and the counter electrode 238 can include different materials.

[0168] The first semiconductor layer 231 can include a p-type semiconductor layer. The p-type semiconductor layer can include a material having In x Al y Ga 1-x- ysemiconductor material of a composition formula of InAlGaN or AlInN, and can be doped with an n-type dopant such as Si, Ge, and Sn. For example, the second semiconductor layer 232 can include GaN doped with an n-type dopant.

[0169] The second semiconductor layer 232 can include an n-type semiconductor layer. The n-type semiconductor layer can include a semiconductor material of a composition formula of In x Al y Ga 1-x- y semiconductor material of a composition formula of InAlGaN or AlInN, and can be doped with an n-type dopant such as Si, Ge, and Sn. For example, the second semiconductor layer 232 can include GaN doped with an n-type dopant.

[0170] The intermediate layer 233 is a region in which electrons and holes are recombined. As the electrons and holes are recombined, the intermediate layer 233 can transition to a lower energy level and can generate light having a wavelength corresponding thereto. The intermediate layer 233 can also be referred to as an active layer. For example, the intermediate layer 233 can include a semiconductor material of a composition formula of In x Al y Ga 1-x-y semiconductor material of a composition formula of InAlGaN or AlInN, and can be doped with an n-type dopant such as Si, Ge, and Sn. For example, the second semiconductor layer 232 can include GaN doped with an n-type dopant.

[0171] When the intermediate layer 233 includes a material having an MQW structure, the intermediate layer 233 can have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. Alternatively, the intermediate layer 233 can have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked. The intermediate layer 233 can include different semiconductor materials depending on a wavelength of light emitted. In an embodiment, the intermediate layer 233 can emit blue light.

[0172] The encapsulation layer 300 can be disposed on the light emitting diode 230 and can protect the light emitting diode 230 from external force and / or moisture penetration. The encapsulation layer 300 can include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer 300 can have a structure in which an inorganic encapsulation layer containing an inorganic insulating material, an organic encapsulation layer containing an organic insulating material, and an inorganic encapsulation layer stack containing an inorganic insulating material are included. In another embodiment, the encapsulation layer 300 can contain an organic material such as a resin. In some embodiments, the encapsulation layer 300 can contain urethane epoxy acrylate. The encapsulation layer 300 can contain a photosensitive material such as a photoresist.

[0173] The functional layer 400 can be disposed on the encapsulation layer 300. That is, the functional layer 400 can be disposed on the light emitting diode 230. The functional layer 400 can include a light shielding layer 410 and an overcoat layer 420.

[0174] The light shielding layer 410 can define a light shielding layer opening overlapping the light emitting diode 230 in a plan view. Since the light shielding layer 410 defines a plurality of openings, the light shielding layer 410 can have a grid shape or a mesh shape. The light shielding layer 410 can contain a light shielding material and can contain a black material. The light shielding material can include a resin or a paste containing carbon black, carbon nanotubes, a black dye, or metal particles. The metal particles can be, for example, nickel, aluminum, molybdenum, and / or an alloy thereof. In addition, the light shielding material can include metal oxide particles such as chromium oxide or metal nitride particles such as chromium nitride. Since the light shielding layer 410 contains a light shielding material, reflection of external light due to a metal structure disposed below the light shielding layer 410 can be reduced.

[0175] The overcoat layer 420 can be disposed on the light shielding layer 410 to fill the openings of the light shielding layer 410. The overcoat layer 420 can be integrally formed throughout the first to third sub-pixels SP1, SP2, and SP3. The overcoat layer 420 can be a colorless light-transmitting layer having no color in a visible light band and can planarize an upper surface of the functional layer 400. The overcoat layer 420 can contain an organic material such as acrylic, benzocyclobutene ("BCB"), or hexamethyldisiloxane ("HMDSO").

[0176] Figures 9a to 9c FIG. 1 is a cross-sectional view schematically illustrating a light emitting diode of a display apparatus according to an embodiment. Figure 10a FIG. 2 is a plan view schematically illustrating a hole structure of a display apparatus according to an embodiment. Figure 10b FIG. 3 is a perspective view schematically illustrating a hole structure of a display apparatus according to an embodiment.

[0177] Figure 9a FIG. 4 is a plan view schematically illustrating a first sub-pixel SP1 (see Figure 7is a magnified cross-sectional view of the first light emitting diode 1230 of the first sub-pixel SP1 (see Figure 9b is a magnified cross-sectional view of the second light emitting diode 2230 of the second sub-pixel SP2 (see Figure 7 ), and Figure 9c is a magnified cross-sectional view of the third light emitting diode 3230 of the third sub-pixel SP3 (see Figure 7 ).

[0178] First, referring to Figure 9a , the first light emitting diode 1230 can include a first sub-pixel electrode 1235, a first-1 semiconductor layer 1231, a first intermediate layer 1233, a second-1 semiconductor layer 1232, and a first counter electrode 1238.

[0179] As described above, the first sub-pixel electrode 1235 can be disposed on the first electrode pad 241 and electrically connected to the first pixel driving circuit portion PC1 (see Figure 8 ), and the first-1 semiconductor layer 1231 can be electrically connected to the first sub-pixel electrode 1235 through the first bonding metal layer 236. The first counter electrode 1238 can be disposed on the second electrode pad 242 and electrically connected to the second voltage line VSSL (see Figure 8 ), and the second-1 semiconductor layer 1232 can be electrically connected to the first counter electrode 1238 through the second bonding metal layer 237.

[0180] The first intermediate layer 1233 can be disposed between the first-1 semiconductor layer 1231 and the second-1 semiconductor layer 1232 and can emit light. In an embodiment, the first intermediate layer 1233 can have an MQW structure and can emit blue light.

[0181] The second-1 semiconductor layer 1232 can have a porous structure in which a plurality of pores P are defined in a semiconductor material doped with an n-type dopant. The second-1 semiconductor layer 1232 can have a double porous layer structure including a first porous layer 232a and a second porous layer 232b disposed below the first porous layer 232a. In an embodiment, the structure of the pores P of the first porous layer 232a and the structure of the pores P of the second porous layer 232b can be different from each other.

[0182] The first porous layer 232a can include first pores P1 extending in a direction perpendicular to a main surface of the substrate 100 (i.e., in a third direction (e.g., z direction)), and the second porous layer 232b can include second pores P2 extending in a randomly variable direction. The main surface of the substrate 100 is parallel to the first direction (e.g., x direction) and the second direction (e.g., y direction).

[0183] The structure of the pores P will be described with reference to Figure 10a and Figure 10b . First, referring toFigure 10a The 2-1 semiconductor layer 1232 can have a plurality of holes P defined therein. Although Figure 10a The 2-1 semiconductor layer 1232 is shown as having 5 holes P defined therein, but this is for ease of explanation, and in another embodiment, the 2-1 semiconductor layer 1232 can have a greater number of holes P defined therein.

[0184] The holes P can have a planar diameter of about 100 nm to about 200 nm in size. As used herein, the "planar diameter" of a hole is the diameter of a cross-section obtained by a plane perpendicular to the extension direction of the hole. In an embodiment, the first intermediate layer 1233 can emit blue light in a wavelength range of about 400 nm to about 495 nm. In this case, when the diameter of the holes P is greater than half the wavelength of the light emitted from the first intermediate layer 1233, scattering of the light can not easily occur, and thus, when the diameter of the holes P exceeds 200 nm, the light extraction efficiency can decrease. Accordingly, the diameter of the holes P can be 200 nm or less. In addition, considering the size of quantum dots to be disposed in the holes P, which will be described below, the diameter of the holes P can be 100 nm or more.

[0185] Referring to Figure 10b The holes P can include first holes P1 of the first porous layer 232a and second holes P2 of the second porous layer 232b. The first holes P1 can have a cylindrical shape extending in a third direction (e.g., a z direction). That is, the first holes P1 can have a cylindrical hole structure passing through the first porous layer 232a. The second holes P2 can have a helical cylindrical shape extending in a randomly variable direction. That is, the second holes P2 can have a helical cylindrical shape passing through the second porous layer 232b. For example, as shown in FIG. 2B, the second holes P2 can have a helical structure wound with a constant predetermined curvature. However, the structure of the second holes P2 is not limited thereto, and the second holes P2 can extend in a random direction and have a cylindrical shape wound with various curvatures. In addition, the holes P can have a structure in which the first holes P1 and the second holes P2 are connected to each other and extend. Figure 10b The holes P including the first holes P1 and the second holes P2 can have a thickness of about 2 µm to about 7 µm in a direction perpendicular to the major surface of the substrate 100 (see

[0186] Figure 8 In an embodiment, the thickness of the first holes P1 and the thickness of the second holes P2 can be equal to each other in a direction perpendicular to the major surface of the substrate 100 (see Figure 8 Figure 8 In an embodiment, the thickness of the first porous layer 232a and the thickness of the second porous layer 232b can be equal to each other in a direction perpendicular to the major surface of the substrate 100 (see ​​

[0187] The structure of the holes P can be formed by an electrochemical etching method. The nanoscale holes P can be defined in the n-type semiconductor layer, such as the 2-1 semiconductor layer 1232, by electrochemical etching, and the size, shape, and distribution of the holes P can be differently adjusted depending on the etchant, voltage, and / or doping concentration during the electrochemical etching process.

[0188] For example, when a sample such as a GaN epitaxial wafer is immersed in a specific solvent and then an external voltage is applied to the sample, the n-type semiconductor layer can be etched by generating carriers by means of the external bias. That is, when a voltage is applied to the sample, selective etching of the n-type semiconductor layer can occur under specific conditions and a porous layer can be formed. Specifically, when an electric field is applied in a direction perpendicular to the main surface of the substrate 100 (see Figure 8 ), the electrolyte material penetrates the n-type semiconductor layer in the vertical direction according to the electric field, and thus, the holes P can be defined as a vertical cylindrical shape like the first holes P1. In addition, when the electric field applied from the outside in the vertical direction is released, the electrolyte material penetrates the n-type semiconductor layer in a random direction, and thus, the holes P can be defined as a cylindrical shape extending in a randomly variable direction like the second holes P2.

[0189] Through the etching process described above, the 2-1 semiconductor layer 1232 can have a dual porous layer structure in which the holes P have different structures. That is, in the display device 1 according to the embodiment, since the n-type semiconductor layer includes the second porous layer 232b in which the second holes P2 are defined in a random direction and the first porous layer 232a in which the first holes P1 are defined in a vertical direction, the light extraction effect can be increased.

[0190] Specifically, the light emitted from the first intermediate layer 1233 can be scattered in a random direction through the second holes P2 of the second porous layer 232b. That is, because the n-type semiconductor material (e.g., GaN) of the second porous layer 232b and the base resin 250, which will be described later, have different refractive indices, and the second holes P2 are arranged to extend in various directions, the light emitted from the first intermediate layer 1233 can be more effectively scattered. In an embodiment, since the second porous layer 232b is used to scatter light, the first light emitting diode 1230 can not include an additional scatterer.

[0191] Also, because the first porous layer 232a defines the first hole P1 in the vertical direction therein, only vertical light among the light passing through the second porous layer 232b can be extracted from the first light emitting diode 1230. That is, because the n-type semiconductor material of the first porous layer 232a and the base resin 250 have different refractive indexes, and the first hole P1 extends in the vertical direction, the light passing through the second porous layer 232b can be emitted in the vertical direction. For example, among the light passing through the second porous layer 232b, the light emitted in the vertical direction can be extracted in the vertical direction as it is through the first hole P1. Also, among the light passing through the second porous layer 232b, some light emitted in the lateral direction can be extracted in a direction close to the vertical through reflection at the interface of the first hole P1. In other words, the first hole P1 of the first porous layer 232a can increase the amount of light emitted in the vertical direction, and thus, can effectively improve the light extraction efficiency of the display device 1.

[0192] Referring back to Figure 9a , the first quantum dot Q1 and the base resin 250 can be placed in the first hole P1 of the first porous layer 232a and the second hole P2 of the second porous layer 232b. The first quantum dot Q1 can be disposed in the base resin 250 within the hole P in a dispersed form, and can be injected into the hole P. The first quantum dot Q1 and the base resin 250 can be injected through an inkjet process, a slot coating process, a spin coating process, or the like. The base resin 250 can be a light-transmissive material, and can include a polymer resin such as silicone resin, epoxy resin, acrylic, BCB, or HMDSO.

[0193] A quantum dot is an inorganic material having a size of several nanometers, and has a band gap of a specific wavelength, and thus, when the quantum dot absorbs light having energy higher than the band gap, the quantum dot can emit light of a different wavelength. The quantum dot can control the color of the emitted light depending on the particle size, and accordingly, the quantum dot can have various emission colors such as blue, red, and green. In an embodiment, the first quantum dot Q1 disposed in the first sub-pixel SP1 can convert blue light emitted from the first intermediate layer 1233 into red light. The first quantum dot Q1 can absorb blue light and shift its wavelength according to energy transition to emit red light. That is, the first porous layer 232a and the second porous layer 232b including the first quantum dot Q1 can serve as a color conversion layer that converts blue light into red light.

[0194] The first quantum dot Q1 can have a core-shell structure with a core portion and a shell portion, or can have a particle structure without a shell. The core-shell structure can be a single-shell structure or a multi-shell structure (for example, a double-shell structure). The quantum dot can include a Group II-VI series semiconductor, a Group III-V series semiconductor, a Group IV-VI series semiconductor, a Group IV series semiconductor, and / or a graphene quantum dot. The first quantum dot Q1 can include, for example, Cd, Se, Zn, S, and / or InP, and can have a diameter of several tens of nm or less, for example, a diameter of about 10 nm or less.

[0195] Since the first quantum dot Q1 is arranged in the second hole P2 of the second porous layer 232b in a random direction as described above, the color conversion efficiency of the first light emitting diode 1230 can be effectively improved. That is, since the second hole P2 has a structure extending in a random direction, blue light whose color has not been converted can be scattered through the second hole P2 and converted to red light by the first quantum dot Q1.

[0196] In addition, as described above, light converted to red light and scattered in the second porous layer 232b can be extracted as light in a vertical direction through the first porous layer 232a. However, since the first quantum dot Q1 is also arranged in the first porous layer 232a, blue light that has not been converted to red light in the second porous layer 232b can be converted to red light by the first quantum dot Q1 arranged in the first porous layer 232a. Accordingly, the display device 1 according to the embodiment can have excellent color conversion efficiency and light extraction efficiency. In an embodiment, since the color conversion efficiency within the light emitting diode 230 (see Figure 8 ) is excellent, an additional color filter layer can not be provided on the light emitting diode 230 (see Figure 8 ).

[0197] In addition to the first porous layer 232a and the second porous layer 232b, the 2-1 semiconductor layer 1232 can further include a base layer 232c. The base layer 232c can be a portion of the 2-1 semiconductor layer 1232 that directly contacts the first intermediate layer 1233, and can be disposed between the first intermediate layer 1233 and the second porous layer 232b.

[0198] Like the first porous layer 232a and the second porous layer 232b, the base layer 232c can include a semiconductor material doped with an n-type dopant. For example, the base layer 232c can include GaN doped with an n-type dopant. However, unlike the first porous layer 232a and the second porous layer 232b, the base layer 232c can include a non-porous structure. That is, the base layer 232c can be a 2-1 semiconductor layer 1232 in which no pores P are disposed. The reason that the pores P are not disposed in the base layer 232c can be to increase the light emission efficiency of the first intermediate layer 1233. The base layer 232c can have a thickness of about 0.3 μm to about 0.5 μm in a direction perpendicular to the main surface of the substrate 100 (see FIG. 1). Figure 8

[0199] The first light emitting diode 1230 can further include a protective layer 239. The protective layer 239 can be disposed at the side of the first light emitting diode 1230. Specifically, the protective layer 239 can cover both sides of the 1-1 semiconductor layer 1231, both sides of the first intermediate layer 1233, and both sides of the 2-1 semiconductor layer 1232. The protective layer 239 can be provided as a single layer or multiple layers. When the protective layer 239 is provided as multiple layers, the protective layer 239 can have a distributed Bragg reflector (“DBR”) structure in which first and second layers including inorganic films and having different refractive indices are alternately stacked.

[0200] Next, referring to Figure 9b , the second light emitting diode 2230 can have the same structure as that of the first light emitting diode 1230, but can include second quantum dots Q2 instead of the first quantum dots Q1. As described before, the quantum dots can control the color of light emitted depending on the particle size, and accordingly, the quantum dots can have various emission colors such as blue, red, and green. In an embodiment, the second quantum dots Q2 disposed in the second sub-pixel SP2 can convert blue light emitted from the first intermediate layer 1233 into green light. The second quantum dots Q2 can absorb the blue light and shift its wavelength according to energy transition to emit green light. That is, the first porous layer 232a and the second porous layer 232b including the second quantum dots Q2 can serve as a color conversion layer that converts blue light into green light.

[0201] In addition, because the 2-2 semiconductor layer 2232 also has a double porous layer structure including the first porous layer 232a and the second porous layer 232b, the second light emitting diode 2230 can have excellent color conversion efficiency and light extraction efficiency similar to the first light emitting diode 1230.

[0202] Next, referring to Figure 9c ​Quantum dots may not be disposed in the hole P of the third light-emitting diode 3230, and only the substrate resin 250 may fill the hole P. Specifically, the third sub-pixel SP3 may be a blue light-emitting sub-pixel, and since the third intermediate layer 3233 already emits blue light, a color conversion process may not be necessary. Accordingly, quantum dots may not be disposed in the second-third semiconductor layer 3232 of the third light-emitting diode 3230, and therefore, the first porous layer 232a and the second porous layer 232b may be used as light-transmitting layers.

[0203] However, even when quantum dots are not arranged in the third light-emitting diode 3230, the first porous layer 323a of the third light-emitting diode can still have a first hole P1 in the first vertical direction, and the second porous layer 232b can have a second hole P2 in a random direction. That is, because the second-third semiconductor layer 3232 also has a double porous layer structure including the first porous layer 232a and the second porous layer 232b, the third light-emitting diode 3230 can have excellent light extraction efficiency similar to the first light-emitting diode 1230.

[0204] Figure 11a This is a schematic cross-sectional view of a light-emitting diode of a display device according to another embodiment. Figure 11b This is a schematic cross-sectional view of a light-emitting diode of a display device according to another embodiment. (Reference) Figure 11a and Figure 11b Apart from the features of the first porous layer 232a and the second porous layer 232b, the other features are the same as those of the reference layer. Figures 7 to 10b The described characteristics are the same. Figure 11a and Figure 11b In, with Figures 7 to 10b Those figure labels in the same figure indicate that they are the same as those in the figure. Figures 7 to 10b Those components are the same as those components, and therefore, their redundant descriptions are omitted and the differences will be described below.

[0205] First, refer to Figure 11a The first light-emitting diode 1230' may include a first semiconductor layer 1231, a first intermediate layer 1233, and a second semiconductor layer 1232'. The second semiconductor layer 1232' may include a first porous layer 232a', a second porous layer 232b', and a substrate layer 232c.

[0206] However, in one embodiment, in a third direction (e.g., the z-direction), the thickness of the first hole P1 can be greater than the thickness of the second hole P2. That is, in a direction perpendicular to the substrate 100 (see... Figure 8In the direction of the main surface of the first porous layer 232a', the thickness can be greater than the thickness of the second porous layer 232b'. Accordingly, because the length of the first hole P1 extending in the vertical direction (e.g., the z-direction) increases, the amount of light extracted in the vertical direction from the light emitted from the first intermediate layer 1233 can increase. As a result, according to... Figure 11a The display device shown in the embodiment can effectively improve light extraction efficiency. Figure 11a The structure shown is applicable not only to the first light-emitting diode 1230', but also to the second light-emitting diode 2230 (see...). Figure 8 ) and the third light-emitting diode 3230 (see Figure 8 ).

[0207] Next, refer to Figure 11b The first light-emitting diode 1230'' may include a first semiconductor layer 1231, a first intermediate layer 1233, and a second semiconductor layer 1232''. The second semiconductor layer 1232'' may include a first porous layer 232a'', a second porous layer 232b'', and a substrate layer 232c.

[0208] However, in one embodiment, in a third direction (e.g., the z-direction), the thickness of the second hole P2 can be greater than the thickness of the first hole P1. That is, in a direction perpendicular to the substrate 100 (see... Figure 8 In the direction of the main surface of the first porous layer 232a'', the thickness of the second porous layer 232b'' can be greater than the thickness of the first porous layer 232a''. Accordingly, because the length of the second pore P2 extending in a random direction increases, the scattering rate of light emitted from the first intermediate layer 1233 can increase. When the scattering rate increases, unconverted light in the blue light emitted from the first intermediate layer 1233 can be scattered and converted into red light through the first quantum dot Q1. As a result, according to... Figure 11b The display device shown in the embodiment can effectively improve color conversion efficiency. Figure 11b The structure shown is applicable not only to the first light-emitting diode 1230'', but also to the second light-emitting diode 2230 (see...). Figure 8 ).

[0209] Figure 12 This is a schematic cross-sectional view of a portion of a display device according to another embodiment. Reference Figure 12 Apart from the features of functional layer 400, other features are similar to the reference. Figures 7 to 10b The described characteristics are the same. Figure 12 In, with Figures 7 to 10b Those figure labels in the same figure indicate that they are the same as those in the figure. Figures 7 to 10b Those components are the same as those components, and therefore, their redundant descriptions are omitted and the differences will be described below.

[0210] refer to Figure 12 In addition to the light-shielding layer 410 and the outer coating layer 420, the functional layer 400 may further include a color filter layer 430. The color filter layer 430 may include first to third color filters 431, 432, and 433, respectively, corresponding to the first to third sub-pixels SP1, SP2, and SP3. The first to third color filters 431, 432, and 433 may overlap with the first to third light-emitting diodes 1230, 2230, and 3230, respectively, in a direction perpendicular to the main surface of the substrate 100. The first to third color filters 431, 432, and 433 may filter the light emitted from the first to third light-emitting diodes 1230, 2230, and 3230, respectively.

[0211] The first color filter 431 allows only red light in the wavelength range of about 580 nm to about 780 nm to pass through, the second color filter 432 allows only green light in the wavelength range of about 495 nm to about 580 nm to pass through, and the third color filter 433 allows only blue light in the wavelength range of about 400 nm to about 495 nm to pass through. Accordingly, the color filter layer 430 can increase the color purity of the light by allowing only light in specific wavelength bands of the light emitted from the light-emitting diode 230 to pass through.

[0212] Furthermore, the color filter layer 430 can reduce external light reflection in the display device 1. For example, when external light reaches the first color filter 431, only light with the preset wavelength described above can pass through the first color filter 431, and light with other wavelengths can be absorbed by the first color filter 431. Therefore, in the external light incident on the display device 1, only light with the preset wavelength described above can pass through the first color filter 431, and some light can be reflected from the counter electrode 238 or sub-pixel electrode 235 below the first color filter 431 and emitted to the outside again. As a result, because only some of the external light incident at the location of the first sub-pixel SP1 is reflected to the outside, external light reflection can be reduced. This description can also be applied to the second color filter 432 and the third color filter 433.

[0213] In other words, according to such Figure 12 In the display device 1 of the embodiment shown, since the light-emitting diode 230 includes a double porous layer structure and quantum dots, the color conversion efficiency and light extraction efficiency can be initially improved. Furthermore, since the functional layer 400 includes a color filter layer 430, the color conversion efficiency can be further improved, and external light reflection can be reduced. As a result, the display device 1 according to another embodiment can achieve images with better quality.

[0214] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device comprising: a substrate including a display area and a non-display area outside the display area; and a plurality of light emitting diodes arranged in the display area, wherein each of the plurality of light emitting diodes has a double porous layer structure including a first porous layer and a second porous layer disposed below the first porous layer, the first porous layer defining first pores extending in a direction perpendicular to a major surface of the substrate therein, and the second porous layer defining second pores extending in a randomly variable direction therein. 2.The display device of claim 1, wherein quantum dots are arranged in the first pores and the second pores. 3.The display device of claim 2, further comprising a base resin arranged in the first pores and the second pores, wherein the quantum dots are dispersedly arranged in the base resin. 4.The display device of claim 3, wherein the display area includes first sub-pixels for emitting red light, second sub-pixels for emitting green light, and third sub-pixels for emitting blue light, the quantum dots are arranged in light emitting diodes of the first sub-pixels and light emitting diodes of the second sub-pixels, and the plurality of light emitting diodes includes the light emitting diodes of the first sub-pixels and the light emitting diodes of the second sub-pixels. 5.The display device of claim 4, wherein the first pores and the second pores arranged in the third sub-pixels are filled with the base resin and free of the quantum dots. 6.The display device of claim 1, wherein the first pores and the second pores extend and connect to each other. 7.The display device of claim 1, wherein the first pores have a cylindrical shape. 8.The display device of claim 1, wherein the second pores have a helical cylindrical shape. 9.The display device of claim 1, wherein a planar diameter of each of the first pores and the second pores is about 100 nanometers (nm) to about 200 nm. a thickness of the first porous layer and a thickness of the second porous layer are equal to each other in the direction perpendicular to the major surface of the substrate.

10. The display device according to claim 1, wherein the thickness of the first porous layer is greater than the thickness of the second porous layer in the direction perpendicular to the major surface of the substrate.

11. The display device according to claim 1, wherein the thickness of the second porous layer is greater than the thickness of the first porous layer in the direction perpendicular to the major surface of the substrate.

12. The display device according to claim 1, wherein 13.The display device of claim 1, wherein each of the plurality of light emitting diodes further comprises: a first semiconductor layer doped with a p-type dopant; a second semiconductor layer doped with an n-type dopant; and an intermediate layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the first porous layer and the second porous layer are included in the second semiconductor layer. ​ ​ 14. The display device of claim 13, wherein the first porous layer has a structure in which the first holes are defined in a material constituting the second semiconductor layer, and the second porous layer has a structure in which the second holes are defined in a material constituting the second semiconductor layer.

15. The display device according to claim 14, wherein the material constituting the second semiconductor layer includes a semiconductor material having a composition formula of In x Al y Ga 1-x-y N, wherein 0 < x < 1, 0 < y < 1, and 0 < x + y < 1.

16. The display device of claim 13, wherein the second semiconductor layer further comprises a base layer disposed between the intermediate layer and the second porous layer, wherein the base layer has a non-porous structure.

17. The display device of claim 16, wherein each of the first porous layer and the second porous layer has a thickness of about 2 micrometers (pm) to about 7 pm.

18. The display device of claim 16, wherein the base layer has a thickness of about 0.3 pm to about 0.5 pm.

19. The display device of claim 13, wherein each of the plurality of light emitting diodes further comprises: a sub-pixel electrode electrically connected to the first semiconductor layer; and a counter electrode electrically connected to the second semiconductor layer, wherein the sub-pixel electrode is connected to a pixel circuit arranged in the display area, and the counter electrode is electrically connected to a voltage line for receiving a low potential voltage.

20. The display device of claim 1, further comprising: a light shielding layer disposed over each of the plurality of light emitting diodes and defining a light shielding layer opening overlapping the light emitting diode therein; and an overcoat layer disposed on the light shielding layer.

21. The display device of claim 20, wherein the overcoat layer fills the light shielding layer opening.

22. The display device of claim 20, further comprising a color filter layer, the color filter layer filling the light shielding layer opening, wherein the overcoat layer covers the light shielding layer and the color filter layer.

23. The display device of claim 20, further comprising an encapsulation layer disposed between the light shielding layer and each of the plurality of light emitting diodes.

24. The display device of claim 1, further comprising: island portions arranged in the display area and spaced apart from each other along rows and columns; and bridge portions connecting adjacent ones of the island portions to each other, wherein each of the island portions includes at least one of the plurality of light emitting diodes.

25. The display device of claim 24, wherein the bridge portions each have a serpentine shape. ​ ​ ​

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