In-band flatness compensation method and system based on large-bandwidth spectrum analyzer

Abstract

The invention discloses an in-band flatness compensation method and system based on a large-bandwidth spectrum analyzer, and relates to the technical field of signal processing, and the method comprises the following steps: obtaining and optimizing a complex compensation coefficient table corresponding to the in-band frequency response of a radio frequency front-end channel filter through a dynamic inner ring calibration and compensation optimization system; receiving a to-be-measured radio frequency signal, filtering the to-be-measured radio frequency signal through the radio frequency front-end channel filter, and performing analog-to-digital conversion and digital down-conversion processing to form a to-be-measured baseband I / Q data frame; performing windowing and fast Fourier transform on the baseband I / Q data frame to be measured to obtain a frequency spectrum of a signal to be measured; performing frequency domain complex multiplication on the frequency spectrum of the signal to be measured and the corresponding complex compensation coefficient in the compensation coefficient table to obtain a compensated signal frequency spectrum; and performing inverse fast Fourier transform on the compensated signal spectrum, and outputting an I / Q signal. According to the invention, logic resource consumption and errors can be reduced.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to an in-band flatness compensation method and system based on a large bandwidth spectrum analyzer. Background Technology

[0002] In modern spectrum analyzers, before a signal enters the ADC chip for sampling, it typically passes through a filter with a constant passband bandwidth in the front-end channel. This filter is the RF front-end channel filter, and its passband bandwidth determines the maximum analysis bandwidth of the spectrum analyzer. However, because the RF front-end channel filter is an analog filter composed of analog components, its passband cannot be as flat as a digital filter. This results in excessively large differences in signal amplitude within the analysis bandwidth after the signal passes through the RF front-end channel filter, affecting normal spectrum analysis. The common industry solution to this problem is to use a digital compensation filter implemented using digital processing devices such as FPGAs after the ADC chip to compensate for the flatness of the digital signal sampled by the ADC chip. The coefficients of this digital compensation filter are calculated by a compensation algorithm in the host computer software based on the actual in-band flatness of the RF front-end channel filter. After passing through this digital filter, the signal amplitude differences within the analysis bandwidth become very small due to the compensation effect, and will not affect subsequent digital signal processing and spectrum analysis.

[0003] The first drawback of this approach is its excessive resource consumption when the signal bandwidth is large. This approach directly filters the digital signal sampled by the ADC chip in the time domain. Although the principle is relatively simple, as the analysis bandwidth of modern spectrum analyzers increases and the compensation requirements become more stringent, the order of the digital compensation filter in this approach will become increasingly higher. In the specific FPGA implementation, the logic resources required will increase, and these logic resources must work in parallel at the same time. Consequently, the logic resources available for subsequent digital signal processing will decrease. For example, when the analysis bandwidth reaches the GHz level and the required flatness after compensation is ±0.1dBm, the order of the digital compensation filter required will reach thousands, which is simply impossible to achieve in a typical FPGA chip.

[0004] The second drawback is the relatively large error. As can be seen from the block diagram, this scheme must rely on an independent signal source located outside the entire spectrum analyzer to provide the calibration signal. This increases the compensation calibration loop and introduces many unforeseen errors: First, the calibration signal emitted by the external signal source itself has a certain error. Second, the calibration signal passes through many RF amplifiers, filters, and other RF signal conditioning circuits from the analyzer to the ADC chip for sampling. These conditioning circuits also have certain errors. These errors cannot be eliminated in this scheme. Therefore, when high flatness is required, the compensation effect of this scheme will not be ideal. Summary of the Invention

[0005] To reduce logic resource consumption and errors, this application provides an in-band flatness compensation method and system based on a large bandwidth spectrum analyzer.

[0006] On the one hand, this application provides an in-band flatness compensation method based on a large bandwidth spectrum analyzer, which adopts the following technical solution: A method for in-band flatness compensation based on a high-bandwidth spectrum analyzer, executed by a field-programmable gate array within the spectrum analyzer, includes the following steps: The complex compensation coefficient table corresponding to the in-band frequency response of the RF front-end channel filter is obtained and optimized through the dynamic inner loop calibration and compensation optimization system. The system receives the radio frequency signal to be tested, filters the radio frequency signal to be tested through the radio frequency front-end channel filter, and performs analog-to-digital conversion and digital down-conversion processing to form the baseband I / Q data frame to be tested. Windowing and Fast Fourier Transform are applied to the baseband I / Q data frame to be tested to obtain the spectrum of the signal to be tested; The spectrum of the signal under test is multiplied by the corresponding complex compensation coefficients in the compensation coefficient table in the frequency domain to obtain the compensated signal spectrum. The inverse fast Fourier transform is performed on the compensated signal spectrum to output the time-domain I / Q signal after in-band flatness compensation.

[0007] Optionally, obtaining the complex compensation coefficient table corresponding to the in-band frequency response of the RF front-end channel filter includes: Based on the target compensation accuracy and the bandwidth of the RF front-end channel filter, determine the number of frequency points N required for flatness compensation; The calibration signal is generated sequentially at N discrete frequency points using a step-sweep method, and the calibration signal is fed into the input of the RF front-end channel filter. The signal output from the RF front-end channel filter is processed to extract the measured amplitude response value at each swept frequency point; Based on the measured amplitude response values ​​at each frequency point and the preset ideal amplitude response values, the corresponding complex compensation coefficients are calculated, and the complex compensation coefficients of all N frequency points are stored to form the complex compensation coefficient table.

[0008] Optionally, the step of sequentially generating calibration signals at N discrete frequency points using a stepped frequency sweep method includes: The field-programmable gate array (FPGA) controls its internal direct digital frequency synthesizer to generate a digital calibration signal, which is then converted into an analog calibration signal after digital-to-analog conversion.

[0009] Optionally, the step-sweep frequency method is implemented by updating the frequency control word of the direct digital frequency synthesizer, and the frequency control word satisfies the following formula: FW (k) = FW0 + k * (BW / N); Where k is an integer from 0 to N-1; FW(k) is the frequency control word corresponding to the kth sweep point; BW is the passband bandwidth of the RF front-end channel filter; and FW0 is the control word corresponding to the sweep start frequency.

[0010] Optionally, the processing of the signal output from the RF front-end channel filter to extract the measured amplitude response value at each swept frequency point includes: The signal output from the RF front-end channel filter is sequentially subjected to analog-to-digital conversion and digital down-conversion to obtain a baseband I / Q signal sequence; The spectrum of the calibration signal is obtained by windowing and performing a fast Fourier transform on the baseband I / Q signal sequence. For each swept frequency point, the measured amplitude response value at the corresponding frequency point is extracted from the spectrum of the calibration signal.

[0011] Optionally, the calculation of the corresponding complex compensation coefficient based on the measured amplitude response values ​​at each frequency point and the preset ideal amplitude response values ​​includes: Calculate the ratio of the ideal value of the amplitude response to the measured value of the amplitude response to obtain the amplitude compensation factor; Based on the phase information of the baseband I / Q signal sequence, calculate the phase offset of the current frequency point relative to the reference frequency point, and take its negative value as the phase compensation factor. The complex compensation coefficient is synthesized from the amplitude compensation factor and the phase compensation factor.

[0012] Optionally, the dynamic inner loop calibration and compensation optimization system performs the following steps: Broadband test signal sequences are generated by controlling the internal direct digital frequency synthesizer through a field-programmable gate array; The test signal sequence can be selectively fed into a standard inner loop calibration path or a full-link calibration path via an RF switch matrix. The standard inner loop calibration path is characterized by the test signal being fed directly to the analog-to-digital converter after digital-to-analog conversion, bypassing the RF front-end channel filter. The full-link calibration path is characterized by the test signal being fed back to the analog-to-digital converter after digital-to-analog conversion, via the RF front-end channel filter. Switch to the standard inner loop calibration path, measure and calculate the inherent frequency response error data of the inner loop calibration path; Switch to the full-link calibration path and measure the overall frequency response data, including the RF front-end channel filter. Error stripping is performed on the overall frequency response measured data based on the inherent frequency response error data to obtain the pure RF front-end channel filter frequency response. Based on the pure RF front-end channel filter frequency response, an initial complex compensation coefficient table is calculated and generated.

[0013] Optionally, after calculating and generating an initial complex compensation coefficient table based on the pure RF front-end channel filter frequency response, the method further includes an iterative optimization step: The initial complex compensation coefficient table is loaded into the signal generation parameters of the direct digital frequency synthesizer in a digital predistortion manner; The direct digital frequency synthesizer is controlled to generate a new test signal sequence, which is then measured again through the second path; Based on the new measurement results and the residual error of the ideal response, the complex compensation coefficient table is optimized and updated in reverse. Repeat the above iterative steps until the residual error is lower than the preset threshold to obtain the final optimized complex compensation coefficient table.

[0014] Optionally, after performing error stripping on the overall frequency response measured data based on the inherent frequency response error data to obtain the pure RF front-end channel filter frequency response, the method further includes: The complex compensation coefficients at each discrete frequency point calculated based on the pure frequency response are subjected to frequency domain smoothing filtering. High-density interpolation is performed on the smoothed discrete coefficients to generate a high-resolution complex compensation coefficient table for the frequency domain complex multiplication operation.

[0015] On the other hand, the in-band flatness compensation system based on a large bandwidth spectrum analyzer provided in this application adopts the following technical solution: An in-band flatness compensation system based on a high-bandwidth spectrum analyzer includes: an RF front-end channel filter, an analog-to-digital converter, a field-programmable gate array (FPGA), and a memory; the FPGA is configured to perform the method described therein.

[0016] In summary, this application includes at least one of the following beneficial technical effects: This application first uses a dynamic inner loop calibration and compensation optimization system to obtain and optimize a complex compensation coefficient table corresponding to the in-band frequency response of the RF front-end channel filter. Then, it receives the RF signal under test, filters it through the RF front-end channel filter, and performs analog-to-digital conversion and digital down-conversion to form a baseband I / Q data frame under test. Next, it performs windowing and fast Fourier transform on the baseband I / Q data frame to obtain the spectrum of the signal under test. Then, it performs a frequency domain complex multiplication operation on the spectrum of the signal under test and the corresponding complex compensation coefficients in the compensation coefficient table to obtain the compensated signal spectrum. Finally, it performs an inverse fast Fourier transform on the compensated signal spectrum to output the time-domain I / Q signal after in-band flatness compensation. The calculation is relatively simple; the compensation algorithm is directly implemented by the FPGA logic, eliminating the need for host computer software. The compensation algorithm no longer requires calculating the amplitude and phase responses based on the pre-compensation I / Q signals and the desired ideal in-band flatness to synthesize a digital compensation filter. Instead, it only requires a simple division operation using the spectrum of the FFT-derived I / Q signals and the desired ideal in-band flatness. In this system, the calibration signal is directly generated by a digital device like a DDS, eliminating the need for a separate external signal source. Since the amplitude of the calibration signal generated by the DDS is almost consistent at every frequency point, the entire compensation and calibration loop only contains errors generated by the DAC chip and the RF channel filter to be compensated, eliminating errors from the RF link and various conditioning circuits, significantly improving the compensation effect.

[0017] There are no longer any time-domain filtering operations in this system, so there is no need to implement a high-order digital compensation filter. All calculations are performed by multiplication, FFT, and IFFT. On the other hand, the calculations within a certain I / Q data frame are serial, so at any given moment, not all multipliers or FFT circuits need to work simultaneously. This greatly reduces the consumption of logic resources within the FPGA and simplifies the implementation difficulty of the system to a certain extent. Attached Figure Description

[0018] Figure 1 This is a flowchart of an in-band flatness compensation method based on a large bandwidth spectrum analyzer according to an embodiment of this application; Figure 2 This is a structural block diagram of an in-band flatness compensation system based on a large bandwidth spectrum analyzer according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0023] Example 1 This application discloses an in-band flatness compensation method based on a large bandwidth spectrum analyzer.

[0024] Reference Figure 1 A method for in-band flatness compensation based on a high-bandwidth spectrum analyzer, executed by a field-programmable gate array within the spectrum analyzer, includes the following steps: S10. Obtain and optimize the complex compensation coefficient table corresponding to the in-band frequency response of the RF front-end channel filter through the dynamic inner loop calibration and compensation optimization system. S20. Receive the radio frequency signal to be tested, filter the radio frequency signal to be tested through the radio frequency front-end channel filter, and perform analog-to-digital conversion and digital down-conversion processing to form the baseband I / Q data frame to be tested. Specifically, the external RF signal under test enters through the instrument's input port and first undergoes band selection and filtering via the RF front-end channel filter. The filtered analog signal is then sampled by a high-speed ADC (Analog-to-Digital Converter) and converted into a digital signal stream. This digital signal stream is fed into an FPGA (Field-Programmable Gate Array), where it is mixed, filtered, and decimated by a DDC (Digital Down-Conversion Module), ultimately forming a baseband or intermediate frequency (IF) baseband I / Q data frame under test. Each data frame contains a fixed length of I and Q sampling points.

[0025] S30. Window and fast Fourier transform the baseband I / Q data frame to be tested to obtain the spectrum of the signal to be tested; Each frame of I / Q data is first windowed, such as with Hanning or Blackman windows, to reduce spectral leakage. Then, the windowed time-domain I / Q data is fed into the FFT engine to perform a Fast Fourier Transform, obtaining the spectrum X(f) of the signal under test. X(f) is a complex array containing amplitude and phase information for each frequency bin.

[0026] S40. Perform a frequency domain complex multiplication operation on the spectrum of the signal under test and the corresponding complex compensation coefficients in the compensation coefficient table to obtain the compensated signal spectrum; Perform a frequency-point-by-frequency complex multiplication operation on the spectrum X(f) obtained in step S30 and the corresponding coefficient C(f) in the high-resolution complex compensation coefficient table read from the memory.

[0027] That is, for each FFT frequency point index k (corresponding to the physical frequency f) k ),calculate: Y(f k ) = X(f k ) * C(f k ) Among them, C(f) k Based on its high-resolution characteristics, the result can be obtained by looking up a table or by real-time calculation. k The exact corresponding compensation coefficients are obtained. This operation is efficiently performed within the FPGA by a parallel complex multiplier, yielding the compensated signal spectrum Y(f). This operation directly corrects the distortion introduced by the non-flat filter response in the frequency domain.

[0028] S50. Perform an inverse fast Fourier transform on the compensated signal spectrum to output a time-domain I / Q signal after in-band flatness compensation.

[0029] Perform an inverse fast Fourier transform (IFFT) on the compensated spectrum Y(f) to convert it back to the time domain. The output of the IFFT is the time-domain I / Q signal after in-band flatness compensation. This signal has eliminated the effects of the non-ideal in-band frequency response of the RF front-end channel filter, and its amplitude is flatter and its phase linearity is improved.

[0030] Optionally, step S10, obtaining the complex compensation coefficient table corresponding to the in-band frequency response of the RF front-end channel filter, includes: S101. Determine the number of frequency points N required for flatness compensation based on the target compensation accuracy and the bandwidth of the RF front-end channel filter. S102. Generate calibration signals for N discrete frequency points sequentially using a step-sweep frequency method, and feed the calibration signals into the input terminal of the RF front-end channel filter; S103. Process the signal output by the RF front-end channel filter to extract the measured amplitude response value at each swept frequency point; S104. Based on the measured amplitude response values ​​at each frequency point and the preset ideal amplitude response values, calculate the corresponding complex compensation coefficients and store the complex compensation coefficients of all N frequency points to form the complex compensation coefficient table.

[0031] In step S101, N determines the frequency resolution of the compensation coefficient table, directly affecting the precision of the compensation. If N is too small, it cannot accurately characterize the details of the filter's frequency response (especially where the ripple is severe), resulting in a large residual error after compensation; if N is too large, the calibration time increases, and the computation and storage costs increase. The higher the target compensation accuracy requirement, the larger the value of N.

[0032] In one specific embodiment, N is typically determined by the system designer based on a combination of factors including the filter bandwidth BW, the target compensation accuracy ΔA, and the storage and processing capabilities of the FPGA. For example, for a channel with BW = 100 MHz, to achieve a compensation accuracy better than 0.2 dB, N might be chosen as 201 or 401, i.e., a frequency spacing of approximately 0.5 MHz or 0.25 MHz.

[0033] In one embodiment, step S102, the step of sequentially generating calibration signals at N discrete frequency points using a stepped frequency sweep method, includes: The field-programmable gate array (FPGA) controls its internal direct digital frequency synthesizer to generate a digital calibration signal, which is then converted into an analog calibration signal after digital-to-analog conversion.

[0034] Furthermore, the step-sweep frequency method is implemented by updating the frequency control word of the direct digital frequency synthesizer, and the frequency control word satisfies the following formula: FW (k) = FW0 + k * (BW / N); Where k is an integer from 0 to N-1; FW(k) is the frequency control word corresponding to the kth sweep point; BW is the passband bandwidth of the RF front-end channel filter; and FW0 is the control word corresponding to the sweep start frequency.

[0035] The digital calibration signal is generated by the Direct Digital Synthesizer (DDS) module inside the FPGA. DDS offers advantages such as high frequency resolution, fast switching speed, and phase continuity. Stepped frequency sweeps are implemented using an updated frequency control word (FTW). The control logic within the FPGA calculates and updates the DDS's FTW sequentially according to a preset N and the sweep range. The digital sine wave (or cosine wave, used as the I path; the Q path can be set to 0 or generate quadrature components through Hilbert transform) generated by the DDS is converted into an analog calibration signal by a subsequent digital-to-analog converter. This analog signal needs to undergo appropriate conditioning (such as attenuation and amplification) to match the input level requirements of the RF front-end channel filter before being fed into its input.

[0036] In one embodiment, step S103, processing the signal output by the RF front-end channel filter to extract the measured amplitude response value at each swept frequency point, includes: The signal output from the RF front-end channel filter is sequentially subjected to analog-to-digital conversion and digital down-conversion to obtain a baseband I / Q signal sequence; The spectrum of the calibration signal is obtained by windowing and performing a fast Fourier transform on the baseband I / Q signal sequence. For each swept frequency point, the measured amplitude response value at the corresponding frequency point is extracted from the spectrum of the calibration signal.

[0037] The complex compensation coefficients, calculated based on the measured amplitude response values ​​at each frequency point and the preset ideal amplitude response values, include: Calculate the ratio of the ideal value of the amplitude response to the measured value of the amplitude response to obtain the amplitude compensation factor; Based on the phase information of the baseband I / Q signal sequence, calculate the phase offset of the current frequency point relative to the reference frequency point, and take its negative value as the phase compensation factor. The complex compensation coefficient is synthesized from the amplitude compensation factor and the phase compensation factor.

[0038] Specifically, when calculating the amplitude compensation factor, an ideal amplitude response value A is first preset.ideal Typically, to flatten the in-band response, A ideal It can be set to the in-band average gain or the measured gain at a specific reference frequency (such as the center frequency). For each frequency point f k Calculate the amplitude compensation factor A comp (f k ) = A ideal / A measured (f k This factor, if greater than 1, indicates that the amplitude at that frequency point needs to be increased; if less than 1, it indicates that it needs to be attenuated.

[0039] When calculating the phase compensation factor, the target of phase compensation is usually to compensate for the nonlinear phase of the filter (i.e., group delay ripple), so that it presents a linear phase or a fixed phase difference after compensation.

[0040] The instantaneous phase of the single-frequency signal can be calculated from the processed baseband I / Q signal sequence (e.g., by arctan(Q / I)).

[0041] Select a reference frequency point (e.g., f0, usually the start point or center frequency of the frequency sweep), and denot its phase as Φ. measured (f0).

[0042] Calculate the current frequency point f k Phase offset ΔΦ(f) relative to the reference frequency k ) = Φ measured (f k ) -Φ measured (f0). This offset includes the nonlinear phase component introduced by the filter.

[0043] The phase compensation factor is the negative of this offset, i.e., Φ. comp (f k ) = -ΔΦ(f k This means that the compensation operation will apply a reverse phase rotation at that frequency to counteract the phase distortion of the filter.

[0044] Then, complex compensation coefficients are synthesized, combining the amplitude and phase compensation factors into a complex number: C(f k ) = A comp (f k ) * exp(j * Φ comp (f k )). Where j is the imaginary unit, exp(j * Φ comp (f k )) represents a unit complex phasor.

[0045] Finally, press frequency f. kIn ascending order, all calculated C(f) values k The complex numbers (k=0, 1, ..., N-1) are stored in a fast-access memory (such as block RAM or distributed RAM) of the FPGA, forming a lookup table. During storage, each complex number is typically decomposed into two fixed-point numbers, the real part (I) and the imaginary part (Q), for direct use by subsequent frequency-domain complex multiplication modules.

[0046] Optionally, the dynamic inner loop calibration and compensation optimization system performs the following steps: Broadband test signal sequences are generated by controlling the internal direct digital frequency synthesizer through a field-programmable gate array; The test signal sequence can be selectively fed into a standard inner loop calibration path or a full-link calibration path via an RF switch matrix. The standard inner loop calibration path is characterized by the test signal being fed directly to the analog-to-digital converter after digital-to-analog conversion, bypassing the RF front-end channel filter. The full-link calibration path is characterized by the test signal being fed back to the analog-to-digital converter after digital-to-analog conversion, via the RF front-end channel filter. Switch to the standard inner loop calibration path, measure and calculate the inherent frequency response error data of the inner loop calibration path; Switch to the full-link calibration path and measure the overall frequency response data, including the RF front-end channel filter. Error stripping is performed on the overall frequency response measured data based on the inherent frequency response error data to obtain the pure RF front-end channel filter frequency response. Based on the pure RF front-end channel filter frequency response, an initial complex compensation coefficient table is calculated and generated.

[0047] In one specific embodiment, after performing error stripping on the overall frequency response measured data based on the inherent frequency response error data to obtain the pure RF front-end channel filter frequency response, the method further includes: The complex compensation coefficients at each discrete frequency point calculated based on the pure frequency response are subjected to frequency domain smoothing filtering. High-density interpolation is performed on the smoothed discrete coefficients to generate a high-resolution complex compensation coefficient table for the frequency domain complex multiplication operation.

[0048] Specifically, the FPGA controls its internal direct digital frequency synthesizer (DDS) to generate a wideband test signal sequence. This signal needs to cover the entire passband bandwidth (BW) of the filter to be compensated. Preferably, this sequence can be a chirp signal with a frequency that varies linearly with time, whose spectrum is approximately flat within the target bandwidth; or a multi-tone signal synthesized from multiple single-frequency signals uniformly distributed in the frequency domain. An FPGA-controlled RF switch matrix is ​​integrated into the system. This matrix allows the test signal (after being converted to an analog signal by an internal DAC) to be directed to two independent physical paths: Standard Inner Loop Calibration Path: In this path, the switch matrix bypasses the RF front-end channel filter under test (DUT) with the DAC output test signal. The signal is fed back directly to the instrument's analog-to-digital converter (ADC) input through a precisely designed, low-insertion-loss, and frequency-response-flattened through-path or attenuation network. This path characterizes the inherent frequency response error H of the inner loop from "DDS -> DAC -> ADC -> digital processing chain". sys (f) The sources include the amplitude-frequency characteristics of the DAC, the sampling aperture jitter and nonlinearity of the ADC, the insertion loss-frequency characteristics of the analog switch, and the fixed deviations introduced by digital downconversion, filtering and other processing.

[0049] Full-link calibration path: In this path, the switch matrix guides the test signal to the normal signal receiving link, allowing it to pass completely through the RF front-end channel filter under test before being input to the ADC. The frequency response H measured in this path is... total (f) is the true response H of the filter. filter (f) The inherent error H of the above system sys The result of the convolution (product in the frequency domain) of (f).

[0050] In one specific embodiment, error stripping is performed in the digital domain. Assuming the system is a linear time-invariant system, then in the frequency domain: H total (f) = H filter (f) · H sys (f). Therefore, the pure RF front-end channel filter frequency response H filter (f) This can be obtained through complex number division: H filter (f) = H total (f) / H sys (f).

[0051] Specifically, for each discrete frequency point f after FFT k Take H respectively total (f k ) and H sys (fk The complex representation of (real part + imaginary part, or amplitude + phase). Performing complex division, for example in the amplitude-phase domain, yields: Amplitude: |H filter (f k )| = |H total (f k )| / |H sys (f k )| Phase: ∠H filter (f k ) = ∠H total (f k ) - ∠H sys (f k ) This step removes the influence of the measurement system's own imperfect characteristics, so that the subsequent compensation coefficients are only for the filter itself, thus theoretically achieving compensation accuracy close to the measurement system's noise floor.

[0052] Specifically, based on the pure RF front-end channel filter frequency response, an initial complex compensation coefficient table is calculated and generated, including: Based on the extracted pure response H ilter (f) Calculate the initial compensation coefficients according to the preset ideal response (e.g., amplitude flatness of 0 dB, phase linearity). For each frequency point f k : Amplitude compensation factor: A comp _ init (f k ) = A ideal / |H filter (f k )| Phase compensation factor: Φ comp_init (f k ) = - (∠H filter (f k ) - ∠Φ ideal (f k )), where ∠Φ ideal (f k () is a linear phase reference.

[0053] Complex compensation coefficient: C init (f k ) = A comp_init (f k ) * exp(j * Φ comp_init (f k )).

[0054] All C init(f k Store as the initial complex compensation coefficient table.

[0055] Furthermore, after calculating and generating the initial complex compensation coefficient table based on the pure RF front-end channel filter frequency response, the process also includes an iterative optimization step: The initial complex compensation coefficient table is loaded into the signal generation parameters of the direct digital frequency synthesizer in a digital predistortion manner; The direct digital frequency synthesizer is controlled to generate a new test signal sequence, which is then measured again through the second path; Based on the new measurement results and the residual error of the ideal response, the complex compensation coefficient table is optimized and updated in reverse. Repeat the above iterative steps until the residual error is lower than the preset threshold to obtain the final optimized complex compensation coefficient table.

[0056] The obtained initial coefficient table C init (f) The signal generation parameters of the DDS are digitally predistorted. Specifically, when a component with frequency f needs to be generated, the output amplitude and initial phase of the DDS will be determined by C. init (f) Make corrections. For example, if C init If (f) = M * e^(jθ), then when generating the signal at this frequency, its nominal digital amplitude is multiplied by M, and the initial phase is increased by θ. In this way, the generated test signal has theoretically compensated for the filter distortion in advance.

[0057] The RF switch matrix is ​​kept in the full-link calibration path. A broadband test signal sequence similar to that of the S301 is regenerated using a DDS with predistortion parameters and fed into the system for measurement. After the same ADC acquisition and FFT processing, new measured overall frequency response data H are obtained. total_new (f). Then compare the new measurement result H. total_new (f) The expected ideal response H ideal (f) (Typically, this is the all-pass response). Calculate the residual error E. residual (f) = H ideal (f) / H total_new (f).

[0058] Reverse optimization: Update the initial compensation coefficient table based on the residual error. The update rule is: C updated (f) =C init (f) * E residual (f). This is equivalent to making a fine adjustment to address the remaining distortion based on the original compensation.

[0059] The convergence condition for iterative convergence is that iteration stops when the residual error falls below a preset threshold after a certain iteration. The threshold can be set according to system requirements; for example, it may require the root mean square value of the in-band amplitude fluctuation to be less than 0.05 dB, and the maximum fluctuation to be less than 0.1 dB. The resulting compensation coefficient table C... final (f) is the final optimized complex compensation coefficient table, whose compensation accuracy has been verified and improved through closed-loop testing.

[0060] In one specific embodiment, the frequency domain smoothing filtering method is to process C(f k The amplitude and phase sequences of the signal are treated as one-dimensional signals, and a low-pass filter, such as a moving average filter or a Gaussian filter, is applied to them. The bandwidth of the filter should be set wide enough to preserve the true trend of the filter response while filtering out noise components that are much higher than the rate of change of that trend. Smoothing is performed in the frequency domain to ensure the smoothness of the compensation curve.

[0061] In one specific embodiment, since the smoothed coefficient table is still discrete, its frequency resolution is determined by the number of calibration points N. However, in actual compensation, the FFT frequency of the signal under test may not be perfectly aligned with these discrete calibration points. To solve this problem, high-density interpolation is required.

[0062] With the smoothed coefficients of dispersion C smooth (f k As nodes, a high-precision interpolation algorithm (such as cubic spline interpolation or sinc interpolation) is used to generate a high-resolution complex compensation coefficient table with a much larger number of frequency points than N. For example, if the original N=201, a coefficient table containing 2048 or 4096 points can be generated through interpolation.

[0063] Through the steps described above, this high-resolution table allows for the rapid acquisition of a compensation coefficient C that closely approximates the true optimal value for any FFT frequency point f during actual compensation, through a simple table lookup operation. high_res (f) avoids errors introduced by coefficient mismatch and ensures the accuracy and continuity of compensation calculation.

[0064] Example 2 Reference Figure 2This application also discloses an in-band flatness compensation system based on a high-bandwidth spectrum analyzer, comprising: an RF front-end channel filter, an analog-to-digital converter (ADC), a field-programmable gate array (FPGA), and a memory, such as DDR or high-speed RAM; the FPGA is configured to execute the method described. The FPGA, as the core of digital signal processing, typically includes or logically implements: a direct digital frequency synthesizer (DDS) module, a digital down-conversion (DDC) module, a fast Fourier transform (FFT) / inverse fast Fourier transform (IFFT) engine, a complex multiplier, and control logic. The system also includes an FPGA-controlled RF switch matrix for switching signal paths during the calibration phase.

[0065] Example 3 This application also discloses a computer device, including one or more processors and a memory; One or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs being configured to perform the methods described above.

[0066] Example 4 This application also discloses a computer-readable storage medium storing a computer program that can be loaded by a processor and execute the method.

[0067] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a device including one or any combination of the above-mentioned memories. The computer may be a variety of computing devices, including smart terminals and servers.

[0068] In the above embodiments of this disclosure, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0070] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0072] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable non-volatile storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a non-volatile storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned non-volatile storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0073] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for in-band flatness compensation based on a wide bandwidth spectrum analyzer, characterized by, executed by a field programmable gate array in the spectrum analyzer, comprising the following steps: A complex compensation coefficient table corresponding to the in-band frequency response of the radio frequency front-end channel filter is obtained and optimized through a dynamic inner loop calibration and compensation optimization system. A to-be-tested radio frequency signal is received, the to-be-tested radio frequency signal is filtered through the radio frequency front-end channel filter, and analog-to-digital conversion and digital down-conversion processing are performed to form a to-be-tested baseband I / Q data frame. The to-be-tested baseband I / Q data frame is windowed and subjected to fast Fourier transform to obtain a spectrum of the to-be-tested signal. The spectrum of the to-be-tested signal is subjected to frequency domain complex multiplication operation with corresponding complex compensation coefficients in the compensation coefficient table to obtain a compensated signal spectrum. The compensated signal spectrum is subjected to inverse fast Fourier transform to output a time domain I / Q signal subjected to in-band flatness compensation.

2. The compensation method according to claim 1, characterized in that, The complex compensation coefficient table corresponding to the in-band frequency response of the radio frequency front-end channel filter is obtained and optimized through the dynamic inner loop calibration and compensation optimization system, comprising: The number N of frequency points required for flatness compensation is determined according to a target compensation accuracy and a bandwidth of the radio frequency front-end channel filter. Calibration signals of N discrete frequency points are sequentially generated in a step-by-step frequency sweeping manner, and the calibration signals are fed into an input end of the radio frequency front-end channel filter. The signal output by the radio frequency front-end channel filter is processed to extract an amplitude response measured value at each frequency sweeping frequency point. Based on the amplitude response measured value of each frequency point and a preset amplitude response ideal value, corresponding complex compensation coefficients are calculated, and the complex compensation coefficients of all N frequency points are stored to form the complex compensation coefficient table.

3. The compensation method according to claim 2, characterized in that, The step of sequentially generating calibration signals of N discrete frequency points in a step-by-step frequency sweeping manner comprises: A direct digital frequency synthesizer inside the field programmable gate array is controlled to generate a digital calibration signal, and the calibration signal is formed after digital-to-analog conversion.

4. The compensation method according to claim 3, characterized in that, The step-by-step frequency sweeping manner is realized by updating a frequency control word of the direct digital frequency synthesizer, and the frequency control word satisfies the following formula: FW(k) = FW0 + k * (BW / N); wherein k is an integer from 0 to N-1; FW(k) is a frequency control word corresponding to the kth frequency sweeping point; BW is a passband bandwidth of the radio frequency front-end channel filter; and FW0 is a control word corresponding to a frequency sweeping start frequency.

5. The compensation method of claim 2, wherein, The signal output by the radio frequency front-end channel filter is processed to extract an amplitude response measured value at each frequency sweeping frequency point, comprising: The signal output by the radio frequency front-end channel filter is sequentially subjected to analog-to-digital conversion and digital down-conversion processing to obtain a baseband I / Q signal sequence. The baseband I / Q signal sequence is windowed and subjected to fast Fourier transform to obtain a spectrum of the calibration signal. For each frequency sweeping frequency point, an amplitude response measured value at the corresponding frequency point is extracted from the spectrum of the calibration signal.

6. The compensation method according to claim 5, characterized in that, The complex compensation coefficient corresponding to each frequency point is calculated based on the amplitude response measured value of each frequency point and a preset amplitude response ideal value. calculating a ratio of the ideal value of the amplitude response and the measured value of the amplitude response to obtain an amplitude compensation factor; calculating a phase offset of a current frequency point relative to a reference frequency point according to phase information of the baseband I / Q signal sequence, and taking a negative value thereof as a phase compensation factor; synthesizing the complex compensation coefficient from the amplitude compensation factor and the phase compensation factor.

7. The compensation method of claim 1, wherein, The dynamic inner loop calibration and compensation optimization system performs the following steps: controlling a direct digital frequency synthesizer inside a field programmable gate array to generate a wideband test signal sequence; selectively feeding the test signal sequence into a standard inner loop calibration path or a full link calibration path through a radio frequency switch matrix; wherein the standard inner loop calibration path represents a path in which the test signal is converted into an analog signal after digital-to-analog conversion, bypasses the radio frequency front-end channel filter, and is directly fed back to an analog-to-digital converter; and the full link calibration path represents a path in which the test signal is converted into an analog signal after digital-to-analog conversion, passes through the radio frequency front-end channel filter, and is then fed back to the analog-to-digital converter; switching to the standard inner loop calibration path to measure and calculate inherent frequency response error data of the inner loop calibration path; switching to the full link calibration path to measure overall frequency response measured data including the radio frequency front-end channel filter; based on the inherent frequency response error data, error stripping the overall frequency response measured data to obtain a pure radio frequency front-end channel filter frequency response; based on the pure radio frequency front-end channel filter frequency response, calculating and generating an initial complex compensation coefficient table.

8. The compensation method according to claim 7, characterized in that, After the initial complex compensation coefficient table is calculated and generated based on the pure radio frequency front-end channel filter frequency response, an iterative optimization step is further included: loading the initial complex compensation coefficient table into signal generation parameters of the direct digital frequency synthesizer in a digital pre-distortion manner; controlling the direct digital frequency synthesizer to generate a new test signal sequence and measuring again through the second path; based on a residual error between the new measurement result and an ideal response, inversely optimizing and updating the complex compensation coefficient table; repeating the above iterative steps until the residual error is lower than a preset threshold, to obtain a final optimized complex compensation coefficient table.

9. The compensation method according to claim 7 or 8, characterized in that, After the pure radio frequency front-end channel filter frequency response is obtained by error stripping the overall frequency response measured data based on the inherent frequency response error data, the following steps are further included: performing frequency domain smoothing filtering processing on the complex compensation coefficient of each discrete frequency point calculated based on the pure frequency response; performing high-density interpolation on the smoothed discrete coefficient to generate a high-resolution complex compensation coefficient table for the frequency domain complex multiplication operation.

10. A system for in-band flatness compensation based on a wide bandwidth spectrum analyzer, comprising: comprises: a radio frequency front-end channel filter, an analog-to-digital converter, a field programmable gate array, and a memory; the field programmable gate array is configured to perform the method according to any one of claims 1 to 9.

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