Communication sensing type quantum circuit optimization method and system for distributed quantum computing

Abstract

The invention relates to the technical field of quantum computing, and provides a distributed quantum computing-oriented communication sensing type line optimization method and system. The method comprises the following steps: 1, receiving a quantum circuit to be optimized, and confirming the number of quantum bits and the number of quantum bit gates of the quantum circuit to be optimized; 2, based on preset quantum processors, quantum bits in the quantum circuit to be optimized are divided into the quantum processors, and an initial quantum circuit is obtained; and 3, constructing a mixed cost function containing global gate number cost and traditional gate number cost, and searching the quantum circuit with the lowest mixed cost in the equivalent space of the initial quantum circuit as an optimized quantum circuit. According to the method, a quantum bit division scheme is preposed into a fixed optimization background through division first and optimization cooperation, so that the whole line optimization process can actively search lines with better communication overhead under the condition of sensing communication constraints, and the calculation overhead is kept at a reasonable level.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a communication-aware line optimization method and system for distributed quantum computing. Background Technology

[0002] Quantum computing, as a new paradigm for information processing utilizing the properties of quantum mechanics, has demonstrated the potential for exponential speedup compared to classical computers in solving certain complex computational problems. Examples include Shor's algorithm for prime factorization of large numbers, Grover's algorithm for searching unordered databases, and the HHL algorithm for solving systems of linear equations. This enormous potential has made quantum computing a research focus in both academia and industry worldwide in recent years.

[0003] However, the practical development of quantum computing faces severe challenges. Currently, we are in the era of noisy intermediate-scale quantum (NISQ), and existing quantum processing units (QPUs) suffer from a series of limitations, including a limited number of qubits, short coherence time, and high error rates in gate operations and measurements. These limitations cause errors to accumulate during computation, severely impacting the execution fidelity of algorithms and the scalability of individual quantum chips, making it extremely difficult to continue building large-scale, high-performance single-quantum-chip quantum computers.

[0004] To overcome the limitations of NISQ devices in terms of scale and performance, distributed quantum computing (DQC) has been proposed as a promising solution. Its core idea is to interconnect multiple smaller quantum processing units (QPUs) to collaboratively complete large-scale quantum computing tasks, thereby achieving system-level scaling of computing resources. This multi-processor architecture decomposes a problem into multiple QPUs for parallel processing, potentially enabling the construction of quantum computing systems far more powerful than those based on a single chip.

[0005] While distributed architectures offer scalability, they also introduce new challenges: communication between QPUs. Achieving communication between QPUs primarily relies on quantum teleportation. This technique enables the transfer of quantum states between distant QPUs without moving physical particles, but this process depends on pre-shared quantum entanglement resources (such as EPR pairs) and classical communication. Compared to gate operations within a QPU, inter-QPU gate operations require communication, which is time-consuming, resource-intensive, and more prone to introducing errors and noise. Therefore, inter-QPU communication overhead becomes a major bottleneck restricting the overall performance of distributed quantum computing systems. Minimizing the frequency and scale of inter-QPU communication is therefore crucial for optimizing the performance and efficiency of DQC.

[0006] In this context, efficient quantum circuit compilation technology is indispensable. In quantum circuit compilation, circuit generation is responsible for converting high-level quantum algorithms into gate sequences executable by the underlying hardware. Then, circuit optimization reduces metrics such as the total number of quantum gates or circuit depth to improve circuit efficiency. Finally, qubit mapping and routing operations adapt the logic circuit to a quantum chip with a specific topology. Here, we mainly focus on the circuit optimization part. Pattern matching is a commonly used method in circuit optimization. This method first establishes template rules, then scans the quantum circuit to identify and replace matching specific circuit patterns, thereby reducing the target cost of the corresponding circuit while ensuring circuit equivalence. Figure 1 The examples include two simple variations of the rules and an instance of applying the rules under pattern matching. By applying the rules, the number of gates in the circuit was reduced.

[0007] Distributed quantum circuit compilation (DQC) introduces new challenges. Current distributed quantum circuit compilation reduces communication costs through two steps: circuit partitioning and non-local gate processing. In circuit partitioning, qubits are divided into different QPUs, where two-bit gates between different QPUs are identified as global gates. The goal of circuit partitioning is to minimize the number of global gates generated, as fewer global gates generally mean lower communication overhead. Then, non-local gate processing converts the global gates into executable communication operations, merging transmitted information as much as possible during the conversion to reduce the number of transmissions. Figure 2 This demonstrates an example of distributed quantum circuit partitioning. The qubits are divided into two partitions: the first partition contains the qubits... q 1 and q 2. The second one contains qubits. q 3 and q 4. The red dotted door spanning two partitions here is a global door.

[0008] In summary, in distributed quantum computing scenarios, the typical compilation process for distributed quantum circuits is as follows: first, the input quantum circuit is optimized using traditional methods (e.g., aiming to reduce the total number of quantum gates), or even without optimization; then, the circuit is partitioned to obtain the partition with the minimum number of global gates; finally, the global gates are converted into specific non-local gate operations. This "optimize first, then partition" process has a fundamental problem: the circuits input to the distributed compiler do not consider the fact that they will be partitioned later during the optimization phase, causing the existing distributed circuit compilation to deviate from the scheme with the lowest communication overhead from the very beginning. Summary of the Invention

[0009] To address the problem that existing quantum circuit compilation processes do not consider the subsequent partitioning of qubits in the initial stage, causing distributed circuit compilation to deviate from the goal of minimizing communication overhead from the outset, this invention proposes a communication-aware circuit optimization method and system for distributed quantum computing. Through the paradigm of "partitioning first, optimization in tandem," the qubit partitioning scheme is placed as a fixed optimization background in advance, enabling the entire circuit optimization process to actively search for circuits with better communication overhead under the condition of being aware of communication constraints, while maintaining the computational overhead at a reasonable level.

[0010] In a first aspect, the present invention provides a communication-aware line optimization method for distributed quantum computing, comprising: Step 1: Receive the quantum circuit to be optimized and confirm the number of qubits and the number of qubit gates of the quantum circuit to be optimized; Step 2: Based on the preset quantum processor, divide the qubits in the quantum circuit to be optimized into each quantum processor to obtain the initial quantum circuit; Step 3: Construct a hybrid cost function that includes the cost of global gates and the cost of traditional gates. Search for the quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit as the optimized quantum circuit.

[0011] Further, in step 2, the qubits in the quantum circuit to be optimized are divided into various quantum processors, specifically including: treating the quantum circuit to be optimized as a graph, where the quantum circuit is the node, the qubit gate is the edge, and the number of qubit gates is the edge weight; dividing the graph using the Metis algorithm, and assigning the qubits corresponding to the same node in the partitioned graph to the same quantum processor.

[0012] Furthermore, in step 3, the formula for the hybrid cost function is as follows: C mix= α ⋅ C total+ β ⋅C global in, C "mix" represents the cost of mixing. α and β Indicates hyperparameters, C global represents the number of global gates. C total represents the total number of qubit gates; In the formula, C global=|𝔾 global | Among them, 𝔾 global This represents the global gate set.

[0013] Furthermore, in step 3, a beam search algorithm is used to search for the quantum circuit with the lowest mixing cost in the equivalent space of the initial quantum circuit.

[0014] Furthermore, the aforementioned use of the beam search algorithm to search for the quantum circuit with the lowest mixing cost in the equivalent space of the initial quantum circuit specifically includes: Step 3.1: Place the initial quantum circuit into a priority queue as the best circuit, and add the hash value of the initial quantum circuit to a hash table; Step 3.2: Select the quantum circuit with the lowest mixing cost from the priority queue, apply the rules in the set of qubit gate transformation rules to the quantum circuit to generate a new quantum circuit. If the new quantum circuit is valid and its hash value is not in the hash table, calculate the mixing cost of the new quantum circuit using the mixing cost function; if the new quantum circuit is invalid or its hash value is in the hash table, proceed to step 3.2. Step 3.3: Verify whether the hybrid cost is less than the optimal cost constraint. If it is less, add the new quantum circuit to the priority queue and record the hash value of the new quantum circuit in the hash table. If it is greater, proceed to step 3.2. Step 3.4: If the mixing cost of the new quantum circuit is lower than that of the optimal circuit, then update the new quantum circuit to the optimal circuit; Step 3.5: Repeat steps 3.2 to 3.4 until all quantum circuits in the priority queue generate new quantum circuits that no longer satisfy the optimal cost constraint.

[0015] Secondly, the present invention provides a communication-aware line optimization system for distributed quantum computing, comprising: A quantum circuit receiving unit is used to receive the quantum circuit to be optimized and to confirm the number of qubits and the number of qubit gates of the quantum circuit to be optimized. The quantum circuit partitioning unit is used to partition the qubits in the quantum circuit to be optimized into various quantum processors based on a preset quantum processor, so as to obtain the initial quantum circuit. The quantum circuit optimization unit is used to construct a hybrid cost function that includes the global gate quantity cost and the traditional gate quantity cost, and to search for the quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit as the optimized quantum circuit.

[0016] Thirdly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as described in the first aspect.

[0017] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0018] The beneficial effects of this invention are as follows: The method provided by this invention directly reduces the number of quantum teleportations required for distributed execution by actively optimizing and reducing the number of global gates, significantly reducing communication overhead and improving the performance of distributed quantum computing systems. Furthermore, this invention does not blindly increase the total number of gates at the expense of reduced communication; the proposed cost function... C The `total` term ensures the optimization direction while maintaining computational efficiency, thus avoiding resource waste. Because the optimization process pre-considers partitioning, the inherent partition-friendly nature of the final output circuit, after mapping, makes it easier to obtain partitioning schemes with fewer global gates, resolving the core contradiction between the optimization results and partitioning objectives of traditional methods. The method of this invention does not depend on specific circuit structures or algorithm categories and has been verified as effective on various quantum algorithms, including arithmetic circuits, multipliers, and Toffoli gates. Attached Figure Description

[0019] Figure 1 The circuit optimization diagram provided in the background of this invention; Figure 2 A schematic diagram of distributed quantum circuit partitioning is provided for the background technology of this invention; Figure 3 A flowchart illustrating a communication-aware line optimization method for distributed quantum computing, provided as an embodiment of the present invention; Figure 4 A flowchart illustrating the beam search algorithm provided in an embodiment of the present invention; Figure 5The parameter variation diagrams for different quantum circuit optimization processes provided in the embodiments of the present invention are shown; where (a) represents the gf2^4_mult circuit, (b) represents the mod_red_21 circuit, (c) represents the barenco_tof_4 circuit, and (d) represents the csla_mux_3 circuit. Figure 6 This is a normalized graph showing the changes in the number of global gates for different lines under different partitioning methods provided in this embodiment of the invention. Figure 7 A schematic diagram of a communication-aware line optimization system for distributed quantum computing provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0021] like Figure 3 As shown, this embodiment of the invention provides a communication-aware line optimization method for distributed quantum computing, including: S101: Receive the quantum circuit to be optimized and confirm the number of qubits and the number of qubit gates of the quantum circuit to be optimized; Specifically, define a containing n qubits and m A quantum circuit with n quantum gates, containing only single-qubit and two-qubit gates. This quantum circuit is represented as 𝒞=(ℚ, 𝔾), where ℚ = { q 1, q 2, ..., q n} is the set of qubits, and 𝔾={ g 1, g 2, ..., g m} is a set of quantum gates, where the quantum gates in} are either single-qubit gates or two-qubit gates.

[0022] S102: Based on the preset quantum processor, the qubits in the quantum circuit to be optimized are divided into various quantum processors to obtain the initial quantum circuit; Specifically, when a quantum circuit is partitioned, qubits are assigned to specific QPUs. A two-qubit gate operating on different QPUs is called a global gate. Implementing a global gate requires more resources. Therefore, for a quantum circuit, finding a circuit partition that contains fewer global gates is important. Here, a circuit partition is defined as a qubit mapping 𝒫 that maps logical qubits to their corresponding QPUs: 𝒫: Q →{1, 2, ... , k}, in k This refers to the number of QPUs. The initial partitioning setting is equivalent to determining the mapping of a qubit, and different mapping results can be set for different application scenarios.

[0023] S103: Construct a hybrid cost function that includes the cost of global gates and the cost of traditional gates, and search for the quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit as the optimized quantum circuit.

[0024] The quantum circuit optimization method provided in this invention breaks away from the traditional serial compilation process of "optimize first, then partition," and adopts a paradigm of "partitioning linearly and optimizing collaboratively." It establishes an open, multi-layered optimization framework that can be easily extended to complex distributed architectures with more than two QPUs for quantum circuit optimization. During each cost assessment in the optimization phase, the number of global gates in the partitioning phase is used as a basis, enabling "predictability" of the final communication overhead during the optimization process. This allows for proactive selection of circuit transformations that are more conducive to partitioning.

[0025] Based on the above embodiments, this invention provides specific steps for partitioning. Specifically, the qubits in the quantum circuit to be optimized are partitioned into various quantum processors. This includes: treating the quantum circuit to be optimized as a graph, where the quantum circuits are nodes, qubit gates are edges, and the number of qubit gates is the edge weight; partitioning the graph using the Metis algorithm; and partitioning the qubits corresponding to the same node in the partitioned graph into the same quantum processor.

[0026] It is understood that this embodiment provides steps for quantum circuit partitioning using the Metis algorithm. It should be noted that this invention offers flexibility in the partitioning phase, supporting multiple partitioning initialization strategies: it can employ graph-based partitioning algorithms (such as Metis) to construct a weighted graph based on the frequency of dual-gate operations between qubits, or it supports simple rule-based strategies (such as evenly distributing according to qubit index order). The partitioning result remains constant throughout the optimization process, ensuring that all circuits are compared under a unified communication cost evaluation criterion.

[0027] Based on the above embodiments, this invention provides a hybrid cost function model, the formula of which is shown below: C mix= α ⋅ C total+ β ⋅ C global in, C "mix" represents the cost of mixing. C global represents the number of global gates. C total represents the total number of qubit gates, which is a traditional metric for computational complexity. α and β The hyperparameters represent the trade-off between the total number of gates and the global number of gates by precisely balancing the proportion of computational and communication overhead in the overall cost. The parameter values ​​can be dynamically adjusted according to the actual characteristics of the target hardware platform (such as the ratio of single-gate operation time to single-transfer time), thus establishing the priority of communication optimization in distributed computing from a cost model perspective. The core issue of this invention is whether it is possible to reduce... C Global while preventing C A significant increase in total.

[0028] In the formula, C global=|𝔾 global | Among them, 𝔾 global Denotes the global gate set, 𝔾 global = { g i ∈ 𝔾| g i It is an effect in q a and q b Two-bit gate and 𝒫( q a ) ≠𝒫( q b )};For example, Figure 2 The set of global gates for the middle circuit. global yes{ g 8, g 10 , g 14 , g 16}, corresponding C The global value is 4.

[0029] It is understandable that the hybrid cost function presented in this embodiment serves as the hybrid optimization objective in the optimization phase, and proposes to include the number of global gates ( C Global is one of the core optimization metrics, and is compared with the traditional number of gates (Gate number). C The total cost function is weighted and combined to form a hybrid cost function specifically designed for distributed quantum computing. C This is the fundamental feature that distinguishes it from all traditional single-machine optimizers.

[0030] Based on the above embodiments, in order to minimize C mix, such as Figure 4 As shown, this embodiment of the invention provides that in the optimization stage of S103, a beam search algorithm is used to search for the quantum circuit with the lowest mixing cost in the equivalent space of the initial quantum circuit, specifically including: S103.1: Add the initial quantum circuit C0 to the priority queue. Q In the process, the optimal route is selected, and the hash value of the initial quantum route is added to the hash table. D seen.

[0031] This step can be understood as the initial stage in the beam search algorithm, where the initial line C0 is pushed into the priority queue. Q And add its hash value to the hash table. D Seen in the middle. The hash table here. D The `seen` option is used to record the hash values ​​of all explored routes to prevent redundant calculations.

[0032] S103.2: Select the quantum circuit with the lowest mixing cost from the priority queue. C The rules in the qubit gate transformation rule set 𝜒 xfer Application in this quantum circuit C The above generates new quantum circuits C new If new quantum circuits C new Valid and its hash value is not in the hash table D In the seen model, new quantum circuits are calculated using a hybrid cost function. C new The mixed costs; if new quantum circuits C new Invalid or its hash value in the hash table D If seen, then S103.2 is executed. It should be noted that the qubit gate transformation rule set 𝜒 is an existing set of rules for optimizing quantum circuits in this field, and will not be elaborated here.

[0033] S103.3: Verify whether the hybrid cost is less than the optimal cost constraint. γ · Cmix(C best If it is less than 1, then the new quantum circuit will be used. C new Add to priority queue Q and new quantum circuits C new The hash value is recorded in a hash table; if it is greater than γ, then S103.2 is executed. Here, γ is a hyperparameter controlling the exploration of the search space; if... γ =1, the algorithm performs a search constrained by strict cost-reduction transformation rules. In this embodiment, γ The value is set to 1.05 to expand the equivalent line search space.

[0034] S103.4: If a new quantum circuit is introduced C new Hybrid costs are lower than the optimal route C best This will lead to the new quantum circuit. C new Updated to the best route C best .

[0035] S103.5: Repeat steps S103.2 to S103.4 until all quantum circuits in the priority queue generate new quantum circuits that no longer meet the optimal cost constraint.

[0036] Specifically, this embodiment employs a beam search algorithm to search for the optimal route among equivalent routes within a pattern matching structure. Pattern matching is a commonly used method in route optimization. This method first establishes template rules, then identifies and replaces specific matching route patterns by scanning quantum circuits, thereby reducing the corresponding target cost of the route while ensuring route equivalence.

[0037] To verify the effectiveness of the method provided by this invention, the following experiment was conducted in this embodiment. First, in this embodiment, the corresponding parameters were set to... α =1, β =25, these values ​​are based on the time delay settings for the master gate and the global gate. γ The value is set to 1.05 to expand the equivalent circuit search space. The maximum search time is 24 hours. Table 1 shows the optimization results of the proposed architecture under different circuits. For each circuit, the following information is provided: number of qubits; original and global gate counts; optimized counts; and the corresponding gate reduction rate. As shown in Table 1, the method of the present invention achieves significant improvements in both the number of gates and the number of global gates. For all circuits, the optimized gate count is reduced by an average of 16.89%, and the optimized global gate count is reduced by an average of 31.24%. This demonstrates the effectiveness of the present invention in optimizing circuits for distributed quantum computing.

[0038] Table 1 Optimization results of the optimized framework instance To verify the necessity of the hybrid objective function, the optimization objective in the framework was replaced with the total number of gates, the global number of gates, and optimizing the total number of gates first and then the global number of gates, with the parameter settings remaining the same as above. Table 2 shows the comparison results under the example. From the perspective of average optimization rate, optimizing only... C total The results significantly reduced the total number of gates, and due to the reduction in the total number of gates, the number of global gates also decreased slightly. However, optimizing only... C global At this time, the number of global gates decreases, but the total number of gates increases. Two-stage optimization significantly reduces the number of global gates, but only slightly reduces the total number of gates. C mix The optimization results ideally reduce the total number of gates and the global number of gates. Comparison of optimization results with different cost functions shows that a hybrid cost function is necessary for circuit optimization in distributed quantum computing.

[0039] Table 2 Comparison of optimization results under different optimization objectives exist Figure 5 In the example, the parameter changes of four typical lines during the optimization process are shown. In each subgraph, x The axis represents the total number of doors. y The axes represent the total number of global gates. Each point represents the total number of gates and the total number of global gates for the optimal route locked by the current search algorithm. The route located in the lower left corner of the graph is better. For each route, the intersection point of the four paths represents the initial route before optimization. Only optimization is performed. C total The path shows that the total number of quantum gates in the optimal path gradually decreases as optimization progresses. Simultaneously, the global gate count also has a high probability of decreasing. Only optimization... C global In the path optimization, as the number of global gates for the optimal route decreases, the total number of gates increases. The two-stage optimization scheme combines the characteristics of the previous two schemes that optimize a single metric. The hybrid cost function... C mix The optimization path demonstrates the ideal optimization trajectory, in which C total and C global The optimization results show better performance compared to other objective functions, further demonstrating the necessity of a hybrid cost function.

[0040] Furthermore, the impact of partition initialization on the optimization results was evaluated by replacing the Metis partitioning in the instance with a brute-force initialization method. The hyperparameter selection remained the same as above. Table 3 shows the optimization results of the instance under brute-force initialization, demonstrating that the average optimization rate of the circuit under brute-force initialization is similar to that under the Metis partitioning case, reflecting the robustness of the framework.

[0041] Table 3 Optimization results under brute-force initial partitioning The changes in the number of global gates for different lines under Metis partitioning and brute-force partitioning are normalized by dividing the value of the global gates under both partitioning and brute-force partitioning by the initial number of global gates under brute-force partitioning. The comparison results are shown below. Figure 6 As can be seen, the optimized Metis partitioning result also has a lower number of global gates. However, due to the substitutability of the initialization method within the framework, the framework's effectiveness can be maintained for a longer period by replacing it with the latest partitioning method.

[0042] like Figure 7 As shown, this embodiment of the invention also provides a communication-aware line optimization system for distributed quantum computing, comprising: A quantum circuit receiving unit is used to receive the quantum circuit to be optimized and to confirm the number of qubits and the number of qubit gates of the quantum circuit to be optimized. The quantum circuit partitioning unit is used to partition the qubits in the quantum circuit to be optimized into various quantum processors based on a preset quantum processor, so as to obtain the initial quantum circuit. The quantum circuit optimization unit is used to construct a hybrid cost function that includes the global gate quantity cost and the traditional gate quantity cost. It searches for the quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit, and uses it as the optimized quantum circuit.

[0043] It should be noted that the communication-aware line optimization system for distributed quantum computing provided in this embodiment of the invention is for implementing the above method. Its specific functions can be referred to in the above method embodiments, and will not be repeated here.

[0044] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8As shown, the electronic device may include a processor 801, a communications interface 802, a memory 803, and a communication bus 804. The processor 801, communications interface 802, and memory 803 communicate with each other via the communication bus 804. The processor 801 can call logical instructions in the memory 803 to execute a communication-aware circuit optimization method for distributed quantum computing, which includes steps S101-S103 of the above embodiments.

[0045] Furthermore, when the logical instructions in the aforementioned memory 803 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0046] This invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the communication-aware line optimization method for distributed quantum computing provided in the above-described method embodiments, including steps S101 to S103 of the above embodiments.

[0047] This invention also provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the communication-aware line optimization method for distributed quantum computing provided in the above-described method embodiments, including steps S101 to S103 of the above embodiments.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication-aware routing optimization method for distributed quantum computing, characterized in that, Comprising: Step 1: receiving a quantum circuit to be optimized, and confirming the number of quantum bits and the number of quantum bit gates in the quantum circuit to be optimized; Step 2: based on a preset quantum processor, dividing the quantum bits in the quantum circuit to be optimized into each quantum processor to obtain an initial quantum circuit; Step 3: constructing a hybrid cost function including a global gate number cost and a traditional gate number cost, searching for a quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit as the optimized quantum circuit.

2. The communication-aware link optimization method for distributed quantum computing according to claim 1, wherein, In step 2, the quantum bits in the quantum circuit to be optimized are divided into each quantum processor, specifically including: taking the quantum circuit to be optimized as a graph, wherein the quantum circuit is taken as a node, the quantum bit gate is taken as an edge, and the number of quantum bit gates is taken as the weight of the edge; the graph is divided by using a Metis algorithm, and the quantum bits corresponding to the same point in the divided result graph are divided into the same quantum processor.

3. The communication-aware link optimization method for distributed quantum computing according to claim 1, wherein, In step 3, the hybrid cost function formula is as follows: C mix= α ⋅ C total+ β ⋅ C global wherein, C mix denotes a mixing cost, α and β denotes a hyperparameter, C global denotes a number of global gates, C total denotes a total number of qubit gates; In the formula, C global = | G global | wherein, G global denotes the global gate set.

4. The communication-aware link optimization method for distributed quantum computing according to claim 1, wherein, In step 3, a beam search algorithm is used to search for a quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit.

5. The communication-aware link optimization method for distributed quantum computing according to claim 4, wherein, The beam search algorithm used to search for a quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit specifically includes: Step 3.1: placing the initial quantum circuit into a priority queue as the best circuit, and adding the hash value of the initial quantum circuit to a hash table; Step 3.2: selecting a quantum circuit with the smallest hybrid cost from the priority queue, applying a rule in a quantum bit gate transformation rule set to the quantum circuit to generate a new quantum circuit, if the new quantum circuit is valid and its hash value is not in the hash table, calculating the hybrid cost of the new quantum circuit by the hybrid cost function; if the new quantum circuit is invalid or its hash value is in the hash table, step 3.2 is executed; Step 3.3: verifying whether the hybrid cost is less than the best cost constraint, if yes, adding the new quantum circuit to the priority queue, and recording the hash value of the new quantum circuit in the hash table, if no, step 3.2 is executed; Step 3.4: if the hybrid cost of the new quantum circuit is lower than that of the best circuit, updating the new quantum circuit as the best circuit; Step 3.5: repeating steps 3.2 to 3.4 until the new quantum circuits generated by all quantum circuits in the priority queue no longer satisfy the best cost constraint.

6. A communication-aware routing optimization system for distributed quantum computing, characterized in that, Comprising: A quantum circuit to be optimized receiving unit is configured to receive a quantum circuit to be optimized, and confirm the number of quantum bits and the number of quantum bit gates in the quantum circuit to be optimized; A quantum circuit to be optimized dividing unit is configured to divide the quantum bits in the quantum circuit to be optimized into each quantum processor based on a preset quantum processor to obtain an initial quantum circuit; A quantum circuit to be optimized optimizing unit is configured to construct a hybrid cost function including a global gate number cost and a traditional gate number cost, and search for a quantum circuit with the lowest hybrid cost in the equivalence space of the initial quantum circuit as the optimized quantum circuit.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the method of any one of claims 1 to 5 when executing the program.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the method of any one of claims 1 to 5 when executed by a processor.

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