Signal de-bouncer against power supply jitter

Abstract

The application provides an anti-power-jitter signal de-bouncing circuit, which comprises a signal delay circuit, a power-on protection circuit, an output buffer circuit and an interference detection circuit. When the power supply produces a momentary drop disturbance and returns to a normal state, the voltage states of the input signal, the first output signal and the second output signal cannot be kept synchronous. The interference detection circuit can detect the level state inversion of one of the input signal, the first output signal and the second output signal. The generated control signal controls the voltage of the corresponding circuit node of the signal shaping link of the output buffer circuit to be pulled up to the positive rail voltage of the power supply or pulled down to the negative rail voltage of the power supply, so that the level state of the third output signal is maintained as the previous level state and is not affected by the power supply noise disturbance, thereby ensuring the robustness of the system.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a signal dejittering circuit that resists power supply jitter. Background Technology

[0002] Signal debouncing circuits are commonly used analog unit circuits. In noisy environments, short-term large fluctuations in the input signal can lead to system malfunctions. To improve system robustness, critical signals are debounced using debouncing circuits, allowing the system to function normally even when the input signal is abnormally interfered with. However, in operating environments with significant power supply noise and jitter, even if the input signal remains unchanged, large jumps in the positive and negative rails of the power supply can cause the output signal of the debouncing circuit to produce an incorrect state, leading to system malfunctions or even failure. Summary of the Invention

[0003] This invention provides a signal de-jittering circuit that is resistant to power supply jitter. The aim is to ensure that the output signal of the signal de-jittering circuit is not interfered with by power rail noise and remains a valid signal even when the positive and negative rails of the system power supply experience high-frequency, large-amplitude fluctuations.

[0004] To solve the above-mentioned technical problems, the present invention provides a signal de-jitter circuit, which includes:

[0005] A signal delay circuit is used to shape and delay the input signal to obtain the first output signal;

[0006] A power-on protection circuit is used to buffer the first output signal to obtain a second output signal. The power-on protection circuit is connected to a power supply and is used to control the charging and discharging of the first output signal during the power-on phase of the power supply, so that the level of the second output signal is maintained at the level of the input signal.

[0007] An output buffer circuit has a signal shaping link, which performs shaping and buffering processing on the second output signal to output a third output signal;

[0008] An interference detection circuit is used to generate a control signal based on the input signal, the first output signal, and the second output signal; when the level state of one of the input signal, the first output signal, and the second output signal flips, the control signal controls the voltage of at least one circuit node of the signal shaping link to be pulled up to the positive rail voltage of the power supply or pulled down to the negative rail voltage of the power supply, so that the level state of the third output signal remains unchanged.

[0009] Optionally, the signal delay circuit includes an inverter chain and an RC delay unit connected to the inverter chain.

[0010] Optionally, the signal delay circuit includes a first inverter, a second inverter, a first resistor, and a first capacitor. The input terminal of the first inverter is connected to the input signal, the output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the negative rail of the power supply through the first capacitor, and the second terminal of the first resistor outputs the first output signal.

[0011] Optionally, the power-on protection circuit includes a first pull-up switch, a first pull-down switch, a first buffer, and a logic control unit; the input terminal of the first buffer is connected to the first output signal, the output terminal of the first buffer outputs the second output signal, the first terminal of the first pull-up switch is connected to the positive rail of the power supply, the second terminal of the first pull-up switch is connected to the input terminal of the first buffer, the first terminal of the first pull-down switch is connected to the input terminal of the first buffer, the second terminal of the first pull-down switch is connected to the negative rail of the power supply, and the control terminals of the first pull-up switch and the first pull-down switch are both connected to the logic control unit. The logic control unit controls one of the first pull-up switch and the first pull-down switch to be turned on according to the second output signal.

[0012] Optionally, the logic control unit includes a first NAND gate and a first NOR gate. The first input terminal of the first NAND gate and the first input terminal of the first NOR gate are connected. The second input terminal of the first NAND gate and the second input terminal of the first NOR gate are both connected to the second output signal. The output terminal of the first NAND gate is connected to the control terminal of the first pull-up switch, and the output terminal of the first NOR gate is connected to the control terminal of the first pull-down switch.

[0013] Optionally, the first pull-up switch is a PMOS transistor, and the first pull-down switch is an NMOS transistor.

[0014] Optionally, the output buffer circuit includes a second NAND gate, a third inverter, a fourth inverter, a fifth inverter, and a second buffer connected in series to form the signal shaping link, and the control signal includes a first control signal, a second control signal, a third control signal, and a fourth control signal;

[0015] The first input terminal of the second NAND gate is connected to the second output signal, and the second input terminal of the second NAND gate is connected to the first control signal. The second control signal is used to control the voltage of the circuit node between the output terminal of the second NAND gate and the input terminal of the third inverter to be pulled down to the negative rail voltage of the power supply.

[0016] The circuit node between the output terminal of the third inverter and the input terminal of the fourth inverter is connected to the positive rail of the power supply via a second capacitor and to the negative rail of the power supply via a third capacitor. The third control signal is used to control the voltage of the circuit node between the output terminal of the third inverter and the input terminal of the fourth inverter to be pulled down to the negative rail of the power supply.

[0017] The circuit node between the output of the fifth inverter and the input of the second buffer is connected to the negative rail of the power supply via a fourth capacitor. The fourth control signal is used to control the voltage of the circuit node between the output of the fifth inverter and the input of the second buffer to be pulled up to the positive rail voltage of the power supply.

[0018] Optionally, the output buffer circuit further includes a second pull-up switch, a second pull-down switch, and a third pull-down switch;

[0019] Optionally, the first end of the second pull-down switch is connected to the circuit node between the output of the second NAND gate and the input of the third inverter, the second end of the second pull-down switch is connected to the negative rail of the power supply, and the second control signal controls the on / off state of the second pull-down switch.

[0020] Optionally, the first end of the third pull-down switch is connected to the circuit node between the output terminal of the third inverter and the input terminal of the fourth inverter, the second end of the third pull-down switch is connected to the negative rail of the power supply, and the third control signal controls the on / off state of the third pull-down switch.

[0021] Optionally, the first end of the second pull-up switch is connected to the positive rail of the power supply, the second end of the second pull-up switch is connected to the circuit node between the output of the fifth inverter and the input of the second buffer, and the fourth control signal controls the on / off state of the second pull-up switch.

[0022] Optionally, the second pull-up switch is a PMOS transistor, and the second pull-down switch and the third pull-down switch are both NMOS transistors.

[0023] Optionally, the interference detection circuit includes a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a third NAND gate, an OR gate, a third NOR gate, and an AND gate; the input terminal of the sixth inverter and the first input terminal of the third NOR gate are connected to the first output signal, the output terminal of the sixth inverter is connected to the second input terminal of the third NAND gate, the first input terminal of the third NAND gate is connected to the second output signal, the output terminal of the third NAND gate is connected to the first input terminal of the OR gate, the second input terminal of the OR gate is connected to the input signal, the output terminal of the OR gate outputs the first control signal, the input terminal of the eighth inverter is connected to the input terminal of the OR gate, and the output terminal of the eighth inverter outputs the third control signal; the input terminal of the seventh inverter is connected to the second output signal, the output terminal of the seventh inverter is connected to the second input terminal of the third NOR gate, the output terminal of the third NOR gate is connected to the second input terminal of the AND gate, the output terminal of the AND gate outputs the second control signal, the input terminal of the ninth inverter is connected to the output terminal of the AND gate, and the output terminal of the ninth inverter outputs the fourth control signal.

[0024] In the aforementioned signal debouncing circuit, when the power supply experiences a momentary dip and returns to normal, the voltage states of the input signal, the first output signal, and the second output signal cannot remain synchronized. The interference detection circuit can detect the level state flip of either the first or second output signal. The generated control signal will control the voltage of the corresponding circuit node in the signal shaping link of the output buffer circuit to be pulled up to the positive rail voltage or pulled down to the negative rail voltage of the power supply, ensuring that the level state of the third output signal remains at its previous level state, unaffected by power supply noise disturbances, thus ensuring the robustness of the system. Attached Figure Description

[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0026] Figure 1 This is a schematic diagram of a debouncing circuit in the prior art.

[0027] Figure 2 This is a waveform diagram of the power rail disturbance signal and the output signal in a debouncing circuit in the prior art.

[0028] Figure 3 This is a schematic diagram of a signal de-jittering circuit according to an embodiment of the present invention.

[0029] Figure 4 This is a schematic diagram of an interference detection circuit according to an embodiment of the present invention.

[0030] Figure 5This is a waveform diagram of the power rail disturbance signal and the circuit output signal in a signal debouncing circuit according to an embodiment of the present invention.

[0031] In the attached image:

[0032] 100 - Signal delay circuit; INV1 - First inverter; INV2 - Second inverter; R1 - First resistor; C1 - First capacitor;

[0033] 101 - Power-on protection circuit; MP1 - First pull-up switch transistor; MN1 - First pull-down switch transistor; BUF1 - First buffer; NAND1 - First NAND gate; NOR1 - First NOR gate;

[0034] 102 - Interference detection circuit; INV6 - Sixth inverter; INV7 - Seventh inverter; INV8 - Eighth inverter; INV9 - Ninth inverter; NAND3 - Third NAND gate; OR2 - OR gate; NOR3 - Third NOR gate; AND - AND gate;

[0035] 103 - Output buffer circuit; NAND2 - Second NAND gate; INV3 - Third inverter; INV4 - Fourth inverter; INV5 - Fifth inverter; BUF2 - Second buffer; MP2 - Second pull-up switch; MN2 - Second pull-down switch; MN3 - Third pull-down switch. Detailed Implementation

[0036] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0037] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] Figure 1 This is a schematic diagram of a debouncing circuit in the prior art. (See attached image.) Figure 1 The debouncing circuit includes an inverter INV0, a ​​CMOS inverter composed of an NMOS transistor Q2 and a PMOS transistor Q1, and a resistor R. deg and capacitor C deg The system consists of an RC delay unit and a hysteresis buffer BUF0. The working principle is as follows: the input signal Vin is shaped by an inverter INV0 and a CMOS inverter, then delayed by the RC delay unit to output the Vcap signal. Finally, the Vcap signal is hystereted and shaped by the hysteresis buffer BUF0 to output the Vout signal. This achieves debouncing of the input signal Vin.

[0039] Traditional debouncing circuits are suitable for use in systems with relatively stable power supplies. However, when the power supply noise of the debouncing circuit is high, it may produce incorrect outputs, which will lead to a decrease in the robustness of the system. Figure 2This is a waveform diagram of the power rail disturbance signal and the output signal in a debouncing circuit of the prior art. The power rail disturbance signal, that is, the positive or negative rail voltage of the power supply, shows a large fluctuation. (See reference...) Figure 2 When the positive rail voltage VDD of the power supply experiences a large fluctuation, if the input signal Vin is high at this time, Vin will follow the change in VDD. Because the charge stored in the Vcap signal during the power supply fluctuation will discharge during the VDD drop, the amplitude (voltage amplitude) of the Vcap signal decreases. When VDD returns to normal, the Vcap signal fails to return to its pre-drop high level in time, causing the subsequent hysteresis buffer BUF0 to misinterpret Vcap as low. This results in a change in the state of the output signal Vout, causing system malfunction. Similarly, when the negative rail GND of the power supply experiences a strong disturbance, the state of Vout will change similarly.

[0040] In view of this, one embodiment of the present invention provides a signal de-jittering circuit that is resistant to power supply jitter. Under the condition that the positive and negative rails of the system power supply generate high-frequency large-amplitude fluctuations, the output signal of the signal de-jittering circuit will not be interfered with by power rail noise and will still be output as a valid signal.

[0041] Figure 3 This is a schematic diagram of a signal de-jitter circuit according to an embodiment of the present invention. Figure 4 This is a schematic diagram of an interference detection circuit according to an embodiment of the present invention. (See attached diagram.) Figure 3 and Figure 4This invention schematically provides a signal debouncing circuit, including a signal delay circuit 100, a power-on protection circuit 101, an output buffer circuit 103, and an interference detection circuit 102. The signal delay circuit 100 shapes and delays the input signal Vin to obtain a first output signal Vcap, thus achieving debouncing and delay processing of the input signal Vin. The power-on protection circuit 101 buffers the first output signal Vcap to obtain a second output signal Vset. The power-on protection circuit 101 is connected to a power supply and is used to control the charging and discharging of the first output signal Vcap during the power-on phase, ensuring that the level of the second output signal Vset remains the same as the level of the input signal Vin. Therefore, during the process of the power supply's positive rail voltage rising from zero to VDD (within a time range of several microseconds to tens of microseconds), the charging and discharging control of the first output signal Vcap by the power-on protection circuit 101 ensures that the level of the second output signal Vset does not erroneously flip. The output buffer circuit 103 has a signal shaping link that shapes and buffers the second output signal Vset to output the third output signal Vout. The interference detection circuit 102 is used to detect the respective states of the input signal Vin, the first output signal Vcap, and the second output signal Vset, and to generate a control signal based on the input signal Vin, the first output signal Vcap, and the second output signal Vset. When the level state of one of the input signal Vin, the first output signal Vcap, and the second output signal Vset flips, the control signal controls the voltage of at least one circuit node of the shaping link to be pulled up to the positive rail voltage VDD or pulled down to the negative rail voltage GND of the power supply, so that the level state of the third output signal Vout remains unchanged.

[0042] Figure 5 This is a waveform diagram of the power rail disturbance signal and the circuit output signal in a signal debouncing circuit according to an embodiment of the present invention, combined with... Figure 5 In the signal debouncing circuit of the present invention, when the power supply experiences a momentary dip and returns to normal, the voltage states of the input signal Vin, the first output signal Vcap, and the second output signal Vset cannot be kept synchronized. The interference detection circuit 102 can detect the level state flip of one of the input signal Vin, the first output signal Vcap, and the second output signal Vset. The generated control signal will control the voltage of the corresponding circuit node of the signal shaping link of the output buffer circuit 103 to be pulled up to the positive rail voltage of the power supply or pulled down to the negative rail voltage of the power supply, so as to ensure that the level state of the third output signal Vout remains at the previous level state, unaffected by power supply noise disturbance, and ensuring the robustness of the system.

[0043] Continue reading Figure 3The signal delay circuit 100 includes an inverter chain for shaping the signal and an RC signal delay unit for delaying the signal. In one embodiment, the signal delay circuit 100 includes a first inverter INV1, a second inverter INV2, a first resistor R1, and a first capacitor C1. The input terminal of the first inverter INV1 is connected to the input signal Vin, the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, the output terminal of the second inverter INV2 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the negative rail of the power supply through the first capacitor C1, and the second terminal of the first resistor R1 outputs a first output signal Vcap. Thus, the inverter chain consisting of the first inverter INV1 and the second inverter INV2 shapes the input signal Vin, and the RC delay unit consisting of the first resistor R1 and the first capacitor C1 delays the input signal Vin. The delay time is determined by the parameters of the first resistor R1 and the first capacitor C1. It should be noted that there are one or more first inverters INV1 and one or more second inverters INV2, and the sum of the number of first inverters INV1 and second inverters INV2 is an even number.

[0044] The power-on protection circuit 101 includes a first pull-up switch MP1, a first pull-down switch MN1, a first buffer BUF1, and a logic control unit (NAND1, NOR1). The input terminal of the first buffer BUF1 is connected to the first output signal Vcap, and the output terminal of the first buffer BUF1 outputs the second output signal Vset. The first terminal of the first pull-up switch MP1 is connected to the positive rail of the power supply, and the second terminal of the first pull-up switch MP1 is connected to the input terminal of the first buffer BUF1. The first terminal of the first pull-down switch MN1 is connected to the input terminal of the first buffer BUF1, and the second terminal of the first pull-down switch MN1 is connected to the negative rail of the power supply. The control terminals of the first pull-up switch MP1 and the first pull-down switch MN1 are both connected to the logic control unit. The logic control unit controls one of the first pull-up switch MP1 and the first pull-down switch MN1 to be turned on according to the second output signal Vset.

[0045] For example, when the input signal Vin is high, the logic control unit controls the first pull-up switch MP1 to turn on and the first pull-down switch MN1 to turn off. This pulls the first output signal Vcap up to the positive rail voltage of the power supply, ensuring a high-level output of the first output signal Vcap, and consequently ensuring a high-level output of the second output signal Vset. Conversely, when the input signal Vin is low, the logic control unit controls the first pull-up switch MP1 to turn off and the first pull-down switch MN1 to turn on. This pulls the first output signal Vcap down to the negative rail voltage of the power supply, ensuring a low-level output of the first output signal Vcap, and consequently ensuring a low-level output of the second output signal Vset.

[0046] For example, the first pull-up switch MP1 is a PMOS transistor, and the first pull-down switch MN1 is an NMOS transistor.

[0047] In one embodiment, the logic control unit includes a first NAND gate NAND1 and a first NOR gate NOR1. The first input terminal of the first NAND gate NAND1 and the first input terminal of the first NOR gate NOR1 are connected. The second input terminal of the first NAND gate NAND1 and the second input terminal of the first NOR gate NOR1 are both connected to the second output signal Vset. The output terminal of the first NAND gate NAND1 is connected to the control terminal of the first pull-up switch MP1, and the output terminal of the first NOR gate NOR1 is connected to the control terminal of the first pull-down switch MN1.

[0048] Thus, when the input signal Vin is low, the power supply quickly powers on from zero to a steady state (i.e., to the operating voltage VDD). At this time, the voltage of the first output signal Vcap does not have time to change, so the initial value of the voltage of the second output signal Vset is 0. The inputs of the first NAND gate NAND1 are all zero. The output signal of the first NAND gate NAND1 controls the first pull-up switch MP1 to always be in the off state. At the same time, the output signal of the first NOR gate NOR1 controls the first pull-down switch MN1 to always be in the on state, pulling the voltage of the first output signal Vcap down to zero potential. Therefore, during the power-on process, the voltage of the first output signal Vcap is always at a stable zero voltage, thereby avoiding the erroneous flipping of the voltage of the second output signal Vset. Correspondingly, when the input signal Vin is high, the power supply quickly powers up from zero to the steady-state operating voltage. Similarly, the output signal of the first NAND gate NAND1 controls the first pull-up switch MP1 to always be in the on state, and the output signal of the first NOR gate NOR1 controls the first pull-down switch MN1 to always be in the off state. Therefore, throughout the process, the voltage of the first output signal Vcap is always pulled up to VDD, thereby ensuring that the voltage of the second output signal Vset is in the high-level state and avoiding the incorrect flipping of the voltage of the second output signal Vset.

[0049] Continue reading Figure 3 The output buffer circuit 103 includes a second NAND gate NAND2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, and a second buffer BUF2, which are connected in series to form the signal shaping link. The control signals include a first control signal VC1, a second control signal VC2, a third control signal VC1B, and a fourth control signal VC2B. The first input terminal of the second NAND gate NAND2 is connected to the second output signal Vset, and the second input terminal of the second NAND gate NAND2 is connected to the first control signal VC1. The second control signal VC2 is used to control the voltage of the circuit node between the output terminal of the second NAND gate NAND2 and the input terminal of the third inverter INV3 to be pulled down to the negative rail voltage of the power supply. The circuit node between the output terminal of the third inverter INV3 and the input terminal of the fourth inverter INV4 is connected to the positive rail of the power supply via a second capacitor, and to the negative rail of the power supply via a third capacitor. The third control signal VC1B is used to control the voltage of the circuit node between the output terminal of the third inverter INV3 and the input terminal of the fourth inverter INV4 to be pulled down to the negative rail of the power supply. The circuit node between the output of the fifth inverter INV5 and the input of the second buffer BUF2 is connected to the negative rail of the power supply via a fourth capacitor. The fourth control signal VC2B is used to control the voltage of the circuit node between the output of the fifth inverter INV5 and the input of the second buffer BUF2 to be pulled up to the positive rail voltage of the power supply. Specifically, the circuit node between the output of the second NAND gate NAND2 and the input of the third inverter INV3 is circuit node A, the circuit node between the output of the third inverter INV3 and the input of the fourth inverter INV4 is circuit node B, and the circuit node between the output of the fifth inverter INV5 and the input of the second buffer BUF2 is circuit node C. Thus, the first to fourth control signals are obtained based on the state monitoring results of the input signal Vin, the first output signal Vcap, and the second output signal Vset. The first control signal VC1 and the second output signal Vset are used as the inputs of the second NAND gate NAND2 to obtain the voltage state of circuit node A. The second control signal VC2 controls whether the voltage of circuit node A is pulled down to GND, the third control signal VC1B controls whether the voltage of circuit node B is pulled down to GND, and the fourth control signal VC2B controls whether the voltage of circuit node C is pulled up to VDD, thereby ensuring that the state of the third output signal Vout does not change and is consistent with the level state of the previously input signal Vin.

[0050] Furthermore, regarding the voltage pull-down method of control circuit node A, the voltage pull-down method of circuit node B, and the voltage pull-up method of circuit node C, the output buffer circuit 103 also includes a second pull-up switch MP2, a second pull-down switch MN2, and a third pull-down switch MN3. The first terminal of the second pull-down switch MN2 is connected to the circuit node between the output terminal of the second NAND gate NAND2 and the input terminal of the third inverter INV3. The second terminal of the second pull-down switch MN2 is connected to the negative rail of the power supply. The second control signal VC2 controls the on / off state of the second pull-down switch MN2. The first terminal of the three pull-down switch MN3 is connected to the circuit node between the output of the third inverter INV3 and the input of the fourth inverter INV4. The second terminal of the third pull-down switch MN3 is connected to the negative rail of the power supply. The third control signal VC1B controls the on / off state of the third pull-down switch MN3. The first terminal of the second pull-up switch MP2 is connected to the positive rail of the power supply. The second terminal of the second pull-up switch MP2 is connected to the circuit node between the output of the fifth inverter INV5 and the input of the second buffer BUF2. The fourth control signal VC2B controls the on / off state of the second pull-up switch MP2. Thus, the second control signal VC2 controls the on / off state of the second pull-down switch MN2, thereby controlling whether the voltage at circuit node A is pulled down to GND. The third control signal VC1B controls the on / off state of the third pull-down switch MN3, thereby controlling whether the voltage at circuit node B is pulled down to GND. The fourth control signal VC2B controls the on / off state of the second pull-up switch MP2, thereby controlling whether the voltage at circuit node C is pulled up to VDD.

[0051] For example, the second pull-up switch MP2 is a PMOS transistor, and the second pull-down switch MN2 and the third pull-down switch MN3 are both NMOS transistors.

[0052] See Figure 4In one embodiment, the interference detection circuit 102 includes a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a third NAND gate NAND3, an OR gate OR2, a third NOR gate NOR3, and an AND gate. The input terminal of the sixth inverter INV6 and the first input terminal of the third NOR gate NOR3 are connected to the first output signal Vcap. The output terminal of the sixth inverter INV6 is connected to the second input terminal of the third NAND gate NAND3. The first input terminal of the third NAND gate NAND3 is connected to the second output signal Vset. The output terminal of the third NAND gate NAND3 is connected to the first input terminal of the OR gate OR2. The second input terminal of the OR gate OR2 is connected to the input signal Vi. n, the output of OR gate OR2 outputs the first control signal VC1, the input of the eighth inverter INV8 is connected to the input of OR gate OR2, and the output of the eighth inverter INV8 outputs the third control signal VC1B; the input of the seventh inverter INV7 is connected to the second output signal Vset, the output of the seventh inverter INV7 is connected to the second input of the third NOR gate NOR3, the output of the third NOR gate NOR3 is connected to the second input of the AND gate AND, the output of the AND gate AND outputs the second control signal VC2, the input of the ninth inverter INV9 is connected to the output of the AND gate AND, and the output of the ninth inverter INV9 outputs the fourth control signal VC2B.

[0053] Combination Figure 3 and Figure 4 The specific circuit structure demonstrated below provides a detailed explanation of the working principle of the signal debouncing circuit of the present invention. It should be noted that the following explanation uses an input signal Vin at a high level as an example. When the input signal Vin is at a low level, those skilled in the art can understand the working principle of the signal debouncing circuit of the present invention based on the explanation when the input signal Vin is at a high level, and will not be described in detail here.

[0054] When there is no power supply jitter interference, if the input signal Vin is high, then the first output signal Vcap is high, the second output signal Vset is high, and the generated first control signal VC1 is high, controlling the output of NAND2 to be inversely related to the Vset signal, that is, the voltage VA at point A is low; the fourth control signal VC2B is high, controlling the second pull-up switch MP2 to turn off, the third control signal VC1B is low, controlling the third pull-down switch MN3 to turn off, and the second control signal VC2 is low, controlling the second pull-down switch MN2 to turn off. Therefore, the third output signal Vout is high.

[0055] When the input signal Vin is high and the power supply voltage is subjected to high-frequency, large-amplitude pulse disturbances, such as a sudden drop in power supply VDD near GND followed by a rapid recovery to normal potential, the impedances of the three nodes—input signal Vin, first output signal Vcap, and second output signal Vset—cannot remain synchronized during the power drop and recovery process. Their voltages will exhibit inconsistencies due to power jitter. While the input signal Vin follows VDD throughout the power change, the discharge of the first capacitor C1 causes the first output signal Vcap to change slower than the input signal Vin during power recovery. Furthermore, the second output signal Vset is controlled not only by the first output signal Vcap but also by the coupling of parasitic capacitances during power recovery. Therefore, the change in the second output signal Vset during power recovery is asynchronous with the change in the first output signal Vcap, exhibiting a time delay. This can be categorized into two cases:

[0056] a) During the process where the delay of the first output signal Vcap is greater than the delay of the second output signal Vset, because the input signal Vin is high, the first control signal VC1 is also output as high. At this time, the Vset signal is a pulse signal that changes rapidly from low to high. The NAND2 output signal VA is a pulse signal that changes rapidly from high to low. After Vset jumps to high, it outputs a stable low level. The third control signal VC1B is low, controlling the third pull-down switch MN3 to turn off. The second control signal VC2 generates a high-level pulse signal, controlling the second pull-down switch MN2 to turn on. The fourth control signal VC2B generates a low-level pulse signal, controlling the second pull-up switch MP2 to turn on. Therefore, the voltage at point A is discharged to low level by the second pull-down switch MN2, and the voltage at point C is pulled up to VDD by the second pull-up switch MP2, thereby charging to high level, thus ensuring that the third output signal Vout is not disturbed during this process.

[0057] b) Considering that if the power supply jitter is very rapid, the change in the second output signal Vset may be faster than the change in the input signal Vin, meaning the delay of the second output signal Vset is less than the delay of the input signal Vin. Therefore, during the period when the delay of the second output signal Vset is less than the delay of the input signal Vin, the first control signal VC1 generates a low-level pulse, and the NAND2 output VA generates a high-level pulse signal; the third control signal VC1B generates a high-level pulse, controlling the third pull-down switch MN3 to turn on, and the second control signal VC2 generates a low-level pulse, controlling the second pull-down switch MN2 to turn off, and VC2B... A high-level pulse is generated, controlling the second pull-up switch MP2 to turn off. At this time, the voltage at point A controls the output of NAND2 to charge during the low-level pulse period of VC1. During this time, the voltage at node B is discharged. Therefore, the voltage at node B during this process depends on the voltage division of the second and third capacitors, and the duration of the low-level pulse depends on the voltage division and pull-down impedance of the third inverter INV3 and the third pull-down switch MN3, as well as the voltage division of the second and third capacitors. By reasonably selecting the values ​​of C2 and C3, the voltage at point B does not drop significantly during this process. Thus, the voltage at node C is in the charging state of the fourth capacitor C4 during the low-level pulse period. When the pulse ends, the voltage at node C is pulled up to VDD by the second pull-up switch MP2, thereby ensuring that the output state of the third output signal Vout remains stable.

[0058] In summary, this invention provides a signal dejittering circuit to resist power supply jitter. The signal dejittering circuit includes a signal delay circuit, a power-on protection circuit, an output buffer circuit, and an interference detection circuit. The signal delay circuit is used to shape and delay the input signal to obtain a first output signal. The power-on protection circuit is used to buffer the first output signal to obtain a second output signal. The power-on protection circuit is connected to the power supply and is used to control the charging and discharging of the first output signal during the power-on phase, so that the level of the second output signal is maintained at the level of the input signal. The output buffer circuit has a signal shaping link, which shapes and buffers the second output signal to output a third output signal. The interference detection circuit is used to generate a control signal based on the input signal, the first output signal, and the second output signal. When the level of one of the input signal, the first output signal, and the second output signal flips, the control signal pulls the voltage of at least one circuit node of the signal shaping link up to the positive rail voltage of the power supply or pulls it down to the negative rail voltage of the power supply, so that the level of the third output signal remains unchanged. Thus, when the power supply experiences a momentary dip and returns to normal, the voltage states of the input signal, the first output signal, and the second output signal cannot remain synchronized. The interference detection circuit can detect the level state flip of either the first or second output signal. The generated control signal will control the voltage of the corresponding circuit node in the signal shaping link of the output buffer circuit to be pulled up to the positive rail voltage or pulled down to the negative rail voltage of the power supply, ensuring that the level state of the third output signal remains at its previous level, unaffected by power supply noise disturbances, thus ensuring the robustness of the system.

[0059] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A signal dejittering circuit that resists power supply jitter, characterized in that, include: A signal delay circuit is used to shape and delay the input signal to obtain the first output signal; A power-on protection circuit is used to buffer the first output signal to obtain a second output signal. The power-on protection circuit is connected to a power supply and is used to control the charging and discharging of the first output signal during the power-on phase of the power supply, so that the level of the second output signal is maintained at the level of the input signal. An output buffer circuit has a signal shaping link, which performs shaping and buffering processing on the second output signal to output a third output signal; An interference detection circuit is used to generate a control signal based on the input signal, the first output signal, and the second output signal; when the level state of one of the input signal, the first output signal, and the second output signal flips, the control signal controls the voltage of at least one circuit node of the signal shaping link to be pulled up to the positive rail voltage of the power supply or pulled down to the negative rail voltage of the power supply, so that the level state of the third output signal remains unchanged.

2. The signal dejittering circuit against power supply jitter according to claim 1, characterized in that, The signal delay circuit includes an inverter chain and an RC delay unit connected to the inverter chain.

3. The signal dejittering circuit against power supply jitter according to claim 2, characterized in that, The signal delay circuit includes a first inverter, a second inverter, a first resistor, and a first capacitor. The input terminal of the first inverter is connected to the input signal, the output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the negative rail of the power supply through the first capacitor, and the second terminal of the first resistor outputs the first output signal.

4. The signal dejittering circuit against power supply jitter according to claim 1, characterized in that, The power-on protection circuit includes a first pull-up switch, a first pull-down switch, a first buffer, and a logic control unit. The input terminal of the first buffer is connected to the first output signal, and the output terminal of the first buffer outputs the second output signal. The first terminal of the first pull-up switch is connected to the positive rail of the power supply, and the second terminal of the first pull-up switch is connected to the input terminal of the first buffer. The first terminal of the first pull-down switch is connected to the input terminal of the first buffer, and the second terminal of the first pull-down switch is connected to the negative rail of the power supply. The control terminals of the first pull-up switch and the first pull-down switch are both connected to the logic control unit. The logic control unit controls one of the first pull-up switch and the first pull-down switch to be turned on according to the second output signal.

5. The signal dejittering circuit against power supply jitter according to claim 4, characterized in that, The logic control unit includes a first NAND gate and a first NOR gate. The first input terminal of the first NAND gate and the first input terminal of the first NOR gate are connected. The second input terminal of the first NAND gate and the second input terminal of the first NOR gate are both connected to the second output signal. The output terminal of the first NAND gate is connected to the control terminal of the first pull-up switch, and the output terminal of the first NOR gate is connected to the control terminal of the first pull-down switch.

6. The signal dejittering circuit against power supply jitter according to claim 4, characterized in that, The first pull-up switch is a PMOS transistor, and the first pull-down switch is an NMOS transistor.

7. The signal dejittering circuit against power supply jitter according to claim 1, characterized in that, The output buffer circuit includes a second NAND gate, a third inverter, a fourth inverter, a fifth inverter, and a second buffer connected in series to form the signal shaping link. The control signals include a first control signal, a second control signal, a third control signal, and a fourth control signal. The first input terminal of the second NAND gate is connected to the second output signal, and the second input terminal of the second NAND gate is connected to the first control signal. The second control signal is used to control the voltage of the circuit node between the output terminal of the second NAND gate and the input terminal of the third inverter to be pulled down to the negative rail voltage of the power supply. The circuit node between the output terminal of the third inverter and the input terminal of the fourth inverter is connected to the positive rail of the power supply via a second capacitor and to the negative rail of the power supply via a third capacitor. The third control signal is used to control the voltage of the circuit node between the output terminal of the third inverter and the input terminal of the fourth inverter to be pulled down to the negative rail of the power supply. The circuit node between the output of the fifth inverter and the input of the second buffer is connected to the negative rail of the power supply via a fourth capacitor. The fourth control signal is used to control the voltage of the circuit node between the output of the fifth inverter and the input of the second buffer to be pulled up to the positive rail voltage of the power supply.

8. The signal dejittering circuit against power supply jitter according to claim 7, characterized in that, The output buffer circuit further includes a second pull-up switch, a second pull-down switch, and a third pull-down switch; The first end of the second pull-down switch is connected to the circuit node between the output of the second NAND gate and the input of the third inverter, the second end of the second pull-down switch is connected to the negative rail of the power supply, and the second control signal controls the on / off state of the second pull-down switch. The first end of the third pull-down switch is connected to the circuit node between the output terminal of the third inverter and the input terminal of the fourth inverter, the second end of the third pull-down switch is connected to the negative rail of the power supply, and the third control signal controls the on / off state of the third pull-down switch. The first end of the second pull-up switch is connected to the positive rail of the power supply, the second end of the second pull-up switch is connected to the circuit node between the output of the fifth inverter and the input of the second buffer, and the fourth control signal controls the on / off state of the second pull-up switch.

9. The signal dejittering circuit against power supply jitter according to claim 8, characterized in that, The second pull-up switch is a PMOS transistor, and the second pull-down switch and the third pull-down switch are both NMOS transistors.

10. The signal dejittering circuit against power supply jitter according to claim 7, characterized in that, The interference detection circuit includes a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a third NAND gate, an OR gate, a third NOR gate, and an AND gate. The input terminal of the sixth inverter and the first input terminal of the third NOR gate are connected to the first output signal. The output terminal of the sixth inverter is connected to the second input terminal of the third NAND gate. The first input terminal of the third NAND gate is connected to the second output signal. The output terminal of the third NAND gate is connected to the first input terminal of the OR gate. The second input terminal of the OR gate is connected to the input signal. The output terminal of the OR gate outputs the first control signal. The input terminal of the eighth inverter is connected to the input terminal of the OR gate. The output terminal of the eighth inverter outputs the third control signal. The input terminal of the seventh inverter is connected to the second output signal. The output terminal of the seventh inverter is connected to the second input terminal of the third NOR gate. The output terminal of the third NOR gate is connected to the second input terminal of the AND gate. The output terminal of the AND gate outputs the second control signal. The input terminal of the ninth inverter is connected to the output terminal of the AND gate. The output terminal of the ninth inverter outputs the fourth control signal.

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