Symbol-level guess noise decoding system

Abstract

The invention provides a symbol-level guess noise decoding system. The symbol-level guess noise decoding system comprises a check matrix H storage module, a preprocessing module, a hard decision check module, a sorting module, an error pattern EP generation module and a code word generation module, receiving a symbol sequence and a check matrix H, inputting the received symbol sequence and the check matrix H into a preprocessing module, obtaining a hard decision bit sequence through hard decision, selecting candidate symbols through linear reliability calculation (LRC), calculating reliability, and obtaining a mapping matrix through candidate symbol-syndrome mapping (CSM); a hard decision verification module verifies the hard decision bit sequence, and a sorting module sorts candidate symbols according to a reliability increasing sequence; and the error mode EP generation module guesses the EP according to the sorting sequence, verifies the EP by using the mapping matrix, and outputs the EP which is verified to be correct to the code word generation module to obtain a decoding code word. According to the scheme, a large number of repeated operations in invalid tests are avoided, the calculation complexity is greatly reduced, and the hardware resource overhead can be remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of guessing noise decoding technology, and more particularly to a symbol-level guessing noise decoding system. Background Technology

[0002] The existing ORBGRAND decoding scheme based on symbol-level reliability ordering has attracted widespread attention because it can skip the soft demodulation step at the receiver and directly use symbol-level soft information for decoding. However, this scheme has the following two bottlenecks: First, the scheme needs to pre-calculate the Euclidean distance difference of the symbol-level soft information to determine candidate symbols and their reliability, which introduces high decoding delay and computational complexity, and faces significant area overhead in hardware implementation; second, each test in the decoding process requires a complete process of converting the symbol sequence into a bit sequence and then performing verification, and the frequent occurrence of the above operations leads to low computational efficiency. Summary of the Invention

[0003] Purpose of the invention: The technical problem to be solved by the present invention is to provide a symbol-level guessing noise decoding system that addresses the shortcomings of the prior art, including a parity check matrix H storage module, a preprocessing module, a hard decision check module, a sorting module, an error mode EP generation module, and a codeword generation module;

[0004] The original parity-check matrix H is loaded into the parity-check matrix H storage module. Then, the received symbol sequence Y and the parity-check matrix H are sent to the preprocessing module. The preprocessing module first performs hard decision on the received symbols to obtain the hard decision symbol sequence. and hard decision bit sequence Then, the K candidate symbols and their reliability are obtained using the linear reliability calculation (LRC) method, and the mapping matrix H is obtained using the candidate symbol-corrector mapping (CSM) method. M This is used in the subsequent Error Mode (EP) generation module;

[0005] The hard decision verification module checks the hard decision bit sequence. Perform verification and calculation The calibration vector obtained by multiplying the calibration matrix H is considered correct if it is an all-zero vector. This is the hard-decision bit sequence. That is, the decoding result; otherwise, a verification error is found. The sorting module sorts the candidate symbols in ascending order of reliability, and the sorting order is used for decoding tests.

[0006] Decoding tests are implemented by the error mode (EP) generation module and the codeword generation module;

[0007] The codeword generation module is used to output the decoded codeword.

[0008] The original parity check matrix H is used to check the codeword. Each column in H represents the corrector after an error occurs in the corresponding bit of the codeword.

[0009] Mapping matrix H M Used to verify error modes, H M Each column in the diagram represents the corrector after an error occurs in the corresponding bit of the error mode EP. Each bit in the error mode corresponds to a candidate symbol.

[0010] The formula for the "candidate symbol-corrector" mapping CSM method is as follows:

[0011]

[0012] φ={i∣d i =1, i=0,1,…,n-1},

[0013] H M =[h i |i∈φ](1),

[0014] Where b represents the bit sequence obtained by hard demodulating the candidate symbol sequence. Represents the hard decision bit sequence, symbol This represents bitwise XOR, i.e., XORing sequence b and... Each bit in the sequence is XORed accordingly; the intermediate parameter sequence d records the bits that are different between each candidate symbol and the hard decision symbol. i Let represent the i-th bit in sequence d, n be the sequence length, φ be the set of positions in sequence d where the bit is 1, and h be the position of the ith bit. i Represents the i-th column in the original parity-check matrix H, for a specific column vector h. i By combining them, we can obtain the mapping matrix H. M .

[0015] The linear reliability (LRC) calculation method includes: for the i-th received symbol Y in the received symbol sequence Y... i Let Y i The hard decision symbol is Y i The candidate symbol is t i Using the distance δ i as a candidate symbol t i The reliability is calculated using the following formula: exceedance distance δ i :

[0016]

[0017] in, The distance between the candidate symbol and the hard decision symbol;

[0018] Substituting the candidate sign values ​​into formula (2), we get:

[0019]

[0020] The error mode EP generation module performs error mode guessing and verification. The following four steps that need to be repeated are optimized into the following two steps: guessing and verification. That is, the guessed error mode EP is directly verified. If the verification fails, the next guess is performed until the correct error mode EP is obtained.

[0021] The codeword generation module first restores the error positions contained in the error mode EP to their original order using a multiplexer, and then processes the hard decision symbol sequence according to the error mode EP. Perform a one-time replacement and demodulation operation.

[0022] The error location, i.e., the hard decision symbol sequence, contained in the error mode EP. The position of the error symbol in the sequence, using candidate symbols to pair the sequence. The incorrect symbols in the sequence are replaced to obtain a new symbol sequence. Then Demodulation into bit sequence That is, the final output decoded codeword.

[0023] The present invention also provides an electronic device, including a processor and a memory, the memory storing program code that, when executed by the processor, causes the processor to run the system.

[0024] The present invention also provides a storage medium storing a computer program or instructions that execute the system when the computer program or instructions are run on a computer.

[0025] Beneficial effects: Existing solutions require repeating the four steps (guess-substitute-demodulation-verification) several times for decoding each received codeword, resulting in high computational complexity. This solution refactors the four repeated steps in the original decoding test into two steps: 1) guess; 2) verification, which directly verifies incorrect guess patterns. Only after successful verification is substitution and demodulation performed once. Compared to existing solutions, this approach avoids numerous repetitive operations in invalid tests, significantly reducing computational complexity and hardware resource consumption during implementation.

[0026] Secondly, existing schemes, in the pre-computation of symbol-level soft information, require calculating the reliability of candidate symbols for each received symbol, necessitating numerous squaring operations and sorting networks, introducing significant decoding delay and area overhead. This scheme, through mathematical derivation, simplifies the pre-computation process into a linear piecewise function of the received symbols. Without affecting decoding performance, it eliminates all squaring and sorting operations in the pre-computation process, greatly reducing the complexity and area overhead of the pre-computation module in hardware implementation. Attached Figure Description

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0028] Figure 1 This is a flowchart of the construction process of the mapping matrix.

[0029] Figure 2 These are PAM4 and PAM8 constellation diagrams.

[0030] Figure 3 These are the decoding test flowcharts for the existing scheme (a) and the optimized decoding test flowchart for this scheme (b).

[0031] Figure 4 This is a hardware architecture diagram of a symbol-level ORBGRAND decoder for Pulse Amplitude Modulation (PAM).

[0032] Figure 5 This is a graph showing the frame error rate (FER) performance under PAM4 and PAM8 modulation. Detailed Implementation

[0033] This scheme encodes a k-bit information sequence to obtain an n-bit transmit codeword x. x is then converted into a transmit symbol sequence X of length L = n / log2M through M-order PAM modulation. This transmitted symbol sequence X is then transmitted through an additive white Gaussian noise channel to obtain the receive symbol sequence Y. During decoding, K candidate symbols are selected for each received symbol, for a total of K*L candidate symbols. The error mode is a K*L bit sequence, with each bit corresponding to one candidate symbol.

[0034] This scheme proposes a Candidate-to-Syndrome (CSM) mapping method. By establishing a mapping relationship between candidate symbols and synthesizers, the codeword parity-check matrix H is reorganized to construct a mapping matrix H that can be directly used for error mode detection. M Its size is (nk)×(K*L), which matches the length K*L of the error mode.

[0035] The original parity-check matrix H is used to check the codeword. Each column of H represents the corrector for a corresponding bit error in the codeword. Similarly, the mapping matrix H... M Used to verify error modes, H M Each column in the matrix represents a corrector for the corresponding bit error in the error mode, and each bit in the error mode corresponds to a candidate symbol, thus establishing a one-to-one correspondence between candidate symbols and correctors. Here, we take pulse amplitude modulation (PAM8) (M=8), K=1 as an example, with the mapping matrix H... M The construction flowchart is as follows Figure 1 As shown, this process will be completed before error pattern guessing.

[0036] The specific process can be abstracted into the following three formulas:

[0037]

[0038] φ={i∣d i =1, i=0,1,…,n-1},

[0039] H M =[h i |i∈φ](1),

[0040] Where b represents the bit sequence obtained by hard demodulating the candidate symbol sequence. This represents the bit sequence obtained by hard-decision processing of the received symbol sequence. The symbol ⊕ indicates bitwise XOR, i.e., XORing the sequence b with... Each bit in the sequence is XORed accordingly. The intermediate parameter sequence d records the bits that are different between each candidate symbol and the hard decision symbol. i Let φ represent the i-th bit in sequence d, φ be the set of positions in sequence d where the bit is 1, and h be the set of positions where the bit is 1. i Represents the i-th column in the original parity-check matrix H, for a specific column vector h. i By combining them, we can obtain the mapping matrix H. M .

[0041] PAM modulation typically employs Gray code mapping. The PAM4 and PAM8 constellation diagrams used in this scheme are as follows: Figure 2As shown in a and b in the diagram. When K=1, only one candidate symbol is selected for each received symbol. For example, for the received symbol +1.3, its hard decision symbol is +1, and its candidate symbol is +3. The candidate symbol is adjacent to the received symbol, so it differs from the received symbol by only one bit. The column vector in the parity check matrix H corresponding to this differing bit represents the impact on the corrector after the hard decision symbol is replaced by the candidate symbol. That is, the column vector in H corresponding to the differing bits in the candidate symbol and the hard decision symbol is equal to the corrector of the candidate symbol. For non-Gray code modulation, or when K>1, there may be multiple differing bits. The corrector of the candidate symbol can be obtained by bitwise XORing the correctors corresponding to these multiple differing bits. The CSM method proposed in this scheme obtains the mapping matrix H by selecting and combining specific column vectors in the parity check matrix H. M And ensured H M Matches the dimensions of the error pattern.

[0042] The mapping matrix H constructed based on the above process M This scheme optimizes the original four-step (guess-substitute-demodulation-verification) process, which required multiple repetitions in the decoding test, into two steps (guess-verification). Specifically, it directly verifies the guessed incorrect pattern EP; if the verification fails, it proceeds with the next guess until a correctly verified EP is obtained. Then, it only needs to analyze the hard-decision symbol sequence based on the EP. After performing a substitution and demodulation step, the error locations, i.e., the sequences, contained in the EP are... The position of the error symbol in the sequence, using candidate symbols to pair the sequence. The incorrect symbols in the sequence are replaced to obtain a new symbol sequence. Then Demodulation into bit sequence That is, the final output decoded codeword. Figure 3 a and Figure 3 Figure 'b' shows the decoding test flowcharts for the existing scheme and this scheme, respectively. For the guessed error pattern, This is the new sequence obtained by replacing the hard decision symbol sequence. To The existing schemes use the original parity-check matrix H to obtain the bit sequence from hard demodulation. Verification is performed. In this solution, s HD The verification result of the hard-decision bit sequence is obtained using the mapping matrix H. M Directly addressing the error pattern of guessing Perform a verification; if the obtained corrector matches s... HDIf the results are the same, it means the guessed incorrect pattern EP passes the verification. Only then are substitution and demodulation operations performed to finally obtain the correct codeword. The CSM optimization method proposed in this scheme eliminates a large number of substitution and demodulation operations in invalid tests, significantly reducing decoding complexity.

[0043] 1. Pre-calculation simplification

[0044] For the i-th received symbol Y in the received symbol sequence Y i Let its hard decision symbol be The candidate symbol is t i Using the distance δ i as a candidate symbol t i The reliability of the overtake distance in existing solutions is calculated using the following formula:

[0045]

[0046] Where δ i That is, beyond the distance, |t i -Y i | 2 Let be the squared Euclidean distance between the candidate symbol and the received symbol. The squared Euclidean distance between the hard decision symbol and the received symbol.

[0047] This scheme proposes a linearized reliability computation (LRC) method, which simplifies equation (2) to the received symbol Y through mathematical transformation. i The piecewise linear function. Next, taking PAM8 modulation as an example, this scheme sets 13 decision thresholds {-6, -5, ..., 6} for PAM8 symbols (for PAM4 modulation, it sets 5 decision thresholds {-2, -1, 0, 1, 2}). The hard decision symbol and candidate symbol are obtained by comparing the amplitude of the received symbol. Secondly, equation (2) is transformed mathematically as follows:

[0048]

[0049] in, Let K be the distance between the candidate symbol and the hard decision symbol. This scheme only considers the cases of K=1 and K=2, which is obvious. It is always equal to the constant 2, therefore Some are constants. Since the ORBGARND algorithm only focuses on the sorting order of reliability (i.e., relative size), the simplification scheme in (3) does not affect the computational accuracy in decoding.

[0050] Based on the decision threshold mentioned above, this scheme further substitutes the candidate symbol value into formula (3), and the exceedance distance δ i The calculation can be simplified to only involving the received symbol Y. i Related piecewise linear functions:

[0051]

[0052] The above method eliminates the exponentiation and sorting operations in the pre-computation process of existing schemes, greatly reducing the complexity and area overhead of the module in hardware implementation.

[0053] 2. Overall hardware circuit

[0054] The hardware architecture of the symbol-level ORBGRAND decoder for PAM modulation proposed in this scheme is as follows: Figure 4 As shown, the circuit mainly consists of the following modules: a parity check matrix H storage module, a preprocessing module, a hard-decision check module, a sorting module, an error mode (EP) generation module, and a codeword generation module. The original parity check matrix H is loaded into the parity check matrix H storage module, and then the received symbol sequence Y and the parity check matrix H are sent to the preprocessing module. The preprocessing module first performs hard decision processing on the received symbols to obtain the hard-decision symbol sequence. and hard decision bit sequence Then, candidate symbols and their reliability are obtained through the linear reliability calculation method (LRC), and the mapping matrix H is obtained through the candidate symbol-compensator (CSM) mapping method. M This is used in the subsequent Error Mode (EP) generation module;

[0055] The hard decision verification module checks the hard decision bit sequence. Perform verification and calculation The calibration vector obtained by multiplying the calibration matrix H is considered correct if it is an all-zero vector. This is the hard-decision bit sequence. The decoding result is determined by the order of the candidate symbols; otherwise, an error is detected. The sorting module sorts the candidate symbols in ascending order of reliability, and this sorting order is used for decoding testing. Decoding testing is implemented by an error mode (EP) generation module and a codeword generation module. The EP generation module performs error mode guessing and verification, optimizing the previously repeated four steps (guess, substitute, demodulate, and verify) into two steps: guess and verify. Specifically, it directly verifies the guessed error mode EP; if the verification fails, it proceeds to the next guess until a correctly verified EP is obtained. The codeword generation module first restores the error positions contained in the EP to their pre-sorting order using a multiplexer, and then performs a hard-decision symbol sequence based on the EP. A one-time substitution and demodulation operation is performed, and the error locations, i.e., the sequences, contained in the EP are... The position of the error symbol in the sequence, using candidate symbols to pair the sequence. The incorrect symbols in the sequence are replaced to obtain a new symbol sequence. Then Demodulation into bit sequence That is, the final output decoded codeword.

[0056] The proposed linear reliability calculation (LRC) method for pre-computing symbol-level soft information is applicable to the cases where the number of candidate symbols is K=1 and K=2, but the optimized design of the decoding test process can be applied to all K values.

[0057] The proposed optimized decoding test process design and the "candidate symbol-corrector" mapping CSM method have certain scalability. It is not only applicable to PAM modulation but can also be extended to other higher-order modulation schemes, such as Quadrature Amplitude Modulation (QAM) and Phase Shift Keying (PSK). By reconstructing the parity-check matrix using the dissimilar bits in candidate symbols and hard-decision symbols, unnecessary operations in invalidation testing can be avoided under other modulation schemes, thereby reducing computational complexity.

[0058] The proposed linear reliability (LRC) calculation method for symbol-level soft information pre-computation has certain scalability. It is not only applicable to one-dimensional PAM modulation such as PAM4 and PAM8, but can also be extended to two-dimensional PAM modulation such as PAM6. PAM6 uses two adjacent symbols as the horizontal and vertical axes to represent a point in the constellation diagram. When pre-computing its symbol-level soft information, by processing the two symbols on the horizontal and vertical axes separately, following the simplification approach of this scheme, its complexity and area overhead can also be reduced.

[0059] In this embodiment, a Cyclic Redundancy Check (CRC) code with n=128 and k=112, generating a polynomial of 0x8005, is considered for transmission through an Additive White Gaussian Noise (AWGN) channel. Simulation experiments were conducted under PAM4 and PAM8 modulation, and the bit signal-to-noise ratio (BNR) E under the two modulation schemes was compared with that of the original ORBGRAND algorithm. b The curves of / N0 and frame error rate FER are as follows: Figure 5 As shown:

[0060] from Figure 5 As can be seen, setting the number of candidate symbols K=1 and K=2 in this scheme does not cause performance loss. Selecting only one candidate symbol (K=1) can achieve performance almost identical to the original ORBGRAND algorithm.

[0061] This invention implements the proposed symbol-level ORBGRAND decoder in hardware under the condition of K=1, and synthesizes it using TSMC's 28nm process. The comparison results with existing symbol-level ORBGRAND decoder schemes (baseline schemes in Table 1) and bit-level ORBGRAND hardware implementation schemes in other published documents are shown in Table 1. The codewords of Documents 1, 2 and 4 are CRC-assisted polar codes CA-polar.

[0062] Table 1. Hardware Implementation Results of This Scheme, Baseline Scheme, and Other Work

[0063]

[0064] In the table, Document 1 is: SMAbbas, T. Tonnellier, F. Ercan, M. Jalaleddine, and W.J. Gross, "High-throughput and energy-efficient VLSI architecture for orderedreliability bits GRAND," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.30, no.6, pp.681–693, 2022.

[0065] Document 2 is: C. Condo, "A fixed latency ORBGRAND decoder architecture with LUT-aided error-pattern scheduling," IEEE Transactions on Circuits and SystemsI: Regular Papers, vol.69, no.5, pp.2203–2211, 2022.

[0066] Document 3 is: A.Riaz, A.Yasar, F.Ercan, W.An, J.Ngo, K.Galligan, M.Medard, KRDuffy, and RTYazicigil, "ASub-0.8-pJ / bit Universal Soft-Detection DecoderUsing ORBGRAND," IEEE Journal of Solid-State Circuits, vol.60, no.7, pp.2645–2659, 2024.

[0067] Document 4 is: C.Ji,

[0068] As shown in the table, the proposed decoder hardware circuit achieves area efficiencies of 1.2 times and 2.3 times that of existing schemes under PAM4 and PAM8 modulation, respectively. Furthermore, compared to existing schemes, this scheme reduces latency by 33% under PAM8 modulation. Compared to bit-level ORBGRAND hardware implementations in other published literature, this scheme achieves area efficiencies of 1.86 times and 1.94 times under PAM4 and PAM8 modulation, respectively. These results demonstrate that this scheme significantly reduces complexity and area overhead compared to existing schemes, while also reducing decoding latency.

[0069] This invention provides a symbol-level guessing noise decoding system. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A symbol-level guessing noise decoding system, characterized in that, It includes a parity check matrix H storage module, a preprocessing module, a hard decision check module, a sorting module, an error mode EP generation module, and a codeword generation module; The original parity-check matrix H is loaded into the parity-check matrix H storage module. Then, the received symbol sequence Y and the parity-check matrix H are sent to the preprocessing module. The preprocessing module first performs hard decision on the received symbols to obtain the hard decision symbol sequence. and hard decision bit sequence Then, the K candidate symbols and their reliability are obtained using the linear reliability calculation (LRC) method, and the mapping matrix H is obtained using the candidate symbol-corrector mapping (CSM) method. M This is used in the subsequent Error Mode (EP) generation module; The hard decision verification module checks the hard decision bit sequence. Perform verification and calculation The calibration vector obtained by multiplying the calibration matrix H is considered correct if it is an all-zero vector. This is the hard-decision bit sequence. That is, the decoding result; Otherwise, if the verification fails, the sorting module will sort the candidate symbols in ascending order of reliability. The sorting order will be used for decoding tests. Decoding tests are implemented by the error mode (EP) generation module and the codeword generation module; The codeword generation module is used to output the decoded codeword.

2. The system according to claim 1, characterized in that, The original parity check matrix H is used to check the codeword. Each column in H represents the corrector after an error occurs in the corresponding bit of the codeword.

3. The system according to claim 2, characterized in that, Mapping matrix H M Used to verify error modes, H M Each column in the diagram represents the corrector after an error occurs in the corresponding bit of the error mode EP. Each bit in the error mode corresponds to a candidate symbol.

4. The system according to claim 3, characterized in that, The formula for the candidate symbol-corrector mapping (CSM) method is as follows: φ={i∣d i =1,i=0,1,…,n-1}, H M =[h i ∣i∈φ](1), Where b represents the bit sequence obtained by hard demodulating the candidate symbol sequence. This represents a hard-decision bit sequence, and the symbol ⊕ indicates bitwise XOR, i.e., XORing the sequence b with... Each bit in the sequence is XORed accordingly; the intermediate parameter sequence d records the bits that are different between each candidate symbol and the hard decision symbol. i Let represent the i-th bit in sequence d, n be the sequence length, φ be the set of positions in sequence d where the bit is 1, and h be the position of the ith bit. i Represents the i-th column in the original parity-check matrix H, for a specific column vector h. i By combining them, we can obtain the mapping matrix H. M .

5. The system according to claim 4, characterized in that, The linear reliability (LRC) calculation method includes: for the i-th received symbol Y in the received symbol sequence Y... i Let Y i The hard decision symbol is Y i The candidate symbol is t i Using the distance δ i as a candidate symbol t i The reliability is calculated using the following formula: exceedance distance δ i : in, The distance between the candidate symbol and the hard decision symbol; Substituting the candidate sign values ​​into formula (2), we get:

6. The system according to claim 5, characterized in that, The error mode EP generation module performs error mode guessing and verification. The following four steps that need to be repeated are optimized into the following two steps: guessing and verification. That is, the guessed error mode EP is directly verified. If the verification fails, the next guess is performed until the correct error mode EP is obtained.

7. The system according to claim 6, characterized in that, The codeword generation module first restores the error positions contained in the error mode EP to their original order using a multiplexer, and then processes the hard decision symbol sequence according to the error mode EP. Perform a one-time replacement and demodulation operation.

8. The system according to claim 7, characterized in that, The error location, i.e., the hard decision symbol sequence, contained in the error mode EP. The position of the error symbol in the sequence, using candidate symbols to pair the sequence. The incorrect symbols in the sequence are replaced to obtain a new symbol sequence. Then Demodulation into bit sequence That is, the final output decoded codeword.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing program code that, when executed by the processor, causes the processor to run the system as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The system contains computer programs or instructions that, when run on a computer, execute the system as described in any one of claims 1 to 8.

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