Shift register, gate drive circuit, display device and gate drive method

Abstract

The invention discloses a shift register, a gate driving circuit, a display device and a gate driving method. The shift register comprises a pull-up node control circuit (10), a pull-down node control circuit (20), an output circuit (30) and an induction compensation circuit (40). The pull-up node control circuit (10) is configured to control an electrical signal of a pull-up node (QA). And the output circuit (30) comprises a gate driving output end and is configured to output a composite signal to the gate driving output end under the control of the electric signal of the pull-up node (QA). The pull-down node control circuit (20) is configured to at least input a first voltage end signal to the pull-down node (QB) under the control of an electric signal of the pull-up node (QA). The induction compensation circuit (40) is configured to output an induction signal under the control of an electric signal of the pull-down node (QB).

Description

Shift register, gate drive circuit, display device and gate drive method Cross-references to related applications

[0001] This application claims priority to Chinese patent application No. 2024110485375, filed on July 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display device, and a gate driving method. Background Technology

[0003] In related technologies, most display products use GOA (Gate Driver On Array) technology to achieve line-by-line scanning drive function, thus saving the use of traditional gate drivers (Gate Driver ICs). However, some transistors in the GOA experience threshold voltage and other characteristic drift, making it difficult for the GOA to accurately output scanning signals. Summary of the Invention

[0004] This disclosure provides a shift register, a gate driving circuit, a display device, and a gate driving method, aiming to at least partially solve the problem that the GOA is difficult to accurately output scanning signals due to the characteristic drift of some transistors such as threshold voltage in the GOA.

[0005] In a first aspect of this disclosure, a shift register is provided, the shift register comprising: a pull-up node control circuit configured to control an electrical signal of a pull-up node; an output circuit including a gate drive output terminal, the output circuit being configured to output a composite signal to the gate drive output terminal under the control of the electrical signal of the pull-up node; a pull-down node control circuit configured to input a first voltage terminal signal to the pull-down node under the control of the electrical signal of the pull-up node; and an induction compensation circuit configured to output an induction signal under the control of the electrical signal of the pull-down node.

[0006] In some implementations, it further includes a first stabilizing circuit configured to electrically control the pull-up node under the electrical signal control of the pull-down node.

[0007] In some embodiments, the pull-up node control circuit includes: an input sub-circuit configured to input a first power signal to the pull-up node under the control of a charging input signal; and a pull-down node control circuit configured to input a second power signal or the first voltage terminal signal to the pull-down node under the control of an electrical signal from the pull-up node.

[0008] In some embodiments, the pull-up node control circuit further includes: a reset protection sub-circuit configured to perform electrical signal control on the pull-up synchronization node under the electrical signal control of the pull-up node, the pull-up synchronization node being connected to the first stabilizing circuit; the first stabilizing circuit is further configured to perform electrical signal control on the pull-up synchronization node under the electrical signal control of the pull-down node.

[0009] In some embodiments, the system further includes: a selection compensation circuit configured to charge the pull-up control node under the control of a selection compensation control signal and to charge the pull-up node under the control of a sub-clock signal.

[0010] In some embodiments, the induction compensation circuit includes a sensing sub-circuit configured to generate the induction signal based on a first control signal when the level of the pull-down node is higher than a threshold voltage.

[0011] In some embodiments, the sensing sub-circuit includes: at least one sensing transistor, the control terminal of which is connected to the pull-down node; the sensing transistor is configured to turn on when the level of the pull-down node is higher than a threshold voltage, so that the first control signal passes through the sensing transistor to generate the sensing signal.

[0012] In some embodiments, the at least one sensing transistor includes: a first sensing transistor, a first terminal of which is connected to the first control signal; and a second sensing transistor, a first terminal of which is connected to a second terminal of the first sensing transistor, wherein the sensing signal is output through the second terminal of the second sensing transistor.

[0013] In some implementations, the first control signal and the selection compensation control signal share the same signal line, and the selection compensation control signal is a control signal for compensating the composite signal.

[0014] In some embodiments, the induction compensation circuit further includes an output control sub-circuit configured to output the induction signal under the control of a second control signal.

[0015] In some embodiments, the output control sub-circuit includes: an output control transistor, the control terminal of which is connected to the second control signal, the first terminal of which is connected to the second terminal of the second sensing transistor, and the sensing signal being output through the second terminal of the output control transistor.

[0016] In some implementations, the first control signal is a delayed version of the second control signal.

[0017] In some embodiments, the inductive compensation circuit further includes a voltage regulator sub-circuit configured to stabilize the level of the pull-down node when the level of the first control signal changes.

[0018] In some embodiments, the voltage regulator sub-circuit includes: a voltage regulator capacitor, the first end of which is connected to the pull-down node, and the second end of which is connected to a second voltage terminal signal.

[0019] In some embodiments, the inductive compensation circuit further includes a voltage regulating sub-circuit configured to adjust the level of the pull-down node under the control of a third control signal.

[0020] In some embodiments, the voltage regulating sub-circuit includes: a voltage regulating transistor, the control terminal of which is connected to the third control signal, the first terminal of which is connected to the pull-down node, and the second terminal of which is connected to the first voltage terminal signal.

[0021] In some embodiments, the shift register further includes a first stabilizing circuit, the first stabilizing circuit including: a first noise reduction transistor, the control terminal of the first noise reduction transistor being connected to the pull-down node, and a first terminal of the first noise reduction transistor being connected to the pull-up node; and a second noise reduction transistor, the control terminal of the second noise reduction transistor being connected to the pull-down node, and a first terminal of the second noise reduction transistor being connected to a second terminal of the first noise reduction transistor, the second terminal of the second noise reduction transistor being connected to the first voltage terminal signal.

[0022] In some embodiments, the induction compensation circuit further includes an induction control sub-circuit configured to connect the level of the connection point of the first noise reduction transistor and the second noise reduction transistor to the induction sub-circuit under the control of a fourth control signal.

[0023] In some embodiments, the sensing control sub-circuit includes: a sensing control transistor, the control terminal of which is connected to the fourth control signal, the first terminal of which is connected to the second terminal of the first noise reduction transistor and the first terminal of the second noise reduction transistor, and the second terminal of which is connected to the second terminal of the first sensing transistor and the first terminal of the second sensing transistor.

[0024] In some embodiments, the pull-up node control circuit includes: a first input transistor, the control terminal of which is connected to the charging input signal, and a first terminal of which is connected to a first power signal; a second input transistor, the control terminal of which is connected to the charging input signal, a first terminal of which is connected to the first terminal of the first input transistor, and a second terminal of which is connected to the pull-up node; an input protection transistor, the control terminal of which is connected to the pull-down node, a first terminal of which is connected to the first power signal, and a second terminal of which is connected to the second terminal of the first input transistor and the first terminal of the second input transistor; and a first reset transistor, the control terminal of which is connected to the display total reset signal. The first end of the body transistor is connected to the pull-up node; the second reset transistor, the control terminal of the second reset transistor is connected to the display total reset signal, the first end of the second reset transistor is connected to the second end of the first reset transistor, the second end of the first noise reduction transistor, and the first end of the second noise reduction transistor, and the second end of the second reset transistor is connected to the first voltage terminal signal; the first reset protection transistor, the control terminal of the first reset protection transistor is connected to the pull-up node, and the first end of the first reset protection transistor is connected to the first power supply signal; the second reset protection transistor, the control terminal of the second reset protection transistor is connected to the pull-up node, the first end of the second reset protection transistor is connected to the second end of the first reset protection transistor, and the second end of the second reset protection transistor is connected to the second end of the first reset transistor and the first end of the second reset transistor.

[0025] In some embodiments, a second stabilizing circuit is also included, comprising: a first total reset transistor, the control terminal of which is connected to a total reset signal, and a first terminal of which is connected to the pull-up node; and a second total reset transistor, the control terminal of which is connected to the total reset signal, and a first terminal of which is connected to a second terminal of the first total reset transistor, a first terminal of the second noise reduction transistor, a second terminal of the first noise reduction transistor, a second terminal of the second reset protection transistor, a second terminal of the first reset transistor, and a first terminal of the second reset transistor, and a second terminal of which is connected to the first power supply signal.

[0026] In some embodiments, the pull-down node control circuit includes: a first pull-up transistor, the control terminal and a first terminal of the first pull-up transistor being connected to a second power supply signal; a second pull-up transistor, the control terminal of the second pull-up transistor being connected to the second power supply signal, and the first terminal of the second pull-up transistor being connected to the second terminal of the first pull-up transistor; a pull-down transistor, the control terminal of the pull-down transistor being connected to the pull-up node, the first terminal of the pull-down transistor being connected to the second terminal of the second pull-up transistor, and the second terminal of the pull-down transistor being connected to a second voltage terminal signal; a first inverting transistor, the control terminal of the first inverting transistor being connected to the second terminal of the second pull-up transistor and the first terminal of the pull-down transistor, the first terminal of the first inverting transistor being connected to the second power supply signal, and the second terminal of the first inverting transistor being connected to the pull-down node; and a second inverting transistor, the control terminal of the second inverting transistor being connected to the pull-up node, the first terminal of the second inverting transistor being connected to the pull-down node, and the second terminal of the second inverting transistor being connected to a first voltage terminal signal.

[0027] In some embodiments, the connection point of the first sensing transistor and the second sensing transistor is connected to the connection point of the first noise reduction transistor and the second noise reduction transistor.

[0028] In some embodiments, the induction compensation circuit further includes a sustaining sub-circuit configured to maintain the level of the control terminal of the induction transistor under the control of a fifth control signal.

[0029] In some embodiments, the sustaining sub-circuit includes: a first sustaining transistor connected in series between the pull-down node and the second inverting transistor; the control terminal of the first sustaining transistor is connected to the fifth control signal, a first terminal of the first sustaining transistor is connected to the pull-down node, and a second terminal of the first sustaining transistor is connected to the first terminal of the second inverting transistor.

[0030] In some embodiments, the sustaining sub-circuit further includes: a second sustaining transistor connected in series between the second pull-up transistor and the pull-down transistor; the control terminal of the second sustaining transistor is connected to the fifth control signal, the first terminal of the second sustaining transistor is connected to the second terminal of the second pull-up transistor, and the second terminal of the second sustaining transistor is connected to the first terminal of the pull-down transistor.

[0031] In some embodiments, the sustaining sub-circuit includes: a third sustaining transistor connected in series between the pull-down node and the control terminal of the sensing transistor; the control terminal of the third sustaining transistor is connected to the fifth control signal, a first terminal of the third sustaining transistor is connected to the pull-down node, and a second terminal of the third sustaining transistor is connected to the control terminal of the sensing transistor; and a fourth sustaining transistor, the control terminal of the fourth sustaining transistor is connected to the first control signal, a first terminal of the fourth sustaining transistor is connected to a sixth control signal, and a second terminal of the fourth sustaining transistor is connected to the second terminal of the third sustaining transistor and the control terminal of the sensing transistor.

[0032] In some implementations, the sixth control signal shares the same signal line as the second power signal.

[0033] In some embodiments, the output circuit includes at least one output sub-circuit, and the composite signal includes the output signals of each of the output sub-circuits in the output circuit; each output sub-circuit includes: a first output transistor, the control terminal of the first output transistor being connected to the pull-up node, a first terminal of the first output transistor being connected to a clock signal, and a second terminal of the first output transistor outputting the output signal of the output sub-circuit; an output capacitor, the first terminal of the output capacitor being connected to the pull-up node and the control terminal of the first output transistor, and the second terminal of the output capacitor being connected to the second terminal of the first output transistor; and a second output transistor, the control terminal of the second output transistor being connected to the pull-down node, the first terminal of the second output transistor being connected to the second terminal of the first output transistor, and the second terminal of the second output transistor being connected to a first voltage terminal signal.

[0034] In some embodiments, a pull-down node stabilization circuit is also included, the pull-down node stabilization circuit comprising: an initial inverting transistor, the control terminal of the initial inverting transistor being connected to a charging input signal, the first terminal of the initial inverting transistor being connected to the pull-down node, and the second terminal of the initial inverting transistor being connected to the first voltage terminal signal.

[0035] In some embodiments, a selection compensation circuit is further included. The selection compensation circuit includes a charging sub-circuit, comprising a charging capacitor, a first charging transistor, a second charging transistor, and a third charging transistor. A selection compensation control signal is connected to the first terminal of the charging capacitor, the control terminal of the first charging transistor, and the control terminal of the second charging transistor. A selection compensation control signal is connected to the second terminal of the charging capacitor. A pull-up control node is connected to the second terminal of the first charging transistor. A charging input signal is connected to the first terminal of the second charging transistor. The second terminal of the second charging transistor is connected to the pull-up control node. The control terminal of the third charging transistor is connected to the pull-up control node. A charging input signal is connected to the first terminal of the third charging transistor. A first power supply signal; the second terminal of the third charging transistor is connected to the second terminal of the first charging transistor and the first terminal of the second charging transistor; a storage sub-circuit includes a storage capacitor; the first terminal of the storage capacitor is connected to the first power supply signal, and the second terminal of the storage capacitor is connected to the pull-up control node; an isolation sub-circuit includes a first isolation transistor and a second isolation transistor; the control terminal of the first isolation transistor is connected to the pull-up control node, the first terminal of the first isolation transistor is connected to the first power supply signal, the control terminal of the second isolation transistor is connected to a sub-clock signal, the first terminal of the second isolation transistor is connected to the second terminal of the first isolation transistor, and the second terminal of the second isolation transistor is connected to the pull-up node.

[0036] In some embodiments, the pull-down node stabilization circuit further includes: a first discharge transistor, the control terminal of which is connected to the sub-clock signal, and a first terminal of which is connected to the pull-down node; and a second discharge transistor, the control terminal of which is connected to the pull-up control node, the first terminal of which is connected to the second terminal of the first discharge transistor, and the second terminal of which is connected to the first voltage terminal signal.

[0037] In a second aspect of this disclosure, a gate driving circuit is provided, the gate driving circuit including at least one first shift register and a plurality of second shift registers cascaded with the first shift register, wherein at least one of the first shift register and the second shift registers is a shift register as provided in the first aspect.

[0038] In some embodiments, the sensed signal carries the threshold voltage of the target transistor; when at least one of the first shift register and the second shift register includes a first stabilizing circuit as provided in the first aspect, the target transistor includes a first noise reduction transistor and a second noise reduction transistor in each of the shift registers; when at least one of the first shift register and the second shift register includes an output sub-circuit as provided in the first aspect, the target transistor includes a second output transistor in each of the shift registers.

[0039] In a third aspect of this disclosure, a display device is provided, the display device including a gate driving circuit as provided in the second aspect.

[0040] In a fourth aspect of this disclosure, a gate driving method is provided, the gate driving method comprising: pulling up the level of a pull-up node under the control of a charging input signal, and adjusting the level of a pull-down node based on the level of the pull-up node, the level of the pull-down node being opposite to the level of the pull-up node; outputting a composite signal based on the levels of the pull-up node and the pull-down node; pulling down the level of the pull-up node under the control of a display total reset signal, and adjusting the level of the pull-down node based on the level of the pull-up node; and outputting a sensing signal based on the level of the pull-down node to adjust the driving voltage of a target transistor, the sensing signal carrying a threshold voltage of the target transistor.

[0041] According to one or more embodiments of the present disclosure, the shift register, gate driving circuit, display device, and gate driving method are provided. By adding an inductive compensation circuit to output an inductive signal under the control of the electrical signal of the pull-down node, the threshold voltage bias of the target transistor can be simulated using the inductive compensation circuit. The threshold voltage of the target transistor is carried in the inductive signal, so the driving voltage of the target transistor can be adjusted according to the threshold voltage of the target transistor to compensate for the voltage bias of the target transistor. In this way, when the threshold voltage of some transistors (i.e., the target transistor) in the GOA is positively offset, the inductive compensation circuit can understand the change in the threshold voltage of the target transistor, and then dynamically compensate the driving voltage of the target transistor according to the threshold voltage of the target transistor, so as to achieve accurate driving of the target transistor and ultimately improve the accuracy of the GOA output scan signal. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 shows a schematic diagram of the structure of a shift register in one or more embodiments of the present disclosure.

[0044] Figure 2 shows the block diagram of each module in the shift register of Figure 1.

[0045] Figure 3 shows the circuit diagram of each module in the shift register of Figure 2.

[0046] Figure 4 shows the timing diagram of some signals in the shift register of Figure 3.

[0047] Figure 5 shows the circuit diagram of the transmission signal during the blanking phase of Figure 4.

[0048] Figure 6 shows the circuit diagram of the first stage of signal transmission in Figure 4.

[0049] Figure 7 shows the circuit diagram of the second stage of the scanning signal transmission in Figure 4.

[0050] Figure 8 shows the circuit diagram of the third stage of the scanning signal transmission in Figure 4.

[0051] Figure 9 shows the timing diagram of the relevant signals of the induction compensation circuit in Figure 3.

[0052] Figure 10 shows another timing diagram of the signals related to the induction compensation circuit in Figure 3.

[0053] Figure 11 shows another block diagram of the shift register in Figure 1.

[0054] Figure 12 shows the circuit diagram of the shift register in Figure 11.

[0055] Figure 13 shows the timing diagram of the relevant signals of the induction compensation circuit in Figure 12.

[0056] Figure 14 shows another block diagram of the shift register in Figure 1.

[0057] Figure 15 shows the circuit diagram of the shift register in Figure 14.

[0058] Figure 16 shows the timing diagram of the relevant signals of the induction compensation circuit in Figure 15.

[0059] Figure 17 shows another circuit diagram of the shift register in Figure 1.

[0060] Figure 18 shows another circuit diagram of the shift register of Figure 1.

[0061] Figure 19 shows another circuit diagram of the shift register of Figure 1.

[0062] Figure 20 shows the timing diagram of the signals related to the induction compensation circuit in Figures 18 and 19.

[0063] Figure 21 shows another circuit diagram of the shift register of Figure 1.

[0064] Figure 22 shows the timing diagram of the relevant signals of the induction compensation circuit in Figure 21.

[0065] Figure 23 shows another timing diagram of the signals related to the induction compensation circuit in Figure 21.

[0066] Figure 24 shows another timing diagram of the signals related to the induction compensation circuit in Figure 21.

[0067] Figure 25 shows a simulation diagram of the shift register portion of the signal in Figure 3.

[0068] Figure 26 shows a schematic diagram of the gate drive circuit in one or more embodiments of the present disclosure.

[0069] Figure 27 shows a partial block diagram of the first shift register in Figure 26.

[0070] Figure 28 shows a partial block diagram of the second shift register in Figure 26.

[0071] Figure 29 shows a circuit diagram of the second shift register in Figure 28.

[0072] Figure 30 shows another circuit diagram of the second shift register in Figure 28.

[0073] Figure 31 shows a flowchart of a gate driving method in one or more embodiments of the present disclosure.

[0074] Figure reference numerals: 10: Pull-up node control circuit; 11: Input sub-circuit; 12: Reset sub-circuit; 13: Input protection sub-circuit; 14: Reset protection sub-circuit; 20: Pull-down node control circuit; 21: First inverting sub-circuit; 22: Second inverting sub-circuit; 30: Output circuit; 31: Output sub-circuit; 40: Induction compensation circuit; 41: Induction sub-circuit; 42: Output control sub-circuit; 43: Voltage regulation sub-circuit; 44: Voltage adjustment sub-circuit; 45: Induction control sub-circuit; 46: Holding sub-circuit; 50: First stabilizing circuit; 60: Second stabilizing circuit; 70: Pull-down node stabilizing circuit; 80: Selection compensation circuit; 81: Charging sub-circuit; 82: Storage sub-circuit; 83: Isolation sub-circuit; 84: Discharge circuit; 100: First shift register; 200: Second shift register. Detailed Implementation

[0075] To enable those skilled in the art to more clearly understand this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0076] AMOLED (Active-matrix organic light-emitting diode) products have advantages such as high contrast, wide viewing angle, and fast response speed, and are expected to replace LCDs as the mainstream choice for next-generation displays. In the pixel circuits of AMOLED products, due to process limitations, all designs use N-type TFTs (Thin Film Transistors). Since AMOLED products require EL (electroluminescent) devices to emit light, and the light-emitting current required by the EL devices is provided by the drive TFT, it is necessary to increase the consistency of EL device characteristics to ensure the uniformity of light emission in AMOLED products. This is usually achieved through external compensation using GOA (Glass Orifice). However, in related technologies, some transistors in the GOA are subjected to prolonged PBTS (Positive Bias Temperature Stress), causing a positive drift in the threshold voltage of the transistors, making it difficult for the GOA to accurately output scanning signals.

[0077] Figure 1 is a schematic diagram of the shift register structure in one or more embodiments of this disclosure. Referring to Figure 1, a first aspect embodiment of this disclosure provides a shift register including a pull-up node control circuit 10, a pull-down node control circuit 20, an output circuit 30, and an induction compensation circuit 40. The pull-up node control circuit 10 is configured to control the electrical signal of the pull-up node QA. The output circuit 30 includes a gate drive output terminal and is configured to output a composite signal to the gate drive output terminal under the control of the electrical signal of the pull-up node QA. The pull-down node control circuit 20 is configured to input a first voltage terminal signal VGL1 to the pull-down node QB under the control of the electrical signal of the pull-up node QA. The induction compensation circuit 40 is configured to output an induction signal Se under the control of the electrical signal of the pull-down node QB.

[0078] For example, the pull-up node control circuit 10 can control the electrical signal of pull-up node QA by pulling up the level of pull-up node QA under the control of the charging input signal STU, or by pulling down the level of pull-up node QA under the control of the display total reset signal STD. The pull-down node control circuit 20 is configured to adjust the level of pull-down node QB based on the level of pull-up node QA (the level of pull-down node QB is opposite to the level of pull-up node QA), which may include, but is not limited to, inputting the first voltage terminal signal VGL1 to pull-down node QB under the control of the electrical signal of pull-up node QA, and inputting the second power supply signal GVDD2 to pull-down node QB under the control of the electrical signal of pull-up node QA, that is, inputting the second power supply signal GVDD2 or the first voltage terminal signal VGL1 to pull-down node QB under the control of the electrical signal of pull-up node QA. The output circuit 30 is configured to output a composite signal based on the levels of the pull-up node QA and the pull-down node QB. This can include, but is not limited to, outputting a composite signal to the gate drive output terminal under the electrical signal control of the pull-up node QA. The induction compensation circuit 40 can simulate the threshold voltage bias of the target transistor, carrying the threshold voltage of the target transistor in the induction signal Se. Therefore, the drive voltage of the target transistor can be adjusted according to the induction signal Se to compensate for the voltage bias of the target transistor.

[0079] For example, the level of the pull-down node QB being opposite to the level of the pull-up node QA means that when the level of the pull-up node QA is high, the level of the pull-down node QB is low, and when the level of the pull-up node QA is low, the level of the pull-down node QB is high.

[0080] The aforementioned shift register includes a pull-up node control circuit 10, a pull-down node control circuit 20, an output circuit 30, and an induction compensation circuit 40. The pull-up node control circuit 10 pulls up the level of the pull-up node QA under the control of the charging input signal STU, or pulls down the level of the pull-up node QA under the control of the display total reset signal STD. The pull-down node control circuit 20 adjusts the level of the pull-down node QB based on the level of the pull-up node QA. The level of the pull-down node QB is opposite to the level of the pull-up node QA. The output circuit 30 outputs a composite signal based on the levels of the pull-up node QA and the pull-down node QB. In this way, the cascaded shift registers can realize the progressive scan driving function of GOA, which can reduce manufacturing costs and simplify the process, making the bezel of the display panel narrower. Furthermore, the induction compensation circuit 40 outputs an induction signal Se under the electrical signal control of the pull-down node QB. The induction compensation circuit 40 simulates the threshold voltage bias of the target transistor and carries the threshold voltage of the target transistor in the induction signal Se. Therefore, the driving voltage of the target transistor can be adjusted according to the threshold voltage of the target transistor to compensate for the voltage bias of the target transistor. In this way, when the threshold voltage of the target transistor shifts in the positive direction, the induction compensation circuit 40 can understand the change in the threshold voltage of the target transistor, and then dynamically compensate the driving voltage of the target transistor according to the threshold voltage of the target transistor, so as to achieve precise driving of the target transistor and ultimately improve the accuracy of the GOA output scan signal.

[0081] Figure 2 is a block diagram of the various modules in the shift register of Figure 1. Referring to Figure 2, in some embodiments, the pull-up node control circuit 10 may include an input sub-circuit 11 and a reset sub-circuit 12. The input sub-circuit 11 is configured to pull up the level of the pull-up node QA under the control of the charging input signal STU, such as inputting the first power signal GVDD1 to the pull-up node QA under the control of the charging input signal STU. The reset sub-circuit 12 is configured to pull down the level of the pull-up node QA under the control of the display total reset signal STD.

[0082] For example, the input sub-circuit 11 may include at least one input transistor, the control terminal of which is connected to a charging input signal STU. The input transistor is configured to turn on when the level of the charging input signal STU is higher than a threshold voltage, so that a first power supply signal GVDD1 is written to the pull-up node QA.

[0083] Figure 3 is a circuit diagram of each module in the shift register of Figure 2. Referring to Figure 3, at least one input transistor may include a first input transistor T1 and a second input transistor T2. The first terminal of the first input transistor T1 is connected to the first power supply signal GVDD1. The first terminal of the second input transistor T2 is connected to the first terminal of the first input transistor T1. The second terminal of the second input transistor T2 is connected to the pull-up node QA.

[0084] Referring to Figure 2, the pull-up node control circuit 10 may further include an input protection sub-circuit 13. The input protection sub-circuit 13 is configured to write a first power supply signal GVDD1 to the connection point of the first input transistor T1 and the second input transistor T2 when the level of the pull-down node QB is higher than a threshold voltage.

[0085] Since the levels of pull-down node QB and pull-up node QA are opposite, when the level of pull-down node QB is higher than the threshold voltage, the level of pull-up node QA is lower than the threshold voltage. At this time, although the first input transistor T1 and the second input transistor T2 are in the off state, the input terminal of the first power signal GVDD1 can leak to the pull-up node QA through the first input transistor T1 and the second input transistor T2. Here, when the level of pull-down node QB is higher than the threshold voltage, the input protection sub-circuit 13 writes the first power signal GVDD1 to the connection point of the first input transistor T1 and the second input transistor T2. Both the first and second terminals of the first input transistor T1 are connected to the first power signal GVDD1, and the voltages of the first and second terminals of the first input transistor T1 are the same, preventing the first power signal GVDD1 from leaking to the pull-up node QA through the first input transistor T1 and the second input transistor T2, significantly reducing the leakage current of the shift register in this stage.

[0086] Referring to Figure 3, the input protection sub-circuit 13 may include an input protection transistor T3, the control terminal of which is connected to a pull-down node QB. The input protection transistor T3 is configured to write a first power supply signal GVDD1 to the connection point of the first input transistor T1 and the second input transistor T2 when the level of the pull-down node QB is higher than a threshold voltage.

[0087] The first terminal of the input protection transistor T3 is connected to the first power supply signal GVDD1, and the second terminal of the input protection transistor T3 is connected to the second terminal of the first input transistor T1 and the first terminal of the second input transistor T2.

[0088] For example, the reset sub-circuit 12 may include at least one reset transistor, the control terminal of which is connected to the display total reset signal STD. The reset transistor is configured to turn on when the level of the display total reset signal STD is higher than a threshold voltage, so that the first voltage terminal signal VGL1 is written to the pull-up node QA.

[0089] Please refer to Figure 3. At least one reset transistor may include a first reset transistor T4 and a second reset transistor T5. The first terminal of the first reset transistor T4 is connected to the pull-up node QA, the first terminal of the second reset transistor T5 is connected to the second terminal of the first reset transistor T4, and the second terminal of the second reset transistor T5 is connected to the first voltage terminal signal VGL1.

[0090] Referring to Figure 2, the pull-up node control circuit 10 may further include a reset protection sub-circuit 14. The reset protection sub-circuit 14 is configured to control the pull-up synchronization node Q3 with electrical signals under the control of the pull-up node QA. For example, when the level of the pull-up node QA is higher than the threshold voltage, the first power supply signal GVDD1 is written to the connection point of the first reset transistor T4 and the second reset transistor T5 (i.e., the pull-up synchronization node Q3).

[0091] Since the levels of pull-down node QB and pull-up node QA are opposite, when the level of pull-up node QA is higher than the threshold voltage, the level of pull-down node QB is at the threshold voltage. At this time, although the first reset transistor T4 and the second reset transistor T5 are in the off state, pull-up node QA can still leak through the first reset transistor T4 and the second reset transistor T5 to the input terminal of the first voltage terminal signal VGL. Here, when the level of pull-up node QA is higher than the threshold voltage, the reset protection sub-circuit 14 writes the first power supply signal GVDD1 to the connection point of the first reset transistor T4 and the second reset transistor T5. Both the first and second terminals of the first reset transistor T4 are connected to the first power supply signal GVDD1, and the voltages of the first and second terminals of the first reset transistor T4 are the same, preventing pull-up node QA from leaking through the first reset transistor T4 and the second reset transistor T5 to the input terminal of the first voltage terminal signal VGL, significantly reducing the leakage current of the shift register in this stage.

[0092] The reset protection sub-circuit 14 may include at least one reset protection transistor, the control terminal of which is connected to the pull-up node QA. The reset protection transistor is configured to turn on when the level of the pull-up node QA is higher than a threshold voltage, so that the first power supply signal GVDD1 is written to the connection point of the first reset transistor T4 and the second reset transistor T5.

[0093] Referring to Figure 3, at least one reset protection transistor may include a first reset protection transistor T6 and a second reset protection transistor T7. The first terminal of the first reset protection transistor T6 is connected to the first power supply signal GVDD1. The first terminal of the second reset transistor T7 is connected to the second terminal of the first reset protection transistor T6, and the second terminal of the second reset transistor T7 is connected to the second terminal of the first reset transistor T4 and the first terminal of the second reset transistor T5. By implementing the reset protection sub-circuit 14 through the series connection of two reset protection transistors, the reliability of the reset protection sub-circuit 14 can be improved.

[0094] In some embodiments, referring to FIG2, the shift register may further include a first stabilizing circuit 50, which is configured to electrically control the pull-up node QA under the electrical signal control of the pull-down node QB, such as pulling down the level of the pull-up node QA when the level of the pull-down node QB is higher than a threshold voltage. By adding the first stabilizing circuit 50 to pull down the level of the pull-up node QA when the level of the pull-down node QB is higher than the threshold voltage, it can cooperate with the reset sub-circuit 13 to ensure that the level of the pull-up node QA is pulled down.

[0095] For example, the first stabilizing circuit 50 can be connected to the pull-up synchronizing node Q3, and can also be configured to electrically control the pull-up synchronizing node Q3 under the electrical signal control of the pull-down node QB.

[0096] For example, the first stabilization circuit 50 may include at least one noise reduction transistor, the control terminal of which is connected to the pull-down node QB. The noise reduction transistor is configured to turn on when the level of the pull-down node QB is higher than a threshold voltage, so as to write the first voltage terminal signal VGL1 into the pull-up node QA.

[0097] Referring to Figure 3, at least one noise reduction transistor may include a first noise reduction transistor T8 and a second noise reduction transistor T9. The first terminal of the first noise reduction transistor T8 is connected to the pull-up node QA. The first terminal of the second noise reduction transistor T9 is connected to the second terminal of the first noise reduction transistor T8, the second terminal of the second reset transistor T7, the second terminal of the first reset transistor T4, and the first terminal of the second reset transistor T5. The second terminal of the second noise reduction transistor T9 is connected to the first voltage terminal signal VGL1. By implementing the first stabilization circuit 50 through the series connection of two noise reduction transistors, the reliability of the first stabilization circuit 50 can be improved.

[0098] For example, when the shift register includes the first stabilization circuit 50, the target transistor may include each noise reduction transistor in the first stabilization circuit 50.

[0099] In some embodiments, referring to FIG2, the shift register may further include a second stabilizing circuit 60, which is configured to pull down the level of the pull-up node QA under the control of the total reset signal TRS. The second stabilizing circuit 60 and the reset sub-circuit 13 can be reset at different stages. The reset sub-circuit 13 can reset only the shift register after a row of pixel sub-circuits has been scanned, while the second stabilizing circuit 60 can reset all shift registers after a frame of image has been scanned.

[0100] For example, the second stabilizing circuit 60 may include at least one total reset transistor, the control terminal of which is connected to a total reset signal TRS. The total reset transistor is configured to write a first voltage terminal signal VGL1 to the pull-up node QA under the control of the total reset signal TRS.

[0101] Referring to Figure 3, at least one total reset transistor may include a first total reset transistor T10 and a second total reset transistor T11. The first terminal of the first total reset transistor T10 is connected to the pull-up node QA. The first terminal of the second total reset transistor T11 is connected to the second terminal of the first total reset transistor T10, the first terminal of the second noise reduction transistor T9, the second terminal of the first noise reduction transistor T8, the second terminal of the second reset protection transistor T7, the second terminal of the first reset transistor T4, and the first terminal of the second reset transistor T5. The second terminal of the second total reset transistor T11 is connected to the first voltage terminal signal VGL1. By implementing the second stabilization circuit 60 through the series connection of two total reset transistors, the reliability of the second stabilization circuit 60 can be improved.

[0102] In some embodiments, referring to FIG2, the pull-down node control circuit 20 may include a first inverting sub-circuit 21 and a second inverting sub-circuit 22. The first inverting sub-circuit 21 is configured to adjust the level of a first node Q1 based on the level of a pull-up node QA, wherein the level of the first node Q1 is opposite to the level of the pull-up node QA. The second inverting sub-circuit 22 is configured to adjust the level of a pull-down node QB based on the level of the first node Q1 and the level of the pull-up node QA.

[0103] For example, the level of the first node Q1 being opposite to the level of the pull-up node QA means that when the level of the pull-up node QA is high, the level of the first node Q1 is low, and when the level of the pull-up node QA is low, the level of the first node Q1 is high.

[0104] By first adjusting the level of the first node Q1 based on the level of the pull-up node QA, the level of the first node Q1 is opposite to the level of the pull-up node QA. Then, by adjusting the level of the pull-down node QB based on the levels of the first node Q1 and the pull-up node QA, it can be ensured that the level of the pull-down node QB is opposite to the level of the pull-up node QA.

[0105] For example, the first inverting sub-circuit 21 may include at least one pull-up transistor and one pull-down transistor. The control terminal of the pull-up transistor is connected to a second power supply signal GVDD2 and is configured to write the second power supply signal GVDD2 into the first node Q1. The control terminal of the pull-down transistor is connected to the pull-up node QA and is configured to write a second voltage terminal signal VGL2 into the first node Q1 when the level of the pull-up node QA is higher than a threshold voltage.

[0106] Referring to Figure 3, at least one pull-up transistor may include a first pull-up transistor T12 and a second pull-up transistor T13. The first terminal of the first pull-up transistor T12 is connected to the second power supply signal GVDD2. The first terminal of the second pull-up transistor T13 is connected to the second terminal of the first pull-up transistor T12, and the second terminal of the second pull-up transistor T13 is connected to the first node Q1. The first terminal of the pull-down transistor T14 is connected to the first node Q1, and the second terminal of the pull-down transistor T14 is connected to the second voltage terminal signal VGL2. By implementing the first inverting sub-circuit 21 through two pull-up transistors connected in series, the reliability of the first inverting sub-circuit 21 can be improved.

[0107] For example, the second inverting sub-circuit 22 may include a first inverting transistor and a second inverting transistor. The first inverting transistor is configured to write a second voltage terminal signal VGL2 into the pull-down node QB when the level of the first node Q1 is higher than a threshold voltage. The second inverting transistor is configured to write a first voltage terminal signal VGL1 into the pull-down node QB when the level of the pull-up node QA is higher than a threshold voltage.

[0108] Referring to Figure 3, the control terminal of the first inverting transistor T15 is connected to the first node Q1, the first terminal of the first inverting transistor T15 is connected to the second power supply signal GVDD2, and the second terminal of the first inverting transistor T15 is connected to the pull-down node QB. The control terminal of the second inverting transistor T16 is connected to the pull-up node QA, the first terminal of the second inverting transistor T16 is connected to the pull-down node QB, and the second terminal of the second inverting transistor T16 is connected to the first voltage terminal signal VGL1.

[0109] For example, the voltage of the second power supply signal GVDD2 can be adjusted according to the threshold voltage of the target transistor, and the level of the pull-down node QB changes accordingly, thereby compensating the drive voltage of the target transistor (such as the first noise reduction transistor T8 and the second noise reduction transistor T9).

[0110] In some embodiments, referring to FIG2, the shift register may further include a pull-down node stabilization circuit 70. The pull-down node stabilization circuit 70 is configured to write the first voltage terminal signal VGL1 into the pull-down node QB under the control of the charging input signal STU. Since the input sub-circuit 11 writes the first power supply signal GVDD1 into the pull-up node QA under the control of the charging input signal STU, by adding the pull-down node stabilization circuit 70, the first voltage terminal signal VGL1 can be written into the pull-down node QB under the control of the charging input signal STU. This can cooperate with the pull-down node control circuit 20 to ensure that the pull-down node QB is low when the pull-up node QA is high.

[0111] For example, the pull-down node stabilization circuit 70 may include an initial inverting transistor, the control terminal of which is connected to the charging input signal STU. The initial inverting transistor is configured to turn on when the level of the charging input signal STU is higher than a threshold voltage, so that a first voltage terminal signal VGL1 is written to the pull-down node QB.

[0112] Please refer to Figure 3. The first terminal of the initial inverting transistor T17 is connected to the pull-down node QB, and the second terminal of the initial inverting transistor T17 is connected to the first voltage terminal signal VGL1.

[0113] In some embodiments, referring to FIG2, the output circuit 30 may include at least one output sub-circuit 31, and the composite signal includes the output signal OUT of each output sub-circuit 31 in the output circuit 30. The output sub-circuit 31 is configured to generate and output the output signal OUT based on the level of the pull-up node QA and the level of the pull-down node QB, using the clock signal CLKD.

[0114] For example, the clock signal CLKD input to the output sub-circuit 31 can be different for each circuit. Accordingly, the output signal OUT of the output sub-circuit 31 can be different for each circuit.

[0115] When the shift register is driving GOA, the output circuit 30 of the shift register may include multiple output sub-circuits 31. The composite signal OUT output by one output sub-circuit 31 serves as the charging input signal STU and / or the display total reset signal STD of other shift registers cascaded with the shift register. The composite signals OUT output by other output sub-circuits 31 serve as the scanning signals of at least one row of pixel sub-circuits. The composite signals OUT output by different output sub-circuits 31 serve as the scanning signals of different rows of pixel sub-circuits.

[0116] When the shift register is a dummy GOA, the output circuit 30 of the shift register may include only one output sub-circuit 31. The composite signal OUT output by the output sub-circuit 31 serves as the charging input signal STU and / or the display total reset signal STD for other shift registers cascaded with the shift register. Alternatively, the output circuit 30 may include multiple output sub-circuits 31. The composite signal OUT output by one output sub-circuit 31 serves as the charging input signal STU and / or the display total reset signal STD for other shift registers cascaded with the shift register, while the composite signals OUT output by other output sub-circuits 31 are not used as the scanning signal for the pixel sub-circuit.

[0117] For example, the shift register can be a dummy GOA.

[0118] The output sub-circuit 31 may include a first output transistor, an output capacitor, and a second output transistor. The control terminal of the first output transistor is connected to a pull-up node QA and is configured to conduct when the level of pull-up node QA is higher than a threshold voltage, thereby outputting the composite signal OUT. The output capacitor is configured to further pull up the level of pull-up node QA, so that the level of pull-up node QA is higher than the threshold voltage. The control terminal of the second output transistor is connected to a pull-down node QB and is configured to conduct when the level of pull-down node QB is higher than the threshold voltage, thereby resetting the composite signal OUT.

[0119] Referring to Figure 3, the first terminal of the first output transistor T18 is connected to the clock signal CLKD, and the composite signal OUT is output through the second terminal of the first output transistor. The first terminal of the output capacitor C1 is connected to the pull-up node QA and the control terminal of the first output transistor T18, and the second terminal of the output capacitor C1 is connected to the second terminal of the first output transistor T18. The first terminal of the second output transistor T19 is connected to the second terminal of the first output transistor T18, and the second terminal of the second output transistor T19 is connected to the first voltage terminal signal VGL1.

[0120] For example, when the output circuit 30 includes at least one output sub-circuit 31, the target transistor may include a second output transistor T19 in each of the output sub-circuits 31.

[0121] Figure 4 shows the timing diagram of some signals in the shift register of Figure 3. Figure 5 shows the circuit diagram of the signal transmission during the blanking stage of Figure 4. Figure 6 shows the circuit diagram of the signal transmission during the first scanning stage of Figure 4. Figure 7 shows the circuit diagram of the signal transmission during the second scanning stage of Figure 4. Figure 8 shows the circuit diagram of the signal transmission during the third scanning stage of Figure 4. Arrows in Figures 5-8 indicate the direction of signal transmission at each stage, and solid lines represent conducting transistors, while dashed lines represent cut-off transistors. The following is a brief introduction to part of the shift register's operation, based on Figures 4-8.

[0122] Please refer to Figures 4 and 5. During the blanking phase, the charging input signal STU is low, the first input transistor T1 and the second input transistor T2 are off, and the initial inverter transistor T17 is off. The total reset signal STD is low, and the first reset transistor T4 and the second reset transistor T5 are off.

[0123] When the total reset signal TRS is high, the first total reset transistor T10 and the second total reset transistor T11 are turned on, and the first voltage terminal signal VGL1 is written to the pull-up node QA as low.

[0124] When pull-up node QA is low, the first reset protection transistor T6 and the second reset protection transistor T7 are off, and the pull-down transistor T14 and the second inverter transistor T16 are off. The first pull-up transistor T12 and the second pull-up transistor T13 are on, and the second power supply signal GVDD2 is written to the first node Q1, making Q1 high. When Q1 is high, the first inverter transistor T15 is on, and the second power supply signal GVDD2 is written to the pull-down node QB, making QB high.

[0125] When the pull-down node QB is high, the input protection transistor T3 is turned on, and the first power supply signal GVDD1 is written to the second node Q2 (i.e., the connection point between the first input transistor T1 and the second input transistor T2), making the second node Q2 high. Both the first and second terminals of the first input transistor T1 are connected to the first power supply signal GVDD1, and the voltages at the first and second terminals of the first input transistor T1 are the same. This prevents leakage from the first input transistor T1 from affecting the pull-up node QA to be low, and consequently affecting the pull-down node QB to be high.

[0126] When the pull-down node QB is high, the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned on, and the first voltage terminal signal VGL1 is written to the pull-up node QA, so the pull-up node QA is low.

[0127] When the pull-up node QA is low, the first output transistor T18 is off. When the pull-down node QB is high, the second output transistor T19 is on, and the first voltage terminal signal VGL1 is output. Therefore, the composite signal OUT is low.

[0128] Referring to Figures 4 and 6, in the first scanning stage, the charging input signal STU is high, the first input transistor T1 and the second input transistor T2 are turned on, and the first power supply signal GVDD1 is written to the pull-up node QA, making pull-up node QA high. Simultaneously, the initial inverting transistor T17 is turned on, and the first voltage terminal signal VGL1 is written to the pull-down node QB, making pull-down node QB low. With pull-down node QB low, the input protection transistor T3 is turned off.

[0129] The display shows that the overall reset signal STD is low, and the first reset transistor T4 and the second reset transistor T5 are off. The pull-up node QA is high, and the first reset protection transistor T6 and the second reset protection transistor T7 are on. The first power supply signal GVDD1 is written to the pull-up synchronization node Q3 (the connection point of the first reset transistor T4 and the second reset transistor T5), making the pull-up synchronization node Q3 high. Both the first and second terminals of the first reset transistor T4 are connected to the first power supply signal GVDD1, and the voltages at the first and second terminals of the first reset transistor T4 are the same, preventing leakage from the first reset transistor T4 from affecting the high level of the pull-up node QA.

[0130] The first pull-up transistor T12 and the second pull-up transistor T13 are turned on, and the second power supply signal GVDD2 is written to the first node Q1. Simultaneously, pull-up node QA is at a high level, pull-down transistor T14 is turned on, and the second voltage terminal signal VGL2 is written to the first node Q1. Therefore, the voltage level of the first node Q1 is lower than the threshold voltage, and the first inverting transistor T15 is turned off. When pull-up node QA is at a high level, the second inverting transistor T16 is turned on, and the first voltage terminal signal VGL1 is written to the pull-down node QB, making the pull-down node QB low.

[0131] When the pull-down node QB is low, the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned off. Additionally, when the total reset signal TRS is low, the first total reset transistor T10 and the second total reset transistor T11 are turned off.

[0132] Pull-up node QA is high, but the threshold voltage of the first output transistor T18 is not reached, so the first output transistor T18 is off. Pull-down node QB is low, and the second output transistor T19 is off. Therefore, the composite signal OUT is low.

[0133] Referring to Figures 4 and 7, in the second scanning stage, the charging input signal STU is low, the first input transistor T1 and the second input transistor T2 are off, and the pull-up node QA remains high. Furthermore, the initial inverting transistor T17 is off, and the pull-down node QB remains low. With the pull-down node QB low, the input protection transistor T3 is off.

[0134] The display shows that the total reset signal STD is low, and the first reset transistor T4 and the second reset transistor T5 are off. The pull-up node QA is high, and the first reset protection transistor T6 and the second reset protection transistor T7 are on. The first power supply signal GVDD1 is written to the pull-up synchronization node Q3, making Q3 high. Both the first and second terminals of the first reset transistor T4 are connected to the first power supply signal GVDD1, and the voltages at the first and second terminals of the first reset transistor T4 are the same, preventing leakage of the first reset transistor T4.

[0135] The first pull-up transistor T12 and the second pull-up transistor T13 are turned on, and the second power supply signal GVDD2 is written to the first node Q1. Simultaneously, pull-up node QA is at a high level, pull-down transistor T14 is turned on, and the second voltage terminal signal VGL2 is written to the first node Q1. Therefore, the voltage level of the first node Q1 is lower than the threshold voltage, and the first inverting transistor T15 is turned off. When pull-up node QA is at a high level, the second inverting transistor T16 is turned on, and the first voltage terminal signal VGL1 is written to the pull-down node QB, making the pull-down node QB low.

[0136] When the pull-down node QB is low, the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned off. Additionally, when the total reset signal TRS is low, the first total reset transistor T10 and the second total reset transistor T11 are turned off.

[0137] When the clock signal CLKD is high, the output capacitor further pulls up the level of the pull-up node QA. Since the level of pull-up node QA is higher than the threshold voltage of the first output transistor T18, the first output transistor T18 is turned on, and the clock signal CLKD is output. Therefore, the composite signal OUT is high.

[0138] Please refer to Figures 4 and 8. In the third stage of scanning, the charging input signal STU is low, the first input transistor T1 and the second input transistor T2 are turned off, and the initial inverting transistor T17 is turned off.

[0139] When the overall reset signal STD is high, the first reset transistor T4 and the second reset transistor T5 are turned on. The first voltage terminal signal VGL1 is written to the pull-up sync node Q3 and the pull-up node QA, making the pull-up sync node Q3 and the pull-up node QA low. When the pull-up node QA is low, the first reset protection transistor T6 and the second reset protection transistor T7 are turned off.

[0140] When pull-up node QA is low, pull-down transistor T14 and the second inverter transistor T16 are off. First pull-up transistor T12 and second pull-up transistor T13 are on, and the second power supply signal GVDD2 is written to first node Q1, making first node Q1 high. When first node Q1 is high, first inverter transistor T15 is on, and the second power supply signal GVDD2 is written to pull-down node QB, making pull-down node QB high.

[0141] When the pull-down node QB is high, the input protection transistor T3 is turned on, and the first power supply signal GVDD1 is written to the second node Q2, making the second node Q2 high. Both the first and second terminals of the first input transistor T1 are connected to the first power supply signal GVDD1, and the voltages at the first and second terminals of the first input transistor T1 are the same, preventing leakage of the first input transistor T1.

[0142] When the pull-down node QB is high, the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned on, and the first voltage terminal signal VGL1 is written to the pull-up node QA, making the pull-up node QA low. Additionally, the total reset signal TRS is low, and the first total reset transistor T10 and the second total reset transistor T11 are turned off.

[0143] When the pull-up node QA is low, the first output transistor T18 is off. When the pull-down node QB is high, the second output transistor T19 is on, and the first voltage terminal signal VGL1 is output. Therefore, the composite signal OUT is low.

[0144] Based on the above, the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 are all subjected to prolonged PBTS, which will cause the threshold voltage to shift in the positive direction, making it difficult for the shift register to accurately output the composite signal OUT.

[0145] In some embodiments, referring to FIG2, the induction compensation circuit 40 may include an induction sub-circuit 41. The induction sub-circuit 41 is configured to generate an induction signal Se based on a first control signal DCLK1 when the level of the pull-down node QB is higher than a threshold voltage.

[0146] The first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 are all turned on when the level of the pull-down node QB is higher than the threshold voltage. The sensing sub-circuit 41 is configured to generate a sensing signal Se based on the first control signal DCLK1 when the level of the pull-down node QB is higher than the threshold voltage. The sensing signal Se can carry the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 (i.e., the threshold voltage of the target transistor), thereby adjusting the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 (i.e., the voltage of the second power supply signal GVDD2) to compensate for the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 that has shifted positively, so that the shift register can accurately output the composite signal OUT.

[0147] For example, the sensing sub-circuit 41 may include at least one sensing transistor, the control terminal of which is connected to a pull-down node QB. The sensing transistor is configured to turn on when the level of the pull-down node QB is higher than a threshold voltage, so that the first control signal DCLK1 passes through the sensing transistor to generate a sensing signal Se.

[0148] The sensing sub-circuit 41 includes at least one sensing transistor. The control terminal of the sensing transistor is connected to the pull-down node QB. The sensing transistor is configured to turn on when the level of the pull-down node QB is higher than the threshold voltage. Similar to the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, the threshold voltage change of the sensing transistor can reflect the threshold voltage change of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19. This allows for adjustment of the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 to compensate for the positive offset of the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, enabling the shift register to accurately output the composite signal.

[0149] Please refer to Figure 3. At least one sensing transistor may include a first sensing transistor T20 and a second sensing transistor T21. The first terminal of the first sensing transistor T20 is connected to the first control signal DCLK1. The first terminal of the second sensing transistor T21 is connected to the second terminal of the first sensing transistor T20. The sensing signal Se is output through the second terminal of the second sensing transistor T21.

[0150] The first sensing transistor T20 and the second sensing transistor T21 are connected in series, which is the same as the connection method of the first noise reduction transistor T8 and the second noise reduction transistor T9 connected in series. By changing the threshold voltage of the sensing transistors, the threshold voltage changes of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 can be more accurately reflected. This allows for more precise adjustment of the driving voltages of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, so as to better compensate for the positive offset threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, enabling the shift register to accurately output composite signals.

[0151] As exemplarily shown in Figure 2, the induction compensation circuit 40 may further include an output control sub-circuit 42. The output control sub-circuit 42 is configured to output the induction signal Se under the control of the second control signal DCLK2.

[0152] By adding an output control sub-circuit 42, the output of the sensing signal Se is controlled by the second control signal DCLK2. The output of the sensing signal Se can be controlled, and the sensing signal Se is only output during the blanking stage. This does not affect the level of each node during the scanning stage and avoids interference with the normal operation of the circuit (such as outputting composite signals).

[0153] Please refer to Figure 3. The output control sub-circuit 42 may include an output control transistor T22. The control terminal of the output control transistor T22 is connected to the second control signal DCLK2. The first terminal of the output control transistor T22 is connected to the second terminal of the second sensing transistor T21. The sensing signal Se is output through the second terminal of the output control transistor T22.

[0154] The control terminal of the output control transistor T22 is connected to the second control signal DCLK2. The first terminal of the output control transistor T22 is connected to the second terminal of the second sensing transistor T21. The sensing signal Se is output through the second terminal of the output control transistor T22. Thus, the output control transistor T22 is turned on when the level of the second control signal DCLK2 is higher than the threshold voltage, so as to output the sensing signal Se.

[0155] Figure 9 is a timing diagram of the relevant signals of the induction compensation circuit in Figure 3. Referring to Figure 9, for example, the first control signal DCLK1 can be a delayed signal of the second control signal DCLK2.

[0156] The second control signal DCLK2 is initially high, turning on the output control transistor T22. At this time, the first control signal DCLK1 is low, therefore the sensing signal Se is low, resetting the sensing signal Se. The first control signal DCLK1 then changes from low to high, at which point the sensing signal Se is high, carrying the threshold voltage of the sensing transistor.

[0157] The voltage of the second power supply signal GVDD2 is less than 10V, so the voltage of the pull-down node QB is less than 10V. Meanwhile, the high level of the first control signal DCLK1 is 20V to 24V, causing the sensing transistor to operate in the saturation region. As the voltage of the sensing signal Se gradually increases to the point where the voltage of the pull-down node QB minus the threshold voltage of the sensing transistor, the sensing transistor turns off, thus obtaining the threshold voltage of the sensing transistor.

[0158] Figure 10 is another timing diagram of the related signals of the induction compensation circuit in Figure 3. Referring to Figure 10, for example, the first control signal DCLK1 and the selection compensation control signal OE can share the same signal line. The selection compensation control signal OE is a control signal for compensating the composite signal.

[0159] By sharing the same signal line with the selection compensation control signal OE, the first control signal DCLK1 does not need to have an additional signal line, which can reduce the number of signal lines.

[0160] In one possible embodiment, referring to FIG2, the induction compensation circuit 40 may further include a voltage regulator sub-circuit 43. The voltage regulator sub-circuit 43 is configured to stabilize the level of the pull-down node QB when the level of the first control signal DCLK1 changes.

[0161] By adding a voltage regulator circuit 43 to stabilize the level of the pull-down node QB when the level of the first control signal DCLK1 changes, the level change of the first control signal DCLK1 can be prevented from affecting the level of the pull-up node QA, thus ensuring the compensation accuracy.

[0162] For example, referring to Figure 3, the voltage regulator sub-circuit 43 may include a voltage regulator capacitor C2. The first end of the voltage regulator capacitor C2 is connected to the pull-down node QB, and the second end of the voltage regulator capacitor C2 is connected to the second voltage terminal signal VGL2.

[0163] The first end of the voltage regulator capacitor C2 is connected to the pull-down node QB, and the second end of the voltage regulator capacitor C2 is connected to the second voltage terminal signal VGL2, which can stabilize the level of the pull-down node QB when the level of the first control signal DCLK1 changes.

[0164] Figure 11 is another structural block diagram of the shift register of Figure 1. Referring to Figure 11, in another possible embodiment, the induction compensation circuit 40 may further include a voltage regulating sub-circuit 44. The voltage regulating sub-circuit 44 is configured to adjust the level of the pull-down node QB under the control of the third control signal DCLK3.

[0165] By adding a voltage regulating sub-circuit 44 to adjust the level of the pull-down node QB under the control of the third control signal DCLK3, the voltage range of the sensing signal Se can be controlled, ensuring the accuracy of the sensing signal Se.

[0166] Figure 12 is a circuit diagram of the shift register in Figure 11. Referring to Figure 12, for example, the voltage regulating sub-circuit 44 may include a voltage regulating transistor T23. The control terminal of the voltage regulating transistor T23 is connected to the third control signal DCLK3. The first terminal of the voltage regulating transistor T23 is connected to the pull-down node QB. The second terminal of the voltage regulating transistor T23 is connected to the first voltage terminal signal VGL1.

[0167] The first terminal of the voltage regulator transistor T23 is connected to the pull-down node QB, and the second terminal of the voltage regulator transistor T23 is connected to the first voltage terminal signal VGL1. It can be turned on under the control of the third control signal DCLK3, and the first voltage terminal signal VGL1 is written into the pull-down node QB. At this time, the first inverting transistor T15 is also turned on, and the second power supply signal GVDD2 is also written into the pull-down node QB. The first inverting transistor T15 and the voltage regulator transistor T23 perform voltage division, so the level of the pull-down node QB can be adjusted.

[0168] Figure 13 is a timing diagram of the relevant signals of the induction compensation circuit in Figure 12. Please refer to Figure 13. The third control signal DCLK3 can be the same as the first control signal DCLK1.

[0169] For example, the third control signal DCLK3 and the first control signal DCLK1 can share the same signal line, reducing the number of signal lines.

[0170] Figure 14 is another structural block diagram of the shift register of Figure 1. Referring to Figure 14, in another possible embodiment, the induction compensation circuit 40 may further include an induction control sub-circuit 45. The induction control sub-circuit 45 is configured to connect the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 to the induction sub-circuit 41 under the control of the fourth control signal DCLK4.

[0171] By adding an induction control sub-circuit 45 under the control of the fourth control signal DCLK4, the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 is connected to the induction sub-circuit 41. Based on the overall changes of the first noise reduction transistor T8 and the second noise reduction transistor T9, the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be aligned. Therefore, the threshold voltage changes of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be better simulated, and the threshold voltage changes of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be more realistically reflected. This allows for more precise adjustment of the driving voltages of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, so as to better compensate for the positive offset threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, enabling the shift register to accurately output the composite signal OUT.

[0172] Figure 15 is a circuit diagram of the shift register in Figure 14. Referring to Figure 15, for example, the sensing control sub-circuit 45 may include a sensing control transistor T24. The control terminal of the sensing control transistor T24 is connected to the fourth control signal DCLK4. The first terminal of the sensing control transistor T24 is connected to the second terminal of the first noise reduction transistor T8 and the first terminal of the second noise reduction transistor T9. The second terminal of the sensing control transistor T24 is connected to the second terminal of the first sensing transistor T20 and the first terminal of the second sensing transistor T21.

[0173] The control terminal of the sensing control transistor T24 is connected to the fourth control signal DCLK4. The first terminal of the sensing control transistor T24 is connected to the second terminal of the first noise reduction transistor T8 and the first terminal of the second noise reduction transistor T9. The second terminal of the sensing control transistor T24 is connected to the second terminal of the first sensing transistor T20 and the first terminal of the second sensing transistor T21. Under the control of the fourth control signal DCLK4, the level of the connection point of the first sensing transistor T20 and the second sensing transistor T21 can be aligned with the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9. Thus, the threshold voltage change of the first sensing transistor T20 and the second sensing transistor T21 can better simulate the threshold voltage change of the first noise reduction transistor T8 and the second noise reduction transistor T9. This allows for more precise adjustment of the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, better compensating for the positive offset threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, enabling the shift register to accurately output the composite signal OUT.

[0174] Figure 16 is a timing diagram of the relevant signals of the induction compensation circuit in Figure 15. Referring to Figure 16, the fourth control signal DCLK4 is high during the scanning phase to align the connection level of the first sensing transistor T20 and the second sensing transistor T21 with the connection level of the first noise reduction transistor T8 and the second noise reduction transistor T9. The fourth control signal DCLK4 first goes low during the blanking phase and last goes high, preventing the sensing signal Se from affecting the connection level of the first sensing transistor T20 and the second sensing transistor T21.

[0175] In the above embodiment, the connection point of the first sensing transistor T20 and the second sensing transistor T21 is not connected to the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, which can prevent the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 from interfering with the threshold voltage of the target transistor of the sensing signal Se.

[0176] Figure 17 is another circuit diagram of the shift register in Figure 1. Referring to Figure 17, in some embodiments, the connection point of the first sensing transistor T20 and the second sensing transistor T21 can be connected to the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, that is, the sensing compensation circuit 40 is connected to the pull-up synchronization node Q3.

[0177] By connecting the connection point of the first sensing transistor T20 and the second sensing transistor T21 to the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, the voltage levels of the connection points of the first sensing transistor T20 and the second sensing transistor T21 can be aligned with the voltage levels of the connection points of the first noise reduction transistor T8 and the second noise reduction transistor T9. This allows the threshold voltage changes of the first sensing transistor T20 and the second sensing transistor T21 to better simulate the threshold voltage changes of the first noise reduction transistor T8 and the second noise reduction transistor T9. Consequently, the driving voltages of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 can be adjusted more precisely to better compensate for the positive offset threshold voltages of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, enabling the shift register to accurately output composite signals.

[0178] Figure 18 is another circuit diagram of the shift register of Figure 1. Referring to Figure 18, by way of example, the induction compensation circuit 40 may also include a sustaining sub-circuit 46. The sustaining sub-circuit 46 is configured to maintain the level of the control terminal of the induction transistor under the control of the fifth control signal DCLK5.

[0179] By adding a sustaining sub-circuit 46 to maintain the level of the control terminal of the sensing transistor under the control of the fifth control signal DCLK5, the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor can be improved.

[0180] Referring to Figure 18, in one possible embodiment, the sustaining sub-circuit 46 may include a first sustaining transistor T25, which is connected in series between the pull-down node QB and the second inverting transistor T16. The control terminal of the first sustaining transistor T25 is connected to the fifth control signal DCLK5, the first terminal of the first sustaining transistor T25 is connected to the pull-down node QB, and the second terminal of the first sustaining transistor T25 is connected to the first terminal of the second inverting transistor T16.

[0181] The control terminal of the first sustaining transistor T25 is connected to the fifth control signal DCLK5. The first terminal of the first sustaining transistor T25 is connected to the pull-down node QB, and the second terminal of the first sustaining transistor T25 is connected to the first terminal of the second inverting transistor T16. Under the control of the fifth control signal DCLK5, the pull-down node QB and the second inverting transistor T16 can be isolated, preventing the second inverting transistor T16 from affecting the level of the pull-down node QB, thereby maintaining the level of the control terminal of the sensing transistor and improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0182] Figure 19 is another circuit diagram of the shift register of Figure 1. Referring to Figure 19, exemplarily, the sustaining sub-circuit 46 may further include a second sustaining transistor T26, which is connected in series between the second pull-up transistor T13 and the pull-down transistor T14. The control terminal of the second sustaining transistor T26 is connected to the fifth control signal DCLK5. The first terminal of the second sustaining transistor T26 is connected to the second terminal of the second pull-up transistor T13, and the second terminal of the second sustaining transistor T26 is connected to the first terminal of the pull-down transistor T14.

[0183] The control terminal of the second sustaining transistor T26 is connected to the fifth control signal DCLK5. The first terminal of the second sustaining transistor T26 is connected to the second terminal of the second pull-up transistor T13, and the second terminal of the second sustaining transistor T26 is connected to the first terminal of the pull-down transistor T14. Under the control of the fifth control signal DCLK5, the second pull-up transistor T13 and the pull-down transistor T14 can be isolated to prevent the pull-down transistor T14 from affecting the level of the control terminal of the first inverting transistor T15, and thus to prevent affecting the level of the pull-down node QB. This maintains the level of the control terminal of the sensing transistor and improves the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0184] Figure 20 is a timing diagram of the relevant signals of the induction compensation circuit in Figures 18 and 19. Referring to Figure 20, the fifth control signal DCLK5 is high during the scanning phase, and both the first holding transistor T25 and the second holding transistor T26 are turned on to ensure the normal operation of the pull-down node control circuit 20. During the blanking phase, the fifth control signal DCLK5 first goes low and last goes high, which avoids affecting the level of the pull-down node QB, thereby maintaining the level of the control terminal of the sensing transistor and improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0185] Figure 21 is another circuit diagram of the shift register of Figure 1. Referring to Figure 21, in another possible embodiment, the sustaining sub-circuit 46 may include a third sustaining transistor T27 and a fourth sustaining transistor T28. The third sustaining transistor T27 is connected in series between the pull-down node QB and the control terminal of the sensing transistor. The control terminal of the third sustaining transistor T27 is connected to the fifth control signal DCLK5, the first terminal of the third sustaining transistor T27 is connected to the pull-down node QB, and the second terminal of the third sustaining transistor T27 is connected to the control terminal of the sensing transistor. The control terminal of the fourth sustaining transistor T28 is connected to the first control signal DCLK1, the first terminal of the fourth sustaining transistor T28 is connected to the sixth control signal DCLK6, and the second terminal of the fourth sustaining transistor T28 is connected to the second terminal of the third sustaining transistor T27 and the control terminal of the sensing transistor.

[0186] The control terminal of the third sustaining transistor T27 is connected to the fifth control signal DCLK5. The first terminal of the third sustaining transistor T27 is connected to the pull-down node QB, and the second terminal of the third sustaining transistor T27 is connected to the control terminal of the sensing transistor. Under the control of the fifth control signal DCLK5, the pull-down node QB and the control terminal of the sensing transistor can be isolated, preventing the level of the pull-down node QB from affecting the level of the control terminal of the sensing transistor. At the same time, the control terminal of the fourth sustaining transistor T28 is connected to the first control signal DCLK1, the first terminal of the fourth sustaining transistor T28 is connected to the sixth control signal DCLK6, and the second terminal of the fourth sustaining transistor T28 is connected to the second terminal of the third sustaining transistor T27 and the control terminal of the sensing transistor. Under the control of the first control signal DCLK1, the sixth control signal DCLK6 can drive the sensing transistor to conduct, thereby maintaining the level of the control terminal of the sensing transistor and improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0187] Figure 22 is a timing diagram of the relevant signals of the induction compensation circuit in Figure 21. Referring to Figure 22, the fifth control signal DCLK5 is high during the scanning phase, the third holding transistor T27 is turned on, and the level of the pull-down node QB can be applied to the sensing transistor, so that the sensing transistor and the target transistor have the same voltage environment. The fifth control signal DCLK5 first goes low during the blanking phase and last goes high, which can prevent the level of the pull-down node QB from affecting the level of the control terminal of the sensing transistor. The first control signal DCLK1 is high after the fifth control signal DCLK5 goes low and before the fifth control signal DCLK5 goes high. The fourth holding transistor T28 is turned on, and the sixth control signal DCLK6 drives the sensing transistor to turn on, so that the first control signal DCLK1 generates the sensing signal Se through the sensing transistor.

[0188] Figure 23 is another timing diagram of the related signals of the induction compensation circuit in Figure 21. Referring to Figure 23, for example, the sixth control signal DCLK6 can share the same signal line with the first control signal DCLK1, which can reduce the number of signal lines.

[0189] Figure 24 is another timing diagram of the related signals of the induction compensation circuit in Figure 21. Referring to Figure 24, for example, the sixth control signal DCLK6 can share the same signal line with the second power supply signal GVDD2, which can reduce the number of signal lines.

[0190] Figure 25 is a simulation diagram of the shift register signal in Figure 3. Referring to Figure 25, when the high-level voltage of the pull-down node QB changes due to the change of the threshold voltage Vth of the transistor, the high-level voltage of the sensing signal Se will also change accordingly. Therefore, the threshold voltage Vth of the transistor can be well detected by the sensing signal Se.

[0191] Figure 26 is a schematic diagram of the gate driving circuit in one or more embodiments of the present disclosure. Referring to Figure 26, a second aspect embodiment of the present disclosure provides a gate driving circuit, which includes at least one first shift register 100 and a plurality of second shift registers 200 cascaded with the first shift register 100. The first shift register 100 or the second shift register 200 is a shift register provided in any of the above embodiments.

[0192] For example, the first shift register 100 can be a dummy GOA, outputting only one output signal OUT as the charging input signal STU and / or the display total reset signal STD for other shift registers cascaded with this shift register. The second shift register 200 can be a driver GOA, outputting at least two output signals OUT. One output signal OUT serves as the charging input signal STU and / or the display total reset signal STD for other shift registers cascaded with this shift register, while the other output signals OUT serve as scan signals for at least the pixel sub-circuit, and different output signals OUT serve as scan signals for different row pixel sub-circuits.

[0193] Taking Figure 26 as an example, the gate drive circuit includes four first shift registers 100 and N second shift registers 200. The four first shift registers 100 are first shift register a1, first shift register a2, first shift register a3, and first shift register a4, respectively. The N second shift registers 200 are second shift register b1, second shift register b2, second shift register b3, ..., second shift register bN-1 and second shift register bN, respectively. The output signal OUT of the first shift register a1 is the charging input signal STU of the first shift register a2 and the second shift register b1. The output signal OUT of the first shift register a2 is the charging input signal STU of the second shift register b2. The output signal OUT of the second shift register b1 is the display global reset signal STD of the first shift register a1 and the charging input signal STU of the second shift register b3. The output signal OUT of the second shift register b2 is the display global reset signal STD of the first shift register a2 and the charging input signal STU of the second shift register b4, ... …The output signal OUT of the second shift register bN-1 is the display total reset signal STD of the second shift register bN-3 and the charging input signal STU of the first shift register a3. The output signal OUT of the second shift register bN is the display total reset signal STD of the second shift register bN-2 and the charging input signal STU of the first shift register a4. The output signal OUT of the first shift register a3 is the display total reset signal STD of the second shift register bN-1, and the output signal OUT of the first shift register a4 is the display total reset signal STD of the second shift register bN. Additionally, the charging input signal STU of the first shift register a1 and the display total reset signal STD of the first shift register a3 and first shift register a4 are external input signals.

[0194] Any one of the first shift registers a1, a2, a3, and a4 is a shift register provided in any of the above embodiments, or any one of the second shift registers b1, b2, b3, ..., bN-1, and bN is a shift register provided in any of the above embodiments. Figure 26 shows an example where the first shift register a4 is a shift register provided in any of the above embodiments, with the first control signal DCLK1 connected to the first shift register a4.

[0195] Figure 27 is a structural block diagram of part of the first shift register in Figure 26, and Figure 28 is a structural block diagram of part of the second shift register in Figure 26. Referring to Figures 27, 28, and 2, in some embodiments, both the first shift register 100 and the second shift register 200 may include a pull-up node control circuit 10, a pull-down node control circuit 20, and an output circuit 30. The pull-up node control circuit 10, pull-down node control circuit 20, and output circuit 30 of the first shift register 100, and the pull-up node control circuit 10, pull-down node control circuit 20, and output circuit 30 of the second shift register 200 are the same as those of the shift registers provided in any of the above embodiments. At least one of the first shift registers 100 and the second shift register 200 further includes an induction compensation circuit 40, i.e., the shift register provided in any of the above embodiments. The second shift register 200 also includes a selection compensation circuit 80, which is configured to compensate the composite signal under the control of the selection compensation control signal OE. This may include, but is not limited to, charging the pull-up control node Q4 under the control of the selection compensation control signal OE, and charging the pull-up node QA under the control of the sub-clock signal CKA.

[0196] For example, referring to Figures 27, 28 and 2, the first shift register 100 and the second shift register 200 may further include at least one of a first stabilizing circuit 50, a second stabilizing circuit 60, and a pull-down node stabilizing circuit 70. The first stabilizing circuit 50, the second stabilizing circuit 60, and the pull-down node stabilizing circuit 70 of the first shift register 100 and the second stabilizing circuit 60 and the pull-down node stabilizing circuit 70 of the second shift register 200 are the same as the first stabilizing circuit 50, the second stabilizing circuit 60, and the pull-down node stabilizing circuit 70 of the shift register provided in any of the above embodiments.

[0197] For example, the sensed signal Se carries the threshold voltage of the target transistor. When at least one of the first shift register 100 and the second shift register 200 includes a first stabilization circuit 50, the target transistor may include a noise reduction transistor in each shift register. When at least one of the first shift register 100 and the second shift register 200 includes an output sub-circuit, the target transistor may include a second output transistor in each shift register.

[0198] Referring, as exemplarily to FIG28, the selection compensation circuit 80 may include a charging sub-circuit 81, a storage sub-circuit 82, and an isolation sub-circuit 83. The charging sub-circuit 81 is configured to write the charging input signal STU to the pull-up control node Q4 under the control of the selection compensation control signal OE. The storage sub-circuit 82 is configured to store the charging input signal STU written to the pull-up control node Q4. The isolation sub-circuit 83 is configured to write the charging input signal STU to the pull-up node QA based on the levels of the pull-up control node Q4 and the sub-clock signal CKA.

[0199] Figure 29 is a circuit diagram of one possible shift register of Figure 28. Referring to Figure 29, the charging sub-circuit 81 may include a charging capacitor C3, a first charging transistor T29, a second charging transistor T30, and a third charging transistor T31. The first terminal of the charging capacitor C3, the control terminal of the first charging transistor T29, and the control terminal of the second charging transistor T30 are connected to the selection compensation control signal OE. The second terminal of the charging capacitor C3 is connected to the pull-up control node Q4. The first terminal of the first charging transistor T29 is connected to the charging input signal STU. The first terminal of the second charging transistor T30 is connected to the second terminal of the first charging transistor T29, and the second terminal of the second charging transistor T30 is connected to the pull-up control node Q4. The control terminal of the third charging transistor T31 is connected to the pull-up control node Q4. The first terminal of the third charging transistor T31 is connected to the first power supply signal GVDD1, and the second terminal of the third charging transistor T31 is connected to the second terminal of the first charging transistor T29 and the first terminal of the second charging transistor T30.

[0200] The storage sub-circuit 82 may include a storage capacitor C4, the first terminal of which is connected to the first power supply signal GVDD1, and the second terminal of which is connected to the pull-up control node Q4.

[0201] The isolation sub-circuit 83 may include a first isolation transistor T32 and a second isolation transistor T33. The control terminal of the first isolation transistor T32 is connected to the pull-up control node Q4, and the first terminal of the first isolation transistor T32 is connected to the first power supply signal GVDD1. The control terminal of the second isolation transistor T33 is connected to the sub-clock signal CKA, and the first terminal of the second isolation transistor T33 is connected to the second terminal of the first isolation transistor T32. The second terminal of the second isolation transistor T33 is connected to the pull-up node QA.

[0202] Taking Figure 29 as an example, the operation of the selection compensation circuit 80 is as follows: When the level of the selection compensation control signal OE is higher than the threshold voltage, the first charging transistor T29 and the second charging transistor T30 are turned on, the charging input signal STU is written to the pull-up control node Q4, and stored in the charging capacitor C3 and the storage capacitor C4. Therefore, the pull-up control node Q4 is at a high level.

[0203] When the pull-up control node Q4 is high, the third charging transistor T31 is turned on, the first power signal GVDD1 is written to the pull-up control node Q4, the first power signal GVDD1 further pulls the level of the pull-up control node Q4 high, and stores it in the charging capacitor C3 and the storage capacitor C4.

[0204] When the voltage level of pull-up control node Q4 is higher than the threshold voltage, the first isolation transistor T32 is turned on. Additionally, the second isolation transistor T33 is turned on when the sub-clock signal CKA is higher than the threshold voltage. The first power supply signal GVDD1 is written to pull-up node QA, making QA high. Conversely, when the second isolation transistor T33 is turned off when the sub-clock signal CKA is lower than the threshold voltage, pull-up node QA can remain high.

[0205] For example, the pull-down node control circuit 70 can also be configured to write the first voltage terminal signal VGL1 into the pull-down node QB based on the level of the pull-up control node Q4 and the sub-clock signal CKA.

[0206] Figure 30 is another circuit diagram of the second shift register in Figure 28. Referring to Figure 30, the pull-down node control circuit 70 may further include a first discharge transistor T34 and a second discharge transistor T35. The control terminal of the first discharge transistor T34 is connected to the sub-clock signal CKA, and the first terminal of the first discharge transistor T34 is connected to the pull-down node QA. The control terminal of the second discharge transistor T35 is connected to the pull-up control node Q4, and the first terminal of the second discharge transistor T35 is connected to the second terminal of the first discharge transistor T34. The second terminal of the second discharge transistor T35 is connected to the first voltage terminal signal VGL1.

[0207] Taking Figure 30 as an example, the first discharge transistor T34 is turned on when the level of the sub-clock signal CKA is higher than the threshold voltage, and the second discharge transistor T35 is turned on when the level of the pull-up control node Q4 is higher than the threshold voltage. The first voltage terminal signal VGL1 is written to the pull-down node QB, and the pull-down node QB is at a low level, which is exactly the opposite of the high level of the pull-up node QA.

[0208] A third aspect of this disclosure provides a display device that includes the gate driving circuit provided in any of the above embodiments.

[0209] Figure 31 is a flowchart of a gate driving method in one or more embodiments of the present disclosure. Referring to Figure 31, the gate driving method includes the following steps S101 to S104.

[0210] In step S101, the level of the pull-up node is pulled high under the control of the charging input signal, and the level of the pull-down node is adjusted based on the level of the pull-up node. The level of the pull-down node is opposite to the level of the pull-up node.

[0211] Step S102: Output a composite signal based on the level of the pull-up node and the level of the pull-down node.

[0212] Step S103: Under the control of the display master reset signal, pull down the level of the pull-up node, and adjust the level of the pull-down node based on the level of the pull-up node.

[0213] Step S104: Output a sensing signal based on the level of the pull-down node to adjust the drive voltage of the target transistor. The sensing signal carries the threshold voltage of the target transistor.

[0214] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0215] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0216] In this disclosure, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0217] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0218] Although embodiments of the present disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A shift register, comprising: The pull-up node control circuit is configured to control the electrical signals of the pull-up node; An output circuit, including a gate drive output terminal, is configured to output a composite signal to the gate drive output terminal under the electrical signal control of the pull-up node. The pull-down node control circuit is configured to input a first voltage terminal signal to the pull-down node under the electrical signal control of the pull-up node; An induction compensation circuit is configured to output an induction signal under the electrical signal control of the pull-down node.

2. The shift register according to claim 1, further comprising: The first stabilizing circuit is configured to electrically control the pull-up node under the electrical signal control of the pull-down node.

3. The shift register according to claim 2, wherein, The pull-up node control circuit includes: The input sub-circuit is configured to input a first power signal to the pull-up node under the control of the charging input signal; The pull-down node control circuit is configured to input a second power supply signal or the first voltage terminal signal to the pull-down node under the electrical signal control of the pull-up node.

4. The shift register according to claim 3, wherein, The pull-up node control circuit also includes: A reset protection sub-circuit is configured to electrically control the pull-up synchronization node under the electrical signal control of the pull-up node, the pull-up synchronization node being connected to the first stabilizing circuit; The first stabilizing circuit is further configured to electrically control the pull-up synchronization node under the electrical signal control of the pull-down node.

5. The shift register according to claim 4, further comprising: The selection compensation circuit is configured to charge the pull-up control node under the control of the selection compensation control signal and to charge the pull-up node under the control of the sub-clock signal.

6. The shift register according to any one of claims 1-5, wherein, The induction compensation circuit includes: The sensing sub-circuit is configured to generate the sensing signal based on a first control signal when the level of the pull-down node is higher than a threshold voltage.

7. The shift register according to claim 6, wherein, The sensing sub-circuit includes: At least one sensing transistor, the control terminal of which is connected to the pull-down node; the sensing transistor is configured to turn on when the level of the pull-down node is higher than a threshold voltage, so that the first control signal passes through the sensing transistor to generate the sensing signal.

8. The shift register according to claim 7, wherein, The at least one sensing transistor includes: A first sensing transistor, wherein the first terminal of the first sensing transistor is connected to the first control signal; The second sensing transistor has a first terminal connected to the second terminal of the first sensing transistor, and the sensing signal is output through the second terminal of the second sensing transistor.

9. The shift register according to claim 8, wherein, The first control signal and the selection compensation control signal share the same signal line, and the selection compensation control signal is a control signal for compensating the composite signal.

10. The shift register according to claim 8, wherein, The induction compensation circuit also includes: The output control sub-circuit is configured to output the sensing signal under the control of the second control signal.

11. The shift register according to claim 10, wherein, The output control sub-circuit includes: An output control transistor is provided, the control terminal of which is connected to the second control signal. The first terminal of the output control transistor is connected to the second terminal of the second sensing transistor, and the sensing signal is output through the second terminal of the output control transistor.

12. The shift register according to claim 11, wherein, The first control signal is a delayed version of the second control signal.

13. The shift register according to claim 6, wherein, The induction compensation circuit also includes: A voltage regulator circuit is configured to stabilize the level of the pull-down node when the level of the first control signal changes.

14. The shift register according to claim 13, wherein, The voltage regulator circuit includes: A voltage regulator capacitor, the first end of which is connected to the pull-down node, and the second end of which is connected to the second voltage terminal signal.

15. The shift register according to claim 6, wherein, The induction compensation circuit also includes: The voltage regulator circuit is configured to adjust the level of the pull-down node under the control of a third control signal.

16. The shift register according to claim 15, wherein, The voltage regulating sub-circuit includes: A voltage regulator transistor is provided, wherein the control terminal of the voltage regulator transistor is connected to the third control signal, the first terminal of the voltage regulator transistor is connected to the pull-down node, and the second terminal of the voltage regulator transistor is connected to the first voltage terminal signal.

17. The shift register according to claim 8, further comprising a first stabilizing circuit, the first stabilizing circuit comprising: A first noise reduction transistor, wherein the control terminal of the first noise reduction transistor is connected to the pull-down node, and the first terminal of the first noise reduction transistor is connected to the pull-up node; The second noise reduction transistor has its control terminal connected to the pull-down node, its first terminal connected to the second terminal of the first noise reduction transistor, and its second terminal connected to the first voltage terminal signal.

18. The shift register according to claim 17, wherein, The induction compensation circuit also includes: The sensing control sub-circuit is configured to connect the voltage level of the connection point between the first noise reduction transistor and the second noise reduction transistor to the sensing sub-circuit under the control of a fourth control signal.

19. The shift register according to claim 18, wherein, The sensing control sub-circuit includes: A sensing control transistor is provided, the control terminal of which is connected to the fourth control signal. The first terminal of the sensing control transistor is connected to the second terminal of the first noise reduction transistor and the first terminal of the second noise reduction transistor. The second terminal of the sensing control transistor is connected to the second terminal of the first sensing transistor and the first terminal of the second sensing transistor.

20. The shift register according to claim 17, wherein, The pull-up node control circuit includes: A first input transistor, the control terminal of the first input transistor is connected to a charging input signal, and the first terminal of the first input transistor is connected to a first power supply signal; The second input transistor has its control terminal connected to the charging input signal, its first terminal connected to the first terminal of the first input transistor, and its second terminal connected to the pull-up node. An input protection transistor is provided, wherein the control terminal of the input protection transistor is connected to the pull-down node, the first terminal of the input protection transistor is connected to the first power signal, and the second terminal of the input protection transistor is connected to the second terminal of the first input transistor and the first terminal of the second input transistor. The first reset transistor has its control terminal connected to the display total reset signal, and its first terminal is connected to the pull-up node. The second reset transistor has its control terminal connected to the display total reset signal. The first terminal of the second reset transistor is connected to the second terminal of the first reset transistor, the second terminal of the first noise reduction transistor, and the first terminal of the second noise reduction transistor. The second terminal of the second reset transistor is connected to the first voltage terminal signal. A first reset protection transistor, the control terminal of the first reset protection transistor is connected to the pull-up node, and the first terminal of the first reset protection transistor is connected to a first power supply signal. The second reset protection transistor has its control terminal connected to the pull-up node, its first terminal connected to the second terminal of the first reset protection transistor, and its second terminal connected to both the second terminal of the first reset transistor and the first terminal of the second reset transistor.

21. The shift register of claim 20, further comprising a second stabilizing circuit, the second stabilizing circuit comprising: A first total reset transistor, the control terminal of the first total reset transistor is connected to a total reset signal, and the first terminal of the first total reset transistor is connected to the pull-up node; The second total reset transistor has its control terminal connected to the total reset signal. The first terminal of the second total reset transistor is connected to the second terminal of the first total reset transistor, the first terminal of the second noise reduction transistor, the second terminal of the first noise reduction transistor, the second terminal of the second reset protection transistor, the second terminal of the first reset transistor, and the first terminal of the second reset transistor. The second terminal of the second total reset transistor is connected to the first power supply signal.

22. The shift register according to claim 17, wherein, The pull-down node control circuit includes: The first pull-up transistor has its control terminal and first terminal connected to a second power supply signal. The second pull-up transistor has its control terminal connected to the second power signal, and its first terminal is connected to the second terminal of the first pull-up transistor. A pull-down transistor, the control terminal of which is connected to the pull-up node, the first terminal of which is connected to the second terminal of the second pull-up transistor, and the second terminal of which is connected to a second voltage terminal signal; The first inverting transistor has its control terminal connected to the second terminal of the second pull-up transistor, its first terminal connected to the second power supply signal, and its second terminal connected to the pull-down node. The second inverting transistor has its control terminal connected to the pull-up node, its first terminal connected to the pull-down node, and its second terminal connected to the first voltage terminal signal.

23. The shift register according to claim 22, wherein, The connection point of the first sensing transistor and the second sensing transistor is connected to the connection point of the first noise reduction transistor and the second noise reduction transistor.

24. The shift register according to claim 23, wherein, The induction compensation circuit also includes: The sustaining sub-circuit is configured to maintain the level of the control terminal of the sensing transistor under the control of the fifth control signal.

25. The shift register according to claim 24, wherein, The sustaining sub-circuit includes: A first sustaining transistor is connected in series between the pull-down node and the second inverting transistor; the control terminal of the first sustaining transistor is connected to the fifth control signal, the first terminal of the first sustaining transistor is connected to the pull-down node, and the second terminal of the first sustaining transistor is connected to the first terminal of the second inverting transistor.

26. The shift register according to claim 25, wherein, The sustaining sub-circuit also includes: The second sustaining transistor is connected in series between the second pull-up transistor and the pull-down transistor; the control terminal of the second sustaining transistor is connected to the fifth control signal, the first terminal of the second sustaining transistor is connected to the second terminal of the second pull-up transistor, and the second terminal of the second sustaining transistor is connected to the first terminal of the pull-down transistor.

27. The shift register according to claim 24, wherein, The sustaining sub-circuit includes: A third sustaining transistor is connected in series between the pull-down node and the control terminal of the sensing transistor; the control terminal of the third sustaining transistor is connected to the fifth control signal, the first terminal of the third sustaining transistor is connected to the pull-down node, and the second terminal of the third sustaining transistor is connected to the control terminal of the sensing transistor. A fourth sustaining transistor is provided, wherein the control terminal of the fourth sustaining transistor is connected to the first control signal, the first terminal of the fourth sustaining transistor is connected to the sixth control signal, and the second terminal of the fourth sustaining transistor is connected to the second terminal of the third sustaining transistor and the control terminal of the sensing transistor.

28. The shift register according to claim 27, wherein, The sixth control signal shares the same signal line as the second power signal.

29. The shift register according to any one of claims 1-5, wherein, The output circuit includes at least one output sub-circuit, and the composite signal includes the output signals of each of the output sub-circuits in the output circuit; each output sub-circuit includes: The first output transistor has its control terminal connected to the pull-up node, its first terminal connected to a clock signal, and its second terminal outputting the output signal of the output sub-circuit. An output capacitor, wherein the first terminal of the output capacitor is connected to the pull-up node and the control terminal of the first output transistor, and the second terminal of the output capacitor is connected to the second terminal of the first output transistor; The second output transistor has its control terminal connected to the pull-down node, its first terminal connected to the second terminal of the first output transistor, and its second terminal connected to the first voltage terminal signal.

30. The shift register according to any one of claims 1-5, further comprising a pull-down node stabilization circuit, the pull-down node stabilization circuit comprising: An initial inverting transistor is provided, the control terminal of which is connected to a charging input signal, the first terminal of which is connected to the pull-down node, and the second terminal of which is connected to the first voltage terminal signal.

31. The shift register according to claim 30, further comprising a selection compensation circuit, the selection compensation circuit comprising: The charging sub-circuit includes a charging capacitor, a first charging transistor, a second charging transistor, and a third charging transistor; The first terminal of the charging capacitor, the control terminal of the first charging transistor, and the control terminal of the second charging transistor are connected to a selection compensation control signal. The second terminal of the charging capacitor is connected to a pull-up control node. The first terminal of the first charging transistor is connected to a charging input signal. The first terminal of the second charging transistor is connected to the second terminal of the first charging transistor. The second terminal of the second charging transistor is connected to the pull-up control node. The control terminal of the third charging transistor is connected to the pull-up control node. The first terminal of the third charging transistor is connected to a first power signal. The second terminal of the third charging transistor is connected to the second terminal of the first charging transistor and the first terminal of the second charging transistor. The storage sub-circuit includes a storage capacitor; the first terminal of the storage capacitor is connected to the first power signal, and the second terminal of the storage capacitor is connected to the pull-up control node. The isolation sub-circuit includes a first isolation transistor and a second isolation transistor; The control terminal of the first isolation transistor is connected to the pull-up control node. The first terminal of the first isolation transistor is connected to the first power supply signal. The control terminal of the second isolation transistor is connected to the sub-clock signal. The first terminal of the second isolation transistor is connected to the second terminal of the first isolation transistor. The second terminal of the second isolation transistor is connected to the pull-up node.

32. The shift register according to claim 31, wherein, The pull-down node stabilization circuit also includes: A first discharge transistor, the control terminal of the first discharge transistor is connected to the sub-clock signal, and the first terminal of the first discharge transistor is connected to the pull-down node; The second discharge transistor has its control terminal connected to the pull-up control node, its first terminal connected to the second terminal of the first discharge transistor, and its second terminal connected to the first voltage terminal signal.

33. A gate drive circuit, comprising at least one first shift register and a plurality of second shift registers cascaded with the first shift register, wherein at least one of the first shift register and the second shift registers is a shift register as described in any one of claims 1-32.

34. The gate driving circuit according to claim 33, wherein, The sensed signal carries the threshold voltage of the target transistor; When at least one of the first shift register and the second shift register includes the first stabilizing circuit as described in claim 17, the target transistor includes a first noise reduction transistor and a second noise reduction transistor in each of the shift registers; When at least one of the first shift register and the second shift register includes the output sub-circuit as described in claim 25, the target transistor includes the second output transistor in each of the shift registers.

35. A display device comprising the gate driving circuit as described in claim 33 or 34.

36. A gate driving method, comprising: The level of the pull-up node is pulled high under the control of the charging input signal, and the level of the pull-down node is adjusted based on the level of the pull-up node, wherein the level of the pull-down node is opposite to the level of the pull-up node; A composite signal is output based on the level of the pull-up node and the level of the pull-down node; The pull-up node is pulled low under the control of the display total reset signal, and the level of the pull-down node is adjusted based on the level of the pull-up node; The level of the pull-down node is used to output a sensing signal to adjust the drive voltage of the target transistor, the sensing signal carrying the threshold voltage of the target transistor.

Images