MEMS device and preparation method thereof

Abstract

The invention provides an MEMS device and a preparation method thereof, and relates to the technical field of semiconductors. The method comprises the steps that a first wafer and a second wafer are bonded to obtain a wafer bonding body, and the wafer bonding body comprises a first silicon layer, and a first silicon oxide layer, a second silicon layer, a second silicon oxide layer and a third silicon layer which are sequentially stacked on the first silicon layer; performing ion implantation on the third silicon layer to form a doped region in the third silicon layer; the third silicon layer is removed, a third silicon oxide layer is formed on the second silicon oxide layer, and the third silicon oxide layer and the second silicon oxide layer completely wrap the doped region together; forming a patterned mask on the surface of the first silicon layer; performing deep silicon etching on the first silicon layer to form a first through hole in the first silicon layer; removing the first silicon oxide layer exposed by the first through hole; and removing the patterned mask. The diaphragm prepared by the preparation method of the MEMS device is uniform in thickness and large in effective area, and the thickness uniformity of a plurality of diaphragms is good.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MEMS device and its fabrication method. Background Technology

[0002] Pressure sensors fabricated using the fully depleted silicon-on-insulator (FDSOI) process are widely used in applications requiring high sensor performance at high temperatures because their leakage current does not increase significantly under high-temperature operating conditions. The device layer thickness of FDSOI pressure sensors is typically 100–200 nm, and the buried oxide layer thickness is typically 200–400 nm. The total thickness of the device layer and buried oxide layer is less than 1 μm, which is insufficient to effectively form a diaphragm. Therefore, for FDSOI pressure sensors, the thickness of the device layer and buried oxide layer cannot define the diaphragm thickness, necessitating the use of additional materials to thicken the diaphragm.

[0003] The existing method for thickening the diaphragm of FDSOI pressure sensors is to retain a portion of the single-crystal silicon substrate as part of the diaphragm during back cavity etching. There are two main etching methods: one is to use deep silicon etching process, and the other is to use wet etching process.

[0004] like Figure 1 As shown, deep silicon etching can control the etching depth through menu settings. However, the deep silicon etching process suffers from uniformity issues, especially when etching thicker films. Even if the uniformity of the etching menu is only 3%, when the back cavity film thickness is 300 micrometers or even 500 micrometers, the film thickness deviation within the wafer can reach 9 to 15 micrometers. This is unacceptable for the output quality of pressure sensors on a single wafer. Generally, in the semiconductor manufacturing industry, the overall film thickness deviation of devices produced on a single wafer should not exceed 3%. Applying the above data, the typical diaphragm thickness is between tens and hundreds of micrometers. However, deep silicon etching introduces a deviation of the same or even higher order of magnitude as the diaphragm thickness in a single step, clearly failing to meet process requirements. Moreover, the bottom of the back cavity 11 obtained by deep silicon etching is not flat, resulting in thickness deviations between the center and edges of the same diaphragm 12, which greatly affects the thickness uniformity of the diaphragm 12 within a single diaphragm unit.

[0005] like Figure 2 As shown, the cross-section of the back cavity 11 obtained by wet etching is an inverted trapezoid. Under the premise of the same back cavity opening size, the effective diaphragm area is much smaller than that of deep silicon etching, resulting in a significant loss of device performance compared to the vertical sidewall morphology. Summary of the Invention

[0006] The purpose of this application is to address the shortcomings of the prior art by providing a MEMS device and its fabrication method, which can fabricate a diaphragm with uniform thickness on a wafer and has a large effective diaphragm area.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: A first aspect of this application provides a method for fabricating a MEMS device, comprising: providing a first wafer and a second wafer, and bonding the first wafer and the second wafer to obtain a wafer bond, wherein the wafer bond includes a first silicon layer, a first silicon oxide layer, a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially stacked on the first silicon layer; performing ion implantation on the third silicon layer to form a doped region within the third silicon layer; removing the third silicon layer and forming a third silicon oxide layer on the second silicon oxide layer, wherein the third silicon oxide layer and the second silicon oxide layer together completely encapsulate the doped region; flipping the wafer bond and forming a patterned mask on the surface of the first silicon layer; performing deep silicon etching on the first silicon layer to form a first via on the first silicon layer; removing the first silicon oxide layer exposed by the first via to form a second via on the first silicon oxide layer; and removing the patterned mask.

[0008] Optionally, providing a first wafer and a second wafer, and bonding the first wafer and the second wafer to obtain a wafer bond includes: providing a first wafer and a second wafer, wherein the first wafer includes a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially disposed on the second silicon layer, and the second wafer includes a first silicon layer and a first silicon oxide layer disposed on the first silicon layer; bonding the second silicon layer and the first silicon oxide layer to obtain a wafer bond.

[0009] Optionally, providing the first wafer and the second wafer includes: providing an SOI deposition wafer for preparing the first wafer, wherein two single-crystal silicon layers of the SOI deposition wafer serve as a fourth silicon layer and a third silicon layer, respectively, and a silicon oxide layer between the two single-crystal silicon layers serves as a second silicon oxide layer; thinning the fourth silicon layer to obtain the second silicon layer; providing a single-crystal silicon wafer for preparing the second wafer, wherein the single-crystal silicon wafer serves as the first silicon layer; and forming the first silicon oxide layer on the surface of the first silicon layer using an oxidation process.

[0010] Optionally, providing a first wafer and a second wafer, and bonding the first wafer and the second wafer to obtain a wafer-bonded composite includes: providing two SOI deposition wafers for fabricating the first wafer and the second wafer, respectively; wherein two single-crystal silicon layers of one SOI deposition wafer serve as a fifth silicon layer and a third silicon layer, respectively, and a silicon oxide layer between the two single-crystal silicon layers serves as a third silicon oxide layer; two single-crystal silicon layers of the other SOI deposition wafer serve as a first silicon layer and a second silicon layer, respectively, and a silicon oxide layer between the two single-crystal silicon layers serves as a first silicon oxide layer; forming a second silicon oxide layer on the surface of the second silicon layer using an oxidation process; bonding the second silicon oxide layer to the third silicon layer, and removing the fifth silicon layer and the third silicon oxide layer to obtain a wafer-bonded composite.

[0011] Optionally, removing the fifth silicon layer and the third silicon oxide layer includes: thinning the fifth silicon layer to obtain a sixth silicon layer; completely removing the sixth silicon layer using an etching process; and completely removing the third silicon oxide layer using an etching process and / or a release process.

[0012] Optionally, providing a first wafer and a second wafer, and bonding the first wafer and the second wafer to obtain a wafer bond includes: providing an SOI deposition wafer, wherein two monocrystalline silicon layers of the SOI deposition wafer serve as the first silicon layer and the second silicon layer, respectively, and a silicon oxide layer between the two monocrystalline silicon layers serves as the first silicon oxide layer; forming a second silicon oxide layer on the surface of the second silicon layer using an oxidation process; providing a monocrystalline silicon wafer, bonding the monocrystalline silicon wafer to the second silicon oxide layer, and thinning the monocrystalline silicon wafer to obtain the wafer bond.

[0013] A second aspect of this application provides a method for fabricating a MEMS device, comprising: providing a first wafer, wherein the first wafer includes a first silicon layer, a first silicon oxide layer and a second silicon layer sequentially stacked on the first silicon layer; performing ion implantation on the second silicon layer to form a doped region within the second silicon layer; removing the second silicon layer and forming a second silicon oxide layer on the first silicon oxide layer, wherein the second silicon oxide layer and the first silicon oxide layer together completely encapsulate the doped region; providing a second wafer, wherein the second wafer includes a third silicon layer; forming a patterned mask on the surface of the third silicon layer; performing deep silicon etching on the third silicon layer to form a third via on the third silicon layer; removing the patterned mask and bonding the third silicon layer to the first silicon layer to obtain a wafer bond.

[0014] Optionally, providing the first wafer includes: providing an SOI deposition wafer for preparing the first wafer, wherein two single-crystal silicon layers of the SOI deposition wafer serve as the first silicon layer and the second silicon layer, respectively, and a silicon oxide layer between the two single-crystal silicon layers serves as the first silicon oxide layer.

[0015] Optionally, before bonding the third silicon layer to the first silicon layer, the fabrication method of the MEMS device further includes: thinning the first silicon layer to reduce its thickness.

[0016] A third aspect of the embodiments of this application provides a MEMS device, which is fabricated using the MEMS device fabrication method of any of the above claims.

[0017] The beneficial effects of this application include: This application provides a method for fabricating a MEMS device, comprising: providing a first wafer and a second wafer, and bonding the first wafer and the second wafer to obtain a wafer bond, wherein the wafer bond includes a first silicon layer, a first silicon oxide layer, a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially stacked on the first silicon layer; performing ion implantation on the third silicon layer to form a doped region within the third silicon layer; removing the third silicon layer and forming a third silicon oxide layer on the second silicon oxide layer, wherein the third silicon oxide layer and the second silicon oxide layer together completely encapsulate the doped region; flipping the wafer bond and forming a patterned mask on the surface of the first silicon layer; performing deep silicon etching on the first silicon layer to form a first via on the first silicon layer; removing the first silicon oxide layer exposed by the first via to form a second via on the first silicon oxide layer; and removing the patterned mask. The above-mentioned MEMS device fabrication method uses two wafers bonded together, combined with deep silicon etching process to fabricate MEMS devices. The thickness of the fabricated diaphragm is much greater than the thickness of the device layer, and the thickness of a single diaphragm is uniform, with a large effective area and good thickness uniformity of multiple diaphragms. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is one of the structural schematic diagrams of an existing FDSOI pressure sensor; Figure 2 This is the second schematic diagram of the existing FDSOI pressure sensor. Figure 3 One of the flowcharts for a method of fabricating a MEMS device provided in the embodiments of this application; Figure 4 One of the schematic diagrams of bonding the first wafer and the second wafer in the fabrication method of the MEMS device provided in the embodiments of this application; Figure 5 This is one of the schematic diagrams of the wafer bonding structure provided in the embodiments of this application; Figure 6 One of the schematic diagrams illustrating the fabrication process of the MEMS device provided in the embodiments of this application; Figure 7 The second schematic diagram illustrates the fabrication process of the MEMS device provided in the embodiments of this application; Figure 8 The third schematic diagram illustrating the fabrication process of the MEMS device provided in the embodiments of this application; Figure 9 Fourth schematic diagram of the fabrication process of the MEMS device provided in the embodiments of this application; Figure 10 Fifth schematic diagram illustrating the fabrication process of the MEMS device provided in the embodiments of this application; Figure 11 Sixth schematic diagram of the fabrication process of the MEMS device provided in the embodiments of this application; Figure 12 This is a schematic diagram of the structure of the MEMS device provided in the embodiments of this application; Figure 13 This is one of the structural schematic diagrams of the first wafer provided in the embodiments of this application; Figure 14 This is one of the structural schematic diagrams of the second wafer provided in the embodiments of this application; Figure 15 This is a second schematic diagram of the bonding of the first wafer and the second wafer in the fabrication method of the MEMS device provided in the embodiments of this application; Figure 16 This is a second schematic diagram of the structure of the wafer bonding assembly provided in the embodiments of this application; Figure 17 This is the third schematic diagram of the bonding of the first wafer and the second wafer in the fabrication method of the MEMS device provided in the embodiments of this application; Figure 18 A second flowchart illustrating the fabrication method of the MEMS device provided in this application embodiment; Figure 19 This is a second schematic diagram of the structure of the first wafer provided in the embodiments of this application; Figure 20 Seventh schematic diagram of the fabrication process of the MEMS device provided in the embodiments of this application; Figure 21 Eighth schematic diagram of the fabrication process of the MEMS device provided in the embodiments of this application; Figure 22 Schematic diagram nine illustrating the fabrication process of the MEMS device provided in the embodiments of this application; Figure 23 This is a second schematic diagram of the structure of the second wafer provided in the embodiments of this application; Figure 24 The tenth schematic diagram illustrating the fabrication process of the MEMS device provided in the embodiments of this application; Figure 25This is the fourth schematic diagram of the bonding of the first wafer and the second wafer in the fabrication method of the MEMS device provided in the embodiments of this application.

[0020] Icons: 11-Back cavity; 12-Diaphragm; 100-First wafer; 200-Second wafer; 300-Wafer bonding assembly; 410-First silicon layer; 411-First via; 420-Second silicon layer; 430-Third silicon layer; 431-Third via; 440-Fourth silicon layer; 450-Fifth silicon layer; 460-Sixth silicon layer; 510-First silicon oxide layer; 511-Second via; 520-Second silicon oxide layer; 530-Third silicon oxide layer; 600-Doped region; 700-Patterned mask; 800-MEMS device. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, and the combined embodiments are still within the protection scope of this application.

[0023] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0024] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] The first aspect of the embodiments of this application is referred to. Figure 3 A method for fabricating a MEMS device is provided, comprising: S11: Provide a first wafer and a second wafer, and bond the first wafer and the second wafer to obtain a wafer bond, wherein the wafer bond includes a first silicon layer, a first silicon oxide layer, a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially stacked on the first silicon layer.

[0027] Please refer to the reference. Figure 4 and Figure 5 The first wafer 100 and the second wafer 200 can be connected using either direct bonding or indirect bonding processes. Direct bonding refers to connecting the two wafers through interatomic forces. Indirect bonding refers to connecting the first wafer 100 and the second wafer 200 using an intermediate layer material.

[0028] After surface bonding of the first wafer 100 and the second wafer 200, a wafer bond 300 is formed. The wafer bond 300 includes a first silicon layer 410, a first silicon oxide layer 510, a second silicon layer 420, a second silicon oxide layer 520, and a third silicon layer 430 stacked sequentially. It should be noted that, firstly, among the above film layers, adjacent film layers can be directly bonded together, or other film layers can be provided; the stacking arrangement does not limit the film layers to be bonded sequentially. Secondly, this embodiment does not limit which of the above film layers belong to the first wafer 100 and which belong to the second wafer 200. For example, the first silicon layer 410 and the first silicon oxide layer 510 belong to the second wafer 200, and the second silicon layer 420, the second silicon oxide layer 520, and the third silicon layer 430 belong to the first wafer 100. Alternatively, the first silicon layer 410, the first silicon oxide layer 510, and the second silicon layer 420 belong to the second wafer 200, and the second silicon oxide layer 520 and the third silicon layer 430 belong to the first wafer 100.

[0029] S12: Ion implantation is performed on the third silicon layer to form a doped region within the third silicon layer.

[0030] Please refer to the reference. Figure 6After obtaining the wafer bonding assembly 300, ion implantation is performed on a localized area of ​​the third silicon layer 430 on the side opposite to the second silicon oxide layer 520, thereby forming a doped region 600 within the third silicon layer 430. The doped region 600 penetrates the third silicon layer 430.

[0031] Generally speaking, multiple doped regions 600 need to be formed on a wafer bonding assembly 300, so that after the wafer bonding assembly 300 is cut into multiple MEMS devices 800, each MEMS device 800 includes a doped region 600.

[0032] S13: Remove the third silicon layer and form a third silicon oxide layer on the second silicon oxide layer. The third silicon oxide layer and the second silicon oxide layer together completely encapsulate the doped region.

[0033] Please refer to the reference. Figure 7 After forming the doped region 600, the un-ion-implanted third silicon layer 430 is removed, thus fully exposing the upper and side surfaces of the doped region 600 (the lower surface of the doped region 600 is attached to the second silicon oxide layer 520). Then, please refer to the reference... Figure 8 A third silicon oxide layer 530 is formed on the second silicon oxide layer 520. The third silicon oxide layer 530 completely covers the upper surface and side surfaces of the doped region 600, and together with the second silicon oxide layer 520, the doped region 600 is completely enclosed. The second silicon oxide layer 520, the third silicon oxide layer 530, and the doped region 600 together constitute the device layer.

[0034] The third silicon oxide layer 530 can be formed by depositing silicon oxide material on the second silicon oxide layer 520. It should be noted that the SOI process is referred to here only by the formation of the third oxide layer because the focus of this application is not the SOI process, so it is simplified here.

[0035] S14: Flip the wafer bond and form a patterned mask on the surface of the first silicon layer.

[0036] Please refer to the reference. Figure 9 The wafer bonding assembly 300 is flipped so that its first silicon layer 410 faces upward. Then, a patterned mask 700 is formed on the surface of the first silicon layer 410. The patterned mask 700 can be a photoresist mask, a metal mask, a silicon oxide mask, or a silicon nitride mask, etc.

[0037] The patterning mask 700 covers part of the surface of the first silicon layer 410 and exposes part of it. The portion of the first silicon layer 410 exposed by the patterning mask 700 will be removed in subsequent processes.

[0038] S15: Perform deep silicon etching on the first silicon layer to form a first via on the first silicon layer.

[0039] Please refer to the reference. Figure 10 The first silicon layer 410 is etched using a deep silicon etching process, and the exposed portion of the patterned mask 700 in the first silicon layer 410 is removed, thereby forming a first through-hole 411 that penetrates the first silicon layer 410.

[0040] Because the deep silicon etching process has a very high selectivity for the etching rate between single-crystal silicon and silicon oxide, the etching of the first silicon layer 410 can be stopped at the surface of the first silicon oxide layer 510. Furthermore, when there are multiple first vias 411, the etching of all of them stops at the surface of the first silicon oxide layer 510. This results in not only uniform thickness of the individual diaphragms, but also good thickness uniformity when there are multiple diaphragms. Moreover, the sidewalls of the first vias 411 formed by the deep silicon etching process are vertical, thus, given the same opening size in the patterned mask 700, the effective area of ​​a single diaphragm is also larger.

[0041] S16: Remove the first silicon oxide layer exposed by the first through hole to form a second through hole on the first silicon oxide layer.

[0042] Please refer to the reference. Figure 11 The deep silicon etching process precisely stops at the surface of the first silicon oxide facing the first silicon layer 410. A first via 411 on the first silicon layer 410 exposes a portion of the first silicon oxide. Using the first silicon layer 410, a second via 511 corresponding to the first via 411 can be formed on the first silicon oxide layer 510. The first via 411 and the second via 511 together form the back cavity, and the area above the back cavity is the diaphragm.

[0043] The second through hole 511 can be formed by etching or release processes. It can be understood that the second through hole 511 has the same or substantially the same lateral dimensions as the first through hole 411, the same number of them, and they correspond one-to-one.

[0044] S17: Remove the graphical mask.

[0045] Please refer to the reference. Figure 12 Remove the patterned mask 700 to complete the fabrication of the MEMS device 800.

[0046] The above-mentioned MEMS device fabrication method uses two wafers bonded together, combined with deep silicon etching process to fabricate MEMS device 800. The thickness of the fabricated diaphragm is much greater than the thickness of the device layer, and the thickness of a single diaphragm is uniform, with a large effective area and good thickness uniformity of multiple diaphragms.

[0047] Optionally, a first wafer and a second wafer are provided, and the first wafer and the second wafer are bonded together to obtain a wafer bond comprising: S111: Provide a first wafer and a second wafer, wherein the first wafer includes a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially disposed on the second silicon layer, and the second wafer includes a first silicon layer and a first silicon oxide layer disposed on the first silicon layer.

[0048] S112: Bond the second silicon layer to the first silicon oxide layer to obtain a wafer bond.

[0049] Please refer to Figure 4 In this embodiment, the second silicon layer 420, the second silicon oxide layer 520 and the third silicon layer 430 in the wafer bonding assembly 300 belong to the first wafer 100, and the first silicon layer 410 and the first silicon oxide layer 510 in the wafer bonding assembly 300 belong to the second wafer 200.

[0050] Currently, there are three processes for preparing monocrystalline silicon-thermal oxidized silicon-monocrystalline silicon film structures: SIMOX technology (oxygen injection isolation technology); BESOI technology (bonding etch-back technology); and Smart Cut technology (smart glass technology). Theoretically, combining these three technologies can achieve the fabrication of multilayer thermally oxidized silicon film structures, but it carries the following risks: 1. The alignment accuracy of multiple bonding operations is affected by the bonding equipment; 2. Repeated thinning can easily introduce surface damage; 3. Repeated ion implantation can cause damage to the silicon lattice; 4. The high-temperature process of multiple bonding processes can lead to uncontrollable quality of thermally bonded silicon oxide.

[0051] Therefore, obtaining a multilayer thermally oxidized silicon film structure is difficult to achieve with current fabrication techniques. Thus, in this embodiment, the first wafer 100 includes only one thermally oxidized silicon layer, namely the second silicon oxide layer 520.

[0052] Optionally, providing a first wafer and a second wafer includes: S1111: Provides an SOI deposition wafer for preparing a first wafer. The two single-crystal silicon layers of the SOI deposition wafer serve as the fourth and third silicon layers, respectively, and the silicon oxide layer between the two single-crystal silicon layers serves as the second silicon oxide layer.

[0053] Please refer to Figure 13 The SOI (Silicon On Insulator) deposition wafer includes two single-crystal silicon layers and a silicon oxide layer disposed between the two single-crystal silicon layers. Its layer structure is the same as that of the required first wafer 100. Therefore, the first wafer 100 can be prepared by using the SOI deposition wafer. The SOI deposition wafer is an existing product, which can simplify the preparation process of the MEMS device 800.

[0054] S1112: Thin the fourth silicon layer to obtain the second silicon layer.

[0055] Please refer to the reference. Figure 4 and Figure 12 As mentioned above, the single-crystal silicon layer at the bottom of the SOI wafer (as the fourth silicon layer 440) will eventually become part of the diaphragm. However, the initial thickness of the single-crystal silicon layer at the bottom of the SOI wafer is usually significantly greater than the required diaphragm thickness. Therefore, the fourth silicon layer 440 needs to be thinned to become a thinner second silicon layer 420. The second silicon layer 420 will ultimately be fully retained as part of the diaphragm. The thinning process can be achieved through grinding, chemical mechanical polishing, and etching processes.

[0056] S1113: Provides a single-crystal silicon wafer for preparing a second wafer, wherein the single-crystal silicon wafer serves as the first silicon layer.

[0057] Please refer to Figure 14 The single-crystal silicon wafer consists of only a single-crystal silicon layer, which can serve as the first silicon layer 410 of the second wafer 200 for fabrication of the second wafer 200.

[0058] S1114: An oxidation process is used to form a first silicon oxide layer on the surface of the first silicon layer.

[0059] The first silicon oxide layer 510 of the second wafer 200 is formed on the surface of the first silicon layer 410 by an oxidation process. That is, in a high-temperature environment, the surface material of the single-crystal silicon wafer undergoes a chemical reaction with oxygen or water vapor, causing it to be oxidized into an oxide, thereby forming the first silicon oxide layer 510 covering the first silicon layer 410.

[0060] Optionally, a first wafer and a second wafer are provided, and the first wafer and the second wafer are bonded together to obtain a wafer bond comprising: S113: Provides two SOI deposition wafers, used to prepare the first wafer and the second wafer, respectively.

[0061] S114: Two single-crystal silicon layers in one SOI deposition wafer are used as the fifth silicon layer and the third silicon layer, respectively, and the silicon oxide layer between the two single-crystal silicon layers is used as the third silicon oxide layer.

[0062] S115: The two monocrystalline silicon layers of another SOI deposition wafer are used as the first silicon layer and the second silicon layer, respectively, and the silicon oxide layer between the two monocrystalline silicon layers is used as the first silicon oxide layer.

[0063] S116: A second silicon oxide layer is formed on the surface of the second silicon layer using an oxidation process.

[0064] S117: Bond the second silicon oxide layer to the third silicon layer, and remove the fifth silicon layer and the third silicon oxide layer to obtain a wafer bond.

[0065] Please refer to Figure 15 and Figure 16 In this embodiment, the third silicon layer 430 in the wafer bonding assembly 300 belongs to the first wafer 100, and the first silicon layer 410, the first silicon oxide layer 510, the second silicon layer 420, and the second silicon oxide layer 520 in the wafer bonding assembly 300 belong to the second wafer 200. The first wafer 100 is prepared from one SOI deposition wafer, and the second wafer 200 is prepared from another SOI deposition wafer. The SOI deposition wafer includes two single-crystal silicon layers and a silicon oxide layer disposed between the two single-crystal silicon layers.

[0066] For the SOI deposition wafer forming the second wafer 200, an oxidation process is required to form the second silicon oxide layer 520 required for the second wafer 200 on the surface of the second silicon layer 420. For the SOI deposition wafer forming the first wafer 100, the unnecessary fifth silicon layer 450 and third silicon oxide layer 530 need to be removed.

[0067] It should be noted that the formation of the second silicon oxide layer 520 needs to be performed before bonding, but the removal of the fifth silicon layer 450 and the third silicon oxide layer 530 can be performed before or after bonding.

[0068] Optionally, removing the fifth silicon layer and the third silicon oxide layer includes: S1171: Thin the fifth silicon layer to obtain the sixth silicon layer.

[0069] S1172: The sixth silicon layer is completely removed using an etching process.

[0070] S1173: The third silicon oxide layer is completely removed using an etching process and / or a release process.

[0071] When removing the fifth silicon layer 450 and the third silicon oxide layer 530, the thicker fifth silicon layer 450 can be thinned first to become a thinner sixth silicon layer 460. Then, an etching process can be used to completely remove the sixth silicon layer 460, exposing the underlying third silicon oxide layer 530. Finally, an etching process and / or a release process can be used to completely remove the third silicon oxide layer 530.

[0072] Typical silicon oxide layer removal processes utilize HF (hydrogen fluoride) as the primary etching material. This is because HF-based silicon oxide removal processes generally exhibit high selectivity for silicon oxide (compared to silicon). For example, wet HF etching or VHF (vaporized HF etching) processes can remove relatively thick silicon oxide layers with minimal damage to the silicon or other dielectric layers. This allows for painless removal of the silicon oxide film, resulting in uniform device layer thickness and a smooth backside profile.

[0073] By bonding the first wafer 100 and the second wafer 200 to achieve a single-crystal silicon-thermal silicon oxide-single-crystal silicon film structure, and by applying a high selectivity method during etching, a diaphragm with uniform thickness and a large effective diaphragm area can be fabricated on the wafer.

[0074] Optionally, a first wafer and a second wafer are provided, and the first wafer and the second wafer are bonded together to obtain a wafer bond comprising: S118: Provides an SOI deposition wafer, wherein the two monocrystalline silicon layers of the SOI deposition wafer serve as the first silicon layer and the second silicon layer, respectively, and the silicon oxide layer between the two monocrystalline silicon layers serves as the first silicon oxide layer.

[0075] S119: A second silicon oxide layer is formed on the surface of the second silicon layer using an oxidation process.

[0076] S120: Provides a monocrystalline silicon wafer, bonds the monocrystalline silicon wafer to a second silicon oxide layer, and thins the monocrystalline silicon wafer to obtain a wafer bond.

[0077] Please refer to Figure 16 and Figure 17 In this embodiment, the third silicon layer 430 in the wafer bonding assembly 300 belongs to the first wafer 100, and the first silicon layer 410, the first silicon oxide layer 510, the second silicon layer 420, and the second silicon oxide layer 520 in the wafer bonding assembly 300 belong to the second wafer 200. The first wafer 100 is prepared from a single-crystal silicon wafer, and the second wafer 200 is prepared from an SOI deposition wafer. The single-crystal silicon wafer includes a single-crystal silicon layer, and the SOI deposition wafer includes two single-crystal silicon layers and a silicon oxide layer disposed between the two single-crystal silicon layers.

[0078] For the SOI deposition wafer forming the second wafer 200, an oxidation process is required to form the second silicon oxide layer 520 required for the second wafer 200 on the surface of the second silicon layer 420. For the single-crystal silicon wafer forming the first wafer 100, since its initial thickness is significantly greater than the required thickness of the third silicon layer 430, the single-crystal silicon wafer needs to be thinned.

[0079] It should be noted that the formation of the second silicon oxide layer 520 needs to be performed before bonding, but the thinning process of the single crystal silicon wafer can be performed before or after bonding.

[0080] Alternatively, after removing the patterned mask, the fabrication method of the MEMS device further includes: S18: Cut the wafer bonding assembly to obtain multiple MEMS devices.

[0081] When the aforementioned steps form multiple diaphragms on the wafer bonding assembly 300, after removing the patterned mask 700, the wafer bonding assembly 300 needs to be cut to obtain multiple independent MEMS devices 800. It is understood that the cutting location can be determined based on the structure of the device layers and the location of the back cavity, etc.

[0082] For a second aspect of the embodiments of this application, please refer to Figure 18 A method for fabricating a MEMS device is provided, comprising: S21: Provide a first wafer, wherein the first wafer includes a first silicon layer, a first silicon oxide layer and a second silicon layer sequentially stacked on the first silicon layer.

[0083] Please refer to the reference. Figure 19 The first wafer 100 includes a first silicon layer 410, a first silicon oxide layer 510, and a second silicon layer 420 stacked sequentially. It should be noted that, among the above film layers, two adjacent film layers can be directly bonded together, or other film layers can be provided. The stacking arrangement does not mean that each film layer must be bonded sequentially.

[0084] S22: Ion implantation is performed on the second silicon layer to form a doped region within the second silicon layer.

[0085] Please refer to the reference. Figure 20 Ion implantation is performed on a localized area of ​​the second silicon layer 420 on the side opposite to the first silicon oxide layer 510, thereby forming a doped region 600 within the second silicon layer 420. The doped region 600 extends through the second silicon layer 420.

[0086] Generally speaking, multiple doped regions 600 need to be formed on a first wafer 100, so that after the first wafer 100 is cut into multiple MEMS devices 800, each MEMS device 800 includes a doped region 600.

[0087] S23: Remove the second silicon layer and form a second silicon oxide layer on the first silicon oxide layer. The second silicon oxide layer and the first silicon oxide layer together completely encapsulate the doped region.

[0088] Please refer to the reference. Figure 21 After forming the doped region 600, the second silicon layer 420 that has not undergone ion implantation is removed, thereby fully exposing the upper and side surfaces of the doped region 600 (the lower surface of the doped region 600 is attached to the first silicon oxide layer 510). Then, please refer to the reference. Figure 22A second silicon oxide layer 520 is formed on the first silicon oxide layer 510. The second silicon oxide layer 520 completely covers the upper surface and side surfaces of the doped region 600, and together with the first silicon oxide layer 510, the doped region 600 is completely enclosed. The first silicon oxide layer 510, the second silicon oxide layer 520, and the doped region 600 together constitute the device layer.

[0089] The second silicon oxide layer 520 can be formed by depositing silicon oxide material on the first silicon oxide layer 510. It should be noted that the SOI process is referred to here only as the formation of the second oxide layer because the focus of this application is not the SOI process, so it is simplified here.

[0090] S24: Provide a second wafer, wherein the second wafer includes a third silicon layer.

[0091] Please refer to the reference. Figure 23 The second wafer 200 can be a monocrystalline silicon wafer, which includes a monocrystalline silicon layer, and the monocrystalline silicon layer is the required third silicon layer 430.

[0092] S25: A patterned mask is formed on the surface of the third silicon layer.

[0093] A patterned mask 700 is formed on the surface of the third silicon layer 430. The patterned mask 700 can be a photoresist mask, a metal mask, a silicon oxide mask, or a silicon nitride mask, etc.

[0094] The patterning mask 700 covers part of the surface of the third silicon layer 430 and exposes part of it. The portion of the third silicon layer 430 exposed by the patterning mask 700 will be removed in subsequent processes.

[0095] S26: Perform deep silicon etching on the third silicon layer to form a third via on the third silicon layer.

[0096] Please refer to the reference. Figure 24 The third silicon layer 430 is etched using a deep silicon etching process, removing the exposed portion of the patterned mask 700 within the third silicon layer 430, thereby forming a third via 431 penetrating the third silicon layer 430. Because the sidewalls of the third via 431 formed by the deep silicon etching process are vertical, the effective area of ​​a single diaphragm is also larger, provided the opening size of the patterned mask 700 is the same.

[0097] S27: Remove the patterned mask and bond the third silicon layer to the first silicon layer to obtain a wafer bond.

[0098] Referring to reference 25, after forming the third via 431, the patterned mask 700 needs to be removed, and the third silicon layer 430 with the third via 431 needs to be bonded to the first silicon layer 410 to obtain the wafer bond 300.

[0099] It should be noted that the removal of the patterning mask 700 can be performed before or after bonding. If it is performed after bonding, then during bonding, the surface of the third silicon layer 430 not covered by the patterning mask 700 needs to be bonded to the first silicon layer 410.

[0100] The aforementioned MEMS device fabrication method involves fabricating a diaphragm on a first wafer 100 and fabricating a substrate with through-holes beneath the diaphragm on a second wafer 200. The first wafer 100 and the second wafer 200 are then bonded together to form a wafer bond 300. Combined with deep silicon etching, the resulting diaphragm is significantly thicker than the device layer, exhibiting uniform thickness and a large effective area for each individual diaphragm, while also demonstrating good thickness uniformity across multiple diaphragms.

[0101] Optionally, providing the first wafer includes: S211: Provide an SOI deposition wafer for preparing a first wafer. The two single-crystal silicon layers of the SOI deposition wafer serve as the first silicon layer and the second silicon layer, respectively, and the silicon oxide layer between the two single-crystal silicon layers serves as the first silicon oxide layer.

[0102] Please refer to Figure 19 The SOI (Silicon On Insulator) deposition wafer includes two single-crystal silicon layers and a silicon oxide layer disposed between the two single-crystal silicon layers. Its layer structure is the same as that of the required first wafer 100. Therefore, the first wafer 100 can be prepared by using the SOI deposition wafer. The SOI deposition wafer is an existing product, which can simplify the preparation process of the MEMS device 800.

[0103] Optionally, before bonding the third silicon layer to the first silicon layer, the fabrication method of the MEMS device further includes: S28: Thinning process is performed on the first silicon layer to reduce the thickness of the first silicon layer.

[0104] Please refer to the reference. Figure 25 As mentioned above, the monocrystalline silicon layer at the bottom of the SOI deposited wafer (as the first silicon layer 410) will eventually become part of the diaphragm. However, the initial thickness of the monocrystalline silicon layer at the bottom of the SOI deposited wafer is usually significantly greater than the required thickness of the diaphragm. Therefore, the first silicon layer 410 needs to be thinned. The thinned first silicon layer 410 then becomes part of the diaphragm. The thinning process can be achieved through grinding, chemical mechanical polishing, and etching processes.

[0105] Optionally, after removing the patterned mask and bonding the third silicon layer to the first silicon layer to obtain a wafer bond, the fabrication method of the MEMS device further includes: S28: Cut the wafer bonding assembly to obtain multiple MEMS devices.

[0106] When the aforementioned steps form multiple diaphragms on the wafer bonding assembly 300, after removing the patterned mask 700, the wafer bonding assembly 300 needs to be cut to obtain multiple independent MEMS devices 800. It is understood that the cutting location can be determined based on the structure of the device layers and the location of the back cavity, etc.

[0107] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0108] For the third aspect of this embodiment, please refer to Figure 12 A MEMS device 800 is provided, which is fabricated using any of the above-mentioned MEMS device fabrication methods.

[0109] The MEMS device 800 includes the same structure and beneficial effects as the MEMS device fabrication method in the foregoing embodiments. The structure and beneficial effects of the MEMS device fabrication method have been described in detail in the foregoing embodiments and will not be repeated here.

[0110] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a MEMS device, characterized in that, include: A first wafer and a second wafer are provided, and the first wafer and the second wafer are bonded together to obtain a wafer bond, wherein the wafer bond includes a first silicon layer, a first silicon oxide layer, a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially stacked on the first silicon layer; Ion implantation is performed on the third silicon layer to form a doped region within the third silicon layer; The third silicon layer is removed, and a third silicon oxide layer is formed on the second silicon oxide layer. The third silicon oxide layer and the second silicon oxide layer together completely encapsulate the doped region. The wafer bond is flipped over, and a patterned mask is formed on the surface of the first silicon layer; Deep silicon etching is performed on the first silicon layer to form a first via on the first silicon layer; The first silicon oxide layer exposed by the first via is removed to form a second via on the first silicon oxide layer; Remove the graphical mask.

2. The method for fabricating a MEMS device as described in claim 1, characterized in that, The step of providing a first wafer and a second wafer, and bonding the first wafer to the second wafer to obtain a wafer bond includes: A first wafer and a second wafer are provided, wherein the first wafer includes a second silicon layer, a second silicon oxide layer and a third silicon layer sequentially disposed on the second silicon layer, and the second wafer includes a first silicon layer and a first silicon oxide layer disposed on the first silicon layer; The second silicon layer is bonded to the first silicon oxide layer to obtain a wafer bond.

3. The method for fabricating a MEMS device as described in claim 2, characterized in that, The provision of the first wafer and the second wafer includes: An SOI deposition wafer is provided for preparing a first wafer, wherein two single-crystal silicon layers of the SOI deposition wafer are respectively used as a fourth silicon layer and a third silicon layer, and a silicon oxide layer between the two single-crystal silicon layers is used as a second silicon oxide layer. The fourth silicon layer is thinned to obtain the second silicon layer; A single-crystal silicon wafer is provided for fabricating a second wafer, wherein the single-crystal silicon wafer serves as a first silicon layer; An oxidation process is used to form a first silicon oxide layer on the surface of the first silicon layer.

4. The method for fabricating a MEMS device as described in claim 1, characterized in that, The step of providing a first wafer and a second wafer, and bonding the first wafer to the second wafer to obtain a wafer bond includes: Two SOI deposition wafers are provided, one for fabricating a first wafer and the other for fabricating a second wafer; In one of the SOI deposition wafers, the two single-crystal silicon layers are respectively used as the fifth silicon layer and the third silicon layer, and the silicon oxide layer between the two single-crystal silicon layers is used as the third silicon oxide layer; In another SOI deposition wafer, two single-crystal silicon layers are respectively used as the first silicon layer and the second silicon layer, and the silicon oxide layer between the two single-crystal silicon layers is used as the first silicon oxide layer. A second silicon oxide layer is formed on the surface of the second silicon layer using an oxidation process; The second silicon oxide layer is bonded to the third silicon layer, and the fifth silicon layer and the third silicon oxide layer are removed to obtain a wafer bond.

5. The method for fabricating a MEMS device as described in claim 4, characterized in that, Removing the fifth silicon layer and the third silicon oxide layer includes: The fifth silicon layer is thinned to obtain the sixth silicon layer; The sixth silicon layer was completely removed using an etching process; The third silicon oxide layer is completely removed using an etching process and / or a release process.

6. The method for fabricating a MEMS device as described in claim 1, characterized in that, The step of providing a first wafer and a second wafer, and bonding the first wafer to the second wafer to obtain a wafer bond includes: An SOI deposition wafer is provided, wherein two monocrystalline silicon layers of the SOI deposition wafer are respectively used as a first silicon layer and a second silicon layer, and a silicon oxide layer between the two monocrystalline silicon layers is used as a first silicon oxide layer. A second silicon oxide layer is formed on the surface of the second silicon layer using an oxidation process; A monocrystalline silicon wafer is provided, which is then bonded to a second silicon oxide layer, and the monocrystalline silicon wafer is thinned to obtain a wafer bond.

7. A method for fabricating a MEMS device, characterized in that, include: A first wafer is provided, wherein the first wafer includes a first silicon layer, a first silicon oxide layer and a second silicon layer sequentially stacked on the first silicon layer; Ion implantation is performed on the second silicon layer to form a doped region within the second silicon layer; The second silicon layer is removed, and a second silicon oxide layer is formed on the first silicon oxide layer. The second silicon oxide layer and the first silicon oxide layer together completely encapsulate the doped region. A second wafer is provided, wherein the second wafer includes a third silicon layer; A patterned mask is formed on the surface of the third silicon layer; Deep silicon etching is performed on the third silicon layer to form a third via on the third silicon layer; The patterned mask is removed, and the third silicon layer is bonded to the first silicon layer to obtain a wafer bond.

8. The method for fabricating a MEMS device as described in claim 7, characterized in that, The provision of the first wafer includes: An SOI deposition wafer is provided for preparing a first wafer, wherein two single-crystal silicon layers of the SOI deposition wafer serve as a first silicon layer and a second silicon layer, respectively, and a silicon oxide layer between the two single-crystal silicon layers serves as a first silicon oxide layer.

9. The method for fabricating a MEMS device as described in claim 8, characterized in that, Before bonding the third silicon layer to the first silicon layer, the fabrication method of the MEMS device further includes: The first silicon layer is thinned to reduce its thickness.

10. A MEMS device, characterized in that, The device is prepared by the fabrication method of the MEMS device as described in any one of claims 1 to 6 or the fabrication method of the MEMS device as described in any one of claims 7 to 9.

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