Cable Riser board suitable for multi-platform server and adaptation and multiplexing method

Abstract

The invention discloses a Cable Riser board suitable for a multi-platform server and an adaptation and multiplexing method, and belongs to the technical field of server hardware extension. The Cable Riser board comprises a Riser board main body, a PCIE (Peripheral Component Interface Express) standard signal interface structure, a user-defined signal configuration module and an I2C (Inter-Integrated Circuit) signal compatible module; the PCIE standard signal interface structure can lead out PCIE necessary signals and is provided with reserved Pin welding PADs, the user-defined signal configuration module is adaptive to various user-defined signals, and the I2C signal compatible module is adaptive to the I2C interface connection mode of the FRU and the CEM. The signal adaptation method comprises the following steps: leading out a signal according to a target platform demand, configuring a user-defined path, adapting I2C connection and setting an FRU address; according to the multiplexing method, multiplexing is realized by acquiring platform requirements, formulating a line sequence scheme, performing butt joint adaptation and performing test verification. According to the scheme, multi-platform compatibility is achieved, the hardware reuse rate is increased, the customization development cost and inventory pressure are reduced, adaptation is flexible, signal transmission is stable, and the operation reliability of a server system is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of server hardware expansion technology, and in particular to a CableRiser board adapted to multi-platform servers, and a method for adaptation and reuse. Background Technology

[0002] With the rapid development of cloud computing, big data, and artificial intelligence technologies, servers, as the core computing power carrier, are seeing their application scenarios continuously expand. Server platforms launched by different manufacturers exhibit diverse characteristics in terms of interface specifications and signal configurations. As a key expansion component of servers, cable riser boards are mainly used to realize PCIe slot expansion, signal transmission, and hardware interconnection, supporting flexible expansion of devices such as network cards and GPU cards. Currently, integrated cable and board designs, standardized interfaces, and dustproof protection technologies have emerged, and some solutions can provide customized adaptation services to meet specific platform requirements.

[0003] Currently, most existing cable riser boards in the server field adopt targeted designs, lacking a unified modular architecture and flexible signal adaptation mechanisms. This makes them incompatible with the PCIe signal requirements, custom signal specifications, and I2C interface connection methods of different platforms, resulting in low hardware reuse rates, requiring repeated custom development, and increasing R&D costs and inventory pressure. Furthermore, to meet the personalized configuration requirements of different platforms, existing solutions often require modifications to the core hardware structure to achieve adaptation, leading to low adaptation efficiency. Moreover, during multi-platform interoperability, issues such as unstable signal transmission and insufficient compatibility can easily occur, affecting the overall operational reliability of the server system. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a CableRiser board that is adaptable to multi-platform servers, and a method for adaptation and reuse.

[0005] The objective of this invention is achieved through the following technical solution: A Cable Riser board adaptable to multi-platform servers is provided, including the Riser board body, PCIe standard signal interface structure, custom signal configuration module and I2C signal compatibility module; The PCIe standard signal interface structure is mounted on the Riser board body. This structure includes solder pads for bringing out the necessary PCIe TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal, and VAUX power supply. The PCIe standard signal interface structure also has at least two sets of reserved pin solder pads. The control signals include RST_N, WAKE_N, CLKREQ_N, and PWRBRK_N signals. The reference clock signals include REFCLK_P and REFCLK_N signals. The custom signal configuration module is electrically connected to the PCIe standard signal interface structure. This module includes configuration components for adapting the bandwidth identification ID signal, board type identification ID signal, and cable presence signal. The I2C signal compatibility module is mounted on the Riser board body. This module includes structural components for adapting the I2C interface connection methods of FRU and CEM.

[0006] Furthermore, the configuration components of the custom signal configuration module include a DIP switch group and a resistor selection soldering submodule; the DIP switch group is electrically connected to the reserved pin soldering PAD of the PCIE standard signal interface structure via wires, and the resistor selection soldering submodule is provided with resistor soldering positions of various specifications, and the resistor soldering positions are connected in parallel with the signal output terminal of the DIP switch group.

[0007] Furthermore, the structural components of the I2C signal compatibility module include a shorting pad array and an FRU address configuration submodule. The shorting pad array has multiple sets of selectively shortable pads, and the input terminals of the shorting pad array are electrically connected to the I2C interface of the CEM and the I2C interface of the FRU, respectively. The FRU address configuration submodule is electrically connected to the output terminal of the shorting pad array, and the FRU address configuration submodule includes address adjustment pads that cooperate with the shorting pad array. The Riser board body is also provided with an ESD protection circuit, which is electrically connected to the signal output terminal of the PCIE standard signal interface structure.

[0008] A signal adaptation method for a multi-platform server cable riser board is provided, including the following steps: Step S1: Based on the PCIe signal requirements of the target server platform, extract the necessary PCIe TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal, and VAUX power signal through the PCIe standard signal interface structure. At the same time, select at least one set of reserved pins, solder PADs to extract the reserved pin signals, and connect the reserved pin signals to the custom signal configuration module. Among them, the control signals include RST_N signal, WAKE_N signal, CLKREQ_N signal, and PWRBRK_N signal, and the reference clock signals include REFCLK_P signal and REFCLK_N signal. Step S2: According to the custom signal type of the target server platform, adjust the DIP switch group position of the custom signal configuration module, or solder the specified resistor at the corresponding resistor soldering position of the resistor selection and soldering submodule to complete the custom signal path configuration. Step S3: Based on the I2C interface connection method of the target server platform, selectively short the shorting pad array of the I2C signal compatibility module to connect the I2C interface of FRU and CEM in the target manner. Step S4: Set the I2C slave device address of the FRU that matches the target server platform by using the address adjustment pad of the FRU address configuration submodule to complete the I2C signal compatibility configuration.

[0009] Furthermore, in step S1, the necessary PCIe signals need to be brought out and connected one by one to the corresponding solder pads of the PCIe standard signal interface structure through wires. The number and location of the reserved pin solder pads need to be determined according to the manufacturer's custom requirements of the target server platform.

[0010] Furthermore, in step S2, the adjustment positions of the DIP switch group include pull-up, pull-down, and floating states. The resistor specifications of the resistor selection and welding submodule include multiple types, and the welding operation of the resistor welding position must be performed when the DIP switch group is in the floating state.

[0011] Furthermore, in step S3, the selective shorting of the shorting pad array is achieved using conductive shorting pieces. The connection position of the shorting pieces must correspond to the I2C interface connection method of the target server platform. When the target platform uses a shared I2C interface for FRU and CEM, the shorting pieces are connected to the pad group marked as shared. When the target platform uses independent I2C interfaces for FRU and CEM, the shorting pieces are connected to the pad group marked as separate.

[0012] A method for reusing a multi-platform server cable riser board is provided, including the following steps: Step T1: Obtain the interface requirement parameters of multiple different server platforms to be adapted. The interface requirement parameters include PCIE signal type, custom signal specification, I2C connection method and FRU address information. Step T2: Based on the interface requirement parameters of each server platform, formulate a corresponding Cable connection wiring scheme. The wiring scheme includes the PCIE signal lead correspondence and the custom signal wiring correspondence. Step T3: Connect the same Cable Riser board to the motherboard of each server platform. During the connection process, adjust the Cable connection sequence according to the corresponding platform's wiring scheme. At the same time, by bringing out the necessary PCIE TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal and VAUX power signal, configure a custom signal path, adapt to the I2C interface connection method of FRU and CEM, and set the I2C slave device address of FRU to complete the signal adaptation configuration. Step T4: After the docking is completed, send a test signal to the Cable Riser board through the test equipment to verify the conduction status of the signal transmission path.

[0013] Furthermore, in step T2, the cable connection sequence adjustment scheme needs to be recorded in document form. The document must clearly indicate the connection relationship between the corresponding cable pins and the PADs soldered to the Riser board for each platform, including the correspondence between PCIE signal pins, custom signal pins, and I2C signal pins.

[0014] Furthermore, in step T4, the test signals include PCIE high-speed test signals, I2C communication test signals, and custom signal trigger test signals. When verifying the conduction state, the transmission delay time and signal integrity parameters of each signal need to be recorded. The signal integrity parameters include signal amplitude, signal edge rate, and signal bit error rate.

[0015] The beneficial effects of this invention are: (1) By standardizing signal adaptation and modular architecture design, multi-platform compatibility can be achieved, hardware reuse rate can be improved, and customized development costs and inventory pressure can be reduced; (2) Through flexible signal path configuration and interface adaptation scheme, it can adapt to the personalized needs of different platforms without modifying the core hardware, thereby improving the flexibility and efficiency of adaptation. (3) Through standardized testing and anti-interference design, we ensure stable signal transmission and accurate data interaction, reduce the risk of abnormal operation, and improve long-term reliability. Attached Figure Description

[0016] Figure 1A flowchart illustrating the specific steps of a signal adaptation method for a multi-platform server Cable Riser board provided in this embodiment; Figure 2 The following is a detailed step diagram illustrating a method for reusing a multi-platform server Cable Riser board, provided as an example. Figure 3 This is an example diagram of the I2C signal shorting pad connection provided in the embodiment. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1 A Cable Riser board adaptable to multi-platform servers is provided, including the Riser board body, PCIe standard signal interface structure, custom signal configuration module and I2C signal compatibility module; The PCIe standard signal interface structure is mounted on the Riser board body. This structure includes solder pads for bringing out the necessary PCIe TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal, and VAUX power supply. The PCIe standard signal interface structure also has at least two sets of reserved pin solder pads. The control signals include RST_N, WAKE_N, CLKREQ_N, and PWRBRK_N signals. The reference clock signals include REFCLK_P and REFCLK_N signals. The custom signal configuration module is electrically connected to the PCIe standard signal interface structure. This module includes configuration components for adapting the bandwidth identification ID signal, board type identification ID signal, and cable presence signal. The I2C signal compatibility module is mounted on the Riser board body. This module includes structural components for adapting the I2C interface connection methods of FRU and CEM.

[0019] The configuration components of the custom signal configuration module include a DIP switch group and a resistor selection soldering submodule. The DIP switch group is electrically connected to the reserved pin soldering PAD of the PCIe standard signal interface structure via wires. The resistor selection soldering submodule has resistor soldering positions of various specifications, and the resistor soldering positions are connected in parallel with the signal output terminals of the DIP switch group.

[0020] The I2C signal compatibility module's structural components include a shorting pad array and an FRU address configuration submodule. The shorting pad array has multiple sets of selectively shortable pads, and its input terminals are electrically connected to the I2C interface of the CEM and the I2C interface of the FRU, respectively. The FRU address configuration submodule is electrically connected to the output terminal of the shorting pad array and includes address adjustment pads that cooperate with the shorting pad array. The Riser board body also has an ESD protection circuit, which is electrically connected to the signal output terminal of the PCIE standard signal interface structure.

[0021] See Figure 1 This paper provides a signal adaptation method for a multi-platform server cable riser board, including the following steps: Step S1: Based on the PCIe signal requirements of the target server platform, extract the necessary PCIe TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal, and VAUX power signal through the PCIe standard signal interface structure. At the same time, select at least one set of reserved pins, solder PADs to extract the reserved pin signals, and connect the reserved pin signals to the custom signal configuration module. Among them, the control signals include RST_N signal, WAKE_N signal, CLKREQ_N signal, and PWRBRK_N signal, and the reference clock signals include REFCLK_P signal and REFCLK_N signal. Step S2: According to the custom signal type of the target server platform, adjust the DIP switch group position of the custom signal configuration module, or solder the specified resistor at the corresponding resistor soldering position of the resistor selection and soldering submodule to complete the custom signal path configuration. Step S3: Based on the I2C interface connection method of the target server platform, selectively short the shorting pad array of the I2C signal compatibility module to connect the I2C interface of FRU and CEM in the target manner. Step S4: Set the I2C slave device address of the FRU that matches the target server platform by using the address adjustment pad of the FRU address configuration submodule to complete the I2C signal compatibility configuration.

[0022] In step S1, the necessary PCIe signals need to be brought out and connected one by one to the corresponding solder pads of the PCIe standard signal interface structure through wires. The number and location of the reserved pin solder pads need to be determined according to the manufacturer's custom requirements of the target server platform.

[0023] In step S2, the adjustment positions of the DIP switch group include pull-up, pull-down, and floating states. The resistor specifications of the resistor selection and welding submodule include multiple types, and the welding operation of the resistor welding position must be performed when the DIP switch group is in the floating state.

[0024] In step S3, selective shorting of the shorting pad array is achieved using conductive shorting pieces. The connection position of the shorting pieces must correspond to the I2C interface connection method of the target server platform. When the target platform uses a shared I2C interface for FRU and CEM, the shorting pieces are connected to the pad group marked as shared. When the target platform uses independent I2C interfaces for FRU and CEM, the shorting pieces are connected to the pad group marked as separate.

[0025] See Figure 2 This paper provides a method for reusing a multi-platform server cable riser board, including the following steps: Step T1: Obtain the interface requirement parameters of multiple different server platforms to be adapted. The interface requirement parameters include PCIE signal type, custom signal specification, I2C connection method and FRU address information. Step T2: Based on the interface requirement parameters of each server platform, formulate a corresponding Cable connection wiring scheme. The wiring scheme includes the PCIE signal lead correspondence and the custom signal wiring correspondence. Step T3: Connect the same Cable Riser board to the motherboard of each server platform. During the connection process, adjust the Cable connection sequence according to the corresponding platform's wiring scheme. At the same time, by bringing out the necessary PCIE TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal and VAUX power signal, configure a custom signal path, adapt to the I2C interface connection method of FRU and CEM, and set the I2C slave device address of FRU to complete the signal adaptation configuration. Step T4: After the docking is completed, send a test signal to the Cable Riser board through the test equipment to verify the conduction status of the signal transmission path.

[0026] In step T2, the cable connection sequence adjustment scheme needs to be recorded in document form. The document must clearly indicate the connection relationship between the cable pins and the PADs soldered on the Riser board for each platform, including the correspondence between PCIE signal pins, custom signal pins and I2C signal pins.

[0027] In step T4, the test signals include PCIE high-speed test signals, I2C communication test signals, and custom signal trigger test signals. When verifying the conduction status, the transmission delay time and signal integrity parameters of each signal need to be recorded. The signal integrity parameters include signal amplitude, signal edge rate, and signal bit error rate.

[0028] Example 2 This embodiment is based on a Cable Riser board adapted to multi-platform servers, including a Riser board body, a PCIe standard signal interface structure, a custom signal configuration module, and an I2C signal compatibility module. It provides a Cable Riser board and signal adaptation method adapted to multi-platform servers, and the specific steps are as follows: Before initiating the signal adaptation process, basic preparatory work must be completed to ensure that all modules of the Cable Riser board are working properly. First, check the integrity of the main physical structure of the Riser board, and confirm that the PCIE standard signal interface structure, custom signal configuration module and I2C signal compatibility module are all firmly installed in the preset positions, and that the connecting wires between the modules are not loose or damaged. The wires use anti-interference insulated wires, and there are no cracks in the outer layer and no oxidation in the core wires.

[0029] Verify that the solder pads of the PCIe standard signal interface structure are free from oxidation and cold solder joints, with clean surfaces free of residual solder or rust. Ensure the number of reserved pin solder pads meets at least two requirements, and that pin definitions are clearly marked on the riser board surface. Inspect the custom signal configuration module: DIP switch groups should be in their initial zero-position, with smooth and unhindered movement; the solder pads of the resistor selection submodule should be free of residual solder and have smooth surfaces.

[0030] The I2C signal compatibility module's shorting pad array was confirmed to be free of short circuits and open circuits, and its initial state was checked using a multimeter in continuity mode. The address adjustment pads of the FRU address configuration submodule were kept clean. Finally, the ESD protection circuit on the Riser board was verified: the input terminals were connected to each signal lead-out pad of the PCIe standard signal interface structure, and the output terminals were grounded. An electrostatic discharge scenario was simulated using an electrostatic testing device to confirm that the protection circuit could trigger protection normally.

[0031] S1. PCIE signal output and reserved pin signal access stage: S1.1 Determine the PCIe signal requirements of the target server platform: The PCIe interface signal information of the target server platform motherboard is collected using a logic analyzer, with the collection period covering the complete signal transmission cycle. Based on the collected data, the number of channels and transmission direction of the TX high-speed data signal and RX high-speed data signal to be extracted are determined. The effective level of the control signals (RST_N, WAKE_N, CLKREQ_N, PWRBRK_N) and the phase relationship of the reference clock signals (REFCLK_P, REFCLK_N) are analyzed, and the voltage stability requirements and maximum output current limit of the VAUX power supply are clarified.

[0032] At the same time, we collect manufacturers' custom signal requirements and determine whether additional signals need to be brought out through reserved pins by reading motherboard firmware configurations or technical documents. We also clarify the transmission rate, logic level and timing relationship of these signals to avoid conflicts with necessary PCIe signals.

[0033] S1.2 exposes the necessary PCIe signals: Based on the target platform requirements, connect the necessary PCIe signals to the solder pads of the PCIe standard signal interface structure according to the preset pin definitions. Following the differential pairing principle, connect the positive and negative terminals of each group of TX and RX high-speed data signals to the same group of differential pads, ensuring that the spacing between the differential pads meets the signal integrity design requirements.

[0034] Control signals are accurately led out according to the target platform logic requirements, and their wires are kept at a reasonable distance from high-speed data signal wires to reduce crosstalk; the reference clock signal lead-out path needs to be symmetrical, and the control path length difference should be reduced to reduce timing deviation; the VAUX power signal is connected to the corresponding power soldered PAD, the wire diameter is matched with the maximum output current, and the path is kept away from high-speed data signals to reduce power supply noise interference.

[0035] Signal leads are fixed by soldering, using solder that matches the pad material. Soldering temperature and time are controlled to ensure full solder joints and good conductivity. The ESD protection circuit operates in real time, quickly conducting to ground in the event of electrostatic interference, protecting signal transmission and module safety.

[0036] In some embodiments, the necessary PCIe signals can be brought out using a flexible cable with a shielded layer. The two ends of the cable are soldered to the solder pad and the motherboard interface, respectively. The grounded shielding layer enhances anti-interference performance, adapts to different installation space layouts, and makes installation and maintenance more convenient.

[0037] S1.3 Select the reserved pin for soldering PAD and bring out the signal: Based on the manufacturer's customized requirements, select the appropriate number and location of PADs from at least two sets of reserved pins. Confirm that the electrical characteristics of the reserved pins match the customized signal requirements, that there are no spatial conflicts in the layout, and that the pin distribution matches the transmission path.

[0038] Reserved pins are led out using wires matched to the signal transmission rate. Ordinary insulated wires can be used for low-speed signals, while impedance-matched coaxial wires are selected for high-speed signals. The wires are arranged neatly, maintaining a reasonable distance from other signal wires. Key positions are fixed to prevent displacement, and the led-out signals are labeled for easy access to the configuration module later.

[0039] S1.4 connects the reserved pin signal to the custom signal configuration module: The reserved pin signal is connected to the corresponding input terminal of the custom signal configuration module via a wire. The DIP switch group is electrically connected to the PAD of the reserved pin via a wire to ensure signal transmission without attenuation or distortion.

[0040] Before soldering, the conductor cores are pre-treated by removing the oxide layer and tinning. Soldering time and temperature are controlled to avoid damaging module components. The continuity resistance of each solder joint must be tested with a multimeter to ensure it is within the preset range. Simultaneously, the signal specifications are checked to ensure they match the module input requirements; level conversion or rate adapter components are added if necessary.

[0041] In some embodiments, a pluggable interface design can be adopted, with a pin socket at the module input end and a corresponding pin plug installed at the end of the wire. Signal access is achieved through plugging and unplugging. A latch is provided at the interface to prevent loosening, which facilitates subsequent module replacement and signal adjustment.

[0042] S2. Custom signal path configuration stage: S2.1 Identifies custom signal types of the target server platform: Detect custom signals on the target platform using a spectrum analyzer or signal generator to identify signal types (bandwidth identification ID signal, board type identification ID signal, cable presence signal, etc.). Collect signal waveforms, frequencies, and logic states; analyze encoding methods, bit widths, valid states, and response times; clarify signal logic, transmission requirements, and adaptation standards; and determine whether to configure via pull-up, pull-down, or floating methods.

[0043] If there are multiple custom signals, they need to be identified and classified one by one, their configuration priorities and relationships need to be clarified, and a reasonable configuration order needs to be determined to improve configuration efficiency and accuracy.

[0044] S2.2 Adjusting the DIP switch group settings: According to the signal configuration requirements, adjust the DIP switch group to the corresponding position (pull-up, pull-down, floating). In the pull-up state, the signal is pulled to the power supply voltage through the internal resistor; in the pull-down state, it is pulled to ground potential; and in the floating state, the signal is at high impedance.

[0045] During adjustment, clearly define the correspondence between the switches and signals using the markings on the riser board. After switching, use a multimeter to check the signal output level to ensure it matches expectations. After all adjustments are complete, use a logic analyzer to check the overall output status of each signal to confirm that the waveform is stable and free from abnormal fluctuations or noise.

[0046] In some embodiments, the DIP switch group can be replaced with a programmable logic device, which pre-stores various configuration logics. Instructions are sent through the host computer software, and the device receives and calls the corresponding logic to implement signal state configuration. It supports remote and batch configuration, adapts to batch adaptation scenarios on multiple platforms, and the configuration logic can be expanded through software updates.

[0047] S2.3 Select the welding resistor for the welding submodule: When the DIP switch is in the floating state, configure a custom signal through the resistor selection and soldering submodule. Select resistors of appropriate specifications according to requirements. Pull-up and pull-down resistors must match the signal level and power supply voltage. Current-limiting or voltage-dividing resistors are calculated and determined according to the signal parameters, while considering the resistor power rating to avoid overheating damage.

[0048] Before soldering, pre-treat the resistor leads by trimming them to the appropriate length and removing the oxide layer. Use a temperature-controlled soldering iron to ensure a firm connection between the leads and the pads, free from cold solder joints or poor soldering. Soldering must be performed with the DIP switch in the unstuck position to avoid interference with the configuration.

[0049] In some embodiments, a pluggable resistor socket design can be adopted, with the resistor socket fixed at the soldering position. The resistor is installed by plugging and unplugging, eliminating the need for soldering operations, reducing configuration difficulty, facilitating quick on-site replacement of resistor specifications, and avoiding damage to the solder pads.

[0050] S2.4 Verify custom signal path configuration: Set up a test environment using a vector network analyzer or bit error rate tester, connect the Cable Riser board to the target platform motherboard, connect the input of the test equipment to a custom signal transmitter, and connect the output to a receiver.

[0051] Send test signals simulating real-world scenarios, including corresponding frequency, amplitude, duty cycle, and encoding method. Acquire the output signal waveform and analyze the path continuity, level stability, and logic correctness. If the test fails to meet requirements, check the DIP switch settings, resistor specifications, and soldering quality. Adjust as needed and retest until all custom signal configurations meet the target platform requirements.

[0052] S3. I2C interface connection adaptation phase: S3.1 Determine the I2C interface connection method of the target server platform: By consulting technical documentation or using an I2C bus analyzer, clarify the I2C interface connection method between the FRU and CEM (shared channel or two independent channels). When reviewing documentation, focus on pin definitions and connection diagrams; when using an analyzer, observe whether the I2C pin signal activity of the FRU and CEM is synchronized.

[0053] After determining the connection method, the signal transmission path should be identified. For shared interfaces, the bus aggregation method and pull-up resistor configuration should be clearly defined. For independent interfaces, the two bus paths and anti-interference measures should be confirmed to provide a basis for subsequent short-circuit operations.

[0054] S3.2 Select the corresponding shorting pad group: The I2C signal compatible module's shorting pad array has multiple groups of pads corresponding to different connection methods, clearly labeled on the riser board. Select the corresponding pad group according to the target platform's connection method; select the "Shared" labeled pad group for shared interfaces and the "Separate" labeled pad group for independent interfaces.

[0055] When selecting, confirm that the pad group identification matches the connection method, and check that the pads are intact and free from oxidation, damage or short circuits. If there are multiple redundant pad groups with the same identification, you can select any intact one to operate.

[0056] S3.3 uses a conductive shorting piece to achieve shorting: Select conductive jumpers made of high-conductivity metal, with dimensions matching the pad spacing and appropriate thickness. Connect the jumpers to the selected pad groups according to the connection method. For shared interfaces, connect the I2C_SDA and I2C_SCL pin pads of FRU and CEM to the common bus pads respectively. For independent interfaces, connect them to their respective independent bus pads.

[0057] After connection, use a multimeter to test the pad continuity resistance to ensure that the value is extremely small and stable. At the same time, check that the jumper only covers the target pad and does not contact adjacent pads, which could lead to a short circuit.

[0058] In some embodiments, short circuits can be achieved by welding wires. High conductivity insulated wires are selected, and conductive paths are formed by welding between corresponding pads according to the connection method. The solder joints are firm and free of false soldering, which is suitable for scenarios with high requirements for connection stability. Moreover, no additional shorting pieces are required, reducing material costs.

[0059] In some embodiments, such as Figure 3 As shown, for I2C signal connection adaptation, signal path selection can be achieved by using shorting pads. Taking the connection between PCBA and UBC in the figure as an example, the I2C1_CLK (TP1), I2C1_SDA (TP2) and I2C2_CLK (TP3), I2C2_SDA (TP4) signals in cable 2 are connected by shorting pads on the PCBA to achieve path configuration of I2C signals between different modules; while cable 1 is a reference form without shorting pads, its I2C1_CLK, I2C1_SDA and I2C2_CLK, I2C2_SDA signals are independently led out to the MCIO interface. This short-circuit pad connection method can flexibly adapt to the target server platform's requirements for I2C interface connection. When the FRU and CEM need to share an I2C interface or use an independent I2C interface, the corresponding short-circuit pad connection combination can be selected to achieve this. This provides a specific implementation method for the short-circuit pad array of the I2C signal compatibility module, ensuring the operability and flexibility of I2C interface connection adaptation.

[0060] S3.4 Check the I2C interface connection status: The test environment is set up using an I2C protocol analyzer. The analyzer's SDA and SCL pins are connected to the Riser board's I2C bus. After the device is powered on, it sends test signals to the I2C interface, including start conditions, slave device address, data bytes, and stop conditions.

[0061] Acquire bus signal waveforms and data frames to analyze signal transmission smoothness, and check protocol compliance, address identification accuracy, and data transmission correctness. Pay particular attention to transmission rate, level stability, and bit error rate to ensure compliance with target platform requirements.

[0062] If a connection abnormality is found, check the pad group selection, jumper connection, or wire soldering. Check the pull-up resistor configuration and the power status of FRU and CEM. Adjust and retest until the I2C interface connection is normal and FRU and CEM can exchange data normally.

[0063] S4.FRU I2C slave address configuration phase: S4.1 requires obtaining the I2C slave device address of the FRU: Based on the system configuration and communication protocol requirements of the target server platform, obtain the I2C slave device address requirements of the FRU. First, consult the target platform's system firmware configuration documentation or motherboard technical manual to clarify the FRU's I2C slave device address range, default address, and read / write bit configuration, ensuring that the address encoding format is consistent with the target platform's requirements.

[0064] If the documentation is incomplete or ambiguous, use an I2C address scanner to scan the I2C bus of the target platform. Connect the scanner's SDA and SCL pins to the bus, send different address signals sequentially and check the response, filtering out candidate addresses not occupied by other devices. Based on the FRU hardware design specifications, eliminate address conflicts with other I2C devices, and finally determine and record the unique and compatible FRU2C slave device address.

[0065] S4.2 Set the address via address adjustment pad: The number of address adjustment pads in the FRU address configuration submodule matches the number of bits in the FRU slave device address, with each group of adjustment pads corresponding to one bit of the address. The determined address is converted into binary code, and each group of address adjustment pads is either soldered or left floating according to the design specifications of the FRU address configuration submodule.

[0066] The default soldering state corresponds to address bit "1", and the floating state corresponds to address bit "0" (or the reverse according to design specifications). The pads are adjusted bit by bit strictly according to the binary encoding. Fine-diameter solder is used during soldering, and soldering is performed only on the target pad to avoid solder overflow affecting adjacent pads. Floating pads must be kept clean, free of solder residue or conductive debris to prevent accidental conduction that could lead to address bit errors.

[0067] After configuration, use an I2C address scanner again to verify the configured address, ensuring the scanner can accurately detect the address and that no other device is using it, thus confirming the address configuration is correct. If no address is detected or an address conflict exists, re-check the soldering and floating status of the pads, troubleshoot the problem, and verify again.

[0068] In some embodiments, the FRU address configuration submodule can integrate an address selection switch. Each position of the switch corresponds to a preset slave device address, and the position is clearly marked on the Riser board. Address configuration can be completed simply by switching the switch positions according to the address requirements of the target platform, without the need for soldering. This makes operation more convenient and supports rapid address switching, making it suitable for scenarios requiring frequent FRU address adjustments.

[0069] S4.3 Verify address matching: Connect the configured Cable Riser board to the main device (motherboard I2C main controller) of the target server platform, ensuring that the power supply to the Riser board and the main device is stable and that all interfaces are securely connected.

[0070] The master device sends an address access command to the FRU, which includes the FRU's I2C slave address and read / write operation identifier. After sending the command, the master device monitors whether the I2C bus generates an acknowledgment signal: if the FRU address matches the address in the command, the FRU will pull the SDA line low within a specified clock cycle to generate an acknowledgment, and the master device will continue to perform subsequent data read / write operations; if no acknowledgment signal is detected, it indicates that there is a problem with the address matching.

[0071] Repeated read and write operations were performed to verify the communication stability between the master device and the FRU, and to check for any anomalies such as communication timeouts, data transmission errors, or lost responses. Device information (such as model number and serial number) stored internally in the FRU was read and compared with known data to confirm the accuracy of the read data. Test data was written to the FRU's configuration register, and after writing, the register was read again to verify that the data was stored correctly.

[0072] If an anomaly occurs during communication, recheck the configuration status of the address adjustment pads or the position of the address selection switch, troubleshoot issues such as FRU power supply and I2C bus interference, and re-execute the verification process after adjustment until the master device and FRU can communicate stably and accurately.

[0073] S4.4 completes I2C signal compatibility configuration: After the address matching verification is passed, the entire I2C signal compatibility configuration process is reviewed and checked. It is confirmed that the shorting status of the shorting pad array is consistent with the I2C connection method of the target platform, and that the I2C pin connections of FRU and CEM are correct, with no cross-connections or short circuits.

[0074] Check the auxiliary circuitry of the I2C bus: confirm that the specifications and installation positions of the pull-up resistors meet the design requirements and are firmly soldered; that the ESD protection components (such as TVS diodes) are properly connected and can provide electrostatic protection for the bus; and that the bus wiring is reasonable, maintains sufficient distance from other signal lines, and has no obvious risk of signal crosstalk.

[0075] A complete I2C communication comprehensive test was performed. The master device sequentially interacted with the FRU and CEM through various data exchanges, including reading device parameters, writing configuration commands, and performing status queries. The signal waveforms and data frames throughout the communication process were recorded using an I2C protocol analyzer to ensure no frame loss, bit errors, or response failures. After all checks and tests passed, the I2C signal compatibility configuration process was completed, and the FRU and CEM could reliably and stably transmit I2C signals and exchange data with the master device.

[0076] S5. Cable Riser board reuse implementation stage: S5.1 retrieves interface requirement parameters for multiple different server platforms: We collected interface requirement parameters for multiple server platforms to be adapted. The parameters for each platform include PCIE signal type, custom signal specifications, I2C connection method, and FRU address information.

[0077] For each platform, identify the number of channels for necessary PCIe signals, types of control signals, number of reference clocks, and VAUX power requirements; clarify the usage requirements of reserved pins; record the name, function, logic level, transmission rate, encoding method, and timing relationship of custom signals; determine the I2C interface connection method (shared / independent), transmission rate, and level standard; collect the I2C slave device address, read / write bit configuration, and address information of other I2C devices on the bus from the FRU to avoid address conflicts.

[0078] All platform requirements parameters were categorized and archived to form a clear and unambiguous requirements list, providing an accurate basis for subsequent development of line sequence adjustment plans.

[0079] S5.2 Develop a corresponding cable connection wiring sequence adjustment plan: Based on the interface requirement parameter list for each platform, a customized cable connection wiring scheme is developed for each platform. The scheme clarifies the correspondence between each cable pin and the PAD soldered to the riser board, including the precise correspondence of PCIe signal pins, custom signal pins, and I2C signal pins, and marks the signal transmission direction and key electrical parameters.

[0080] The solution is documented in a standardized format, including a table of cable pin numbers, Riser board solder pad markings, signal types, transmission directions, parameter specifications, and a diagram illustrating the connection between the cable and the Riser board, clearly outlining connection precautions. The document concludes with a signature section for preparation, review, and approval to ensure the solution's validity and traceability.

[0081] In some embodiments, the wiring sequence adjustment scheme can be stored in a non-volatile memory unit (such as EEPROM) on the Cable Riser board. The memory unit is connected to the Riser board control module via an I2C or SPI interface. When the Riser board interfaces with different platforms, the control module can read the stored scheme data, display the wiring sequence requirements via the display module, or send it to a host computer via the communication interface for operators to view, thereby improving the ease of use of the scheme.

[0082] S5.3 same Cable Riser board interoperability with motherboards on different platforms: Prepare a cable that matches the wiring scheme of the target platform, and check that the cable pins are not bent or damaged, and that the insulation layer is undamaged. According to the wiring adjustment scheme, connect each pin of the cable to the corresponding solder pad on the riser board. The connection method can be soldering or plug-in interface: for soldering connections, ensure that the solder joints are firm and have good conductivity; for plug-in connections, align the interface and fix it with a locking structure to prevent loosening during use.

[0083] Reliably connect the Riser board to the motherboard's power and ground interfaces to form a stable power supply and grounding loop, reducing power supply noise and grounding interference. Then, following the signal adaptation process described above, complete the PCIE signal lead-out and reserved pin access, custom signal path configuration, I2C interface connection adaptation, and FRU address configuration in sequence. After each configuration step is completed, perform targeted testing and verification.

[0084] When connecting to different server platforms, there is no need to replace the main Cable Riser board. Only the corresponding Cable connection wiring scheme needs to be changed, the Cable wiring sequence adjusted, and the signal adaptation configuration re-executed. During the connection process, take care to protect the Riser board modules and solder pads, avoiding external impacts and contact with sharp tools. After the operation, clean the Riser board surface to remove dust or residual solder.

[0085] S5.4 performs multi-dimensional performance tests and verifies the conduction status: After each platform is integrated and adapted, a closed-loop testing system is set up to connect the Cable Riser board to the target platform motherboard and testing equipment to ensure that each device works properly.

[0086] The testing equipment generates PCIe high-speed test signals, I2C communication test signals, and custom signal trigger test signals to test the transmission characteristics of these three types of signals. For PCIe high-speed signals, transmission delay time, signal amplitude, edge rate, and bit error rate are tested to ensure compliance with the signal integrity requirements of the target platform. For I2C communication signals, bus on-state, transmission rate, and timing parameters are verified to ensure compliance with the I2C protocol specification. For custom signals, trigger response accuracy and signal stability are tested.

[0087] Test data is recorded and uploaded to the management platform in real time for analysis and judgment: if all test signals can be transmitted smoothly, all parameters meet the platform requirements, and there are no conduction abnormalities, then the platform is compatible and qualified; if there are unqualified items, the cause of the problem is located based on the test data (such as incorrect wiring sequence or improper configuration), and the test is repeated after adjustment until all test items pass the verification.

[0088] VII. Summary of Technical Results This solution achieves significant technical results through the synergy of device structure and detailed methodological steps. First, through the collaborative design of the Riser board body, PCIE standard signal interface structure, custom signal configuration module, and I2C signal compatibility module, the same Cable Riser board can be adapted to different server platforms, significantly improving reusability. This effect is entirely achieved through the device structure, greatly reducing customized development, processing control costs, and inventory pressure.

[0089] This solution offers high adaptability and flexibility, supporting multiple implementation methods for custom signal configuration, I2C interface connection, and wiring sequence adjustment, meeting the personalized needs of various platforms without requiring modifications to the main hardware of the Riser board. It also boasts outstanding signal transmission stability and reliability, with ESD protection design, reasonable wiring and soldering specifications, and multi-dimensional testing and verification effectively reducing crosstalk, timing deviations, bit error rates, and other issues, ensuring long-term reliable operation.

[0090] Finally, the solution is highly maintainable and scalable, with convenient configuration adjustment design and standardized testing process, facilitating on-site maintenance and problem localization. It also supports online updates to adapt to new platforms, making it suitable for server platform iteration scenarios.

[0091] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A Cable Riser board adaptable to multi-platform servers, characterized in that, Includes the main body of the Riser board, the PCIe standard signal interface structure, the custom signal configuration module, and the I2C signal compatibility module; The PCIe standard signal interface structure is mounted on the Riser board body. This structure includes solder pads for bringing out the necessary PCIe TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal, and VAUX power supply. The PCIe standard signal interface structure also has at least two sets of reserved pin solder pads. The control signals include RST_N, WAKE_N, CLKREQ_N, and PWRBRK_N signals. The reference clock signals include REFCLK_P and REFCLK_N signals. The custom signal configuration module is electrically connected to the PCIe standard signal interface structure. This module includes configuration components for adapting the bandwidth identification ID signal, board type identification ID signal, and cable presence signal. The I2C signal compatibility module is mounted on the Riser board body. This module includes structural components for adapting the I2C interface connection methods of FRU and CEM.

2. The Cable Riser board adapted to multi-platform servers according to claim 1, characterized in that, The configuration components of the custom signal configuration module include a DIP switch group and a resistor selection soldering submodule. The DIP switch group is electrically connected to the reserved pin soldering PAD of the PCIE standard signal interface structure via wires. The resistor selection soldering submodule has resistor soldering positions of various specifications, and the resistor soldering positions are connected in parallel with the signal output terminal of the DIP switch group.

3. The Cable Riser board adapted to multi-platform servers according to claim 1, characterized in that, The I2C signal compatibility module comprises a shorting pad array and an FRU address configuration submodule. The shorting pad array has multiple sets of selectively shortable pads, and its input terminals are electrically connected to the I2C interface of the CEM and the I2C interface of the FRU, respectively. The FRU address configuration submodule is electrically connected to the output terminal of the shorting pad array and includes address adjustment pads that cooperate with the shorting pad array. The Riser board body also has an ESD protection circuit, which is electrically connected to the signal output terminal of the PCIE standard signal interface structure.

4. A signal adaptation method for a multi-platform server cable riser board, employing a multi-platform server adapted cable riser board as described in any one of claims 1-3, characterized in that, Includes the following steps: Step S1: Based on the PCIe signal requirements of the target server platform, extract the necessary PCIe TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal, and VAUX power signal through the PCIe standard signal interface structure. At the same time, select at least one set of reserved pins, solder PADs to extract the reserved pin signals, and connect the reserved pin signals to the custom signal configuration module. Among them, the control signals include RST_N signal, WAKE_N signal, CLKREQ_N signal, and PWRBRK_N signal, and the reference clock signals include REFCLK_P signal and REFCLK_N signal. Step S2: According to the custom signal type of the target server platform, adjust the DIP switch group position of the custom signal configuration module, or solder the specified resistor at the corresponding resistor soldering position of the resistor selection and soldering submodule to complete the custom signal path configuration. Step S3: Based on the I2C interface connection method of the target server platform, selectively short the shorting pad array of the I2C signal compatibility module to connect the I2C interface of FRU and CEM in the target manner. Step S4: Set the I2C slave device address of the FRU that matches the target server platform by using the address adjustment pad of the FRU address configuration submodule to complete the I2C signal compatibility configuration.

5. The signal adaptation method for a multi-platform server Cable Riser board according to claim 4, characterized in that, In step S1, the necessary PCIe signals need to be brought out and connected one by one to the corresponding solder pads of the PCIe standard signal interface structure through wires. The number and location of the reserved pin solder pads need to be determined according to the manufacturer's custom requirements of the target server platform.

6. The signal adaptation method for a multi-platform server Cable Riser board according to claim 4, characterized in that, In step S2, the adjustment positions of the DIP switch group include pull-up, pull-down, and floating states. The resistor specifications of the resistor selection and welding submodule include multiple types, and the welding operation of the resistor welding position must be performed when the DIP switch group is in the floating state.

7. The signal adaptation method for a multi-platform server Cable Riser board according to claim 4, characterized in that, In step S3, selective shorting of the shorting pad array is achieved using conductive shorting pieces. The connection position of the shorting pieces must correspond to the I2C interface connection method of the target server platform. When the target platform uses a shared I2C interface for FRU and CEM, the shorting pieces are connected to the pad group marked as shared. When the target platform uses independent I2C interfaces for FRU and CEM, the shorting pieces are connected to the pad group marked as separate.

8. A method for reusing a multi-platform server Cable Riser board, employing a multi-platform server-adapted Cable Riser board as described in any one of claims 1-3, characterized in that, Includes the following steps: Step T1: Obtain the interface requirement parameters of multiple different server platforms to be adapted. The interface requirement parameters include PCIE signal type, custom signal specification, I2C connection method and FRU address information. Step T2: Based on the interface requirement parameters of each server platform, formulate a corresponding Cable connection wiring scheme. The wiring scheme includes the PCIE signal lead correspondence and the custom signal wiring correspondence. Step T3: Connect the same Cable Riser board to the motherboard of each server platform. During the connection process, adjust the Cable connection sequence according to the corresponding platform's wiring scheme. At the same time, by bringing out the necessary PCIE TX high-speed data signal, RX high-speed data signal, control signal, reference clock signal and VAUX power signal, configure a custom signal path, adapt to the I2C interface connection method of FRU and CEM, and set the I2C slave device address of FRU to complete the signal adaptation configuration. Step T4: After the docking is completed, send a test signal to the Cable Riser board through the test equipment to verify the conduction status of the signal transmission path.

9. The method for reusing a multi-platform server Cable Riser board according to claim 8, characterized in that, In step T2, the cable connection sequence adjustment scheme needs to be recorded in document form. The document must clearly indicate the connection relationship between the cable pins and the PADs soldered on the Riser board for each platform, including the correspondence between PCIE signal pins, custom signal pins and I2C signal pins.

10. The method for reusing a multi-platform server Cable Riser board according to claim 8, characterized in that, In step T4, the test signals include PCIE high-speed test signals, I2C communication test signals, and custom signal trigger test signals. When verifying the conduction status, the transmission delay time and signal integrity parameters of each signal need to be recorded. The signal integrity parameters include signal amplitude, signal edge rate, and signal bit error rate.

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