Liquid crystal display panel and liquid crystal display device

Abstract

The invention provides a liquid crystal display panel and a liquid crystal display device. The liquid crystal display panel comprises a plurality of data lines, a plurality of gate lines and a plurality of pixels, one column of pixels is electrically connected with one data line, one row of pixels is electrically connected with two gate lines, the two gate lines are located on the two sides of the row of pixels in the column direction respectively, the polarities of data signals transmitted by every two adjacent data lines are opposite, and the polarities of the data signals transmitted by the two adjacent data lines are opposite. The jth data line is electrically connected with the (j + 6) th data line in the peripheral area, the (j + 1) th data line is electrically connected with the (j + 7) th data line in the peripheral area, the (j + 2) th data line is electrically connected with the (j + 8) th data line in the peripheral area, the (j + 3) th data line is electrically connected with the (j + 9) th data line in the peripheral area, and the (j + 4) th data line is electrically connected with the (j + 10) th data line in the peripheral area. And the (j + 5) th data line is electrically connected with the (j + 11) th data line in the peripheral area. The risk that vertical bright and dark fringes appear on the liquid crystal display panel is reduced, and vertical crosstalk is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a liquid crystal display panel and a liquid crystal display device. Background Technology

[0002] Liquid crystal display (LCD) panels typically consist of multiple data lines, multiple gate lines, and multiple pixels arranged in a pixel array. In a traditional 1G1D (one gate line, one data line) architecture LCD panel, one pixel is electrically connected to one data line and one gate line, a row of pixels is electrically connected to one gate line, and a column of pixels is electrically connected to one data line. The data signals transmitted by adjacent data lines have opposite polarities, forming an alternating positive and negative polarity arrangement; that is, the number of consecutively arranged pixel columns of the same polarity is one.

[0003] To reduce the number and cost of driver chips, the industry has proposed a DLS (Data Line Sharing) architecture for liquid crystal display panels. In a DLS architecture liquid crystal display panel, the number of data lines is half the number of pixel columns, and a data line is located between two columns of pixels and electrically connected to the two adjacent columns of pixels. However, sharing a single data line between two columns of pixels increases the number of consecutively arranged pixel columns of the same polarity in the pixel array to two, which is double the number of consecutively arranged pixel columns of the same polarity compared to the traditional 1G1D architecture.

[0004] Increasing the number of consecutively arranged pixel columns of the same polarity can easily cause noticeable vertical bright and dark stripes in LCD panels. Furthermore, in DLS-based LCD panels, the distance between pixels and the data lines on either side is inconsistent. This imbalance between the parasitic capacitance formed by the pixel and the data line to its left and the parasitic capacitance formed by the pixel and the data line to its right leads to worsened vertical crosstalk, affecting display quality.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a liquid crystal display panel and a liquid crystal display device, which aims to solve the technical problem of vertical bright and dark stripes appearing in liquid crystal display panels in the prior art.

[0007] This application provides a liquid crystal display panel, which includes a display area and a peripheral area. The liquid crystal display panel includes: multiple data lines; multiple gate lines; and multiple pixels arranged in a pixel array. The pixel array includes multiple rows of pixels and multiple columns of pixels. Pixels in the same column have the same color, pixels in adjacent columns have different colors, and pixels in the same row have different colors. Each column of pixels is electrically connected to one data line, and each row of pixels is electrically connected to two gate lines, the two gate lines being located in the column direction of the row of pixels. On both sides, the data signals transmitted by two adjacent data lines have opposite polarities. The j-th data line is electrically connected to the (j+6)-th data line in the outer perimeter area, the (j+1)-th data line is electrically connected to the (j+7)-th data line in the outer perimeter area, the (j+2)-th data line is electrically connected to the (j+8)-th data line in the outer perimeter area, the (j+3)-th data line is electrically connected to the (j+9)-th data line in the outer perimeter area, the (j+4)-th data line is electrically connected to the (j+10)-th data line in the outer perimeter area, and the (j+5)-th data line is electrically connected to the (j+11)-th data line in the outer perimeter area, where j is a positive integer.

[0008] In the aforementioned liquid crystal display panel, the 2i-1th gate line is electrically connected to the pixels located in the j-th, j+2-th, and j+4-th columns of the i-th row of pixels; the 2ith gate line is electrically connected to the pixels located in the j+1-th, j+3-th, and j+5-th columns of the i-th row of pixels; the 2i-1th gate line is also electrically connected to the pixels located in the j+7-th, j+9-th, and j+11-th columns of the i-th row of pixels; and the 2ith gate line is also electrically connected to the pixels located in the j+6-th, j+8-th, and j+10-th columns of the i-th row of pixels, where i is a positive integer.

[0009] In the aforementioned liquid crystal display panel, the 2i+1th gate line is electrically connected to the pixels located in the j+1th, j+3rd, and j+5th columns of the i+1th row of pixels; the 2i+2th gate line is electrically connected to the pixels located in the jth, j+2nd, and j+4th columns of the i+1th row of pixels; the 2i+1th gate line is also electrically connected to the pixels located in the j+6th, j+8th, and j+10th columns of the i+1th row of pixels; and the 2i+2th gate line is also electrically connected to the pixels located in the j+7th, j+9th, and j+11th columns of the i+1th row of pixels.

[0010] In the aforementioned liquid crystal display panel, the 2i+3 gate line is electrically connected to the pixels located in the (j+1), (j+3), and (j+5) columns of the (i+2)th row of pixels; the 2i+4 gate line is electrically connected to the pixels located in the (j), (j+2), and (j+4) columns of the (i+2)th row of pixels; the 2i+3 gate line is also electrically connected to the pixels located in the (j+6), (j+8), and (j+10) columns of the (i+2)th row of pixels; and the 2i+4 gate line is also electrically connected to the pixels located in the (j+7), (j+9), and (j+11) columns of the (i+2)th row of pixels.

[0011] In the aforementioned liquid crystal display panel, the 2i+5th gate line is electrically connected to the pixels located in the j-th, j+2-th, and j+4-th columns of the i+3-th row; the 2i+6th gate line is electrically connected to the pixels located in the j+1-th, j+3-th, and j+5-th columns of the i+3-th row; the 2i+5th gate line is also electrically connected to the pixels located in the j+7-th, j+9-th, and j+11-th columns of the i+3-th row; and the 2i+6th gate line is also electrically connected to the pixels located in the j+6-th, j+8-th, and j+10-th columns of the i+3-th row.

[0012] In the aforementioned liquid crystal display panel, a pixel electrically connected to the (2i-1)th gate line in the i-th row is a first type of pixel, and a pixel electrically connected to the 2ith gate line in the i-th row is a second type of pixel. Each pixel includes a first end and a second end, which are opposite ends of the pixel in the column direction. At least three transistors of the first type of pixel are located at the first end of the first type of pixel, and at least three transistors of the second type of pixel are located at the second end of the second type of pixel, where i is a positive integer. The (2i-1)th gate line is electrically connected to at least one transistor of the first type of pixel at the first end of the first type of pixel, and the 2ith gate line is electrically connected to at least one transistor of the second type of pixel at the second end of the second type of pixel.

[0013] In the aforementioned liquid crystal display panel, the pixel electrodes of the first type of pixel and the pixel electrodes of the second type of pixel in a row are staggered in the column direction.

[0014] In the aforementioned liquid crystal display panel, in the j-th column of pixels, the distance between the pixel electrode of the first type of pixel located in the i-th row and the pixel electrode of the second type of pixel located in the (i+1)-th row is a first distance; in the j-th column of pixels, the distance between the pixel electrode of the second type of pixel located in the (i+1)-th row and the pixel electrode of the second type of pixel located in the (i+2)-th row is a second distance; in the j-th column of pixels, the distance between the pixel electrode of the second type of pixel located in the (i+2)-th row and the pixel electrode of the first type of pixel located in the (i+3)-th row is a third distance; the third distance is greater than the second distance, and the second distance is greater than the first distance.

[0015] In the aforementioned liquid crystal display panel, in the (j+1)th column of pixels, the distance between the pixel electrode of the second type of pixel located in the i-th row and the pixel electrode of the first type of pixel located in the (i+1)th row is the third distance; in the (j+1)th column of pixels, the distance between the pixel electrode of the first type of pixel located in the i+1th row and the pixel electrode of the first type of pixel located in the i+2th row is the second distance; and in the (j+1)th column of pixels, the distance between the pixel electrode of the first type of pixel located in the i+2th row and the pixel electrode of the second type of pixel located in the i+3th row is the first distance.

[0016] This application also provides a liquid crystal display device, including a source driver chip and the aforementioned liquid crystal display panel.

[0017] The liquid crystal display panel and liquid crystal display device provided in the embodiments of this application adopt a quasi-1G1D architecture superimposed with a dual gate line architecture. By electrically connecting data lines corresponding to pixels of the same color in a six-column spacing in the peripheral area, the number of data lines is kept equal to the number of pixel columns, while achieving the technical effect of halving the number of driver chips. Specifically, the j-th data line is electrically connected to the (j+6)-th data line in the peripheral area, the (j+1)-th data line is electrically connected to the (j+7)-th data line in the peripheral area, and so on, so that every two data lines electrically connected in the peripheral area provide data signals to the pixel column of the same color. Since these two data lines are connected to the same source driver chip output terminal after being electrically connected in the peripheral area, it is equivalent to one output terminal of the source driver chip simultaneously driving two columns of pixels of the same color, thereby halving the required number of output channels of the source driver chip and achieving the technical effect of halving the number of driver chips.

[0018] In the liquid crystal display panel and liquid crystal display device of this application, a column of pixels is electrically connected to a data line, and the data signals transmitted by adjacent data lines have opposite polarities, forming an alternating positive and negative polarity arrangement. That is, the number of consecutively arranged pixel columns of the same polarity is 1. Compared to the case where the number of consecutively arranged pixel columns of the same polarity in a DLS architecture liquid crystal display panel is 2, this application reduces the number of consecutively arranged pixel columns of the same polarity by half, making the number of consecutively arranged pixel columns of the same polarity the same as that in a conventional 1G1D architecture liquid crystal display panel. Reducing the number of consecutively arranged pixel columns of the same polarity lowers the risk of vertical bright and dark stripes appearing on the liquid crystal display panel and improves display quality.

[0019] In the liquid crystal display panel and liquid crystal display device of this application, each pixel has data lines with opposite polarities on both sides. Taking a pixel located in the j-th column as an example, one side of this pixel is the (j-1)-th data line, and the other side is the j-th data line. Since the data signals transmitted by adjacent data lines have opposite polarities, the data signals transmitted by the (j-1)-th data line and the j-th data line have opposite polarities. The parasitic capacitance formed by this pixel and the (j-1)-th data line to its left is affected by the data signal of the (j-1)-th data line, and the parasitic capacitance formed by this pixel and the j-th data line to its right is affected by the data signal of the j-th data line. Because the data signals transmitted by the (j-1)-th data line and the j-th data line have opposite polarities, the two parasitic capacitances have opposite effects on the voltage of the pixel, and their effects cancel each other out, reducing the impact of parasitic capacitance imbalance on the pixel voltage, reducing vertical crosstalk, and improving display quality.

[0020] In the liquid crystal display panel and liquid crystal display device of this application, the same data line is electrically connected only to pixels of the same color. When displaying a solid color image, a dual-color mixed image, or a white image, the voltage change amplitude of the data signal transmitted between different frames on the same data line is small, the charging load on the pixels is light, the charging rate of the pixels is high, and the display quality is improved. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the pixel array of a liquid crystal display panel provided in an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the structure of pixels in a liquid crystal display panel provided in an embodiment of this application. Detailed Implementation

[0024] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0026] The technical solutions of different embodiments of this application can be combined with each other.

[0027] like Figure 1As shown, the liquid crystal display device of this application includes a liquid crystal display panel, a timing controller, and a source driver chip. The liquid crystal display panel includes at least one gate driving circuit, multiple data lines DL, multiple gate lines SL, and multiple pixels PX, with the pixels PX arranged in a pixel array. The timing controller provides control signals to the gate driving circuit and the source driver chip. The gate driving circuit provides scan signals to the multiple gate lines SL, and the source driver chip provides data signals to the multiple data lines DL. Pixels PX receive scan signals through the gate lines SL and data signals through the data lines DL, thereby realizing image display.

[0028] The liquid crystal display panel provided in the embodiments of this application includes a display area and a peripheral area, such as Figure 1 and Figure 2 As shown, the liquid crystal display panel includes multiple data lines DL, multiple gate lines SL, and multiple pixels PX. The multiple pixels PX are disposed in the display area and arranged into a pixel array, which includes multiple rows and multiple columns of pixels. Pixels PX in the same column have the same color, pixels PX in adjacent columns have different colors, and pixels PX in the same row have different colors for adjacent pixels PX.

[0029] A pixel PX is electrically connected to one data line DL and one gate line SL. A column of pixels is electrically connected to one data line DL, and the number of data lines DL is equal to the number of columns in the pixel array. A row of pixels is electrically connected to two gate lines SL, located on opposite sides of the row of pixels in the column direction, and the number of gate lines SL is twice the number of rows in the pixel array. The data signals transmitted by adjacent data lines DL have opposite polarities; that is, one data line DL transmits a positive signal, and the adjacent data line DL transmits a negative signal. Positive polarity means that the voltage of the data signal transmitted by the data line DL is greater than the voltage of the common signal of the common electrode, and negative polarity means that the voltage of the data signal transmitted by the data line DL is less than the voltage of the common signal of the common electrode. A column of pixels electrically connected to the same data line DL has the same polarity, and a column of pixels electrically connected to an adjacent data line DL also has the same polarity.

[0030] In the embodiments of this application, such as Figure 2As shown, the j-th data line DL[j] is electrically connected to the (j+6)-th data line DL[j+6] in the outer area; the (j+1)-th data line DL[j+1] is electrically connected to the (j+7)-th data line DL[j+7] in the outer area; the (j+2)-th data line DL[j+2] is electrically connected to the (j+8)-th data line DL[j+8] in the outer area; the (j+3)-th data line DL[j+3] is electrically connected to the (j+9)-th data line DL[j+9] in the outer area; the (j+4)-th data line DL[j+4] is electrically connected to the (j+10)-th data line DL[j+10] in the outer area; and the (j+5)-th data line DL[j+5] is electrically connected to the (j+11)-th data line DL[j+11] in the outer area. Here, j is a positive integer. Data line j[j] and data line j+6[j+6] are electrically connected in the outer area via a conductive connecting line; data line j+1[j+1] and data line j+7[j+7] are electrically connected in the outer area via a conductive connecting line; data line j+2[j+2] and data line j+8[j+8] are electrically connected in the outer area via a conductive connecting line; data line j+3[j+3] and data line j+9[j+9] are electrically connected in the outer area via a conductive connecting line; data line j+4[j+4] and data line j+10[j+10] are electrically connected in the outer area via a conductive connecting line; data line j+5[j+5] and data line j+11[j+11] are electrically connected in the outer area via a conductive connecting line. The conductive connecting line is located in the outer area and is electrically connected to the data line DL.

[0031] The j-th data line DL[j] is electrically connected to the pixel PX of the j-th column C[j]. The (j+6)-th data line DL[j+6] is electrically connected to the pixel PX of the (j+6)-th column C[j+6]. The pixel PX of the j-th column C[j] has the same color as the pixel PX of the (j+6)-th column C[j+6]. The (j+1)-th data line DL[j+1] is electrically connected to the pixel PX of the (j+1)-th column C[j+1]. The (j+7)-th data line DL[j+7] is electrically connected to the pixel PX of the (j+7)-th column C[j+7]. The pixel PX of the (j+1)-th column C[j+1] has the same color as the pixel PX of the (j+7)-th column C[j+7]. Data line j+2 DL[j+2] is electrically connected to pixel PX of column j+2 C[j+2]. Data line j+8 DL[j+8] is electrically connected to pixel PX of column j+8 C[j+8]. Pixel PX of column j+2 C[j+2] has the same color as pixel PX of column j+8 C[j+8]. Data line j+3 DL[j+3] is electrically connected to pixel PX of column j+3 C[j+3]. Data line j+9 DL[j+9] is electrically connected to pixel PX of column j+9 C[j+9]. Pixel PX of column j+3 C[j+3] has the same color as pixel PX of column j+9 C[j+9]. Data line j+4 DL[j+4] is electrically connected to pixel PX of column j+4 C[j+4]. Data line j+10 DL[j+10] is electrically connected to pixel PX of column j+10 C[j+10]. Pixel PX of column j+4 C[j+4] has the same color as pixel PX of column j+10 C[j+10]. Data line j+5 DL[j+5] is electrically connected to pixel PX of column j+5 C[j+5]. Data line j+11 DL[j+11] is electrically connected to pixel PX of column j+11 C[j+11]. Pixel PX of column j+5 C[j+5] has the same color as pixel PX of column j+11 C[j+11].

[0032] In the embodiments of this application, such as Figure 2As shown, the 2i-1th gate line SL[2i-1] is electrically connected to the pixel PX located in the j-th column C[j], the (j+2)-th column C[j+2], and the (j+4)-th column C[j+4] of the pixel PX in the i-th row R[i]. The 2ith gate line SL[2i] is electrically connected to the pixel PX located in the (j+1)-th column C[j+1], the (j+3)-th column C[j+3], and the (j+5)-th column C[j+5] of the pixel PX in the i-th row R[i]. The 2i-1th gate line... Gate line SL[2i-1] is also electrically connected to the pixel PX located in the (j+7)th column C[j+7], (j+9)th column C[j+9], and (j+11)th column C[j+11] of the pixel PX in the i-th row R[i]. Gate line SL[2i] is also electrically connected to the pixel PX located in the (j+6)th column C[j+6], (j+8)th column C[j+8], and (j+10)th column C[j+10] of the pixel PX in the i-th row R[i]. i is a positive integer.

[0033] Gate line SL[2i+1] of row 2i+1 is electrically connected to the pixel PX located in column (j+1) C[j+1], column (j+3) C[j+3], and column (j+5) C[j+5] of row (i+1) R[i+1]. Gate line SL[2i+2] of row 2i+2 is electrically connected to the pixel PX located in column (j) C[j], column (j+2) C[j+2], and column (j+4) C[j+4] of row (i+1) R[i+1]. Gate line SL[2i+1] is also electrically connected to the pixel PX located in column j+6 C[j+6], column j+8 C[j+8], and column j+10 C[j+10] of the pixel PX in row i+1 R[i+1]. Gate line SL[2i+2] is also electrically connected to the pixel PX located in column j+7 C[j+7], column j+9 C[j+9], and column j+11 C[j+11] of the pixel PX in row i+1 R[i+1].

[0034] Gate line SL[2i+3] of row 2i+2 is electrically connected to the pixel PX located in column (j+1) C[j+1], column (j+3) C[j+3], and column (j+5) C[j+5] of row (i+2) R[i+2]. Gate line SL[2i+4] of row 2i+3 is electrically connected to the pixel PX located in column (j) C[j], column (j+2) C[j+2], and column (j+4) C[j+4] of row (i+2) R[i+2]. Gate line SL[2i+3] is also electrically connected to the pixel PX located in column j+6 C[j+6], column j+8 C[j+8], and column j+10 C[j+10] of the pixel PX in row i+2 R[i+2]. Gate line SL[2i+4] is also electrically connected to the pixel PX located in column j+7 C[j+7], column j+9 C[j+9], and column j+11 C[j+11] of the pixel PX in row i+2 R[i+2].

[0035] Gate line SL[2i+5] of row 2i+3 is electrically connected to the pixel PX located in column j C[j], column j+2 C[j+2], and column j+4 C[j+4] of row i+3 R[i+3]. Gate line SL[2i+6] of row 2i+6 is electrically connected to the pixel PX located in column j+1 C[j+1], column j+3 C[j+3], and column j+5 C[j+5] of row i+3 R[i+3]. Gate line SL[2i+5] is also electrically connected to the pixel PX located in column j+7 C[j+7], column j+9 C[j+9], and column j+11 C[j+11] of the pixel PX in row i+3 R[i+3]. Gate line SL[2i+6] is also electrically connected to the pixel PX located in column j+6 C[j+6], column j+8 C[j+8], and column j+10 C[j+10] of the pixel PX in row i+3 R[i+3].

[0036] In the embodiments of this application, a pixel PX electrically connected to the (2i-1)th gate line SL[2i-1] in the i-th row R[i] is a first-type pixel PX1, and a pixel PX electrically connected to the (2i-1)th gate line SL[2i] in the i-th row R[i] is a second-type pixel PX2. A pixel PX includes a first end and a second end, which are opposite ends of the pixel PX in the column direction. A set of transistors (including at least three transistors) of the first-type pixel PX1 is located at the first end of the first-type pixel PX1, and a set of transistors (including at least three transistors) of the second-type pixel PX2 is located at the second end of the second-type pixel PX2. The (2i-1)th gate line SL[2i-1] is electrically connected to at least one transistor of the first-type pixel PX1 at the first end of the first-type pixel PX1, and the (2i-1)th gate line SL[2i] is electrically connected to at least one transistor of the second-type pixel PX2 at the second end of the second-type pixel PX2.

[0037] like Figure 3 As shown, a pixel PX includes a pixel electrode, at least three transistors, and a common electrode. The pixel electrode includes a main pixel electrode and a secondary pixel electrode. The main pixel electrode includes four domains, and the secondary pixel electrode includes four domains, making it an 8-domain pixel electrode. At least three transistors are disposed on one side of the pixel electrode in the column direction, and at least three transistors are not disposed between the main pixel electrode and the secondary pixel electrode.

[0038] At least three transistors are included, comprising a first transistor, a second transistor, and a third transistor. The gate of the first transistor is electrically connected to gate line SL, the source of the first transistor is electrically connected to data line DL, and the drain of the first transistor is electrically connected to the main pixel electrode. The gate of the second transistor is electrically connected to gate line SL, the source of the second transistor is electrically connected to the drain of the first transistor, and the drain of the second transistor is electrically connected to the next pixel electrode. The gate of the third transistor is electrically connected to gate line SL, the source of the third transistor is electrically connected to the drain of the first transistor, and the drain of the third transistor is electrically connected to a storage capacitor.

[0039] In the embodiments of this application, as shown in Table 1, the arrangement of the plurality of pixels PX of the liquid crystal display panel is as shown in Table 1 below:

[0040] Table 1 In Table 1, PX1 represents the first type of pixel PX1, and PX2 represents the second type of pixel PX2.

[0041] In the embodiments of this application, the pixel electrodes of the first type of pixel PX1 and the pixel electrodes of the second type of pixel PX2 in a row are offset from each other in the column direction. This offset means that the edges of the pixel electrodes of the first type of pixel PX1 in the column direction are not flush with the edges of the pixel electrodes of the second type of pixel PX2 in the column direction. Furthermore, the line connecting the center positions of the pixel electrodes of the first type of pixel PX1 and the second type of pixel PX2 is not parallel to the row direction.

[0042] In the embodiments of this application, such as Figure 3 As shown, in the pixel PX of column j C[j], the distance between the pixel electrode of the first type pixel PX1 located in row i R[i] and the pixel electrode of the second type pixel PX2 located in row i+1 R[i+1] is the first distance G1. In the pixel PX of column j C[j], the distance between the pixel electrode of the second type pixel PX2 located in row i+1 R[i+1] and the pixel electrode of the second type pixel PX2 located in row i+2 R[i+2] is the second distance G2. In the pixel PX of column j C[j], the distance between the pixel electrode of the second type pixel PX2 located in row i+2 R[i+2] and the pixel electrode of the first type pixel PX1 located in row i+3 R[i+3] is the third distance G3. The third distance G3 is greater than the second distance G2, and the second distance G2 is greater than the first distance G1.

[0043] In the pixel PX of column j C[j], a 2i gate line SL[2i] and a 2i+1 gate line SL[2i+1] are provided between the pixel electrode of the first type pixel PX1 located in row i R[i] and the pixel electrode of the second type pixel PX2 located in row i+1 R[i+1]. No transistor is provided between the pixel electrode of the first type pixel PX1 located in row i R[i] and the pixel electrode of the second type pixel PX2 located in row i+1 R[i+1]. In the pixel PX of column j C[j], between the pixel electrode of the second type pixel PX2 located in row i+1 R[i+1] and the pixel electrode of the second type pixel PX2 located in row i+2 R[i+2], there are 2i+2 gate lines SL[2i+2], 2i+3 gate lines SL[2i+3] and a set of transistors. The set of transistors consists of at least three transistors of the second type pixel PX2 located in row i+1 R[i+1]. In the pixel PX of column j C[j], between the pixel electrode of the second type pixel PX2 located in row i+2 R[i+2] and the pixel electrode of the first type pixel PX1 located in row i+3 R[i+3], there are 2i+4 gate lines SL[2i+4], 2i+5 gate lines SL[2i+5] and two sets of transistors. The two sets of transistors are at least three transistors of the second type pixel PX2 located in row i+2 R[i+2] and at least three transistors of the first type pixel PX1 located in row i+3 R[i+3].

[0044] In the embodiments of this application, such as Figure 3 As shown, in the (j+1)th column C[j+1] of pixel PX, the distance between the pixel electrode of the second type pixel PX2 located in the i-th row R[i] and the pixel electrode of the first type pixel PX1 located in the (i+1)th row R[i+1] is the third distance G3. In the (j+1)th column C[j+1] of pixel PX, the distance between the pixel electrode of the first type pixel PX1 located in the (i+1)th row R[i+1] and the pixel electrode of the first type pixel PX1 located in the (i+2)th row R[i+2] is the second distance G2. In the (j+1)th column C[j+1] of pixel PX, the distance between the pixel electrode of the first type pixel PX1 located in the (i+2)th row R[i+2] and the pixel electrode of the second type pixel PX2 located in the (i+3)th row R[i+3] is the first distance G1.

[0045] In the pixel PX in column j+1 C[j+1], a second-type pixel PX2 located in row i R[i] and a first-type pixel PX1 located in row i+1 R[i+1] are provided with a 2i gate line SL[2i], a 2i+1 gate line SL[2i+1] and two sets of transistors. The two sets of transistors are at least three transistors of the second-type pixel PX2 located in row i R[i] and at least three transistors of the first-type pixel PX1 located in row i+1 R[i+1]. In the pixel PX in column j+1 C[j+1], a 2i+2 gate line SL[2i+2], a 2i+3 gate line SL[2i+3], and a set of transistors are disposed between the pixel electrode of the first type pixel PX1 located in row i+1 R[i+1] and the pixel electrode of the first type pixel PX1 located in row i+2 R[i+2]. The set of transistors consists of at least three transistors of the first type pixel PX1 located in row i+2 R[i+2]. In the pixel PX in column j+1 C[j+1], the pixel electrode of the first type pixel PX1 located in row i+2 R[i+2] and the pixel electrode of the second type pixel PX2 located in row i+3 R[i+3] are provided with gate line 2i+4 SL[2i+4] and gate line 2i+5 SL[2i+5]. No transistor is provided between the pixel electrode of the first type pixel PX1 located in row i+2 R[i+2] and the pixel electrode of the second type pixel PX2 located in row i+3 R[i+3].

[0046] In embodiments of this application, the liquid crystal display panel further includes a source driver chip. The source driver chip is electrically connected to multiple data lines DL, and provides data signals to the multiple data lines DL. The j-th data line DL[j] and the (j+6)-th data line DL[j+6] are electrically connected in the peripheral area and then electrically connected to one output terminal of the source driver chip. The (j+1)-th data line DL[j+1] and the (j+7)-th data line DL[j+7] are electrically connected in the peripheral area and then electrically connected to another output terminal of the source driver chip. The (j+2)-th data line DL[j+2] and the (j+8)-th data line DL[j+8] are electrically connected in the peripheral area and then electrically connected to yet another output terminal of the source driver chip. The (j+3)-th data line DL[j+2] and the (j+8)-th data line DL[j+8] are electrically connected in the peripheral area and then electrically connected to yet another output terminal of the source driver chip. Data line DL[j+3] and data line DL[j+9] are electrically connected in the peripheral area and then electrically connected to another output terminal of the source driver chip. Data line DL[j+4] and data line DL[j+10] are electrically connected in the peripheral area and then electrically connected to another output terminal of the source driver chip. Data line DL[j+5] and data line DL[j+11] are electrically connected in the peripheral area and then electrically connected to another output terminal of the source driver chip.

[0047] In embodiments of this application, the liquid crystal display panel further includes a gate driving circuit. The gate driving circuit is electrically connected to a plurality of gate lines SL, and provides scan signals to the plurality of gate lines SL. The gate driving circuit sequentially provides scan signals to the 2i-1th gate line SL[2i-1], the 2ith gate line SL[2i], the 2i+1th gate line SL[2i+1], the 2i+2th gate line SL[2i+2], the 2i+3rd gate line SL[2i+3], the 2i+4th gate line SL[2i+4], the 2i+5th gate line SL[2i+5], and the 2i+6th gate line SL[2i+6].

[0048] In embodiments of this application, the color of pixel PX includes one of red, green, and blue. The pixel PX in column j[j] is red, the pixel PX in column j+1[j+1] is green, the pixel PX in column j+2[j+2] is blue, the pixel PX in column j+3[j+3] is red, the pixel PX in column j+4[j+4] is green, the pixel PX in column j+5[j+5] is blue, the pixel PX in column j+6[j+6] is red, the pixel PX in column j+7[j+7] is green, the pixel PX in column j+8[j+8] is blue, the pixel PX in column j+9[j+9] is red, the pixel PX in column j+10[j+10] is green, and the pixel PX in column j+11[j+11] is blue.

[0049] In embodiments of this application, the liquid crystal display panel includes an opposing substrate and an array substrate. The opposing substrate and the array substrate are disposed opposite to each other, and a liquid crystal layer is filled between the opposing substrate and the array substrate. Multiple data lines DL, multiple gate lines SL, pixel electrodes of multiple pixels PX, and transistors are disposed on the array substrate, and a common electrode is disposed on the opposing substrate.

[0050] In embodiments of this application, the liquid crystal display panel further includes a timing controller. The timing controller is electrically connected to the source driver chip and to the gate driver circuit. The timing controller provides image data and control signals to the source driver chip, and provides control signals to the gate driver circuit. The source driver chip provides data signals to multiple data lines DL according to the image data and control signals provided by the timing controller, and the gate driver circuit provides scan signals to multiple gate lines SL according to the control signals provided by the timing controller.

[0051] Embodiments of this application also provide a liquid crystal display device, which includes a source driver chip and the liquid crystal display panel described above.

[0052] An embodiment of this application also provides a driving method for a liquid crystal display panel, applied to the aforementioned liquid crystal display panel. The driving method includes the following steps: transmitting data signals to a column of pixels electrically connected to the j-th data line DL[j] and a column of pixels electrically connected to the j+6 data line DL[j+6] via the j-th data line DL[j] and the j+6 data line DL[j+6]; transmitting data signals to a column of pixels electrically connected to the j+1 data line DL[j+1] and a column of pixels electrically connected to the j+7 data line DL[j+7] via the j+2 data line DL[j+2] and the j+8 data line DL[j+8]; and transmitting data signals to a column of pixels electrically connected to the j+2 data line DL[j+2] and a column of pixels electrically connected to the j+8 data line DL[j+8] via the j+2 data line DL[j+2] and the j+8 data line DL[j+8]... 8] Data signals are transmitted to a column of pixels electrically connected to each other via the (j+3)th data line DL[j+3] and the (j+9)th data line DL[j+9]. Data signals are also transmitted via the (j+4)th data line DL[j+4] and the (j+10)th data line DL[j+10]. Finally, data signals are transmitted via the (j+5)th data line DL[j+5] and the (j+11)th data line DL[j+11].

[0053] The driving method further includes: transmitting scan signals to the pixels PX located in the j-th column C[j], j+2-th column C[j+2], j+4-th column C[j+4], j+7-th column C[j+7], j+9-th column C[j+9], and j+11-th column C[j+11] of the pixel PX in the i-th row R[i] via the 2i-th gate line SL[2i], and transmitting scan signals to the pixels PX located in the j+1-th column C[j+1], j+3-th column C[j+3], j+5-th column C[j+5], j+6-th column C[j+6], j+8-th column C[j+8], and j+10-th column C[j+10] of the pixel PX in the i-th row R[i] via the 2i-th gate line SL[2i].

[0054] The driving method further includes: transmitting scan signals through the 2i+1 gate line SL[2i+1] to the pixels PX located in the j+1 column C[j+1], j+3 column C[j+3], j+5 column C[j+5], j+6 column C[j+6], j+8 column C[j+8], and j+10 column C[j+10] of the pixel PX in the i+1 row R[i+1], and transmitting scan signals through the 2i+2 gate line SL[2i+2] to the pixels PX located in the j column C[j], j+2 column C[j+2], j+4 column C[j+4], j+7 column C[j+7], j+9 column C[j+9], and j+11 column C[j+11] of the pixel PX in the i+1 row R[i+1].

[0055] The data signals transmitted by two adjacent data lines have opposite polarities.

[0056] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A liquid crystal display panel, characterized in that, The liquid crystal display panel includes a display area and a peripheral area, and the liquid crystal display panel includes: Multiple data cables; Multiple gate lines; and Multiple pixels, the multiple pixels are arranged into a pixel array, the pixel array includes multiple rows of pixels and multiple columns of pixels, the pixels in the same column have the same color, the pixels in adjacent columns have different colors, and the pixels in the same row have different colors. In this configuration, a column of pixels is electrically connected to one data line, and a row of pixels is electrically connected to two gate lines. The two gate lines are located on opposite sides of the row of pixels in the column direction. The data signals transmitted by adjacent data lines have opposite polarities. The j-th data line is electrically connected to the (j+6)-th data line in the peripheral area, the (j+1)-th data line is electrically connected to the (j+7)-th data line in the peripheral area, the (j+2)-th data line is electrically connected to the (j+8)-th data line in the peripheral area, the (j+3)-th data line is electrically connected to the (j+9)-th data line in the peripheral area, the (j+4)-th data line is electrically connected to the (j+10)-th data line in the peripheral area, and the (j+5)-th data line is electrically connected to the (j+11)-th data line in the peripheral area, where j is a positive integer.

2. The liquid crystal display panel according to claim 1, characterized in that, The 2i-1 gate line is electrically connected to the pixels in the i-th row located in the j-th, j+2-th, and j+4-th columns. The 2i gate line is electrically connected to the pixels in the i-th row located in the j+1-th, j+3-th, and j+5-th columns. The 2i-1 gate line is also electrically connected to the pixels in the i-th row located in the j+7-th, j+9-th, and j+11-th columns. The 2i gate line is also electrically connected to the pixels in the i-th row located in the j+6-th, j+8-th, and j+10-th columns. Here, i is a positive integer.

3. The liquid crystal display panel according to claim 2, characterized in that, The 2i+1 gate line is electrically connected to the pixels in the (i+1)th row located in the (j+1), (j+3), and (j+5)th columns of the pixel row. The 2i+2 gate line is electrically connected to the pixels in the (i+1)th row located in the (j), (j+2), and (j+4)th columns of the pixel row. The 2i+1 gate line is also electrically connected to the pixels in the (j+6), (j+8), and (j+10)th columns of the pixel row. The 2i+2 gate line is also electrically connected to the pixels in the (j+7), (j+9), and (j+11)th columns of the pixel row.

4. The liquid crystal display panel according to claim 3, characterized in that, The 2i+3 gate line is electrically connected to the pixels located in the (j+1), (j+3), and (j+5) columns of the (i+2)th row. The 2i+4 gate line is electrically connected to the pixels located in the (j), (j+2), and (j+4) columns of the (i+2)th row. The 2i+3 gate line is also electrically connected to the pixels located in the (j+6), (j+8), and (j+10) columns of the (i+2)th row. The 2i+4 gate line is also electrically connected to the pixels located in the (j+7), (j+9), and (j+11) columns of the (i+2)th row.

5. The liquid crystal display panel according to claim 4, characterized in that, Gate line 2i+5 is electrically connected to the pixels in the (i+3)th row located in the j-th, j+2-th, and j+4-th columns. Gate line 2i+6 is electrically connected to the pixels in the (i+3)th row located in the j+1-th, j+3-th, and j+5-th columns. Gate line 2i+5 is also electrically connected to the pixels in the (i+3)th row located in the j+7-th, j+9-th, and j+11-th columns. Gate line 2i+6 is also electrically connected to the pixels in the (i+3)th row located in the j+6-th, j+8-th, and j+10-th columns.

6. The liquid crystal display panel according to claim 1, characterized in that, A pixel electrically connected to the (2i-1)th gate line in the i-th row is a first type of pixel, and a pixel electrically connected to the 2ith gate line in the i-th row is a second type of pixel. Each pixel includes a first end and a second end, which are opposite ends of the pixel in the column direction. At least three transistors of the first type of pixel are located at the first end of the first type of pixel, and at least three transistors of the second type of pixel are located at the second end of the second type of pixel. i is a positive integer. The 2i-1 gate line is electrically connected to at least one transistor of the first type of pixel at the first end, and the 2i gate line is electrically connected to at least one transistor of the second type of pixel at the second end.

7. The liquid crystal display panel according to claim 6, characterized in that, The pixel electrodes of the first type of pixel and the pixel electrodes of the second type of pixel in a row are staggered in the column direction.

8. The liquid crystal display panel according to claim 7, characterized in that, In the j-th column of pixels, the distance between the pixel electrode of the first type of pixel located in the i-th row and the pixel electrode of the second type of pixel located in the (i+1)-th row is the first distance; In the j-th column of pixels, the distance between the pixel electrode of the second type of pixel located in the (i+1)-th row and the pixel electrode of the second type of pixel located in the (i+2)-th row is the second distance; In the j-th column of pixels, the distance between the pixel electrode of the second type of pixel located in the (i+2)-th row and the pixel electrode of the first type of pixel located in the (i+3)-th row is the third distance; The third spacing is greater than the second spacing, and the second spacing is greater than the first spacing.

9. The liquid crystal display panel according to claim 7, characterized in that, In the (j+1)th column of pixels, the distance between the pixel electrode of the second type of pixel in the i-th row and the pixel electrode of the first type of pixel in the (i+1)-th row is the third distance; In the (j+1)th column of pixels, the distance between the pixel electrode of the first type of pixel located in the (i+1)th row and the pixel electrode of the first type of pixel located in the (i+2)th row is the second distance; In the (j+1)th column of pixels, the distance between the pixel electrode of the first type of pixel located in the (i+2)th row and the pixel electrode of the second type of pixel located in the (i+3)th row is the first distance.

10. A liquid crystal display device, characterized in that, It includes a source driver chip and a liquid crystal display panel as described in any one of claims 1 to 9.

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