Wafer stage and etching equipment

Abstract

The invention provides a wafer carrying table and etching equipment. The wafer carrying table comprises an electric control electrode array material disc which sequentially comprises a first ceramic layer, an array electrode material layer and a second ceramic layer from top to bottom. Wherein the array electrode material layer comprises a metal thin plate, and a plurality of electric control electrode array units are distributed on the metal thin plate; the resonant frequency and impedance of each electric control electrode array unit are independently adjusted in response to a control voltage, and then the ion energy at the position where the electric control electrode array unit is located is adjusted.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing equipment technology, and more particularly to etching equipment. Background Technology

[0002] In semiconductor manufacturing, plasma etching is one of the key technologies for achieving micron and nanometer-level feature sizes. As device integration increases, the requirements for the uniformity and precision of the etching process become increasingly stringent. Especially in etching large wafers, such as 12-inch wafers or even larger, achieving highly consistent uniformity becomes exceptionally difficult, directly limiting process progress and product quality improvement.

[0003] Traditional solutions include adjusting the power of the inner and outer coils of the ICP etching apparatus to optimize plasma uniformity, or using a multi-temperature zone electrostatic chuck to control the etching rate and adjust the etching uniformity in different areas. However, these methods have limitations in terms of adjustment range and effectiveness in practical applications, especially in applications that rely on ion energy etching and are not sensitive to the temperature of the chemical reaction, where the adjustment effect is even more limited. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention provides a wafer stage for ICP (Inductively Coupled Plasma) etching equipment, which is particularly suitable for applications that rely on ion energy etching and are not sensitive to the temperature of chemical reactions.

[0005] The wafer stage for ICP etching equipment of the present invention includes an electrically controlled electrode array material disk, which includes, from top to bottom, a first ceramic layer, an array electrode material layer, and a second ceramic layer.

[0006] The array electrode material layer includes a thin metal plate on which multiple electrically controlled electrode array units are distributed. The resonant frequency and impedance of each electrically controlled electrode array unit are independently adjusted in response to a control voltage, thereby adjusting the ion energy at the location of the electrically controlled electrode array unit.

[0007] In one embodiment, the wafer stage of the present invention further includes: The lower metal disk is located below the second ceramic layer. Water channels are integrated within the lower metal disk, and the surface temperature of the wafer is controlled by controlling the water temperature in the water channels.

[0008] In one embodiment, each of the electronically controlled electrode array units consists of a hollowed-out pattern and a planarized varactor diode, forming an equivalent resonant circuit.

[0009] In one embodiment, the perforated pattern is I-shaped.

[0010] In one embodiment, the varactor diode is coupled to the center of the hollow pattern, and the control voltage is applied to both ends of the varactor diode. When the control voltage is adjusted, the resonant frequency and impedance of the equivalent resonant circuit are adjusted.

[0011] In one embodiment, the first ceramic layer is used to support the wafer and prevent corrosion from etching gases.

[0012] In one embodiment, the second ceramic layer serves to conduct heat, bear load, and provide insulation.

[0013] In one embodiment, the distribution of the plurality of electrically controlled electrode array units on the metal sheet is designed according to the geometry of the wafer stage and the uniformity requirements of ion energy distribution during the etching process.

[0014] In one embodiment, the wafer stage has an electrostatic chuck, and the electrically controlled electrode array material disk is embedded in the surface of the electrostatic chuck.

[0015] The present invention also provides an ICP etching apparatus, comprising at least: The reaction chamber has coils wound around its side walls; An RF power supply is connected to the coil via an RF matching unit; The wafer stage, as described above, is located below the reaction chamber; An impedance controller generates the control voltage and is coupled to the wafer stage; The impedance controller is configured to dynamically adjust the ion energy at each point on the wafer stage to improve etching uniformity.

[0016] The wafer stage for ICP etching equipment and the ICP etching equipment of the present invention have the following beneficial technical effects: First, it improves etching uniformity: By precisely controlling the material disk of the electrically controlled electrode array, a high degree of uniformity of ion energy distribution on large-size wafers is achieved, thereby significantly improving etching uniformity.

[0017] Second, it has a fast response speed: by utilizing the fast response characteristics of varactor diodes, the ion energy distribution can be adjusted in a very short time to meet the needs of rapid changes in etching rate during the production process.

[0018] Third, it is easy to operate: the ion energy is adjusted by voltage regulation, which is simple to operate and easy to automate.

[0019] Fourth, strong adaptability: This invention has good adaptability and can be compatible with a variety of materials and process conditions, thus improving the scope of application of the equipment.

[0020] Fifth, high cost-effectiveness: Compared with traditional etching uniformity adjustment schemes, the present invention achieves high-precision etching while reducing costs and complexity, thus exhibiting good economic efficiency. Attached Figure Description

[0021] The above-described invention and the following detailed description will be better understood when read in conjunction with the accompanying drawings. It should be noted that the drawings are merely examples of the claimed invention. In the drawings, the same reference numerals represent the same or similar elements.

[0022] Figure 1 An etching apparatus according to an embodiment of the present invention is shown; Figure 2 A schematic diagram of a wafer stage structure according to an embodiment of the present invention is shown; Figure 3 A schematic diagram of the structure of an array electrode material layer according to an embodiment of the present invention is shown; Figure 4 A schematic diagram of an electrically controlled electrode array unit according to an embodiment of the present invention is shown. Detailed Implementation

[0023] The following detailed description of the features and advantages of the present invention provides sufficient information for any person skilled in the art to understand and implement the invention. Furthermore, based on the specification, claims, and drawings disclosed herein, those skilled in the art can easily understand the related objectives and advantages of the invention. Although the description of the invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may arise based on the claims of the invention. To provide a thorough understanding of the invention, numerous specific details will be included in the following description. The invention may also be implemented without using these details. Moreover, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0025] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0026] It is understood that while terms such as "first," "second," and "third" may be used herein to describe various components, channels, assemblies, regions, layers, and / or parts, these components, channels, assemblies, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, channels, assemblies, regions, layers, and / or parts. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0028] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0029] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0030] This invention proposes a scheme for adjusting the uniformity of the wafer stage in an ICP etching apparatus based on an electrically controlled electrode array material. Specifically, this scheme embeds an electrically controlled electrode array material disk containing multiple electrically controlled electrode array units within the surface of the electrostatic chuck of the wafer stage. The disk consists of a ceramic layer on the upper surface, an inner thin metal array electrode material layer, and a lower ceramic layer. Each electrically controlled electrode array unit comprises an etched metal pattern and a planarized varactor diode; the metal pattern is in the form of a hollowed-out I-shape. By changing the control voltage, the resonant characteristics of the unit can be adjusted, thereby changing the impedance at that unit and influencing and controlling the ion energy at that location.

[0031] The purpose of this invention is as follows: 1. A method is provided that can precisely control the ion energy in different regions to achieve high-precision etching uniformity.

[0032] 2. Achieve high-sensitivity, high-response-speed etching rate adjustment to adapt to rapidly changing production environments.

[0033] 3. Provide a solution that can be integrated on a large scale to meet the needs of large-size wafers.

[0034] 4. Without relying on temperature adjustment, effective control of ion energy is achieved through electronic control. When the process is not sensitive to temperature but sensitive to ion energy, the etching rate of local areas is adjusted to overcome the size load effect during the etching process.

[0035] 5. Improve the adaptability and compatibility of wafer stage to meet the etching requirements of different materials and process conditions.

[0036] The working principle of this invention is based on the electronically controlled resonant characteristics of a varactor diode. By adjusting the voltage, the resonant frequency is changed, thereby affecting the impedance of the electronically controlled electrode array unit. This impedance change can directly affect the distribution of ion energy, thus achieving precise control of the etching rate. Due to the fast response speed of the varactor diode, real-time adjustment can be achieved, meeting the rapid response requirements for etching uniformity in the production process.

[0037] The wafer stage for ICP etching equipment of the present invention includes an electrically controlled electrode array material disk, which includes, from top to bottom, a first ceramic layer, an array electrode material layer, and a second ceramic layer.

[0038] The array electrode material layer includes a thin metal plate on which multiple electrically controlled electrode array units are distributed. The resonant frequency and impedance of each electrically controlled electrode array unit are independently adjusted in response to a control voltage, thereby adjusting the ion energy at the location of the electrically controlled electrode array unit.

[0039] In one embodiment, the wafer stage of the present invention further includes: The lower metal disk is located below the second ceramic layer. Water channels are integrated within the lower metal disk, and the surface temperature of the wafer is controlled by controlling the water temperature in the water channels.

[0040] In one embodiment, each of the electronically controlled electrode array units consists of a hollowed-out pattern and a planarized varactor diode, forming an equivalent resonant circuit.

[0041] In one embodiment, the perforated pattern is I-shaped.

[0042] In one embodiment, the varactor diode is coupled to the center of the hollow pattern, and the control voltage is applied to both ends of the varactor diode. When the control voltage is adjusted, the resonant frequency and impedance of the equivalent resonant circuit are adjusted.

[0043] In one embodiment, the first ceramic layer is used to support the wafer and prevent corrosion from etching gases.

[0044] In one embodiment, the second ceramic layer serves to conduct heat, bear load, and provide insulation.

[0045] In one embodiment, the distribution of the plurality of electrically controlled electrode array units on the metal sheet is designed according to the geometry of the wafer stage and the uniformity requirements of ion energy distribution during the etching process.

[0046] In one embodiment, the wafer stage has an electrostatic chuck, and the electrically controlled electrode array material disk is embedded in the surface of the electrostatic chuck.

[0047] The present invention also provides an ICP etching apparatus, comprising at least: The reaction chamber has coils wound around its side walls; An RF power supply is connected to the coil via an RF matching unit; The wafer stage, as described above, is located below the reaction chamber; An impedance controller generates the control voltage and is coupled to the wafer stage; The impedance controller is configured to dynamically adjust the ion energy at each point on the wafer stage to improve etching uniformity.

[0048] Figure 1 An etching apparatus according to an embodiment of the present invention is shown. The etching apparatus may be an ICP etching apparatus. The etching apparatus includes, but is not limited to, a reaction chamber 101, a wafer stage 102, an RF power supply 103, an RF matching unit 104, a coil 105, an impedance controller 106, a bias RF power supply 107, an air inlet 108, and a cooling water inlet 109.

[0049] The RF power supply 103 is connected to the coil 105 via the RF matching unit 104.

[0050] In one embodiment, the RF power supply 103 is specified to have a frequency of 13.56 MHz and a power of 2000 W.

[0051] Coil 105 is wound around the side wall of reaction chamber 101. A grounded capacitor is coupled to the end of coil 105.

[0052] The reaction chamber 101 is used for processing, such as etching.

[0053] In one embodiment, the reaction chamber 101 is a quartz barrel.

[0054] The wafer stage 102 is located below the reaction chamber 101 and is used to support the wafer. The wafer stage 102 can dynamically and rapidly adjust the ion energy at each point on the wafer stage, thereby achieving ultra-uniform etching.

[0055] The bottom of the wafer stage 102 is provided with a cooling water inlet 109, through which cooling water or coolant enters the wafer stage 102. The bottom of the wafer stage 102 is also connected to a bias RF power supply 107 and an impedance controller 106.

[0056] In one embodiment, the bias RF power supply 107 is specified to have a frequency of 400K and a power of 1000W.

[0057] Impedance controller 106 is used to control the varactor diode capacitance of each unit in the electrically controlled electrode array material within the wafer stage. This method allows for dynamic and rapid adjustment of the ion energy at each point on the wafer stage, thereby achieving ultra-uniform etching.

[0058] Figure 2 A schematic diagram of a wafer stage structure according to an embodiment of the present invention is shown. Figure 2 As shown, the wafer stage 102 integrates an electronically controlled electrode array material disk and a lower metal disk 204.

[0059] The material disk of the electrically controlled electrode array is located above the lower metal disk 204.

[0060] The electronically controlled electrode array material disk comprises, from top to bottom, a first ceramic layer 201, an array electrode material layer 202, and a second ceramic layer 203. This three-layer structure design provides both good mechanical strength and efficient transmission of electrical signals.

[0061] The first ceramic layer 201 mainly serves as a wafer support and a protection against etching gases.

[0062] In one embodiment, the ceramic thickness of the first ceramic layer 201 is approximately 0.2-5 mm.

[0063] In one embodiment, the material of the first ceramic layer 201 includes ceramic materials such as aluminum nitride, silicon carbide, alumina, and silicon dioxide.

[0064] The second ceramic layer 203 mainly serves to conduct heat, bear load, and provide insulation.

[0065] In one embodiment, the ceramic thickness of the second ceramic layer 203 is approximately 1-20 mm.

[0066] In one embodiment, the material of the second ceramic layer 203 includes ceramic materials such as aluminum nitride, aluminum oxide, and silicon dioxide.

[0067] The lower metal disk 204 is located below the second ceramic layer 203. The lower metal disk 204 integrates distributed water channels 205, which control the surface temperature of the wafer through water temperature control. These water channels can be directly or indirectly connected to cooling water inlets.

[0068] Figure 3 A schematic diagram of the structure of an array electrode material layer according to an embodiment of the present invention is shown.

[0069] The array electrode material layer includes a thin metal plate 301. Multiple electrically controlled electrode array units 302 are distributed on the thin metal plate 301. The number of electrically controlled electrode array units 302 can be determined according to actual needs. These multiple electrically controlled electrode array units 302 are distributed on the thin metal plate 301 in a regular pattern.

[0070] In one embodiment, the distribution design of the electrically controlled electrode array unit 302 takes into account the geometry of the wafer stage and the uniformity requirement of ion energy distribution during the etching process in order to achieve the best etching effect.

[0071] The impedance of each electrically controlled electrode array unit 302 can be independently controlled by an impedance controller 106. Specifically, the impedance controller 106 generates a control voltage that acts on each electrically controlled electrode array unit. By changing the control voltage, the impedance of the electrically controlled electrode array unit can be adjusted, thereby precisely influencing and regulating the ion energy at the location of that electrically controlled electrode array unit. This adjustment mechanism allows the wafer stage of the present invention to precisely control the impedance at each electrically controlled electrode array unit, thereby finely regulating the ion energy.

[0072] In one embodiment, the metal sheet 301 may be made of conductive metals such as gold, silver, copper, and aluminum, or their alloys, or conductive dielectric materials such as SiC and TiN.

[0073] Figure 4 A schematic diagram of an electrically controlled electrode array unit according to an embodiment of the present invention is shown.

[0074] like Figure 4As shown, each electronically controlled electrode array unit consists of a hollow pattern 401 and a planarized varactor diode 402, forming an equivalent tunable LC resonant circuit.

[0075] When the control voltage across the varactor diode is changed, its junction capacitance changes with the voltage, thereby adjusting the resonant frequency of the equivalent LC resonant circuit and thus altering the impedance of the electronically controlled electrode array unit. This impedance change affects the ion energy at the location of the unit, thereby achieving high-precision etching uniformity.

[0076] In one embodiment, the cutout pattern 401 is I-shaped.

[0077] In one embodiment, a varactor diode 402 is coupled to the center of the cutout pattern 401.

[0078] In one embodiment, the parameter dimension 403 of the I-shaped structure is approximately 0.5-10 mm; the dimension 404 is approximately 0.5-10 mm; and the parameter dimension 405 is approximately 0.5-50 mm.

[0079] In one embodiment, the diameter of the electrically controlled electrode array unit is approximately 1-100 mm.

[0080] The technical effects of this invention are significant, mainly reflected in the following aspects: 1. Improved etching uniformity: By precisely controlling the material disk of the electrically controlled electrode array, a high degree of uniformity of ion energy distribution on large-size wafers is achieved, thereby significantly improving etching uniformity.

[0081] 2. Fast response speed: Utilizing the fast response characteristics of varactor diodes, the ion energy distribution can be adjusted in a very short time to meet the needs of rapid changes in etching rate during the production process.

[0082] 3. Easy to operate: Ion energy is adjusted by voltage regulation, which is simple to operate and easy to automate.

[0083] 4. High adaptability: The solution has good adaptability and can be compatible with various materials and process conditions, which improves the scope of application of the equipment.

[0084] 5. High cost-effectiveness: Compared with traditional etching uniformity adjustment schemes, the present invention achieves high-precision etching while reducing costs and complexity, thus exhibiting good economic efficiency.

[0085] Those skilled in the art will understand that the various illustrative components, modules, blocks, units, circuits, systems, and steps described in conjunction with the embodiments disclosed herein can be implemented in hardware, software (including firmware, resident software, microcode, etc.), or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, modules, blocks, units, circuits, systems, and steps described above are generalized in their functional form. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0086] The terminology and expressions used above are for descriptive purposes only, and the invention should not be limited to these terms and expressions. The use of these terms and expressions does not mean excluding any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

[0087] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims.

[0088] Similarly, it should be noted that although the present invention has been described with reference to the specific embodiments described above, those skilled in the art should recognize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions can be made without departing from the spirit of the present invention. Therefore, any changes or modifications to the above embodiments within the scope of the essential spirit of the present invention will fall within the scope of the claims of this application.

Claims

1. A wafer carrier, characterized in that, include: The electrically controlled electrode array material disk, from top to bottom, includes: First ceramic layer; Array electrode material layer; Second ceramic layer; The array electrode material layer includes a thin metal plate on which multiple electrically controlled electrode array units are distributed. The resonant frequency and impedance of each electrically controlled electrode array unit are independently adjusted in response to a control voltage, thereby adjusting the ion energy at the location of the electrically controlled electrode array unit.

2. The wafer stage as described in claim 1, characterized in that, Also includes: The lower metal disk is located below the second ceramic layer. Water channels are integrated within the lower metal disk, and the surface temperature of the wafer is controlled by controlling the water temperature in the water channels.

3. The wafer stage as described in claim 1, characterized in that, Each of the electronically controlled electrode array units consists of a hollowed-out pattern and a planarized varactor diode, forming an equivalent resonant circuit.

4. The wafer stage as described in claim 3, characterized in that, The hollowed-out pattern is I-shaped.

5. The wafer stage as described in claim 3, characterized in that, The varactor diode is coupled to the center of the hollow pattern. The control voltage is applied to both ends of the varactor diode. When the control voltage is adjusted, the resonant frequency and impedance of the equivalent resonant circuit are adjusted.

6. The wafer stage as described in claim 1, characterized in that, The first ceramic layer is used to support the wafer and prevent corrosion from etching gases.

7. The wafer stage as described in claim 1, characterized in that, The second ceramic layer serves to conduct heat, bear load, and provide insulation.

8. The wafer stage as described in claim 1, characterized in that, The distribution of the multiple electrically controlled electrode array units on the metal sheet is designed according to the geometry of the wafer stage and the uniformity requirements of ion energy distribution during the etching process.

9. The wafer stage as described in claim 1, characterized in that, The wafer stage has an electrostatic chuck, and the electronically controlled electrode array material disk is embedded in the surface of the electrostatic chuck.

10. An etching apparatus, characterized in that, include: The reaction chamber has coils wound around its side walls; An RF power supply is connected to the coil via an RF matching unit; The wafer stage as described in any one of claims 1 to 9 is located below the reaction chamber; An impedance controller generates the control voltage and is coupled to the wafer stage; The impedance controller is configured to dynamically adjust the ion energy at each point on the wafer stage to improve etching uniformity.

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