Reducing crosstalk between signals

Abstract

The invention provides a method for reducing crosstalk between signals. Each signal trace is provided with an input end and an output end, and transmits a corresponding input signal received by the input end to the output end. Each transmitter is connected to a corresponding input end of a respective signal trace. Each receiver is connected to a corresponding output of a respective signal trace. Each receiver includes a self-biased inverter that is biased in a high gain region. And the direct current working point of each driver is equal to the direct current working point of the corresponding receiver.

Description

[0001] Priority Statement

[0002] This invention relates to and claims priority to the following Indian provisional patent application: Application No. 202541005303, filed January 22, 2025. This invention relates to and claims priority to the following U.S. patent applications: Application No. 19 / 361,037, filed October 17, 2025; and Application No. 19 / 361,039, filed October 17, 2025. The entire contents of these applications are incorporated herein by reference only, without prejudice to this specification. Technical Field

[0003] Embodiments of the present invention generally relate to signal transmission in wired media, and more specifically, to reducing crosstalk between such transmitted signals. Background Technology

[0004] There are often situations where multiple signals need to be transmitted through closely adjacent wires (signal traces). For example, in systems such as complex systems-on-a-chip (SoCs), network devices, and wired transceivers, multiple signals (with different frequencies at their respective input ports) need to be generated and / or transmitted on wires, where each signal may need to be provided to any one of multiple output ports (e.g., on a SOC package pin).

[0005] The signal traces between the transmitter and receiver are very close to each other, which can lead to sufficiently large crosstalk, causing signal degradation / damage, a well-known problem in the relevant technical field. Similar problems can also exist when multiple signals are tightly wired through point-to-point (non-switched) connections.

[0006] Various aspects of the present invention are designed to reduce crosstalk between such transmitted signals. Summary of the Invention

[0007] The present invention provides a circuit characterized in that it comprises: a plurality of signal traces, each signal trace having a corresponding input terminal and a corresponding output terminal, each signal trace being used to transmit the signal received at its corresponding input terminal to its corresponding output terminal; a plurality of transmitters, each transmitter having its output terminal coupled to the input terminal of its corresponding signal trace; and a plurality of receivers, each receiver having its input terminal coupled to the output terminal of its corresponding signal trace, wherein each receiver includes a self-biased inverter biased in a high-gain region, and wherein the DC operating point of each transmitter is equal to the DC operating point of its corresponding receiver.

[0008] In some embodiments, a plurality of signal generators, each signal generator being used to generate the corresponding input signal; and a signal distributor having a plurality of input ports and a plurality of output ports, each input port constituting the input terminal and each output port constituting the output terminal, wherein the signal distributor is operable to couple any one of the plurality of input ports to any one of the plurality of output ports.

[0009] In some embodiments, the self-biased inverter includes: an inverter having an input node and an output node; and a resistor coupled in parallel between the input node and the output node of the inverter.

[0010] In some embodiments, the corresponding signal is a differential signal, and the DC operating point is equal to the common-mode level of the differential signal.

[0011] In some embodiments, each of the plurality of transmitters includes a differential transmitter, each of the plurality of receivers includes a differential receiver, and each of the plurality of signal traces includes a differential trace.

[0012] In some embodiments, each transmitter includes a source-terminated series (SST) inverter.

[0013] In some embodiments, each transmitter includes multiple transmitter slices, each of which can be controllably coupled to the input of its corresponding signal trace.

[0014] In some embodiments, the differential load impedance presented by each of the plurality of receivers is greater than the characteristic impedance of its corresponding signal trace.

[0015] In some embodiments, the differential power supply impedance of each of the plurality of transmitters is less than the characteristic impedance of its corresponding signal trace.

[0016] In some embodiments, each receiver further includes a pair of cross-coupled inverters coupled between the respective output nodes of the corresponding self-biased inverters in the receiver.

[0017] In some embodiments, each receiver further includes a pair of inverter buffers, wherein a first inverter buffer in the pair is coupled to a first output node of each of the self-biased inverters, and a second inverter buffer is coupled to a second output node of each of the self-biased inverters.

[0018] In some embodiments, a pair of self-biased inverters of a first receiver among the plurality of receivers are powered by a first power supply; and a first pair of inverter buffers of the first receiver are powered by a second power supply.

[0019] In some embodiments, the signal distributor couples a first transmitter of the plurality of transmitters to the first receiver, and the first transmitter is also powered by the first power supply.

[0020] In some embodiments, the device further includes a plurality of differential drivers, each differential driver being coupled to the output of a pair of inverter buffers of a corresponding receiver, wherein a first differential driver is coupled to the output of the first pair of inverter buffers, and the first differential driver is powered by a third power supply.

[0021] This invention provides a system, characterized by comprising: multiple processors for executing instructions; multiple memory units for storing instructions and data; an interconnect structure for coupling the processors to the memory units; and a clock integration circuit for generating multiple clock signals, wherein each of the multiple clock signals is coupled to a clock input terminal of a corresponding processor among the multiple processors, the respective clock signal serving as a time reference to coordinate the operation of the corresponding processor, wherein the clock IC includes: multiple signal traces, each signal trace having a corresponding input terminal and a corresponding output terminal, each signal trace being used to transmit the received respective clock signal from the corresponding input terminal to the corresponding output terminal; multiple transmitters, the output of each transmitter being coupled to a corresponding input terminal of a corresponding signal trace; and multiple receivers, the input of each receiver being coupled to a corresponding output terminal of a corresponding signal trace, wherein each receiver includes a self-biased inverter biased in a high-gain region, wherein the DC operating point of each transmitter is the same as the DC operating point of its corresponding receiver.

[0022] In some embodiments, the clock IC further includes: a plurality of phase-locked loops (PLLs), each PLL being used to generate the respective clock signal; and a signal distributor having a plurality of input ports and a plurality of output ports, each input port constituting the input terminal and each output port constituting the output terminal, wherein the signal distributor is operable to couple any one of the plurality of input ports to any one of the plurality of output ports.

[0023] In some embodiments, the self-biased inverter includes: an inverter having an input node and an output node; and a resistor connected in parallel between the input node and the output node of the inverter.

[0024] In some embodiments, the respective clock signals are differential signals, and the DC operating point is equal to the common-mode potential of the differential signal.

[0025] In some embodiments, each receiver further includes: a pair of cross-coupled inverters coupled between respective output nodes of the self-biased inverters of the receiver; and a pair of inverter buffers, wherein a first inverter buffer of the pair is coupled to a first output node of the respective output nodes of the self-biased inverters, and a second inverting buffer is coupled to a second output node of the respective output nodes of the self-biased inverters.

[0026] In some embodiments, the system further includes a plurality of voltage regulators, wherein a pair of self-biased inverters of a first receiver of the plurality of receivers is powered by the first voltage regulator; wherein a first pair of inverter buffers of the first receiver is powered by a second power supply; wherein the signal distributor couples a first transmitter of the plurality of transmitters to the first receiver; wherein the first transmitter is also powered by the first voltage regulator. Attached Figure Description

[0027] Embodiments of the present invention will be described with reference to the accompanying drawings, which are briefly described below.

[0028] Figure 1 This is a block diagram illustrating an example device in which several aspects of the present invention can be implemented.

[0029] Figure 2 This is a schematic diagram illustrating an embodiment of the present invention showing multiple signal paths that are required to selectively connect multiple starting points to multiple ending points.

[0030] Figure 3 This is a schematic diagram illustrating a component in the path from the signal source to the signal endpoint in a device according to an embodiment of the present invention.

[0031] Figure 4A This is a schematic diagram illustrating the implementation details of a self-biased inverter according to an embodiment of the present invention.

[0032] Figure 4B This is a schematic diagram illustrating the output-input relationship of a self-biased inverter, representing an embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram illustrating impedance matching.

[0034] Figure 6A This diagram illustrates how to prevent or reduce phase noise in a clock signal by using a pair of inverters connected back-to-back, showing a waveform.

[0035] Figure 6B The diagram illustrates the waveforms used to prevent / minimize crosstalk in back-to-back connected inverters.

[0036] Figure 7This is a block diagram illustrating a transmitter with a drive intensity control method in one embodiment.

[0037] Figure 8 This is a block diagram illustrating system details of one embodiment of the present invention.

[0038] In the accompanying drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost digit of the corresponding reference numeral. Detailed Implementation

[0039] 1. Overview

[0040] According to one embodiment of the present invention, a circuit includes multiple signal traces having input and output terminals, each signal trace transmitting an input signal received at its corresponding input terminal to its corresponding output terminal. The circuit also includes multiple drivers, each driver coupled to the input terminal of its corresponding signal trace. Receivers are coupled to the corresponding output terminals of the signal traces. According to this embodiment, each receiver includes a self-biased inverter operating in a high-gain region, wherein the DC operating point of each driver is equal to the DC operating point of its corresponding receiver.

[0041] By ensuring a consistent DC operating point and using a self-biased inverter operating in the high-gain region, the use of intermediate components such as coupling capacitors can be avoided, resulting in several advantages. These advantages include: no lower limit on the (clock) signal frequency, reduced signal attenuation, and smaller implementation area.

[0042] In one embodiment, the signal traces are included in a signal distributor operable to connect any input port to any output port, wherein each signal trace constitutes one of the paths from an input port to its corresponding output port.

[0043] Several embodiments of this specification will be illustrated by the following examples. However, those skilled in the art will understand that the present invention can be implemented without certain specific details, or by other methods, elements, materials, etc. In other instances, known structures, materials, or operations have not been shown in detail to avoid obscuring the features disclosed herein. Furthermore, the described features / aspects can be implemented in various combinations, although only some combinations are described herein for the sake of brevity.

[0044] 2. Exemplary device

[0045] Figure 1 This is a block diagram of an exemplary device, illustrating how several aspects of the present invention are implemented. Figure 1The diagram shows relevant portions of an integrated circuit (IC) 100 (which may be a system-on-a-chip SOC), which includes signal generators 110A to 110N, a signal distributor 120, receivers (Rx) 125A to 125N, output drivers (DRV) 130A to 130N, and pins 140A to 140N. IC 100 can be considered a "clock IC".

[0046] According to the conventions used herein, signal generators 110A to 110N may be collectively referred to or individually as reference numeral 110, depending on the context. The same convention applies to other similar components. Other parts of IC 100, such as the power supply and oscillator, are not included in this description for the sake of clarity. Figure 1 This is displayed in the image. Furthermore, Figure 1 The specific blocks shown are merely examples. The various aspects disclosed herein can also be implemented in other devices and environments.

[0047] exist Figure 1 In the example, signal generators 110A through 110N are each a phase-locked loop (PLL) and generate a clock signal. The clock signal frequency described herein can range from a few hertz (Hz) to several gigahertz (GHz). The clock signal can be a square wave (or a general non-sinusoidal wave), a sine wave, etc., although the description herein assumes the use of a square wave.

[0048] While the following description pertains to clock signals, it is understood that the features of this invention are equally applicable to other types of signals, such as information-carrying (modulated) signals, like video signals, sinusoidal RF local oscillator signals for wireless devices, etc. Generally, the signal characteristics and transmission paths (signal lines and their layout / relative positions) from the signal generator to the receiver (or other termination point) can cause crosstalk problems. Furthermore, each path from the transmitter / driver of IC 100 to its pins described herein is described as a differential path transmitting differential signals. However, it will be apparent to those skilled in the art that these paths and signals can also be designed as single-ended signals, with corresponding modifications to the circuits and modules described herein.

[0049] Furthermore, the following description is provided in the context of a signal distributor that selectively forwards signals from any input to any output. It should be noted that when such flexible signal distribution is required, crosstalk issues may be more severe than a one-to-one fixed connection from the signal generator through the receiver to the output pin of IC 100, due to the large number of signal lines and connections (and the resulting wiring congestion), without the need for a signal distributor. However, it should be understood that various aspects of the invention also apply to this simpler one-to-one fixed connection, i.e., without a signal distributor.

[0050] As mentioned above, each of the signal generators 110A–110N is a PLL. Besides the PLL circuitry ( Figure 1 In addition to the components not shown but labeled "Core" in each signal generator 110, each signal generator 110 also includes a transmitter (or driver) numbered 115A to 115N (collectively referred to herein as driver 115). Each PLL 110A–110N core generates a clock signal synchronized with a corresponding reference clock (not shown). In one embodiment, the internal modules of each PLL (phase detector, low-pass filter, etc.) are single-ended circuits, and the generated clock signal is a single-ended signal. However, in another embodiment, IC 100 employs a fully differential PLL to generate a differential clock signal. When the PLL circuit generates a single-ended clock signal, a single-ended to differential converter is used to convert the single-ended clock signal into differential form. In the embodiments described herein, all transmitters, signal distributors 120, receivers, and drivers employ differential circuitry and operate on differential signals. However, in another embodiment, Figure 1 All components and modules are single-ended circuits.

[0051] Each transmitter (Tx) 115 of the signal generator receives a clock signal from the core of the corresponding signal generator 110 and transmits the clock signal to the corresponding input of the signal distributor 120 with the required drive strength. For example, Tx 115A receives a clock signal generated by the core (i.e., the PLL circuit) of PLL 110A and drives the clock signal to input I1 of the signal distributor 120. As known in the art, the required drive strength can be determined based on the path characteristics (impedance, etc.) from the transmitter to the terminal point (such as one of the corresponding receivers Rx 125A–Rx 125N).

[0052] Transmitter 115 is implemented such that its output impedance (source-end termination) is selected as a value relative to the path characteristic impedance from the transmitter to the corresponding receiver to minimize signal distortion and crosstalk, as will be further explained below. Each transmitter 115 can be controlled to drive a clock signal with an appropriate amplitude (signal swing) sufficient to be reliably received by the corresponding receiver while minimizing crosstalk between multiple clock signals. In one embodiment, the clock signal generated by signal generator 110 has a frequency range from 1 Hz to several GHz.

[0053] Signal distributor 120 has multiple input ports (IA to IN) and multiple output ports (OA to ON). Signal distributor 120 receives a corresponding clock signal as input at each input port. For example, in... Figure 1 In the diagram, signal distributor 120 is shown receiving clock signal 112A from Tx 115A at input port IA. Signal distributor 120 is designed to selectively connect any input port to any (single) output port. This selection can be achieved by generating a corresponding control signal, which... Figure 1 Not shown, but can be generated by external input to IC 100, by non-volatile memory cells storing configuration data within IC 100, or by other known techniques. Each input port can be connected to any output port.

[0054] Signal distributor 120 can achieve the connection between input and output ports using specific techniques designed to reduce wiring congestion between or within its internal connection paths / signal traces / transmission paths, thereby reducing crosstalk between clock signals. Some implementation examples of signal distributor 120 include cross-point switch matrices and analog multiplexers. The connection trace from transmitter 115 to receiver 125 via signal distributor 120 is implemented with a structure having controllable impedance. Such connection paths can be fabricated using known methods, such as striplines.

[0055] Each receiver (Rx) 125A-125N is connected to a corresponding output port of signal distributor 120. For example, Rx 125A is shown connected to output port O1. Receiver 125 receives the corresponding clock signal from the output port and amplifies the clock signal to the required level. For example, when the clock is a square wave signal with binary logic levels, receiver 125 can be designed to amplify the received clock signal to a rail-to-rail level. The received clock signal may have a low swing (low amplitude), which may be because the signal originally had a low swing, and / or is distorted due to noise and / or signal reflection (as will be further explained below). After internal buffering, receiver 125 forwards its amplified signal to one of the corresponding output drivers 130. For example, Rx 125A is connected to driver 130A as shown.

[0056] Output driver (DRV) 130 includes multiple drivers 130A–130N, each of which receives its corresponding amplified and buffered clock signal and outputs it to a corresponding output pin 140 of IC 100 with the required drive strength. In one embodiment, the number of signal generators 110 is equal to the number of output pins 140. However, in other alternative embodiments, the number of signal generators may be less than the number of output pins 140.

[0057] In one embodiment, the transmitter 115, signal distributor 120, receiver 125, and output driver 130 are all implemented as circuits capable of processing differential signals, and each of the output pins 140 is a pair of differential output pins. In another alternative embodiment, the transmitter 115, signal distributor 120, receiver 125, and output driver 130 are implemented as circuits capable of processing single-ended signals.

[0058] Figure 2This diagram illustrates a portion of the multiple signal line layout from transmitter Tx 115 through signal distributor 120 to receiver Rx 125 in an example. This portion shows the required signal lines between four signal generators 110A–110D (labeled A, B, C, and D in the diagram, respectively) and five receivers 125A–125E. The paths from the signal generators to the receivers can be controllably connected at corresponding intersection points (e.g., intersection points 210 and 220) by applying control signals to signal distributor 120. Because the clock for each signal generator (110) must be provided to any output pin 140 of IC 100, a large number of interconnect paths or signal lines may need to be configured. Due to chip space constraints, these paths / signal lines may need to be close to each other within IC 100 (e.g., inside signal distributor 120 and its preceding and following connections), making the clock signals on them more susceptible to crosstalk, especially as the number of signal generators and receivers increases. The following describes techniques for reducing crosstalk in such situations.

[0059] 3. Transmitter and Receiver

[0060] Figure 3 The circuitry and components shown in one embodiment of the present invention are from the source of the clock signal to the signal endpoint in IC 100 (in this example, the output pin of the IC). Figure 3 The signal path originates at the core (PLL circuit) output 304+ / 304- of clock generator 110A, passes through transmitter 115A, signal distributor 120, receiver 125A, and driver 130A in output driver (DRV) 130, finally reaching IC pin 140D+ / 140D-. For simplicity and ease of explanation, the example in the figure shows the output of transmitter 115A connected to receiver 125A via the corresponding path in signal distributor 120. However, generally, with proper control of signal distributor 120, the output clock signal of any transmitter 115 can be connected to any receiver 125.

[0061] More specifically, Figure 3This diagram illustrates the implementation of the clock transmitter (or driver) and clock receiver in IC 100. Transmitter 115A is connected to a pair of IC pins 140+ / 140- via receiver 125A and driver 130A in output driver 130. A single-ended to differential converter (not shown) in signal generator 110A converts the single-ended clock output of PLL 110A into differential form, which is then sent to paths 304+ and 304-. Buffers 305P and 305M buffer this differential clock signal before inputting it to corresponding nodes 309P and 309M of the differential transmitter 115A, respectively. The differential transmitter 115A is powered by supply voltage 361 (Vd). Terminal 399 represents ground. Figure 1 All other transmitters and receivers in the system have the same or similar implementation as transmitter 115A and receiver 125A, respectively.

[0062] The differential transmitter 115A, as shown in the figure, comprises a set of (symmetrical) circuit sections, each for receiving and transmitting one complementary signal from a pair of differential signals provided by the outputs of buffers 305P and 305M. The first section includes a P-channel metal-oxide-semiconductor field-effect transistor (PMOS) 310P, an N-channel metal-oxide-semiconductor field-effect transistor (NMOS) 310M, and resistors R1 (312P) and R2 (312M). The other section includes a PMOS 315P, an NMOS 315M, and resistors R3 (316P) and R4 (316M). The resistance values ​​of resistors R1, R2, R3, and R4 are all designed to be the same (R). The differential transmitter 115A is powered by a supply voltage Vd (361).

[0063] Transmitter 115A represents a source-series-terminated (SST) differential inverter. The differential output impedance of transmitter 115A is equal to 2R ohms. In one embodiment, the differential output impedance of transmitter 115A (2R, where R is approximately 100 ohms) (i.e., the source-series-terminated SST value) is designed to be less than the characteristic impedance Zo of the transmission path / channel from transmitter 115A to receiver 125A (and the corresponding path in signal distributor 120), and can be selected from several values ​​described below. In one embodiment, SST is set to Zo / 2. As is well known in the art, the characteristic impedance of a differential trace is the instantaneous impedance seen by the differential signal on the pair of traces, which is determined by the physical and electrical parameters of the trace itself and its surrounding environment. Generally, a smaller SST value (also referred to herein as source-series-terminated Zs) ensures shorter rise and fall times for the transmitted clock signal, making the clock signal more resistant to any noise injection.

[0064] In operation, when the voltages of nodes 309P and 309M correspond to logic high and logic low potentials, respectively, the voltages of nodes / paths 319P and 309M also correspond to logic high and logic low potentials, respectively. When the voltages of nodes 309P and 309M correspond to logic low and logic high potentials, respectively, the voltages of nodes / paths 319P and 309M also correspond to logic low and logic high potentials, respectively. The voltage swings on terminals 319P and 319M are adjustable, as described below. In one embodiment, to minimize crosstalk, the voltage swings on 319P / 319M are set very small (e.g., + / - 700 millivolts (mV)), in which case the supply voltage Vd (361) is set to 1.4V. The voltages at nodes 319P and 319M are determined by the receiver's feedback resistors (resistors 321P and 321M), the transmitter's series resistors (312P, 312M, 316P, and 316M), and the on-resistors of the corresponding NMOS / PMOS transistors.

[0065] When the logic level between nodes 319P and 319M is logic high (positive voltage between nodes 319P and 319M), the voltage between nodes 319P and 319M is represented by the following equation:

[0066] ,

[0067] ,

[0068] Where V319P is the voltage at node 319P, and V319M is the voltage at node 319M.

[0069] Rrx represents the resistance value of resistors 321P and 321M, while Rtx represents the resistance value of resistors 312P, 312M, 316P, and 316M.

[0070] Ron_rx_nmos is the on-resistor of the NMOS transistors in the 320pF and 320mF inverters.

[0071] Ron_rx_pmos is the on-resistor of the PMOS transistors in the 320P and 320M inverters.

[0072] Ron_tx_nmos is the on-resistor for the NMOS transistors 310M and 315M respectively, and

[0073] Ron_tx_pmos is the on-resistor for PMOS transistors 310P and 315P respectively.

[0074] Normally, the values ​​of Ron_rx_nmos and Ron_rx_pmos are equal, as are the values ​​of Ron_tx_nmos and Ron_tx_pmos. However, they can be implemented with different values ​​if needed.

[0075] When the logic level between 319P and 319M is logic low (negative voltage between nodes 319P and 319M), the situation is reversed for voltages V319P and V319M.

[0076] The differential output signals of transmitter (Tx) 115A on paths 319P and 319M pass through signal distributor 120 and are connected to receiver 125A as shown, wherein signal distributor 120 is controlled to connect input port IA to output port OA. Figure 1 For ease of description, Figure 3 The corresponding input and output ports of the signal distributor 120 connected by channels 319P / 319M are not shown. Figure 1 All other transmitters are implemented in a manner similar to that of transmitter 115A and are powered by the same supply voltage Vd, although each transmitter uses a separate power supply, such as a low dropout regulator (LDO).

[0077] The differential receiver 125A, as shown in the figure, includes a pair of self-biased inverters, a pair of back-to-back inverters (390P and 390M), a pair of inverters (330P and 330M), and a pair of inverting buffers (340P and 340M). Figure 1 The other receivers 125 are implemented similarly to receiver 125A. The combination of inverter 320P and resistor 321P represents one self-biased inverter of receiver 125A, while the combination of inverter 320M and resistor 321M represents another self-biased inverter. The inputs of these two self-biased inverters are connected to paths 319P and 319M, respectively. Each of inverters 320P, 320M, 390P, 390M, 330P, and 330M is powered by a supply voltage Vd (361). Inverting buffers 340P and 340M are each powered by a supply voltage 371.

[0078] Figure 1 All other receivers 125 are implemented similarly to receiver 125A. All circuitry in receiver 125 is powered by a supply voltage equal to Vd, which is generated by a separate power supply (e.g., another LDO); except for the pair of inverting buffers in the receiver, which, although also powered by a supply voltage equal to Vd, are generated by another separate power supply (e.g., yet another LDO).

[0079] Figure 4A It is a circuit diagram illustrating the implementation of the self-biased inverter in receiver 125. Figure 3 320P self-biased inverter in Figure 4A The display shows a PMOS 410, an NMOS 420, and a feedback resistor 321P. The PMOS 410 and NMOS 420 are matched transistors that together form an inverter. Resistor 321P is connected between the inverter's output 323P (Vo) and input 319P (Vin) and is implemented with a sufficiently large resistance value (e.g., 350 ohms). As is well known in the art, the feedback resistor (e.g., 321P) biases the self-biased inverter at a bias point (DC level) located in the high-gain region of the self-biased inverter's voltage output versus voltage input relationship, such as... Figure 4B As shown.

[0080] exist Figure 4B In the diagram, the magnitude of the input voltage Vin at node 319P is displayed on the X-axis, while the magnitude of the output voltage Vo at node 323P is displayed on the Y-axis. Since transistors 410 and 420 are matched, the feedback resistors make the bias point (labeled 450) approximately midway between Vd(361) and ground, i.e., Vd / 2. Figure 4A In the output-input relationship diagram, the voltage range of Vin and Vo is 0 to Vd volts.

[0081] Because the bias point is located in a region of very high gain (Vo / Vin), even a small change in Vin relative to the bias voltage will cause a large voltage swing in Vo. This can be observed... Figure 4B The conversion curves were verified. Therefore, the signal at node 319P can be a low-swing, i.e., a low-amplitude signal, but can still reliably induce a rail-to-rail (Vd to 0 volts, and vice versa) swing on the corresponding output signal 323P. Thus, a very small differential voltage swing (e.g., from +700 mV to -700 mV) can produce a large swing (from +Vd to -Vd) at the receiver output. This capability allows the transmitted signal (i.e., the signal on the differential node pair 319P / 319M) to be a non-square wave signal, yet still produce a large voltage swing (+ / -Vd) at the receiver output. This feature is particularly useful at higher frequencies, where square waves are distorted by attenuation from higher harmonics. Therefore, the signal transmitted across nodes 319P / 319M and through signal distributor 120 can be made very small, minimizing crosstalk while still reliably receiving the signal at the receiver.

[0082] The differential load impedance (Zl) presented by receiver 125A is greater than the characteristic impedance (Zo) of the transmission path between receiver (Rx) 125A and transmitter (Tx) 115A. As is well known in the art, differential impedance is the ratio (V / I) of voltage (V) to current (I) drawn under differential excitation. Zl is resistive, and its value is set by the resistance value of the feedback resistor of the self-biased inverter in receiver 125A. By implementing Zl as a large value (2Zo in one embodiment), the signal strength / amplitude of the clock signal driven by the transmitter (e.g., 115A) can be made sufficiently small, thereby reducing the likelihood and / or extent of crosstalk introduced by the clock signal in the transmission path (from the transmitter output to the corresponding receiver input, and through the signal distributor 120). Even if the clock signal experiences any additional amplitude attenuation in the transmission path due to the path impedance Zo, receiver 125A, due to the high gain provided by its self-biased inverter, ensures that the clock signal is reliably received and amplified without error.

[0083] Figure 5 This is a schematic diagram illustrating the source impedance, transmission path impedance, and load impedance in a single-ended circuit, used to clarify the terms source impedance, characteristic impedance, and load impedance. Component 510 represents a signal generator (and its associated transmitter) and corresponds to... Figure 1 Any of the signal generators (e.g., signal generator 110A). Resistor 520 represents the source impedance of signal generator 510 and corresponds to the differential source impedance (2R) of transmitter 115A. Zo represents the characteristic impedance of single-ended transmission path 530 and corresponds to the differential impedance (characteristic impedance) of the transmission path from a transmitter to a corresponding receiver in IC 100 (which also includes the corresponding differential path in signal distributor 120). Resistor 540 represents Figure 5 The impedance of the load, and corresponding to the differential input impedance presented by a receiver (e.g., receiver 125A) in IC 100.

[0084] It is important to note that because the differential output impedance of the differential transmitter in IC 100 (also referred to herein as the "source impedance Zs," which can be set to, for example, Zo / 2) and the load impedance of the differential receiver in IC 100 (for example, 2Zo in this embodiment) are not equal to the characteristic impedance Zo of the transmission channel, the clock signal transmitted from the transmitter to the receiver will exhibit ringing during signal level transitions due to reflections caused by impedance mismatch. While choosing a smaller Zs generally reduces crosstalk, it can also lead to ringing and poor signal integrity. The inventors have found that setting the value of Zl to 2Zo (twice that of Zo) is an optimal setting, which provides the benefit of reduced crosstalk without significantly increasing signal degradation. Furthermore, using a self-biased inverter in the receiver can convert the low-swing, potentially noisy clock signal at its input into a clean, rail-to-rail swing output clock signal.

[0085] The back-to-back inverters (cross-coupled inverters) 390P and 390M act as duty-cycle correctors for the differential clock signal. They align the positive and negative edges of the differential signal pair if they are not aligned (e.g., due to unequal lengths of the two traces). Furthermore, these cross-coupled inverters reduce or suppress common-mode noise that can be induced into the clock signal at the moment of clock switching (e.g., due to crosstalk from another clock signal). Both of these benefits are independent of process, voltage, and temperature (PVT) variations. Therefore, unwanted spurs or phase noise in the clock signal spectrum are either prevented or their amplitude is reduced.

[0086] Figure 6A This is a schematic diagram illustrating the duty cycle correction of a differential signal. Waveform 610 represents... Figure 3 The differential clock signal at the input of receiver 125A is shown. The positive and negative components of the differential signal 610 are labeled P and M, respectively. This clock signal switches states at time t61. However, because the two signal traces traversed by the clock signal are of unequal length, at... Figure 6AIn the clock signal, the P component switches at time t61, while the M component switches slightly later. This asynchronous state change manifests as phase noise in the clock signal spectrum, which is undesirable. The cross-coupled inverter aligns the level transitions of the positive and negative signals in the differential signal pair. When the P component at node 323P switches at time t61, inverter 390P forces the M component at node 323M to switch in the opposite direction, thus aligning the switching moment, as shown in the calibrated clock signal waveform 620. If the switching of the M component occurs earlier than that of the P component, inverter 390M will operate in a similar manner to align the switching moment.

[0087] Figure 6B This is a schematic diagram illustrating how a cross-coupled inverter reduces or eliminates the impact of crosstalk on the clock signal received by receiver 125A. As is well known in the art, crosstalk occurs due to electrical or magnetic coupling between a pair of signals. Crosstalk typically manifests as common-mode noise in differential signals, such as the clock signal described herein. Figure 6B In the waveform, waveform 650 represents the clock signal transmitted from transmitter 115A to receiver 125A. At time t65, the clock level switches, with both components switching simultaneously. Waveform 660 represents noise caused by crosstalk. This noise appears as zero, appearing only as a pulse at or near time t65. This pulse affects clock signal 650 in the form of common-mode noise, inducing equal voltages on both the positive and negative components of clock 650. This noise pulse accelerates the level change of the M component and delays the level change of the P component. The resulting clock waveform... Figure 6B The clock signal represented by 670 has asynchronous level variations in its P and M components at or near time t65. If left uncorrected, this will manifest as phase noise. This is similar to the aforementioned... Figure 6A In the manner described, the cross-coupled inverter operates to realign the switching moments of the two components, thereby eliminating the effects of crosstalk, as shown by the waveform of "corrected" or "realigned" clock 680, which is similar to the "original" clock 650.

[0088] Refer again Figure 3 Inverters 330P and 330M of receiver 125A are used to invert the logic levels of the clock signals on nodes 323P and 323M, respectively. Inverting buffers 340P and 340M receive their respective outputs from inverters 330P and 330M and forward the logic-inverted values ​​of their received signals to output driver 350 with enhanced drive strength. Output driver 350 provides further drive strength and forwards the buffered clock signals to output pins 140D- / 140D+.

[0089] Figure 1 The implementation methods of other transmitters and receivers in the same way as Figure 3 Similar to what is shown.

[0090] According to one aspect of this disclosure, the transmitter 115 and receiver 125 are designed and implemented in a way that eliminates the need for coupling capacitors between the transmitter-receiver pair, and also provides several benefits that will be described below.

[0091] 4. Same common-mode level

[0092] According to one aspect of this disclosure, transmitter 115 and receiver 125 are designed to have the same common-mode (voltage) level. As is well known in the art, the common-mode level (voltage) in a differential circuit or path refers to the DC voltage level shared by both halves of the differential circuit / path, each half being the portion that generates or contains one of the differential signal pairs in the circuit. The common-mode level is equal to half the sum of the voltages on the differential path (over all operating times).

[0093] It can be observed that Figure 3 The transmitter-receiver pair shown, namely Tx 115A and Rx 125A, is powered by the same supply voltage (Vd). First, the DC level, or bias point, of each self-biased inverter is approximately Vd / 2. Second, since the PMOS and NMOS transistors of Tx 115A are matched, and the resistance values ​​(R) of all resistors R1, R2, R3, and R4 are equal, the DC level of each half of the differential inverter / driver 115A is also Vd / 2. Therefore, the common-mode voltages of Tx 115A and Rx125A are equal.

[0094] Furthermore, all components of the Tx 115A and Rx 125A are manufactured using the same process on the same semiconductor die. Therefore, the transistors and resistors at both ends (transmitter and receiver) are matched, and their parameters remain essentially the same regardless of any variations in process, voltage, and temperature (PVT). Consequently, the common-mode levels of the transmitter and receiver will not (at least not substantially) differ with variations in PVT.

[0095] Because all transmitters and receivers have the same common-mode voltage level, a transmitter can be directly connected to a receiver (regardless of whether there is an intermediate signal distributor channel) without the need for AC coupling capacitors between them. Therefore, the diagram shows Tx 115A and Rx 125A connected (through signal distributor 120) without any coupling capacitors between them. If the common-mode voltages are different, then coupling capacitors are needed in the connection path between the transmitter and receiver to prevent the common-mode voltage of one from affecting the operation of the other, and / or to ensure that the receiver can reliably receive the transmitted differential signal.

[0096] Because the transmitter and receiver are directly connected without any coupling capacitors, there is no lower limit to the clock signal frequency. In one embodiment, the clock signal frequency range designed for the signal generator is 1Hz to 2GHz. The implementation area that would otherwise be reserved for coupling capacitors is also eliminated in IC100, thus incurring no loss in this regard.

[0097] Another advantage is that the clock signal does not suffer from amplitude attenuation. This attenuation occurs when the signal must pass through coupling capacitors, as the structure of coupling capacitors may include some series resistors. Furthermore, when implemented on-chip, capacitors may carry parasitic capacitance to ground, which further contributes to the amplitude loss of the clock signal. Moreover, the clock signal on the output pin will not exhibit transients (such as logic level spikes) immediately after power-on, whereas these transients would occur if coupling capacitors were used. These transients may appear for several clock cycles after power-on as the coupling capacitors charge to reach a steady-state average charge corresponding to the clock signal frequency.

[0098] when Figure 1 When the components and blocks are implemented as single-ended circuits and paths, the "DC level" (the voltage around which the signal change occurs) at the transmitter output and receiver input is equal (Vd / 2), so coupling capacitors are not required. The term "DC operating point" is used here to refer to the common-mode level of the differential circuit / path and the DC level of the single-ended circuit / path.

[0099] According to another aspect of this disclosure, the transmitter can be controlled to select one of a plurality of amplitudes to drive the clock signal, which will be described below.

[0100] 5. Controllable transmission amplitude

[0101] Figure 7 This is a schematic diagram illustrating a method for implementing the transmitter in one embodiment of this disclosure. The figure shows... Figure 1The transmitter 115A includes multiple instances (slices) of source-series terminated (SST) differential drivers, namely 710-1 to 710-N, wherein the desired number of slices can be operated to be connected in parallel with each other. In one embodiment, N equals 4, although N can also be greater than or less than 4.

[0102] Each SST driver (transmitter slice) is associated with Figure 3 The SST drives shown are similar to or the same as those shown in the diagram. Figure 3 Only one slice or instance of a driver is shown. Slice 710-1 is shown as... Figure 3 The SST driver 115A shown is identical, except for the addition of switches 750P and 750M. Each of the other slices 710-2, 710-3, etc., also has switches operable to connect or disconnect the slice's output from the common path 319P / 319M. Optionally, each slice's input may also have switches to connect or disconnect the slice from the output of clock generator 110A (through the outputs of buffers 305P and 305M).

[0103] Switches 760P and 760M belong to slice 710-2 and are also displayed. Figure 7 The switches for other slices are not shown. Switches 750P / 750M, 760P / 760M, and other slice switches (not shown) can be controlled to be closed or open in known ways, such as through user input, configuration from external devices, configuration memory on the chip, etc. The clock output from clock generator 110A is received differentially on paths 304+ / 304- and buffered by buffers 305P and 305M. The respective outputs of buffers 305P and 305M are connected to the corresponding input node of each SST driver slice. Figure 7 The connection to input nodes 309P and 309M of slice 710-1 is shown in the figure.

[0104] Depending on the required amplitude of the clock signal transmitted on output 319P / 319M, a corresponding number of slice switches are closed, connecting only the outputs of those slices to output path 319P / 319M. If a lower amplitude clock signal is desired to be driven on path 319P / 319M, fewer slices are used. For example, for the lowest amplitude, only one slice might be used. If a higher amplitude is required, as many slices as needed are used to drive the clock signal on path 319P / 319M. As the number of slices simultaneously driving output 319P / 319M increases, the effective source impedance decreases, and for the same load impedance provided by receiver 125A, the amplitude of the driven clock signal is correspondingly higher. As mentioned above, a lower amplitude can improve crosstalk performance by reducing electrical or magnetic coupling with other clock signal traces.

[0105] It is important to note that the SST driver described herein exhibits lower noise compared to other types of drivers, such as current-mode logic (CML) drivers with tail current sources. Furthermore, the degradation caused by flat-band noise (e.g., the portion offset from the carrier frequency by 10 MHz) in the driven clock signal spectrum is negligible with the SST driver. Moreover, the SST driver has smaller parasitic capacitance, thus enabling support for higher clock frequencies.

[0106] According to another aspect of this disclosure, different circuit sections in the clock signal path from the signal generator / transmitter to the IC 100 output pin employ independent power supplies, as described below.

[0107] 6. Supply Partitioning

[0108] Refer again Figure 3 The diagram shows that separate power supplies are used to power different parts of the signal path from transmitter 115A to output pins 140D+ / 140D-. Figure 3 The diagram shows three low-dropout regulators (LDOs) 360, 370, and 380, each receiving power from a power supply Vs (301, located external to IC 100) and generating stable supply voltages at outputs 361, 371, and 381, respectively. Supply voltage 361 (Vd) is used to power transmitter 115A (e.g., ...). Figure 7The transmitter-receiver-driver (shown as all or only the required number of slices) and receiver 125A are powered. Supply voltage 371 powers inverter buffers 340P and 340M. Supply voltage 381 powers output driver (DRV) 350, which further buffers the clock signal to output pins 140D+ / 140D-. Although not shown, another power supply powers the phase-locked loop (PLL) circuitry of clock generator 110A. Each other transmitter-receiver-driver group is also powered by a similar supply. Figure 3 As shown, it is powered by another set of three LDOs.

[0109] The outputs of the inverter buffers 340P / 340M and the output driver 350 are each connected to large capacitive loads, and their switching currents are greater than those of Tx 115A and / or Rx 125A. Tx 115A and Rx 125A, on the other hand, draw relatively small currents and have low noise. Therefore, supply voltages 371 and 381 may exhibit greater noise or ripple than supply voltage 361. Using separate power supplies for Tx 115A / Rx 125A, buffers 340P / 340M, and output driver 350 ensures that supply noise in LDO 370 and / or LDO 380 (e.g., noise caused by switching currents) does not couple into the electrical path from the clock generator to the corresponding IC output pins. This results in very good isolation between the various electrical paths and low crosstalk.

[0110] The aforementioned techniques enable the reduction of crosstalk when multiple signals need to be routed close together.

[0111] The IC 100 implemented in the above manner can be integrated into a larger system. Details of such an example system will be described below.

[0112] 7. System

[0113] Figure 8 This is a schematic diagram illustrating details of a system in one embodiment of this disclosure. The figure shows a multiprocessor system 800, including a clock IC 100, an oscillator 810, processors 820-820N, interconnects 830, memory 840A-840N, and a power supply 850. The components of the multiprocessor system 800 can be assembled on a printed circuit board (PCB). System 800 typically contains more components and blocks, which are not shown for simplicity and brevity, but are obvious to those skilled in the art.

[0114] Each of the processors 820A through 820N represents one or more processing units (or cores) capable of executing instructions and manipulating data to provide one or more required functions. These processors fetch instructions and store / read data from one or more memories 840A through 840N via interconnect 830.

[0115] Memory units 840A to 840N (memory units) represent a combination of volatile and non-volatile memory used to store instructions and data for use by one or more processors 820A to 820N.

[0116] Interconnect 830 provides electrical paths for connecting processors 820A-820N and memory cells 840A-840N, and can be implemented in a known manner and according to interconnect standards. Processors 820A-820N are connected to interconnect 830 via their respective paths 832A-823N. Memory cells 840A-840N are connected to interconnect 830 via their respective paths 834A-834N. Interconnect 830 is designed to allow the transfer of instructions and data between any processor 820A-820N and any memory cell 840A-840N in a known manner.

[0117] Each of the processors 820A to 820N receives its own clock signal from the clock IC 100 and operates according to the received clock, which serves as a timing reference for coordinating the operation of the respective processor.

[0118] Power supply 850 includes multiple voltage regulators (e.g., LDOs) and, as described above, provides independent power supply voltages for the various sections / blocks within clock IC 100. Oscillator 810 provides a reference clock on path 811 for the phase-locked loop (PLL) in clock IC 100 to generate the clock signal.

[0119] Clock IC 100 and the above Figure 1 As shown and described in (and other figures), the clock IC 100 generates multiple clock signals on pins 140A-140N. These respective clock signals are provided to processors 820A-820N via their respective paths 812A-812N. Paths 812A-812N terminate at their respective clock input terminals of the corresponding processors 820A-820N. The clock IC 100 is implemented as described in the detailed description above, and generates and distributes clock signals to pins 140A-140N with minimal crosstalk by employing the techniques described herein.

[0120] 8. Conclusion

[0121] Throughout this specification, the terms "one embodiment," "an embodiment," or similar expressions mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," and similar expressions appearing throughout this specification may, but are not necessarily, all refer to the same embodiment.

[0122] Although Figures 1 to 8 In the diagram, terminals / nodes are shown as having direct connections (i.e., "connected to") with other various terminals, but it should be understood that there may be additional components in the path (to suit a particular environment), so these connections can be regarded as "electrically coupled" to the same terminals to which they are connected.

[0123] Several aspects of the present invention will be described below with reference to examples. However, those skilled in the art will understand that the present invention can be practiced without one or more specific details, or other methods, elements, materials, etc. may be used. In other cases, well-known structures, materials, or operations will not be described in detail to avoid obscuring the focus of the invention. Furthermore, the described features / aspects can be implemented in various combinations, but for the sake of brevity, only some combinations are described herein.

Claims

1. A circuit, characterized in that, include: Multiple signal traces, each with a corresponding input terminal and a corresponding output terminal, each signal trace is used to transmit the signal received at its corresponding input terminal to its corresponding output terminal; Multiple transmitters, each with its output coupled to the input of its corresponding signal trace; as well as Multiple receivers, each receiver's input is coupled to the output of its corresponding signal trace. Each receiver includes a self-biased inverter biased in the high-gain region. The DC operating point of each transmitter is equal to the DC operating point of its corresponding receiver.

2. The circuit according to claim 1, characterized in that, Multiple signal generators, each signal generator being used to generate the corresponding input signal; and A signal distributor has multiple input ports and multiple output ports, each input port constituting the input terminal and each output port constituting the output terminal. The signal distributor is operable to couple any one of the plurality of input ports to any one of the plurality of output ports.

3. The circuit according to claim 1, characterized in that, This self-biased inverter includes: An inverter having one input node and one output node; and A resistor is connected in parallel between the input and output nodes of the inverter.

4. The circuit according to claim 3, characterized in that, The corresponding signal is a differential signal, and the DC operating point is equal to the common-mode level of the differential signal.

5. The circuit according to claim 4, characterized in that, Each of the plurality of transmitters includes a differential transmitter, each of the plurality of receivers includes a differential receiver, and each of the plurality of signal traces includes a differential trace.

6. The circuit according to claim 5, characterized in that, Each transmitter contains a source-terminated series (SST) inverter.

7. The circuit according to claim 6, characterized in that, Each transmitter contains multiple transmitter slices, and each transmitter slice can be controllably coupled to the input of its corresponding signal trace.

8. The circuit according to claim 7, characterized in that, The differential load impedance presented by each of the plurality of receivers is greater than the characteristic impedance of its corresponding signal trace.

9. The circuit according to claim 8, characterized in that, The differential power supply impedance of each of the plurality of transmitters is less than the characteristic impedance of its corresponding signal trace.

10. The circuit according to claim 9, characterized in that, Each receiver also includes a pair of cross-coupled inverters, which are coupled between the respective output nodes of the corresponding self-biased inverters in the receiver.

11. The circuit according to claim 10, characterized in that, Each receiver also includes a pair of inverter buffers, wherein the first inverter buffer of the pair is coupled to the first output node of the respective output node of the self-biased inverter, and the second inverter buffer is coupled to the second output node of the respective output node of the self-biased inverter.

12. The circuit according to claim 11, characterized in that, A pair of self-biased inverters of the first receiver of the plurality of receivers is powered by a first power supply; and a first pair of inverter buffers of the first receiver is powered by a second power supply.

13. The circuit according to claim 12, characterized in that, The signal distributor couples a first transmitter of the plurality of transmitters to the first receiver, and the first transmitter is also powered by the first power supply.

14. The circuit according to claim 13, characterized in that, It further includes multiple differential drivers, each of which is coupled to the output of a pair of inverter buffers of the corresponding receiver, wherein a first differential driver is coupled to the output of the first pair of inverter buffers, and the first differential driver is powered by a third power supply.

15. A system, characterized in that, include: Multiple processors are used to execute instructions; Multiple memory units are used to store instructions and data; An interconnect structure for coupling the processor to the memory cell; as well as A clock integration circuit is used to generate multiple clock signals, wherein each of the multiple clock signals is coupled to the clock input of a corresponding processor among the multiple processors, and the respective clock signal serves as a time base to coordinate the operation of the corresponding processor. The clock IC includes: Multiple signal traces, each signal trace has a corresponding input terminal and a corresponding output terminal, and each signal trace is used to transmit the received clock signal from the corresponding input terminal to the corresponding output terminal; Multiple transmitters, each transmitter's output coupled to the corresponding input of its corresponding signal trace; and Multiple receivers, each receiver's input coupled to the corresponding output of the corresponding signal trace. Each receiver includes a self-biased inverter biased in the high-gain region. In this configuration, the DC operating point of each transmitter is the same as the DC operating point of its corresponding receiver.

16. The system according to claim 15, characterized in that, The clock IC further includes: Multiple phase-locked loops (PLLs), each PLL used to generate its respective clock signal; and A signal distributor has multiple input ports and multiple output ports, each input port constituting the input terminal and each output port constituting the output terminal. The signal distributor is operable to couple any one of the plurality of input ports to any one of the plurality of output ports.

17. The system according to claim 16, characterized in that, The self-biased inverter includes: An inverter with input and output nodes; and A resistor is connected in parallel between the input and output nodes of the inverter.

18. The system according to claim 17, characterized in that, The respective clock signals are differential signals, and the DC operating point is equal to the common-mode potential of the differential signal.

19. The system according to claim 18, characterized in that, Each receiver further includes: A pair of cross-coupled inverters, coupled between the respective output nodes of the receiver's self-biased inverter; and A pair of inverter buffers, wherein the first inverter buffer of the pair is coupled to the first output node of the respective output node of the self-biased inverter, and the second inverting buffer is coupled to the second output node of the respective output node of the self-biased inverter.

20. The system according to claim 19, characterized in that, It further includes multiple voltage regulators, Among them, a pair of self-biased inverters of the first receiver in the plurality of receivers are powered by a first voltage regulator; The first pair of inverter buffers of the first receiver is powered by the second power supply. The signal distributor couples the first transmitter of the plurality of transmitters to the first receiver; The first transmitter is also powered by the first voltage regulator.

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