Photoelectric detector, forming method and chip

Abstract

The invention provides a photoelectric detector, a forming method and a chip, and the photoelectric detector comprises a semiconductor layer, a passivation layer and an electrode layer. Wherein the semiconductor layer, the passivation layer and the electrode layer are stacked in sequence along a first direction; wherein the electrode layer comprises a first electrode, a second electrode and a matching network; wherein the first electrode and the second electrode are electrically connected with the matching network and the semiconductor layer; the projections of the matching network and the semiconductor layer in the first direction are at least partially overlapped.

Description

Technical Field

[0001] This application relates to the field of optical signal transmission technology, and in particular to a photodetector, a method for forming it, and a chip. Background Technology

[0002] In existing technologies, avalanche photodiodes (APDs), as high-sensitivity photodetectors with internal gain, have important applications in optical communication, and their bandwidth performance directly determines the data transmission rate and capacity of the system. However, current APD chip bandwidth improvement faces several fundamental limitations, restricting their application in next-generation ultra-high-speed optical communication systems. Summary of the Invention

[0003] This application provides a photodetector, a forming method, and a chip that can expand bandwidth and improve integration and durability.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a photodetector, which includes a semiconductor layer, a passivation layer, and an electrode layer; wherein the semiconductor layer, the passivation layer, and the electrode layer are stacked sequentially along a first direction; wherein the electrode layer includes a first electrode, a second electrode, and a matching network; wherein the first electrode and the second electrode are both electrically connected to the matching network and the semiconductor layer.

[0005] In some embodiments, the matching network includes: a first inductor, a second inductor, and a first capacitor; wherein the first inductor and the second inductor are connected in series; the two ends of the series branch formed by the first inductor and the second inductor are respectively connected to the first electrode and the second electrode; the first capacitor is connected in parallel to the second inductor, or in parallel to the series branch formed by the first inductor and the second inductor.

[0006] In some embodiments, the first electrode and the second electrode are arranged around the matching network.

[0007] In some embodiments, the semiconductor layer includes: a first light-absorbing region, a first avalanche multiplication region, a first doped region, a first intrinsic semiconductor region, and a second doped region; wherein the first doped region, the avalanche multiplication region, the first intrinsic semiconductor region, and the second doped region are arranged sequentially along a second direction; wherein the second direction is perpendicular to the first direction; the light-absorbing region is stacked on the avalanche multiplication region along the first direction; the first electrode is in contact with the first doped region; and the second electrode is in contact with the second doped region.

[0008] In some embodiments, the matching network is disposed between the first electrode and the second electrode; both the first electrode and the matching network surround the second electrode.

[0009] In some embodiments, the semiconductor layer includes: a second light absorption region, a second avalanche multiplication region, a third doped region, a second intrinsic semiconductor region, and a fourth doped region; wherein the third doped region, the second intrinsic semiconductor region, the second avalanche multiplication region, the second light absorption region, and the fourth doped region are stacked sequentially along the first direction; the first electrode is in contact with the third doped region; and the second electrode is in contact with the fourth doped region.

[0010] In some embodiments, both the first inductor and the second inductor are spiral inductors.

[0011] In some embodiments, the first capacitor is an interdigital capacitor.

[0012] This application provides a method for forming a photodetector, comprising: providing a substrate; sequentially stacking a semiconductor layer and a passivation layer on the substrate along a first direction; simultaneously forming a first electrode, a second electrode, and a matching network on the passivation layer; wherein the first electrode and the second electrode are both electrically connected to the matching network and the semiconductor layer.

[0013] This application provides a photodetector chip, which includes the photodetector described in any of the above embodiments.

[0014] The embodiments of this application have the following beneficial effects: In this embodiment, the electrode layer of the photodetector includes a first electrode, a second electrode, and a matching network. That is, the matching network is not separately disposed outside the photodetector; it is integrated within the electrode layer containing the first and second electrodes. Thus, compared to solutions where the matching network is separately disposed outside the photodetector, this embodiment eliminates the need for leads and solder joints to connect the matching network to the photodetector, thereby reducing the physical connection interfaces between dissimilar materials and improving the reliability and long-term stability of the entire circuit connection. Simultaneously, integrating the matching network within the electrode layer reduces the possibility of performance degradation due to contact oxidation, corrosion, or fretting wear, preventing performance degradation of inductors, capacitors, and other components within the matching network during long-term use and enhancing long-term stability.

[0015] In this embodiment, the matching network includes two different types of devices: capacitors and inductors. Thus, compared to using only inductors, this application improves and extends the frequency response by introducing new poles and zeros through capacitors. Specifically, this application uses a multi-pole approach to compensate the photodetector 100, thereby further enhancing the bandwidth. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the photodetector provided in the embodiments of this application. Figure 1 ; Figure 2 This is a schematic diagram of the structure of the photodetector provided in the embodiments of this application. Figure 2 ; Figure 3 This is a schematic diagram of the electrode layer structure provided in the embodiments of this application. Figure 1 ; Figure 4 This is a schematic diagram of the electrode layer structure provided in the embodiments of this application. Figure 2 ; Figure 5 This is a schematic diagram of the electrode layer structure provided in the embodiments of this application. Figure 3 ; Figure 6 This is a schematic diagram of the electrode layer structure provided in the embodiments of this application. Figure 4 ; Figure 7 This is a schematic diagram of the structure of the photodetector provided in the embodiments of this application. Figure 3 ; Figure 8 This is a schematic diagram of the electrode layer structure provided in the embodiments of this application. Figure 5 ; Figure 9 This is a schematic diagram of the electrode layer structure provided in the embodiments of this application. Figure 6 ; Figure 10 This is a schematic diagram of the circuit structure of the matching network provided in the embodiments of this application. Figure 1 ; Figure 11 This is a schematic diagram of the circuit structure of the matching network provided in the embodiments of this application. Figure 2 ; Figure 12 This is a schematic diagram of the performance structure of the photodetector provided in the embodiments of this application; Figure 13 This is a schematic flowchart of the method for forming a photodetector provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Figure 1 and Figure 2 This is a schematic diagram of an optional photodetector 100 provided in an embodiment of this application. It should be noted that the photodetector 100 may further include... Figure 1 and Figure 2 The substrate 110 shown. Figure 2 The first direction Z can be perpendicular to the substrate 110, and the second direction Y and the third direction X can be parallel to the substrate 110. Figure 1 No examples were given in the text. Figure 2 The passivation layer 20 and the upper cladding layer 40 are made of silicon dioxide (SiO2).

[0019] It should also be noted that, Figure 1 and Figure 2 The substrate 110 can be a silicon-on-insulator (SOI), comprising a hand substrate 111, a buried oxide layer 112, and a device silicon layer. The device silicon layer can be formed into a semiconductor layer 10 through methods such as ion implantation doping and epitaxial growth. The first electrode 31 and the second electrode 32 can be connected to the semiconductor layer 10 through vias 310. Figure 1 and Figure 2 The photodetector shown is an avalanche photodetector. Other types of photodetectors and substrates are also possible, and no restrictions are placed here.

[0020] In this embodiment of the application, combined with Figure 1 and Figure 2 The photodetector 100 includes a semiconductor layer 10, a passivation layer 20, and an electrode layer 30. The semiconductor layer 10, passivation layer 20, and electrode layer 30 are stacked sequentially along a first direction X. The semiconductor layer 10 receives and absorbs input optical signals, generating charge carriers (electrical signals). The passivation layer 20 has a contact window. The electrode layer 30 contacts the semiconductor layer 10 at the contact window, achieving an electrical connection. Outside the contact window, the passivation layer 20 provides physical and electrical isolation. The passivation layer 20 also protects the semiconductor layer 10 during the formation of the electrode layer 30, preventing damage to the semiconductor layer 10 caused by processes such as etching or ion implantation.

[0021] Here, for reference Figure 1 The electrode layer 30 includes a first electrode 31, a second electrode 32, and a matching network 33. The materials of the first electrode 31, the second electrode 32, and the matching network 33 can be any one or a combination of metals such as aluminum (Al), copper (Cu), or tungsten (Wu). That is, in this embodiment, the matching network 33 is not separately disposed outside the photodetector 100, but is integrated into the electrode layer 30 where the first electrode 31 and the second electrode 32 are located.

[0022] In this way, compared to the scheme of separately setting the matching network 33 outside the photodetector 100, the embodiment of this application does not require the structure of leads and solder joints to connect the matching network 33 to the photodetector 100. This reduces the physical connection interface between heterogeneous materials, improving the reliability and long-term stability of the entire circuit connection. At the same time, the matching network 33 is integrated into the electrode layer 30 where the first electrode 31 and the second electrode 32 are located, reducing the possibility of performance degradation due to contact oxidation, corrosion, or fretting wear. This avoids performance degradation of inductors, capacitors, and other devices in the matching network 33 during long-term use, improving long-term stability.

[0023] Here, for reference Figure 1 The first electrode 31 and the second electrode 32 are both electrically connected to the matching network 33 and the semiconductor layer 10. The first electrode 31 and the second electrode 32 are used to convert the input optical signal into an electrical signal and output it to an external circuit. The matching network 33 can be an LC matching network. The matching network 33 can achieve impedance transformation and frequency compensation by using inductors and capacitors. For example, the matching network 33 includes an inductor, which compensates for or cancels the adverse effects of the detector junction capacitance, "peaking" the frequency response of the electrical signal, so that the photodetector 100 can have a wider and flatter effective response bandwidth.

[0024] Here, for reference Figure 1 The matching network 33 and the semiconductor layer 10 at least partially overlap in projection along the first direction X. In other words, in this embodiment, the matching network 33 is directly stacked on top of the semiconductor layer 10. This significantly reduces the horizontal area occupied by the photodetector, enabling a more compact device layout and improving integration.

[0025] In some embodiments of this application, reference is made to Figure 1The semiconductor layer 10 includes a first light-absorbing region 15, a first avalanche multiplication region 12, a first doped region 11, a first intrinsic semiconductor region 13, and a second doped region 14. The first doped region 11 and the second doped region 14 are formed by N-type or P-type doping of the top silicon layer (Device Silicon) in the substrate 110. The first intrinsic semiconductor region 13 can be an undoped portion of the top silicon layer (Device Silicon). The first light-absorbing region can be made of materials such as indium gallium arsenide (InGaAs), germanium (Ge), germanium tin (GeSn), silicon germanium (SiGe), or silicon (Si) that match the detection wavelength. The first avalanche multiplication region 12 can be made of materials such as indium phosphide (InP) or silicon (Si) that have a high ionization coefficient ratio.

[0026] Here, for reference Figure 1 The first doped region 11, the first avalanche multiplication region 12, the first intrinsic semiconductor region 13, and the second doped region 14 are arranged sequentially along the second direction Y. The first light absorption region 15 is stacked on the first avalanche multiplication region 12 along the first direction Z. In this way, the incident light signal enters the first light absorption region 15. The incident light signal is absorbed in the first light absorption region 15, generating primary electron-hole pairs; subsequently, under the action of the electric field established by the reverse bias, photogenerated carriers (taking holes as an example) are separated and directionally transported to the first avalanche multiplication region 12 below. In the first avalanche multiplication region 12, the extremely high electric field gives the initial carriers huge kinetic energy, triggering an avalanche multiplication effect through a chain-like collisional ionization process, causing the number of carriers to increase exponentially.

[0027] Here, for reference Figure 1 The first electrode 31 is in contact with the first doped region 11. The second electrode 32 is in contact with the second doped region 14. In this way, the multiplied carriers are collected by the first electrode 31 and the second electrode 32, forming an output electrical signal that is amplified by tens to hundreds of times compared to the primary photocurrent.

[0028] Figure 3 This is a schematic diagram of an optional electrode layer 30 provided in an embodiment of the present disclosure. It should be noted that the electrode layer 30 may include one or more metal layers, and there is no limitation here. Figure 3 The electrode layer 30 shown in the example includes metal layers M0 and M1. Figure 3 The metal layer M0 in the middle can be referenced Figure 4 To understand, Figure 3 The metal layer M0 in the middle can be referenced Figure 5 To understand.

[0029] In some embodiments of this application, combined with Figures 3 to 5The first electrode 31 and the second electrode 32 are respectively disposed on both sides of the matching network 33 in the second direction Y. The second direction Y is perpendicular to the first direction Z. Thus, the matching network 33 is disposed between the first electrode 31 and the second electrode 32. That is to say, this application utilizes the space between electrodes that is not effectively utilized in the prior art to form the matching network 33. In this way, the on-chip integration of the matching network 33 is achieved with extremely high space efficiency, thereby significantly improving the integration density of the photodetector 100.

[0030] It should be noted that, in combination Figures 3 to 5 The first electrode 31, the second electrode 32, and the matching network 33 can be disposed in the same metal layer or in different metal layers. A dielectric layer 320 is disposed between metal layers M0 and M1, and a contact plug 311 connects metal layers M0 and M1. For example, Figure 4 and Figure 5 The first electrode 31 (or the second electrode 32) located between different metal layers can be interconnected using contact plugs 311. For example, Figure 5 The first capacitor C1 in the middle and Figure 4 The first inductor L T1 Second inductor L T2 They can be interconnected using contact plugs 311.

[0031] Figure 6 This is a schematic diagram of another optional electrode layer 30 provided in this embodiment. It should be noted that... Figure 6 The first electrode 31, the second electrode 32, and the matching network 33 can be disposed on the same metal layer. The first electrode 31 and the second electrode 32 are arranged together around the matching network 33. In this way, the embodiments of this application achieve on-chip integration of the matching network 33 with extremely high space efficiency, thereby significantly improving the integration density of the photodetector 100.

[0032] In some embodiments of this application, reference is made to Figure 6 First inductor L T1 Second inductor L T2 Both are spiral inductors. Thus, in silicon photonics or compound semiconductor processes, the first inductor L... T1 Second inductor L T2 As a spiral inductor, it can be directly fabricated on the chip or within the packaging substrate to achieve on-chip integration, reducing the size and parasitic parameters of traditional wire-wound inductors and improving system compactness.

[0033] In some embodiments of this application, reference is made to Figure 6The first capacitor, C1, is an interdigitated capacitor. This allows the first capacitor C1 to be directly fabricated on the chip using standard semiconductor planar processes (such as GaAs, InP, or silicon-based processes), and monolithically integrated with semiconductor layer 10 and the spiral inductor. This eliminates the additional soldering and wire bonding steps required for discrete capacitors, significantly reducing parasitic inductance and resistance introduced by package leads, and improving system reliability and consistency. Furthermore, compared to traditional parallel-plate capacitors, the first capacitor C1 exhibits a higher self-resonant frequency and a better quality factor at high frequencies (such as radio frequency and microwave bands). When used for impedance matching, radio frequency bypassing, or forming LC resonant / filter networks, it minimizes signal loss and phase distortion, thereby ensuring the integrity of high-speed data signals.

[0034] Figure 7 This is a schematic diagram of another optional photodetector provided in an embodiment of this disclosure. It should be noted that... Figure 7 The third doped region 201, the second intrinsic semiconductor region 202, the second avalanche multiplication region 203, the second light absorption region 204, and the fourth doped region 205 can all be cylindrical, frustum-shaped, or truncated pyramidal. The areas of the third doped region 201, the second intrinsic semiconductor region 202, the second avalanche multiplication region 203, the second light absorption region 204, and the fourth doped region 205 can decrease sequentially.

[0035] In some embodiments of this application, reference is made to Figure 7 The semiconductor layer 10 includes a third doped region 201, a second intrinsic semiconductor region 202, a second avalanche multiplication region 203, a second light absorption region 204, and a fourth doped region 205.

[0036] Here, for reference Figure 7 The third doped region 201, the second intrinsic semiconductor region 202, the second avalanche multiplication region 203, the second light absorption region 204, and the fourth doped region 205 are stacked sequentially along the first direction Z. Thus, the incident light signal enters the second light absorption region 204. The incident light signal is absorbed in the second light absorption region 204, generating primary electron-hole pairs; subsequently, under the action of the electric field established by the reverse bias, photogenerated carriers (taking holes as an example) are separated and directionally transported to the lower second avalanche multiplication region 203. In the second avalanche multiplication region 203, the extremely high electric field gives the initial carriers enormous kinetic energy, triggering an avalanche multiplication effect through a chain-like collisional ionization process, causing the number of carriers to increase exponentially.

[0037] Here, the first electrode 31 is in contact with the third doped region 201. The second electrode 32 is in contact with the fourth doped region 205. In this way, holes generated by the optical signal move towards the third doped region 201, and electrons generated by the optical signal move towards the fourth doped region 205. A photocurrent (electrical signal) can be formed between the third doped region 201 and the fourth doped region 205. The amplified carriers are collected by the first electrode 31 and the second electrode 32, forming an output electrical signal that is amplified by tens to hundreds of times compared to the primary photocurrent.

[0038] Figure 8 and Figure 9 This is a schematic diagram of another electrode layer 30 provided in this application. It should be noted that... Figure 7 The structure of the middle electrode layer 30 can be referenced. Figure 8 and Figure 9 To understand. Figure 8 The illustrated metal layer M0 includes the first inductor L of the matching network 33. T1 Second inductor L T2 , Figure 9 The illustrated metal layer M1 includes the first capacitor C1 of the matching network 33. The connection method and positional relationship between metal layers M0 and M1 can be referenced above. Figure 3 The embodiments shown are for reference only and will not be described in detail here. Figure 8 and Figure 9 The first electrode 31 in the middle can be arranged in an array and disposed at the edge of the third doped region 201. Figure 8 and Figure 9 The second electrode 32 can be arranged in an array and uniformly distributed in the region where the fourth doped region 205 is located.

[0039] In some embodiments of this application, combined with Figure 8 and Figure 9 The matching network is positioned between the first electrode 31 and the second electrode 32. . Both the first electrode 31 and the matching network surround the second electrode 32. For example, Figure 8 The matching network includes the first inductor L T1 Second inductor L T2 It is arranged around the second electrode 32. Figure 9 The matching network includes a first capacitor C1 arranged around the second electrode 32. In this way, the unused space between the first electrode 31 and the second electrode 32 is used to form the matching network 33. This achieves on-chip integration of the matching network 33 with extremely high space efficiency, thereby further improving the integration density of the photodetector 100.

[0040] In some embodiments of this application, reference is made to Figure 10 Matching network 33 includes a first inductor L T1 Second inductor LT2 And the first capacitor C1. The first inductor L T1 Second inductor L T2 Series connection. First inductor L T1 Second inductor L T2 The two ends of the formed series branch are respectively connected to the first electrode 31 and the second electrode 32 in the above embodiment. The first capacitor C1 is connected in parallel with the second inductor L. T For example, the first inductor L T1 First terminal and second inductor L T2 The first terminal of each is connected to the first terminal of the first capacitor C1. The first terminal of the first capacitor C1 is connected to the first inductor L. T1 Second inductor L T2 The connection node. The first terminal of the first capacitor C1 is grounded by connecting to the second electrode 32 in the above embodiment.

[0041] It should also be noted that, Figure 9 and Figure 10 In this context, Iph represents the photocurrent source, which is the ideal current source of the original photocurrent. Figure 9 and Figure 10 In this context, Ct is the barrier capacitance of the PN junction inside the photodetector. Rt is the dynamic differential resistance of the APD when it operates in the breakdown region. Figure 9 and Figure 10 Ra in the equation is the real part of the impedance that is equivalent to the delay of the avalanche multiplication process. Figure 9 and Figure 10 In this context, Ca is a capacitor connected in parallel with Ra, which is equivalent to the frequency response of the avalanche process. Figure 9 and Figure 10 Rm in the equation is the equivalent noise resistance used to calculate avalanche multiplication random noise. Figure 9 and Figure 10 In this context, Cm is a capacitor connected in parallel with Rm, used to describe the noise frequency characteristics. Figure 9 and Figure 10 In some specific models, Ram may have overlapping meanings with Ra or Rm. Figure 9 and Figure 10 Rs in the figure represents the bulk resistance and contact resistance of the APD semiconductor material and the electrode. Figure 9 and Figure 10 Lm in this context refers to the parasitic inductance generated by the package leads or bonding wires. Figure 9 and Figure 10 Rp in this context refers to the parasitic parallel insulation resistance generated by the packaging material or structure. Figure 9 and Figure 10 Cp in the figure represents the parasitic capacitance between package pins or between a pin and ground. Figure 9 and Figure 10 RL in this context refers to the load resistor in the external detection circuit that determines the gain and bandwidth.

[0042] It should also be noted that Ra, Ca, Rm, and Cm are not actual discrete components, but rather equivalent lumped parameters introduced to simulate the physical fact that "avalanche multiplication takes time" at the circuit level. Rs, Lm, Rp, and Cp represent unavoidable parasitic parameters between the chip's internal and external pins.

[0043] Here, in this embodiment of the application, by carefully designing the parameters of the matching network, the zero-point frequency can be set close to the original circuit cutoff frequency. The peaking effect caused by these zeros can improve the gain in this frequency range, thereby pushing the -3dB cutoff frequency to a higher frequency and increasing the output bandwidth.

[0044] For example, the effect of the matching network 33 design on extending the bandwidth of the photodetector 100 can be as follows: Figure 12 As shown: The frequency variation curve of photodetector 100 without using a matching network is shown in L1, and the frequency variation curve of photodetector 100 with a matching network is shown in L2. That is, the frequency band corresponding to -3dB of photodetector 100 is increased from 20GHz to 40GHz, achieving a 2-fold improvement.

[0045] For example, the first inductor L in the matching network 33 T1 Second inductor L T2 Determining the parameters of the first capacitor C1 may include the following steps: The equivalent circuit model of the photodetector is simulated using software such as ADS. For a specific photodetector structure, the optimal parameter values ​​for the matching network are determined. The parameters of the matching network include: the inductance values ​​of the first and second inductors, the capacitance value of the first capacitor, and the mutual inductance coefficients of the first and second inductors.

[0046] Here, the inductance values ​​of the first and second inductors can be customized by precisely designing the inductor geometry (number of turns, linewidth, and spacing). The capacitance value of the interdigital capacitor can be determined by the characteristics of the number, length, width, and spacing of the finger electrodes. Thus, this application allows for fine-grained, linear adjustment of capacitance and inductance values ​​through layout. Simultaneously, since there are no leads or solder joints causing circuit connection losses, the simulation results are more accurate, and the parameters of the inductors and capacitors selected based on the simulation structure can be more accurate, thereby enabling the photodetector to achieve higher performance.

[0047] It is understood that the matching network in this application embodiment includes two different types of devices: capacitors and inductors. By selecting appropriate inductance and capacitance parameters, the matching network introduces multiple zeros into the transfer function of the photodetector, and simultaneously adjusts the positions of the original poles, optimizing the overall pole and zero layout. This allows the frequency response to remain flat or have a desired shape (e.g., certain characteristics of the Butterworth or Chebyshev response) over a wider range. Thus, compared to simply using inductors, this application improves and extends the frequency response by introducing additional poles and zeros through capacitors. In other words, this application uses a multi-pole approach to compensate for the photodetector 100, thereby further enhancing the bandwidth.

[0048] In some embodiments of this application, reference is made to Figure 10 First inductor L T1 Second inductor L T2 Series connection. First inductor L T1 Second inductor L T2 The two ends of the formed series branch are respectively connected to the first electrode 31 and the second electrode 32 in the above embodiment. The first capacitor C1 is connected in parallel with the first inductor L. T1 Second inductor L T2 The resulting series branch. Thus, compared to simply adding a zero and a pole by setting an inductor, this application improves and extends the frequency response by introducing new poles and zeros through a capacitor. That is, this application uses a multi-pole approach to compensate for the photodetector 100, thereby further improving the bandwidth.

[0049] Figure 12 This application provides an optional method for forming a photodetector, wherein the photodetector 100 in the above embodiment can be formed by... Figure 12 The steps S101 to S103 shown in the example are explained.

[0050] S101, Provide substrate.

[0051] S102. On the substrate, a semiconductor layer and a passivation layer are sequentially stacked along a first direction to form a semiconductor layer.

[0052] In this embodiment, light absorption, multiplication, and charge control regions can be formed on a substrate by stacking thin films of different materials and dopants layer by layer. For example, metal-organic chemical vapor deposition (MOCVD) can be used to sequentially grow the avalanche multiplication layer, the doped region, and the light absorption layer. Alternatively, in this embodiment, a silicon layer can be epitaxially grown on the substrate and doped to form the light absorption, multiplication, and doped regions. Thus, a PN junction and a photogenerated carrier generation region are precisely fabricated, realizing the basic structure for photoelectric conversion.

[0053] Here, a passivation layer is formed to protect the semiconductor surface and reduce electrical noise. This is achieved by depositing an insulating dielectric to passivate dangling bonds and isolate the effects of the environment. For example, plasma-enhanced chemical vapor deposition can be used to coat the semiconductor layer with a layer of silicon nitride or silicon dioxide. This effectively suppresses surface leakage current and dark current, improving the stability and reliability of avalanche photodiodes under high bias voltages.

[0054] S103. A first electrode, a second electrode, and a matching network are simultaneously formed on the passivation layer; wherein the first electrode and the second electrode are both electrically connected to the matching network and the semiconductor layer.

[0055] Here, the first electrode, the second electrode, and the matching network can be fabricated simultaneously through the same process step (such as metal deposition, electroplating, and etching) to form a continuous metal structure. For example, photolithography is used to transfer the patterns of the first electrode, the second electrode, and the matching network onto photoresist, and then the final shape is defined by lift-off or etching. In other words, this application simultaneously forms the first electrode, the second electrode, and the matching network in a single process step. This eliminates the need for an additional process step to form the matching network, improving process efficiency. Furthermore, the first electrode, the second electrode, and the matching network do not require subsequent soldering or bonding, reducing parasitic resistance and improving reliability.

[0056] This application also provides a photodetector chip, including the photodetector described in any of the above embodiments, and having the beneficial effects brought by the photodetector described in any of the above embodiments.

[0057] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A photodetector, characterized in that, The photodetector comprises: a semiconductor layer, a passivation layer, and an electrode layer; wherein... The semiconductor layer, the passivation layer, and the electrode layer are stacked sequentially along a first direction; wherein... The electrode layer includes: a first electrode, a second electrode, and a matching network; wherein... The first electrode and the second electrode are both electrically connected to the matching network and the semiconductor layer; the projection of the matching network and the semiconductor layer along the first direction at least partially overlaps.

2. The photodetector according to claim 1, characterized in that, The matching network includes: a first inductor, a second inductor, and a first capacitor; wherein, The first inductor and the second inductor are connected in series; the two ends of the series branch formed by the first inductor and the second inductor are respectively connected to the first electrode and the second electrode; The first capacitor is connected in parallel to the second inductor, or in parallel to the series branch formed by the first inductor and the second inductor.

3. The photodetector according to claim 2, characterized in that, The first electrode and the second electrode are arranged around the matching network.

4. The photodetector according to claim 3, characterized in that, The semiconductor layer includes: a first light absorption region, a first avalanche multiplication region, a first doped region, a first intrinsic semiconductor region, and a second doped region; wherein... The first doped region, the avalanche multiplication region, the first intrinsic semiconductor region, and the second doped region are arranged sequentially along a second direction; wherein, the second direction is perpendicular to the first direction; The first light absorption region is stacked on the avalanche multiplication region along the first direction; the first electrode is in contact with the first doped region; the second electrode is in contact with the second doped region.

5. The photodetector according to claim 2, characterized in that, The matching network is disposed between the first electrode and the second electrode; Both the first electrode and the matching network surround the second electrode.

6. The photodetector according to claim 5, characterized in that, The semiconductor layer includes: a second light absorption region, a second avalanche multiplication region, a third doped region, a second intrinsic semiconductor region, and a fourth doped region; wherein... The third doped region, the second intrinsic semiconductor region, the second avalanche multiplication region, the second light absorption region, and the fourth doped region are stacked sequentially along the first direction; The first electrode is in contact with the third doped region; the second electrode is in contact with the fourth doped region.

7. The photodetector according to claim 2, characterized in that, Both the first inductor and the second inductor are spiral inductors.

8. The photodetector according to claim 2, characterized in that, The first capacitor is an interdigitated capacitor.

9. A method for forming a photodetector, characterized in that, Provide substrate; On the substrate, a semiconductor layer and a passivation layer are sequentially stacked along a first direction; A first electrode, a second electrode, and a matching network are simultaneously formed on the passivation layer; wherein the first electrode and the second electrode are both electrically connected to the matching network and the semiconductor layer.

10. A photodetector chip, characterized in that, The photodetector chip includes, as claimed in claim 1 The photodetector as described in any one of the 8.

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