Algorithm optimization method and device, electronic equipment and storage medium

Abstract

The invention discloses an algorithm optimization method and device, electronic equipment and a storage medium, and relates to the technical field of algorithm performance optimization. Obtaining each initial processing step in the to-be-optimized algorithm code, a data dependency relationship between the initial processing steps and a processing time delay of each initial processing step; performing step recombination on each initial processing step according to a preset thread number threshold value and the processing time delay to obtain each target processing step; each target processing step is packaged into a thread, a message queue is established between the adjacent threads according to the data dependency relationship, and the message queue is used for transmitting processing data between the adjacent threads; and obtaining an optimized algorithm code based on each thread and each message queue. The throughput capacity of the algorithm can be improved.

Description

Technical Field

[0001] This application relates to the field of algorithm performance optimization technology, and in particular to an algorithm optimization method, apparatus, electronic device and storage medium. Background Technology

[0002] Computationally intensive algorithms such as computer vision, natural language processing, real-time data analysis, and streaming signal processing have been widely used in various industries. In the application scenarios of these algorithms, it is often necessary to process massive amounts of continuously flowing data, which places high demands on the throughput of the algorithms.

[0003] Throughput is an important indicator for measuring algorithm performance, referring to the amount of data or tasks that can be successfully processed per unit of time. However, in practical applications, algorithms generally suffer from insufficient throughput, which restricts their performance and application efficiency in high-throughput scenarios.

[0004] In summary, improving the throughput of algorithms has become a pressing technical problem that needs to be solved in this field.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide an algorithm optimization method, apparatus, electronic device and storage medium, which aims to improve the throughput of the algorithm.

[0007] To achieve the above objectives, this application proposes an algorithm optimization method, which includes: The code of the algorithm to be optimized is analyzed to obtain the initial processing steps, the data dependencies between the initial processing steps, and the processing delay of each initial processing step. Based on the preset thread number threshold and the processing delay, the initial processing steps are reorganized to obtain the target processing steps. Each of the target processing steps is encapsulated as a thread, and a message queue is established between adjacent threads according to the data dependency relationship, wherein the message queue is used to transfer processing data between the adjacent threads; Based on each of the aforementioned threads and message queues, the optimized algorithm code is obtained.

[0008] In one embodiment, the step of analyzing the algorithm code to be optimized to obtain the initial processing steps in the algorithm code to be optimized, the data dependencies between the initial processing steps, and the processing delay of the initial processing steps includes: Static analysis is performed on the code of the algorithm to be optimized to obtain the control flow graph and data dependency graph; The initial processing steps of the algorithm code to be optimized are determined based on the control flow graph, and the data dependencies between the initial processing steps are determined based on the data dependency graph. The processing delay of each initial processing step is obtained by running the algorithm code to be optimized.

[0009] In one embodiment, the step of obtaining the processing delay of each of the initial processing steps by running the algorithm code to be optimized includes: Insert delay acquisition code at the beginning and end positions of the code in each of the initial processing steps; Run the algorithm code to be optimized, which has already had the delay acquisition code inserted; For each of the initial processing steps, the start time and end time of the initial processing step are recorded by the delay acquisition code, and the difference between the end time and the start time is calculated as the processing delay of the initial processing step.

[0010] In one embodiment, the step of reorganizing each of the initial processing steps according to a preset thread count threshold and the processing latency to obtain each target processing step includes: The target average latency for each thread is calculated based on the preset thread number threshold and the processing latency. The initial processing steps with processing latency greater than the target average latency are broken down into multiple sub-steps, wherein the processing latency of each sub-step is less than or equal to the target average latency. The sub-steps and the undivided initial processing steps are merged according to the accumulated delay to obtain each target processing step, wherein the processing delay of the target processing step is less than or equal to the target average delay.

[0011] In one embodiment, the step of merging the sub-steps and the undivided initial processing steps according to the accumulated delay to obtain each target processing step includes: The sub-steps and the undivided initial processing steps are arranged in the order of execution to form a step sequence; The first step in the sequence of steps is taken as the first object to be merged. The processing delay of the first object to be merged and the steps after the first object to be merged is accumulated until the accumulated delay exceeds the target average delay. The step that causes the accumulated delay to exceed the target average delay is taken as the second object to be merged. The steps preceding the second object to be merged are combined into a single target processing step; The second object to be merged is taken as the new first object to be merged. The step of accumulating the processing delay of the first object to be merged and the steps after the first object to be merged, as well as subsequent steps, are executed until all steps in the step sequence are merged into the target processing step.

[0012] In one embodiment, the step of establishing a message queue between adjacent threads based on the data dependency includes: The data structure for the output data of the preceding thread in an adjacent thread is determined based on the data dependency relationship. A message queue is established between the adjacent threads, and the data structure is defined as the data structure for the data transmitted by the message queue.

[0013] In one embodiment, after the step of obtaining the optimized algorithm code based on each of the threads and each of the message queues, the method further includes: When running the optimized algorithm code, monitor the capacity occupancy ratio of each message queue and the utilization rate of each thread; Based on the capacity occupancy ratio and the utilization rate, determine whether the optimized algorithm code meets the preset load balancing conditions; If the optimized algorithm code does not meet the load balancing conditions, an algorithm optimization prompt message will be output.

[0014] Furthermore, to achieve the above objectives, this application also proposes an algorithm optimization device, which includes: The code analysis module is used to analyze the code of the algorithm to be optimized, and to obtain the initial processing steps in the code of the algorithm to be optimized, the data dependencies between the initial processing steps, and the processing delay of the initial processing steps. The step reorganization module is used to reorganize each of the initial processing steps according to a preset thread number threshold and the processing delay to obtain each target processing step; A thread connection module is used to encapsulate each of the target processing steps into a thread, and to establish a message queue between adjacent threads according to the data dependency relationship, wherein the message queue is used to transfer processing data between the adjacent threads; The code generation module is used to obtain optimized algorithm code based on each of the aforementioned threads and message queues.

[0015] In addition, to achieve the above objectives, this application also proposes an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the algorithm optimization method described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the algorithm optimization method described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: In this application, by analyzing the code of the algorithm to be optimized, the initial processing steps, the data dependencies between the initial processing steps, and the processing latency of each initial processing step are obtained. Then, based on the thread number threshold and processing latency, the steps are reorganized, and the initial processing steps are re-integrated into the target processing steps. The target processing steps are then encapsulated into threads, and data transfer between threads is achieved through a message queue, thus constructing the optimized algorithm code. Since each thread can be executed concurrently, that is, different steps in the optimized algorithm code can be executed simultaneously. Therefore, when faced with massive input data, the optimized algorithm does not need to wait for the previous set of data to be processed before processing the next set of data, but can process multiple sets of data in parallel, thereby improving the throughput of the algorithm in practical applications. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the algorithm optimization method of this application in Embodiment 1. Figure 2 This is a flowchart illustrating Embodiment 2 of the algorithm optimization method of this application; Figure 3 This is a schematic diagram of the step division process provided in Embodiment 2 of the algorithm optimization method of this application; Figure 4 This is a schematic diagram of the pipeline construction process provided in Embodiment 2 of the algorithm optimization method of this application; Figure 5 This is a schematic diagram of the algorithm execution workflow provided in Embodiment 2 of the algorithm optimization method of this application; Figure 6 This is a schematic diagram of the module structure of the algorithm optimization device according to an embodiment of this application; Figure 7This is a schematic diagram of the device structure of the hardware operating environment involved in the algorithm optimization method in the embodiments of this application.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] Computationally intensive algorithms such as computer vision, natural language processing, real-time data analysis, and streaming signal processing have been widely used in various industries. In the application scenarios of these algorithms, it is often necessary to process massive amounts of continuously flowing data, which places high demands on the throughput of the algorithms.

[0025] Throughput is an important indicator for measuring algorithm performance, referring to the amount of data or tasks that can be successfully processed per unit of time. However, in practical applications, algorithms generally suffer from insufficient throughput, which restricts their performance and application efficiency in high-throughput scenarios.

[0026] In summary, improving the throughput of algorithms has become a pressing technical problem that needs to be solved in this field.

[0027] To address the aforementioned technical problems, this application analyzes the code of the algorithm to be optimized, obtaining the initial processing steps, the data dependencies between these steps, and the processing latency of each initial processing step. Then, based on a thread count threshold and processing latency, the steps are reorganized, and the initial processing steps are reassembled into target processing steps. These target processing steps are then encapsulated as threads, and data transfer between threads is achieved through a message queue, thus constructing the optimized algorithm code. Since each thread can execute concurrently, different steps in the optimized algorithm code can be executed simultaneously. Therefore, when faced with massive amounts of input data, the optimized algorithm does not need to wait for the previous set of data to finish processing before processing the next set; instead, it can process multiple sets of data in parallel, thereby improving the algorithm's throughput in practical applications.

[0028] It should be noted that the executing entity in this embodiment can be an electronic device with data processing, network communication, and program execution functions. The following description uses an electronic device as an example to illustrate this embodiment and the subsequent embodiments.

[0029] The following presents a first embodiment of the algorithm optimization method of this application. (Refer to...) Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the algorithm optimization method of this application.

[0030] In this embodiment, the algorithm optimization method includes steps S10 to S40: Step S10: Analyze the code of the algorithm to be optimized to obtain the initial processing steps, the data dependencies between the initial processing steps, and the processing delay of each initial processing step in the code of the algorithm to be optimized. It should be noted that the algorithm code to be optimized refers to the source code provided by the user, written in programming languages ​​such as C / C++, Python, and Java; the initial processing step refers to a logically independent and separable section of code identified from the algorithm code to be optimized, which can be a function, a loop body, or a code block defined by a specific control structure; the data dependency relationship refers to the flow and dependency relationship of input and output data between each initial processing step, for example, the output of step A is the input of step B; and the processing latency refers to the time consumed by executing an initial processing step once.

[0031] The system receives the source code of the algorithm to be optimized. In order to improve the code's runtime throughput, it first analyzes the code to understand its internal structure and runtime characteristics. Through analysis, several initial processing steps that constitute the main body of the algorithm can be identified. The data dependencies between these initial processing steps are also identified, that is, the execution order and data transmission of each step are clarified, as well as the processing latency of each initial processing step. This analysis can be achieved by combining static analysis of the algorithm code to be optimized during compilation and dynamic detection during runtime, or by using various methods such as historical performance logs or developer annotations of the algorithm code to be optimized.

[0032] Step S20: Reorganize each initial processing step according to the preset thread number threshold and processing delay to obtain each target processing step; It should be noted that the thread count threshold is a pre-configured parameter, and its value can be set based on various factors such as the number of CPU cores, memory capacity, and other hardware resources of the deployment platform of the algorithm code to be optimized, as well as the business scenario of the application. In this embodiment, the size of the thread count threshold is not specifically limited.

[0033] Since directly using the initial processing steps to build the pipeline may lead to load imbalance due to large differences in latency between steps, in order to improve the overall throughput, the initial processing steps are reorganized. The purpose of reorganization is to make the reorganized target processing steps have similar or even equal processing latency. Specifically, the reorganization can be based on the thread number threshold (i.e., the expected number of target processing steps to be executed in parallel) and the processing latency of each initial processing step. The specific form of reorganization can be various, such as splitting a time-consuming step into multiple sub-steps, or merging multiple consecutive short-latency steps into one step, so as to achieve the effect of latency balance among the reorganized target processing steps.

[0034] Step S30: Each target processing step is encapsulated as a thread, and a message queue is established between adjacent threads according to the data dependency relationship. The message queue is used to pass processing data between adjacent threads. It should be noted that a thread is an independently schedulable and executable unit of execution, and a message queue can store data passed between threads for asynchronous data transmission between adjacent threads. Adjacent threads are two threads that have a direct sequential relationship in the data processing flow. In other words, adjacent threads are linked together by a message queue. The processing result of the previous thread is stored in the message queue, and the next thread retrieves the processing result of the previous thread from the message queue. While the next thread is processing the current group of data, the previous thread can process the next group of data.

[0035] Each target processing step is encapsulated into a separate thread. The encapsulation method can be based on the thread class function written in the programming language used in the code. For each pair of adjacent threads with data dependencies, a message queue is established between them. The preceding thread (i.e., the thread that executes first among the adjacent threads) puts the processed data into the message queue, and the following thread (i.e., the thread that executes later among the adjacent threads) retrieves the data from the message queue for the next step of processing. This allows each thread to work asynchronously and concurrently, and the preceding thread does not need to wait for the following thread to finish processing before it can start processing the next piece of data.

[0036] In one feasible embodiment, step S30 may include steps S301 to S302: Step S301: Determine the data structure of the output data of the preceding thread in the adjacent thread according to the data dependency relationship; Based on the data dependencies of each initial processing step obtained from the analysis, the data structure of the output data of the preceding thread in each pair of adjacent threads is determined. The data structure is a specific type definition in the programming language, such as an integer (int) or a structure (struct Image), to clarify the data type passed between threads.

[0037] In one feasible implementation, the step of determining the data structure of the output data of the preceding thread in adjacent threads based on data dependencies may specifically include: obtaining mapping information recorded during the step reorganization process, the mapping information defining the correspondence between each initial processing step and the target processing step to which it belongs after reorganization; based on the mapping information, resolving the data dependencies existing between the initial processing steps into thread data dependencies between each target processing step; for each pair of adjacent threads with thread data dependencies, analyzing the data types flowing from all initial processing steps contained in the preceding thread to all initial processing steps contained in the subsequent thread, and determining the data structure of the output data of the preceding thread accordingly.

[0038] Step S302: Establish a message queue between adjacent threads and define the data structure as the data structure for the data transmitted by the message queue.

[0039] A message queue is established between adjacent threads, and the data structure is defined as the data structure for the data passed by the message queue. Specifically, for a pair of adjacent threads, thread A and thread B, code to declare a message queue object is automatically generated. When declaring the message queue, the data structure of the data output by thread A is used as the element type of the message queue. At the same time, enqueue operation code and dequeue operation code for the message queue are generated, and the reference or pointer of the message queue is passed as parameters to the functions of thread A and thread B. At the end of its function, thread A inputs the data processing result into the message queue, and at the beginning of its function, thread B retrieves a data processing result from the message queue as input.

[0040] Therefore, by determining the output data structure of each thread and defining the data structure of the data transmitted by the message queue accordingly, it is ensured that the optimized algorithm code can be type-checked at compile time, avoiding runtime errors caused by data type mismatch. At the same time, the message queue with specific data structure avoids the type identification overhead caused by using general type data structure, further improving data processing efficiency.

[0041] Step S40: Based on each thread and each message queue, obtain the optimized algorithm code.

[0042] Parallel pipelines are an efficient processing model that breaks down complex tasks into multiple sequential sub-steps and executes these sub-steps in parallel. After encapsulating all threads and constructing message queues, each thread and message queue is chained together into a complete pipelined data processing framework according to data dependencies. The code form of this data processing framework is the optimized algorithm code, which users can directly compile and call. This optimized algorithm code runs in a parallel pipeline manner, where each thread can process different data in parallel. That is, a data processing task is broken down into multiple sub-steps, and these sub-steps are executed in parallel in their corresponding threads. The functionality of this optimized algorithm code is the same as that of the algorithm code to be optimized, but the data processing throughput is significantly improved through the concurrent pipeline operation.

[0043] Therefore, in this embodiment, by analyzing the code of the algorithm to be optimized, the initial processing steps, the data dependencies between the initial processing steps, and the processing latency of each initial processing step are obtained. Then, the steps are reorganized according to the thread number threshold and the processing latency, and the initial processing steps are re-integrated into the target processing steps. The target processing steps are then encapsulated into threads, and data transfer between threads is achieved through a message queue, thus constructing the optimized algorithm code. Since each thread can be executed concurrently, that is, different steps in the optimized algorithm code can be executed simultaneously. Therefore, when faced with massive input data, the optimized algorithm does not need to wait for the previous set of data to be processed before processing the next set of data, but can process multiple sets of data in parallel, thereby improving the throughput of the algorithm in practical applications.

[0044] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description and will not be repeated hereafter. Based on this, step S10 may include steps S101 to S103: Step S101: Perform static analysis on the code of the algorithm to be optimized to obtain the control flow graph and data dependency graph; It should be noted that static analysis refers to the technique of inferring the nature of code by analyzing its syntax and semantics without actually running the code; a control flow graph (CFG) is a directed graph used to describe the execution order and branch flow of instructions / code blocks in a program or algorithm. It uses basic blocks as nodes and control transfer relationships as directed edges, clearly showing the execution path of the program; a data dependency graph (DDG) is a directed graph used to describe the dependencies between data elements (variables, memory, data flow) in a program or algorithm. It uses data operations (read / write) or data objects as nodes and "data dependencies" as directed edges, reflecting the generation, transmission, and use relationships of data.

[0045] Using existing static analysis tools, such as LLVM, GCC's intermediate representation analyzer, or AST analysis libraries specifically for Python, static analysis is performed on the input algorithm code to be optimized. Specifically, the code is first parsed and its abstract syntax tree is constructed. Then, a control flow graph and a data dependency graph are constructed based on the abstract syntax tree.

[0046] Step S102: Determine the initial processing steps of the algorithm code to be optimized based on the control flow graph, and determine the data dependencies between the initial processing steps based on the data dependency graph; The control flow graph (CFG) is traversed, and several candidate initial processing steps are identified based on predefined granularity rules (e.g., defining a complete function or an outermost loop as a processing step). These steps correspond to specific subgraphs or sets of nodes within the CFG. The data dependency graph is then queried. For each identified initial processing step, the set of variables involved is traversed. If the value of a variable in one step is used by another step, a data dependency edge is established between the two steps, and the direction of the dependency is recorded. By traversing the variable sets involved in all initial processing steps, the data dependencies between each initial processing step can be determined. This process is fully automated and requires no manual annotation.

[0047] Step S103: Obtain the processing delay of each initial processing step by running the algorithm code to be optimized.

[0048] To optimize the algorithm code, the processing latency of each initial processing step is obtained. One feasible implementation is to automatically insert timing code at the boundary of each determined initial processing step (e.g., function entry / exit, or the beginning / end of a loop). Then, the program with the timing code inserted is run using user-provided or automatically generated test cases. During the run, the start and end times of each initial processing step are recorded, thus obtaining the processing latency of each initial processing step. Alternatively, the processing latency can be obtained by monitoring structured logs during code execution or by using link tracing tools.

[0049] In one feasible embodiment, step S103 may include steps S1031 to S1033: Step S1031: Insert delay acquisition code at the beginning and end positions of the code in each initial processing step; The start and end positions of the code refer to the logical starting and ending points of an initial processing step in the code. For function steps, this is usually the first line of the function body and before returning; for loop steps, it is before the loop entry and after the loop exit. The latency acquisition code is a piece of code used to obtain the current high-precision timestamp.

[0050] For each initial processing step, a line or segment of code is automatically inserted before its start position to record the start time, and a line or segment of code is automatically inserted after its end position to record the end time. The inserted latency acquisition code usually also includes the operation of storing the recorded timestamp to a storage location associated with the unique identifier of the initial processing step.

[0051] Step S1032: Run the algorithm code to be optimized with the latency acquisition code already inserted; Compile or execute the complete code containing latency acquisition code. To obtain more accurate latency data, multiple sets of test data can be used to drive the operation. For each initial processing step, the average or mode of the multiple timestamps obtained is taken to calculate the processing latency of that step.

[0052] Step S1033: For each initial processing step, the start time and end time of the initial processing step are recorded by the delay acquisition code, and the difference between the end time and the start time is calculated as the processing delay of the initial processing step.

[0053] During code execution, a timing operation is triggered whenever an initial processing step with inserted latency acquisition code is executed. This involves recording a start timestamp at the beginning of the step and an end timestamp at the end. For loop steps that may be called multiple times, these timestamps are recorded in pairs, meaning a set of timestamps is recorded for each loop. After the code execution is complete, the collected timestamp data is analyzed. For each initial processing step, the difference between the end time and start time for each execution is calculated to obtain the single processing latency.

[0054] Therefore, through automated code instrumentation technology, latency measurement capabilities can be seamlessly embedded into the code of the algorithm to be optimized without relying on external performance profiling tools or modifying the build system, and latency data that is closest to the real execution environment can be obtained.

[0055] In one feasible embodiment, step S20 may include steps S201 to S203: Step S201: Calculate the target average latency for each thread based on the preset thread number threshold and processing latency; It should be noted that the target average latency refers to a calculated baseline latency value, representing the time required for each thread in the pipeline to complete its corresponding target processing step under ideal conditions.

[0056] Before reorganizing the initial processing steps, it is necessary to first establish a quantifiable reorganization target, obtain a preset thread number threshold k, and a list of processing delays for all initial processing steps. Where m represents the number of initial processing steps, t m Let m represent the processing delay of the m-th initial processing step, and calculate the sum of the processing delays of all initial processing steps. Then, calculate the target average delay. The physical meaning of the target average latency is that if the total workload is evenly distributed to k concurrent threads, then the ideal processing time of each thread is the target average latency. Subsequent decomposition and merging operations of the steps are all based on the target average latency, striving to make the processing latency of each final target processing step close to the target average latency.

[0057] Step S202: Decompose the initial processing steps whose processing latency is greater than the target average latency into multiple sub-steps, wherein the processing latency of the sub-steps is less than or equal to the target average latency. Traverse all initial processing steps. If the processing delay ti > θ of an initial processing step is found, it is determined to be an object that needs to be decomposed. The specific decomposition method depends on the internal structure of the step. For example, when any initial processing step contains a loop, assuming that the loop iterates N times and the delay of each iteration is about ti / N, in order to ensure that the delay of the sub-steps after decomposition does not exceed θ, it can be calculated that the loop needs to be decomposed into ceil(ti / θ) sub-steps, where ceil means rounding up the result. Each sub-step undertakes a part of the iteration of the original loop. After decomposition, the original loop step is replaced by multiple sub-steps. These sub-steps are combined to logically correspond to the function of the original step, and their respective delays are less than or equal to the target average delay. For initial processing steps that do not contain obvious decomposable structures, they can be divided according to their data flow or control flow.

[0058] Step S203: The sub-steps and the undivided initial processing steps are merged according to the cumulative delay to obtain each target processing step, wherein the processing delay of the target processing step is less than or equal to the target average delay.

[0059] Step decomposition solves the problem of excessive processing latency in a single step, but may generate many sub-steps with low processing latency or the algorithm code to be optimized may already contain many initial processing steps with low latency. If a thread is directly allocated to each step, the communication overhead between threads will increase dramatically, which is detrimental to throughput performance. Therefore, these steps need to be merged.

[0060] All steps to be merged (including decomposed sub-steps and undecomposed initial processing steps) are arranged in their original data dependency order. Then, starting from the first step, the latency of its subsequent steps is accumulated. As long as the accumulated latency does not exceed the target average latency, it continues to be included in the merging scope. If adding the next step would cause the accumulated latency to exceed the target average latency, the currently accumulated set of steps is merged into a single target processing step. Then, starting from the step that causes the latency to exceed the target average latency, the next round of latency accumulation and step merging begins. This process is iterated until all steps are merged. A target processing step may contain multiple sub-steps and / or multiple undecomposed initial processing steps, or it may contain only one sub-step and / or one undecomposed initial processing step. Thus, the latency of each group of target processing steps is close to but does not exceed the target average latency, and the number of target processing steps is close to or equal to the thread number threshold, achieving the goal of latency equalization across steps.

[0061] It is worth mentioning that in practical applications, the processing latency of different processing steps in the algorithm varies significantly. For example, the processing latency of preprocessing is 2ms, while the processing latency of feature extraction is 50ms. This causes the overall throughput of the algorithm to be limited by the steps with high latency, while the steps with low latency are severely idle, making it impossible to fully utilize computing resources and thus restricting the throughput of the algorithm. In this embodiment, by first breaking down the steps with excessive latency and then merging the steps with excessively low latency, and always using the target average latency as the step reorganization target, it can intelligently reorganize any initial processing steps with excessively large latency differences into a set of concurrent processing steps with balanced latency. This fundamentally solves the "barrel effect" caused by the uneven latency of each processing step in the algorithm, making the latency of each thread and each stage similar. Assuming that the optimized algorithm is divided into k target processing steps with equal processing latency, theoretically the throughput of the algorithm can be increased by k times, thereby improving the throughput of the algorithm.

[0062] In one feasible embodiment, step S203 may include steps S2031 to S2034: Step S2031: Arrange the sub-steps and the undisassembled initial processing steps into a step sequence according to the execution order; It should be noted that a step sequence refers to an ordered list in which the elements are steps to be merged, i.e., sub-steps or initial processing steps that have not been broken down. The order of each step is determined by their execution order or data dependencies.

[0063] Obtain all the steps to be merged after the decomposition process, and arrange them into an ordered list of steps according to the inherent data dependencies between these steps. The merging operation between steps must maintain this order and must not disrupt the dependencies.

[0064] Step S2032: The first step in the step sequence is taken as the first object to be merged. The processing delay of the first object to be merged and the steps after the first object to be merged is accumulated until the accumulated delay exceeds the target average delay. The step that causes the accumulated delay to exceed the target average delay is taken as the second object to be merged. Step S2033: Merge the steps preceding the second object to be merged into a single target processing step; Step S2034: The second object to be merged is taken as the new first object to be merged. The step of accumulating the processing delay of the first object to be merged and the steps after the first object to be merged, as well as subsequent steps, are executed until all steps in the step sequence are merged into the target processing step.

[0065] Starting with the first step in the sequence as the first object to be merged, the latency of each subsequent step is accumulated sequentially. This latency accumulation continues until the total accumulated latency exceeds the target average latency. At this point, the step that caused the accumulated latency to exceed the target average latency is marked as the second object to be merged. Then, all steps from the first object to the second object are merged into a single target processing step. Next, the second object is treated as the new first object to be merged, and the process of accumulating the processing latency of the first object and subsequent steps until the accumulated latency exceeds the target average latency is repeated, designating the step that caused the accumulated latency to exceed the target average latency as the second object to be merged; merging the steps before the second object into a single target processing step; and treating the second object as the new first object to be merged is repeated, until all steps in the sequence have been merged. This ensures that the total processing latency of each merged target processing step is as close as possible to, but does not exceed, the target average latency, thus achieving a balanced distribution of latency across steps.

[0066] For example, in one feasible implementation, a pointer is set to point to the first object to be merged currently being processed. Initially, this pointer points to the first step in the step sequence. Starting from the first object to be merged, the delay values ​​of subsequent steps in the step sequence are sequentially accumulated. An accumulator sum=0 is set. For each step's delay t_current added, sum=sum+t_current is calculated. After each accumulation, it is determined whether sum is greater than the target average delay θ. If sum≤θ, the accumulation continues to the next step; if sum>θ, the accumulation stops, and the current step that results in sum>θ is marked as the second object to be merged. All steps from the first object to be merged to the second object to be merged are merged into a target processing step. The processing delay of this target processing step is the current accumulated value sum minus the processing delay of the second object to be merged.

[0067] Then, the second object to be merged is set as the first object to be merged in the next round of latency accumulation calculation. The processing latency is accumulated using this new first object to be merged until all steps in the step sequence are merged into the target processing step. In the last iteration of the accumulation loop, if the sum of all remaining steps starting from the current first object to be merged still does not exceed the target processing step, then there will be no second object to be merged in the last calculation. Instead, the steps from the first object to be merged to the last step in the step sequence will be merged into the last target processing step.

[0068] Therefore, while ensuring that the data dependency order is not disrupted, as many consecutive small steps as possible are combined together, and at the same time, the processing latency of each target processing step is ensured not to exceed the target average latency, thus producing the optimal latency-balanced step partitioning result.

[0069] In one feasible embodiment, steps S40 may be followed by steps S50 to S70: Step S50: When running the optimized algorithm code, monitor the capacity occupancy ratio of each message queue and the utilization rate of each thread; It should be noted that the message queue capacity utilization rate refers to the ratio of the capacity occupied by the data processing results of the preceding thread currently stored in a message queue to its total capacity, in order to reflect the congestion or idleness of the message queue; the thread utilization rate refers to the proportion of the time that a thread is in an active execution state rather than waiting for input data (i.e., the data processing results of the preceding thread) to the total running time, in order to reflect the busyness of the thread's computing resources.

[0070] During the testing phase or after deployment in actual operation, lightweight monitoring code can be embedded in the generated optimized algorithm code. This monitoring code will periodically or during each queue operation sample the current length of each message queue and the utilization rate of each worker thread, and calculate the capacity utilization ratio by combining the current length of the message queue with its initial capacity. The utilization rate of each thread = 1 - waiting time / total time.

[0071] Step S60: Determine whether the optimized algorithm code meets the preset load balancing conditions based on the capacity occupancy ratio and utilization rate. It should be noted that the load balancing conditions are a set of threshold indicators used to determine whether the optimized algorithm code is running healthily. These conditions can be set based on the actual application scenario. For example, the load balancing conditions can be set as follows: the utilization rate of all threads is higher than the preset utilization rate threshold, and / or the difference in utilization rate of all threads does not exceed the preset difference threshold, and / or the capacity occupancy ratio of all message queues is within the preset capacity range.

[0072] When the optimized algorithm code runs, if the utilization rate of the preceding thread in a group of adjacent threads is high and the utilization rate of the following thread is low, the message queue capacity occupancy ratio between the two will inevitably be too high, leading to data accumulation and affecting the overall throughput and operational stability of the algorithm. Conversely, if the utilization rate of the preceding thread in a group of adjacent threads is low and the utilization rate of the following thread is high, the message queue capacity occupancy ratio between the two will inevitably be too low, resulting in wasted computational resources for the following thread, which will also affect the overall throughput and operational stability of the algorithm. Therefore, during code execution, monitoring data is compared with preset load balancing conditions to determine whether there is a load imbalance problem in the currently running code.

[0073] Step S70: If the optimized algorithm code does not meet the load balancing conditions, output the algorithm optimization prompt information.

[0074] If it is determined that the running status of the optimized algorithm code does not meet the load balancing conditions, an algorithm optimization prompt message will be output. This message can be text, log, or report generated based on monitoring data, used to guide further algorithm optimization. The optimization prompt message can clearly indicate the unique identifier of the thread suspected of being the bottleneck and feasible improvement suggestions.

[0075] If the optimized algorithm code meets the load balancing conditions, no further action is taken.

[0076] Therefore, by monitoring the status of the optimized algorithm code during runtime, the actual effect of the algorithm optimization can be verified, and any shortcomings in the optimization can be fed back to the user or the upper-level system, thereby enhancing the reliability and maintainability of the optimized algorithm code.

[0077] For example, to help understand the implementation flow of the algorithm optimization method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 2 , Figure 2 A simplified flowchart of an algorithm optimization method is provided, specifically: The algorithm code to be optimized is first subjected to static analysis. At this stage, the code is not run, but the control flow graph (CFG) and data dependency graph (DDG) are obtained through code analysis. Then, based on the results of static analysis, the code is divided into steps to eliminate the problem of uneven processing latency among the processing steps in the code, generating a set of target processing steps with the most average processing latency. Then, a pipeline is built according to the target processing steps obtained after division. Each target processing step is encapsulated as an independent thread, and a message queue is established between adjacent threads with direct data dependencies based on the data dependencies between steps. Finally, all threads and all queues are integrated to obtain the optimized algorithm code. The optimized algorithm code has the same function as the algorithm code to be optimized, but the data processing throughput is significantly improved by running the concurrent pipeline.

[0078] The process of dividing the steps is as follows: Figure 3 As shown, static instrumentation is performed on the code of the algorithm to be optimized. Based on the initial processing steps identified by static analysis, latency acquisition code is inserted at the beginning and end positions of each processing step. Then, the instrumented code is run to collect latency data, resulting in a latency distribution heatmap. This heatmap visually displays the differences and distribution of processing latency at each step. Next, a latency balancing decision-maker reorganizes the steps based on the latency distribution heatmap. The decision-maker can classify the steps according to the calculated target average latency. Long-latency steps (i.e., steps whose processing latency exceeds the target average latency) are decomposed using a step decomposition engine, while short-latency consecutive steps (i.e., consecutive steps whose sum of processing latency does not exceed the target average latency) are merged. The engine merges the steps to obtain a target processing step set StepSet={S1,S2...Sn}, where n represents the number of main steps and Sn represents the nth step. Then, data dependency analysis is performed on the recombined data. Based on the data dependency graph generated by static analysis, the source of the required input data for each main step in StepSet can be analyzed, thereby deriving the data structure of the input data for each step and obtaining a data structure set of the input data for the target processing steps, DataSet={D1,D2...Dn}. Finally, the analysis result is obtained: StepSet+DataSet. This set of analysis results fully defines the content and input data structure of each step after the step division.

[0079] The process of building a pipeline is as follows: Figure 4 As shown, the algorithm analysis results are obtained: After StepSet + DataSet, the loop counter is initialized to i=1, and then the loop judgment is entered: i=n+1, that is, to judge whether the number of loops exceeds the number of target processing steps. As long as it does not exceed the number of steps, the following sub-steps are executed iteratively: Initialize message queue Qi based on Di, i.e., generate a type-safe message queue Qi according to data structure Di. This queue will be used to store data waiting to be processed by step Si. Encapsulate algorithm step Si into a separate thread, i.e., encapsulate the code content of step Si into a thread. The operation of this thread is to retrieve data from queue Qi, perform the calculation of step Si, and put the result into the next queue Q(i+1). For the last step Sn, it is to output the result. Connect S(i-1) and Di, i.e., establish an inter-thread communication link to ensure that the output of the predecessor thread S(i-1) (i.e., the data written to message queue Qi) and the input of the current thread Si (i.e., the data read from message queue Qi) are completely matched in data structure. After completing the above operations, let i=i+1, enter the next loop, create queues and threads for the next step, and establish connections. When the loop ends (i.e., i=n+1), it means that all n steps have been processed. At this time, n message queues and n corresponding threads have been generated, and a complete pipeline connection has been established through queue reference passing, resulting in the optimized algorithm code.

[0080] The optimized algorithm code's runtime workflow is as follows: Figure 5 As shown in the diagram, the workflow is illustrated from two dimensions: processing steps and time sequence. Taking a code containing three message queues (Q1, Q2, and Q3) and three threads (S1, S2, and S3) as an example, in terms of processing steps, adjacent threads are connected through message queues. Q1 connects the data source and thread S1, Q2 connects thread S1 and thread S2, and Q3 connects thread S2 and thread S3. The output of S3 is directly used as the final result. In terms of time sequence, at different points in time, different stages of the pipeline are concurrently processing different data units. For example, at a certain moment, thread S1 is processing the data of the Nth task, queue Q1 temporarily stores the data of tasks N+1 to N+i, queue Q2 temporarily stores the data of the N-1th task, thread S2 is processing the data of the N-2th task, queue Q3 temporarily stores the data of the N-3th task, and thread S3 is processing the data of the N-4th task. This overlapping execution in time significantly improves the overall throughput of the algorithm.

[0081] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the algorithm optimization method of this application. Any simple transformations based on this technical concept are all within the protection scope of this application.

[0082] This application also provides an algorithm optimization device, please refer to... Figure 6 The algorithm optimization device includes: The code analysis module 10 is used to analyze the code of the algorithm to be optimized, and to obtain the initial processing steps, the data dependencies between the initial processing steps, and the processing delay of each initial processing step in the code of the algorithm to be optimized. The step reorganization module 20 is used to reorganize each initial processing step according to a preset thread number threshold and processing delay to obtain each target processing step; The thread connection module 30 is used to encapsulate each target processing step into a thread and establish a message queue between adjacent threads according to data dependencies. The message queue is used to pass processing data between adjacent threads. The code generation module 40 is used to obtain optimized algorithm code based on each thread and each message queue.

[0083] Optionally, the code analysis module 10 is also used for: Static analysis is performed on the code of the algorithm to be optimized to obtain the control flow graph and data dependency graph; The initial processing steps of the algorithm code to be optimized are determined based on the control flow graph, and the data dependencies between the initial processing steps are determined based on the data dependency graph. The processing delay of each initial processing step is obtained by running the code of the algorithm to be optimized.

[0084] Optionally, the code analysis module 10 is also used for: Insert delay acquisition code at the beginning and end of the code for each initial processing step; Run the algorithm code to be optimized, which already has latency acquisition code inserted; For each initial processing step, the start and end times of the initial processing step are recorded by the delay acquisition code, and the difference between the end time and the start time is calculated as the processing delay of the initial processing step.

[0085] Optionally, the step reorganization module 20 is also used for: The target average latency for each thread is calculated based on the preset thread count threshold and processing latency. The initial processing steps with processing latency greater than the target average latency are broken down into multiple sub-steps, wherein the processing latency of each sub-step is less than or equal to the target average latency. The sub-steps and the undivided initial processing steps are merged according to the cumulative delay to obtain each target processing step, wherein the processing delay of the target processing step is less than or equal to the target average delay.

[0086] Optionally, the step reorganization module 20 is also used for: Arrange the sub-steps and the un-decomposed initial processing steps into a step sequence according to their execution order; The first step in the step sequence is taken as the first object to be merged. The processing delay of the first object to be merged and the steps after the first object to be merged is accumulated until the accumulated delay exceeds the target average delay. The step that causes the accumulated delay to exceed the target average delay is taken as the second object to be merged. Merge the steps preceding the second object to be merged into a single target processing step; The second object to be merged is treated as the new first object to be merged. The process of accumulating the processing delay of the first object to be merged and the steps following the first object to be merged, as well as subsequent steps, is performed until all steps in the step sequence are merged into the target processing step.

[0087] Optionally, the thread connection module 30 is also used for: Determine the data structure of the output data of the preceding thread in an adjacent thread based on data dependencies; Establish a message queue between adjacent threads and define the data structure as the data structure for the data passed by the message queue.

[0088] Optionally, the algorithm optimization device further includes an optimization module (not shown), which is used for: When running the optimized algorithm code, monitor the capacity utilization ratio of each message queue and the utilization rate of each thread; Determine whether the optimized algorithm code meets the preset load balancing conditions based on the capacity occupancy ratio and utilization rate; If the optimized algorithm code does not meet the load balancing conditions, an algorithm optimization prompt message will be output.

[0089] This application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the status indication method described above.

[0090] The following is for reference. Figure 7 The diagram illustrates an electronic device suitable for implementing embodiments of this application. Figure 7 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0091] like Figure 7As shown, the electronic device may include a processing unit 1001 (e.g., a DSP processor), which can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: an input device 1007 including, for example, a microphone, an accelerometer, etc.; an output device 1008 including, for example, a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 allows the electronic device to exchange data wirelessly or via wired communication with other devices. Although electronic devices with various systems are shown in the figures, it should be understood that it is not required to implement or possess all the systems shown. It can be implemented alternatively or with more or fewer systems.

[0092] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0093] Compared with the prior art, the beneficial effects of the electronic device provided in this application embodiment are the same as the beneficial effects of the algorithm optimization method provided in the above embodiment, and other technical features in the electronic device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0094] It should be understood that the various parts disclosed in the embodiments of this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0095] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0096] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the algorithm optimization method in the above embodiments.

[0097] The computer-readable storage medium provided in this application embodiment may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0098] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0099] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the functions defined in the methods of the embodiments disclosed in this application.

[0100] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0101] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0102] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0103] The readable storage medium provided in this application embodiment is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-described algorithm optimization method. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application embodiment are the same as the beneficial effects of the algorithm optimization method provided in the above-described embodiments, and will not be repeated here.

[0104] This application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the status indication method described above. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the status indication method provided in the above embodiments, and will not be repeated here.

[0105] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. An algorithm optimization method, characterized in that, The algorithm optimization method includes: The code of the algorithm to be optimized is analyzed to obtain the initial processing steps, the data dependencies between the initial processing steps, and the processing delay of each initial processing step. Based on the preset thread number threshold and the processing delay, the initial processing steps are reorganized to obtain the target processing steps. Each of the target processing steps is encapsulated as a thread, and a message queue is established between adjacent threads according to the data dependency relationship, wherein the message queue is used to transfer processing data between the adjacent threads; Based on each of the aforementioned threads and message queues, the optimized algorithm code is obtained.

2. The algorithm optimization method as described in claim 1, characterized in that, The steps of analyzing the algorithm code to be optimized to obtain the initial processing steps, the data dependencies between the initial processing steps, and the processing delay of each initial processing step include: Static analysis is performed on the code of the algorithm to be optimized to obtain the control flow graph and data dependency graph; The initial processing steps of the algorithm code to be optimized are determined based on the control flow graph, and the data dependencies between the initial processing steps are determined based on the data dependency graph. The processing delay of each initial processing step is obtained by running the algorithm code to be optimized.

3. The algorithm optimization method as described in claim 2, characterized in that, The step of obtaining the processing delay of each initial processing step by running the algorithm code to be optimized includes: Insert delay acquisition code at the beginning and end positions of the code in each of the initial processing steps; Run the algorithm code to be optimized, which has already had the delay acquisition code inserted; For each of the initial processing steps, the start time and end time of the initial processing step are recorded by the delay acquisition code, and the difference between the end time and the start time is calculated as the processing delay of the initial processing step.

4. The algorithm optimization method as described in claim 1, characterized in that, The steps of reorganizing each initial processing step according to a preset thread number threshold and the processing delay to obtain each target processing step include: The target average latency for each thread is calculated based on the preset thread number threshold and the processing latency. The initial processing steps with processing latency greater than the target average latency are broken down into multiple sub-steps, wherein the processing latency of each sub-step is less than or equal to the target average latency. The sub-steps and the undivided initial processing steps are merged according to the accumulated delay to obtain each target processing step, wherein the processing delay of the target processing step is less than or equal to the target average delay.

5. The algorithm optimization method as described in claim 4, characterized in that, The step of merging the sub-steps with the undivided initial processing steps based on the accumulated delay to obtain each target processing step includes: The sub-steps and the undivided initial processing steps are arranged in the order of execution to form a step sequence; The first step in the sequence of steps is taken as the first object to be merged. The processing delay of the first object to be merged and the steps after the first object to be merged is accumulated until the accumulated delay exceeds the target average delay. The step that causes the accumulated delay to exceed the target average delay is taken as the second object to be merged. The steps preceding the second object to be merged are combined into a single target processing step; The second object to be merged is taken as the new first object to be merged. The step of accumulating the processing delay of the first object to be merged and the steps after the first object to be merged, as well as subsequent steps, are executed until all steps in the step sequence are merged into the target processing step.

6. The algorithm optimization method as described in claim 1, characterized in that, The step of establishing a message queue between adjacent threads based on the data dependency includes: The data structure for the output data of the preceding thread in an adjacent thread is determined based on the data dependency relationship. A message queue is established between the adjacent threads, and the data structure is defined as the data structure for the data transmitted by the message queue.

7. The algorithm optimization method as described in claim 1, characterized in that, After the step of obtaining the optimized algorithm code based on each of the threads and each of the message queues, the method further includes: When running the optimized algorithm code, monitor the capacity occupancy ratio of each message queue and the utilization rate of each thread; Based on the capacity occupancy ratio and the utilization rate, determine whether the optimized algorithm code meets the preset load balancing conditions; If the optimized algorithm code does not meet the load balancing conditions, an algorithm optimization prompt message will be output.

8. An algorithm optimization device, characterized in that, The algorithm optimization device includes: The code analysis module is used to analyze the code of the algorithm to be optimized, and to obtain the initial processing steps in the code of the algorithm to be optimized, the data dependencies between the initial processing steps, and the processing delay of the initial processing steps. The step reorganization module is used to reorganize each of the initial processing steps according to a preset thread number threshold and the processing delay to obtain each target processing step; A thread connection module is used to encapsulate each of the target processing steps into a thread, and to establish a message queue between adjacent threads according to the data dependency relationship, wherein the message queue is used to transfer processing data between the adjacent threads; The code generation module is used to obtain optimized algorithm code based on each of the aforementioned threads and message queues.

9. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the algorithm optimization method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the algorithm optimization method as described in any one of claims 1 to 7.

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