A register resource scheduling method, system, medium and product

Abstract

The application discloses a register resource scheduling method and system, a medium and a product, and applies to the technical field of processors, and comprises the following steps: determining an integer physical register required quantity and a floating-point physical register required quantity; determining an integer physical register idle quantity and a floating-point physical register idle quantity; comparing the integer physical register required quantity with the integer physical register idle quantity, and comparing the floating-point physical register required quantity with the floating-point physical register idle quantity; in the case that the idle quantity of a first type of physical register cannot satisfy the required quantity, and the idle quantity of a second type of physical register is higher than the required quantity, selecting a physical register from the second type of physical register as the first type of physical register for use; the first type of physical register is any type of physical register in the integer physical register and the floating-point physical register, and the second type is the other type. In this way, the efficiency of instruction out-of-order execution can be improved.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a register resource scheduling method, system, medium, and product. Background Technology

[0002] The RISC-V (Reduced Instruction Set Computing-V) CPU (Central Processing Unit) adopts a modular design, with integer and floating-point instruction dispatch and execution belonging to two independent subsystems. The register renaming function is also designed independently. However, in real-world applications, there are often stages where a large number of integer instructions are processed, but the number of physical registers corresponding to integer instruction renaming is limited, making it impossible to meet the renaming needs of a large number of consecutive integer instructions in a timely manner. Similarly, there are often stages where a large number of floating-point instructions are processed, but the number of physical registers corresponding to floating-point instruction renaming is limited, making it impossible to meet the renaming needs of a large number of consecutive floating-point instructions in a timely manner, thus reducing the efficiency of out-of-order execution.

[0003] It is evident that improving the efficiency of out-of-order instruction execution is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a register resource scheduling method, system, medium, and product that can improve the efficiency of out-of-order instruction execution.

[0005] In a first aspect, the present invention provides a register resource scheduling method, comprising: determining the required number of integer physical registers and the required number of floating-point physical registers; determining the number of idle integer physical registers and the number of idle floating-point physical registers; comparing the required number of integer physical registers with the number of idle integer physical registers, and comparing the required number of floating-point physical registers with the number of idle floating-point physical registers; and, when the number of idle registers of a first type cannot meet the required number, and the number of idle registers of a second type is higher than the required number, selecting a target physical register from the remaining physical registers of the second type of physical registers as the first type of physical register; wherein the first type of physical register is any one of integer physical registers and floating-point physical registers, and the second type of physical register is the other type of physical register among the integer physical registers and the floating-point physical registers.

[0006] Optionally, determine the required number of integer physical registers and the required number of floating-point physical registers, including:

[0007] The maximum number of integer instructions and the maximum number of floating-point instructions that can be executed within the first target time period are determined based on the estimated execution time of a single integer instruction and the estimated execution time of a single floating-point instruction.

[0008] The integer instructions and floating-point instructions are obtained based on the maximum number of integer instructions and the maximum number of floating-point instructions.

[0009] Conflict detection is performed on the read integer and floating-point instructions to determine the required number of integer physical registers and the required number of floating-point physical registers.

[0010] Optional, also includes:

[0011] Receive integer instruction dispatch queue feedback signal within the first preset time interval;

[0012] The number of integer instruction dispatch queue feedback signals that are at the first preset type level is counted, and the estimated execution time of a single integer instruction is determined based on the number and the first preset time interval.

[0013] The feedback signal of the integer instruction dispatch queue is a first preset type level, indicating that the integer instruction dispatch queue has completed one integer instruction issuance.

[0014] Optional, also includes:

[0015] Receive floating-point instruction dispatch queue feedback signal within the second preset time interval;

[0016] The number of floating-point instruction dispatch queue feedback signals that are at the second preset level is counted, and the estimated execution time of a single floating-point instruction is determined based on the number and the second preset time interval.

[0017] The floating-point instruction dispatch queue feedback signal is a second preset type level, indicating that the floating-point instruction dispatch queue has completed a floating-point instruction issuance.

[0018] Optionally, obtaining integer instructions and floating-point instructions based on the maximum number of integer instructions and the maximum number of floating-point instructions includes:

[0019] The instructions fetched from the instruction fetch unit are sequentially retrieved as the number of the largest integer instructions and the number of the largest floating-point instructions.

[0020] Optionally, determine the number of free integer physical registers and the number of free floating-point physical registers, including:

[0021] Determine the number of unreleased integer physical registers;

[0022] The number of free integer physical registers is determined based on the number of unreleased integer physical registers and the total number of integer physical registers.

[0023] Determine the number of unreleased floating-point physical registers;

[0024] The number of free floating-point physical registers is determined based on the number of unreleased floating-point physical registers and the total number of floating-point physical registers.

[0025] Optionally, a target physical register may be selected from the remaining physical registers of the second type of physical registers for use as the first type of physical register, including:

[0026] According to the selection ratio, a target physical register is selected from the remaining physical registers of the second type of physical registers for use as a first type of physical register.

[0027] Optional, also includes:

[0028] Monitor the changing trend of the number of idle physical registers of the first type according to a preset period, and adjust the selection ratio based on the changing trend.

[0029] Optional, also includes:

[0030] If the number of idle integer physical registers and floating-point physical registers cannot meet the demand, determine the first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within the second target time period.

[0031] Based on the first estimated release quantity, the second estimated release quantity, the required quantity of integer physical registers, the number of free integer physical registers, the required quantity of floating-point physical registers, and the number of free floating-point physical registers, free integer physical registers and floating-point physical registers are allocated.

[0032] Optionally, determining the first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within the second target time period includes:

[0033] The first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within the second target time period are determined based on the integer instruction release time and the floating-point instruction release time.

[0034] The release time of the integer instruction is determined based on the release time of the historical integer instruction, and the release time of the floating-point instruction is determined based on the release time of the historical floating-point instruction.

[0035] Optional, also includes:

[0036] During execution, the first release time of integer instructions and the second release time of floating-point instructions are monitored.

[0037] The second target time period is adjusted based on the first release time and the second release time.

[0038] Secondly, the present invention provides a register resource scheduling system, comprising:

[0039] The requirement quantity determination module is used to determine the required number of integer physical registers and the required number of floating-point physical registers;

[0040] The free quantity determination module is used to determine the number of free integer physical registers and the number of free floating-point physical registers;

[0041] The demand analysis module is used to compare the required number of integer physical registers with the number of free integer physical registers, and the required number of floating-point physical registers with the number of free floating-point physical registers.

[0042] The register partitioning module is used to select a target physical register from the remaining physical registers of the second type of physical registers as the first type of physical register when the number of free physical registers of the first type cannot meet the required number and the number of free physical registers of the second type of physical registers is higher than the required number.

[0043] Wherein, the first type of physical register is any one of the integer physical register and the floating-point physical register, and the second type of physical register is the other type of physical register among the integer physical register and the floating-point physical register.

[0044] Optional, also includes:

[0045] The release pre-analysis module is used to determine the first estimated release quantity of the integer physical registers and the second estimated release quantity of the floating-point physical registers within a second target time period when the number of idle units of both the integer physical registers and the floating-point physical registers cannot meet the required quantity.

[0046] Correspondingly, the register partitioning module is also used to allocate idle integer physical registers and floating-point physical registers based on the first estimated release quantity, the second estimated release quantity, the number of integer physical registers required, the number of idle integer physical registers, the number of floating-point physical registers required, and the number of idle floating-point physical registers.

[0047] Thirdly, the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the aforementioned register resource scheduling method.

[0048] Fourthly, the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the aforementioned register resource scheduling method.

[0049] As can be seen, the beneficial effects of the present invention are as follows: First, the required number of integer physical registers and floating-point physical registers, the number of free integer physical registers, and the number of free floating-point physical registers are determined. Then, the required number of integer physical registers and the number of free integer physical registers, as well as the required number of floating-point physical registers and the number of free floating-point physical registers, are compared. When the number of free registers of a certain type cannot meet the required number, and the number of free registers of another type is higher than the required number, a target physical register is selected from the spare physical registers of the other type for use as a physical register of the aforementioned type. In this way, different types of physical registers are scheduled according to the required number and the number of free physical registers. When a large number of instructions of a certain type are executed continuously, and there are not enough registers of the same type, other types of registers can be used for execution, which can improve the efficiency of out-of-order instruction execution. Attached Figure Description

[0050] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of an out-of-order execution architecture for a RISC-V CPU in the prior art.

[0052] Figure 2 A flowchart of a register resource scheduling method provided in an embodiment of the present invention;

[0053] Figure 3 A diagram of a RISC-V CPU out-of-order execution architecture provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of an instruction pre-analysis unit provided in an embodiment of the present invention;

[0055] Figure 5 A schematic diagram of a resource scheduling unit provided in an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of a register resource scheduling system provided in an embodiment of the present invention. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0058] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0059] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] First, the terminology involved in this invention will be explained:

[0061] CPU out-of-order execution refers to allowing instructions to be executed out of program sequence in order to fully utilize hardware resources and improve instruction-level parallelism. It executes ready instructions first, masking latency and increasing throughput.

[0062] Register resource conflicts are a type of data hazard in the CPU pipeline, including: WAW (Write-After-Write) conflicts, which refer to two instructions writing to the same register in program order, but due to out-of-order execution, the later instruction may complete the write first, resulting in an incorrect final result; WAR (Write-After-Read) conflicts, which refer to the later instruction modifying the source register of the previous instruction during out-of-order execution, causing the previous instruction to read an incorrect value; and RAW (Read-After-Write) conflicts, which refer to the situation in a pipelined processor where the current instruction needs to read a value from a register that was written to by a previous instruction.

[0063] Logical registers: Software visible (directly used in assembly code, such as x0–x31, visible registers defined by the instruction set). RISC-V has 32 integer logical registers (x0-x31) and 32 floating-point logical registers (f0-f31).

[0064] Physical registers: Used internally by the hardware and are transparent to the software. For example, there are 32 physical registers (xp0-xp31) used for renaming the integer instruction register, and 32 physical registers (fp0-fp31) used for renaming the floating-point instruction register.

[0065] See Figure 1 As shown, Figure 1 This is a schematic diagram of an out-of-order execution architecture for a RISC-V CPU in existing technology. The out-of-order execution process of a traditional RISC-V CPU includes:

[0066] The instruction fetch unit reads instructions from the I-Cache (instruction cache); the decode unit parses and decodes the read-back instructions. Depending on the instruction, integer instructions are parsed and sent to the integer instruction renaming unit, and floating-point instructions are parsed and sent to the floating-point instruction renaming unit. Register renaming is a processor microarchitecture technique used to resolve data hazards (especially write-after-write and read-after-write hazards). The renaming process maps logical register names in the instructions to physical registers. For example, the original instruction order is as follows: I1: ADD R1, R2, R3 / / Original instruction; I2: MUL R1, R4, R5 / / Subsequent instructions may be executed out of order. Both instructions need to be written to R1. To ensure that I1 and I2 execute simultaneously and to avoid the scenario where I2 finishes executing earlier and overwrites R1, the renaming is performed as follows: I1: ADD P1, P2, P3 / / P1 is a newly allocated physical register; I2: MUL P4, P5, P6 / / P1 is another newly allocated physical register. Even if I2 completes first, it won't overwrite the result of I1 (P1 and P4 are independent). When finally committed in program order, only the physical register of the last instruction will be mapped back to the architecture register R1. That is, only the value of register P4 will be written to R1. Through the above register renaming process, out-of-order execution of I1 and I2 instructions can be achieved. Note that although it's out-of-order execution, the final commit is sequential; the logical order remains unchanged, only the instruction execution speed is increased.

[0067] RISC-V employs a modular design, processing integer and floating-point instructions separately. The integer register renaming unit renames registers for integer instructions; this unit contains physical registers (xp0-xp31) and a mapping table between logical and physical registers. The floating-point register renaming unit renames registers for floating-point instructions; this unit contains physical registers (fp0-fp31) and a mapping table between logical and physical registers. The integer instruction dispatch queue and floating-point instruction dispatch queue dispatch integer / floating-point instructions, after register renaming, to the integer instruction execution unit and floating-point instruction execution unit, respectively, while also performing instruction caching (when the execution unit cannot process the instructions in time). The integer instruction execution unit performs the actual processing of integer instructions, such as addition, subtraction, shifting, and memory operations (reading and writing memory). The floating-point instruction execution unit performs the actual processing of floating-point instructions, such as addition, subtraction, shifting, and multiplication. The write-back unit is responsible for writing the results calculated by the execution unit back to the register file, writing the calculation results to the target register, and updating the processor's internal state. The reorder buffer is used to ensure that instructions, although executed out of order, can be committed (retired) in program order, maintain the consistency of the architectural state, track the state of all executing instructions, save the execution results of uncommitted instructions, and manage the release of physical registers after register renaming.

[0068] The traditional approach to implementing out-of-order execution in RISC-V CPUs primarily relies on register renaming to resolve data dependencies between instructions (WAW / WAR), thereby improving instruction parallelism and achieving out-of-order execution. However, this approach has significant drawbacks: RISC-V CPUs employ a modular design, with integer and floating-point instruction dispatch and execution belonging to two independent subsystems. The register renaming functionality is also designed independently. However, in real-world applications, there are often periods requiring large-scale integer instruction processing. The limited number of physical registers available for integer instruction renaming makes it impossible to promptly handle a large number of consecutive integer instruction renamings. If the integer physical registers are exhausted before the reordering buffer has finished releasing them, instructions must be executed sequentially. Similarly, there are often periods requiring large-scale floating-point instruction processing. Again, the limited number of physical registers available for floating-point instruction renaming makes it impossible to promptly handle a large number of consecutive floating-point instruction renamings. If the floating-point physical registers are exhausted before the reordering buffer has finished releasing them, instructions must be executed sequentially, reducing the efficiency of out-of-order execution. Meanwhile, due to the overall power consumption of the CPU, since the integer and floating-point physical registers are located inside the CPU and operate at very high frequencies (the clock speeds of mainstream high-performance CPUs are all above 2GHz), too many physical registers will greatly increase the power consumption of the RISC-V CPU. Therefore, the data in the integer / floating-point physical registers is also very limited in the design of the RISC-V CPU. To address this, this invention provides a register resource scheduling scheme that improves the utilization of CPU physical resources, increases the efficiency of out-of-order instruction execution, and enhances the performance of out-of-order execution of the RISC-V CPU without increasing the power consumption of the RISC-V CPU.

[0069] Next, a register resource scheduling method provided by an embodiment of the present invention will be described in detail. Figure 2 This is a flowchart of a register resource scheduling method provided in an embodiment of the present invention. The register resource scheduling method includes:

[0070] Step S11: Determine the required number of integer physical registers and the required number of floating-point physical registers.

[0071] The number of integer physical registers required refers to the number of integer physical registers needed, which are registers used to process integer instructions. The number of floating-point physical registers required refers to the number of floating-point physical registers needed, which are registers used to process floating-point instructions.

[0072] In this embodiment, determining the required number of integer physical registers and the required number of floating-point physical registers may include: determining the maximum number of integer instructions and the maximum number of floating-point instructions that can be executed within a first target time period based on the estimated execution time of a single integer instruction and the estimated execution time of a single floating-point instruction; obtaining integer instructions and floating-point instructions based on the maximum number of integer instructions and the maximum number of floating-point instructions; and performing conflict detection on the read integer instructions and floating-point instructions to determine the required number of integer physical registers and the required number of floating-point physical registers.

[0073] This embodiment can calculate the number of integer instructions that are satisfied. Estimated execution time of a single integer instruction + number of floating-point instructions The estimated execution time of a single floating-point instruction is equal to the maximum of the number of integer instructions and the number of floating-point instructions within the first target time period, yielding the maximum number of integer instructions and the maximum number of floating-point instructions. The first target time period is adjustable; its initial value can be a default value, such as 1ms. If the obtained integer and floating-point instructions cannot be executed normally, the time period can be increased; otherwise, it can be decreased or left unadjusted. "Cannot be executed normally" refers to a situation where there are insufficient physical registers during execution. That is, after registers are allocated according to the scheme of this invention, a situation arises where there are insufficient registers during execution.

[0074] This embodiment can also receive integer instruction dispatch queue feedback signals within a first preset time interval; count the number of integer instruction dispatch queue feedback signals that are at a first preset type level, and determine the estimated execution time of a single integer instruction based on the number and the first preset time interval; wherein, the integer instruction dispatch queue feedback signal being at a first preset type level indicates that the integer instruction dispatch queue has completed one integer instruction transmission.

[0075] When the integer instruction dispatch queue completes an instruction dispatch (i.e., the instruction is dispatched to the execution unit), the integer instruction dispatch queue feedback signal is pulled high. The number of times this signal is pulled high within a first preset time interval is counted. Based on the first preset time interval and the number of pulls, the average execution time of a single integer instruction is calculated, and the estimated execution time of a single integer instruction is obtained.

[0076] This embodiment can also receive floating-point instruction dispatch queue feedback signals within a second preset time interval; count the number of floating-point instruction dispatch queue feedback signals that are at a second preset level, and determine the estimated execution time of a single floating-point instruction based on the number and the second preset time interval; wherein, the floating-point instruction dispatch queue feedback signal being at a second preset level indicates that the floating-point instruction dispatch queue has completed one floating-point instruction transmission.

[0077] When the floating-point instruction dispatch queue completes an instruction dispatch (i.e., dispatches the instruction to the execution unit), the floating-point instruction dispatch queue feedback signal is pulled high. The number of times this signal is pulled high within a second preset time interval is counted. Based on the second preset time interval and the number of times the signal is pulled high, the average execution time of a single floating-point instruction is calculated, and the estimated execution time of a single integer instruction is obtained.

[0078] The first preset type level and the second preset type level are used to distinguish between the integer instruction dispatch queue feedback signal and the floating-point instruction dispatch queue feedback signal, and are not used to represent different types of levels; both can be high. The first preset time interval and the second preset time interval can have the same value or different values.

[0079] The process of obtaining integer instructions and floating-point instructions based on the maximum number of integer instructions and the maximum number of floating-point instructions may include: sequentially obtaining the number of integer instructions and the number of floating-point instructions fetched by the instruction fetch unit in the order of the maximum number of integer instructions.

[0080] This embodiment can distinguish and identify integer instructions and floating-point instructions retrieved by the instruction fetch unit, and save them. It can also obtain the number of integer instructions and the number of floating-point instructions that are the largest number of instructions retrieved by the instruction fetch unit in the order of the instructions.

[0081] Furthermore, conflict detection is performed on the acquired integer and floating-point instructions to obtain the required number of integer physical registers and the required number of floating-point physical registers. Conflict detection, specifically register resource conflict detection, can include conflicts of types such as write-after-read and write-after-write.

[0082] Step S12: Determine the number of free integer physical registers and the number of free floating-point physical registers.

[0083] Among them, the number of free integer physical registers is the number of free integer physical registers, and the number of free floating-point physical registers is the number of free floating-point registers.

[0084] This embodiment can determine the number of unreleased integer physical registers; and determine the number of free integer physical registers based on the number of unreleased integer physical registers and the total number of integer physical registers.

[0085] This embodiment can determine the number of integer physical registers that have not been released by the reordering buffer, i.e., the number of unreleased registers. The total number minus the number of unreleased registers gives the number of free integer physical registers.

[0086] This embodiment can determine the number of unreleased floating-point physical registers; and determine the number of free floating-point physical registers based on the number of unreleased floating-point physical registers and the total number of floating-point physical registers.

[0087] This embodiment can determine the number of floating-point physical registers that have not been released by the reordering buffer, that is, the number of unreleased registers. The total number minus the number of unreleased registers gives the number of free floating-point physical registers.

[0088] Step S13: Compare the number of integer physical registers required with the number of integer physical registers available, and the number of floating-point physical registers required with the number of floating-point physical registers available.

[0089] That is, in this embodiment of the invention, the required number of integer physical registers is compared with the number of free integer physical registers to determine whether the number of free registers meets the requirements, and the required number of floating-point physical registers is compared with the number of free floating-point physical registers to determine whether the number of free registers meets the requirements.

[0090] In this embodiment, if the number of free integer physical registers is greater than or equal to the number of required integer physical registers, and the number of free floating-point physical registers is greater than or equal to the number of required floating-point physical registers, then no register adjustment is required.

[0091] Step S14: If the number of free physical registers of the first type cannot meet the required number, and the number of free physical registers of the second type is higher than the required number, select a target physical register from the remaining physical registers of the second type as the first type of physical register; wherein, the first type of physical register is any one of integer physical registers and floating-point physical registers, and the second type of physical register is another type of physical register between the integer physical registers and the floating-point physical registers.

[0092] In other words, if the number of free integer physical registers is greater than the required number of integer physical registers, and the number of free floating-point physical registers is less than the required number of floating-point physical registers, then a physical register is selected from the remaining integer physical registers for use as a floating-point physical register, i.e., for processing floating-point instructions. Conversely, if the number of free floating-point physical registers is greater than the required number of floating-point physical registers, and the number of free integer physical registers is less than the required number of integer physical registers, then a physical register is selected from the remaining floating-point physical registers for use as an integer physical register, i.e., for processing integer instructions. The number of remaining physical registers is the number of free registers minus the required number.

[0093] In this embodiment, selecting a target physical register from the remaining physical registers of the second type of physical registers as a first type of physical register may include: selecting a target physical register from the remaining physical registers of the second type of physical registers as a first type of physical register according to the selection ratio.

[0094] In other words, the embodiments of the present invention can set a selection ratio, that is, select a certain proportion of physical registers from the remaining physical registers to obtain the target physical register. For example, setting it to 50% is because the previous requirements for physical registers were estimated and may not be very accurate. In this way, the processing requirements of the corresponding type of instruction can be guaranteed as much as possible.

[0095] This embodiment can monitor the changing trend of the number of idle physical registers of the first type according to a preset period, and adjust the selection ratio based on the changing trend.

[0096] This embodiment can obtain the number of free physical registers of the first type according to a preset period. The number of free physical registers of the first type can be collected multiple times within the period to obtain the changing trend within the period. If the changing trend of the number of free registers is decreasing, the selection ratio is increased; if the changing trend of the number of free registers is increasing, the selection ratio is decreased.

[0097] This embodiment can also determine the first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within a second target time period when the number of idle integer physical registers and the number of floating-point physical registers cannot meet the demand. Based on the first estimated number of releases, the second estimated number of releases, the demand for integer physical registers, the number of idle integer physical registers, the demand for floating-point physical registers, and the number of idle floating-point physical registers, idle integer physical registers and floating-point physical registers are allocated.

[0098] In other words, the number of idle integer physical registers and floating-point physical registers is less than the required number. The estimated number of integer physical registers and floating-point physical registers to be released during the second target time period can be determined. The second target time period is shorter than the first target time period.

[0099] In this embodiment of the invention, determining the first estimated number of integer physical registers released and the second estimated number of floating-point physical registers released within a second target time period may include: determining the first estimated number of integer physical registers released and the second estimated number of floating-point physical registers released within the second target time period based on integer instruction release time and floating-point instruction release time; wherein, the integer instruction release time is determined based on the release time of historical integer instructions, and the floating-point instruction release time is determined based on the release time of historical floating-point instructions.

[0100] In this embodiment, the integer instruction release time is the average of the release times of multiple historical integer instructions, which is the estimated release time of a single integer instruction. The floating-point instruction release time is the average of the release times of multiple historical floating-point instructions, which is the estimated release time of a single floating-point instruction.

[0101] Determine the time to release integer instructions Integer instruction release quantity + floating-point instruction release time The number of floating-point instructions released equals the maximum number of integer instructions released within the second target time period and the maximum number of floating-point instructions released. Calculating the maximum value avoids frequent adjustments to the second target time period. (Maximum number of integer instructions released...) The number of registers occupied by a single integer instruction can be used to obtain the first estimated number of registers to be freed, and the maximum number of registers to be freed for floating-point instructions. The number of registers used by a single floating-point instruction can be used to obtain the second estimated number of registers released. The number of registers used by a single integer instruction can be determined based on the number of registers used by various integer instructions, such as by taking the average (which is an integer) or the mode. The number of registers used by a single floating-point instruction can be determined based on the number of registers used by various floating-point instructions, such as by taking the average (which is an integer) or the mode.

[0102] Furthermore, embodiments of the present invention can also monitor the first release time of integer instructions and the second release time of floating-point instructions during execution; and adjust the second target time period based on the first release time and the second release time.

[0103] The first release time can be the release time obtained by monitoring a single integer instruction, or the average release time obtained by monitoring multiple integer instructions. The second release time can be the release time obtained by monitoring a single floating-point instruction, or the average release time obtained by monitoring multiple floating-point instructions.

[0104] If the first release time is greater than the integer instruction release time and the second release time is greater than the floating-point instruction release time, then the second target time period is shortened, and the integer instruction release time and floating-point instruction release time can also be increased. If the first release time is less than the integer instruction release time and the second release time is less than the floating-point instruction release time, then the second target time period is increased, and the integer instruction release time and floating-point instruction release time can also be decreased. Otherwise, no adjustment is needed.

[0105] Based on the first estimated release quantity, the second estimated release quantity, the required quantity of integer physical registers, the number of free integer physical registers, the required quantity of floating-point physical registers, and the number of free floating-point physical registers, free integer physical registers and floating-point physical registers are allocated.

[0106] If the sum of the first estimated release quantity and the number of free integer physical registers is greater than the required number of integer physical registers, and the sum of the second estimated release quantity and the number of free floating-point physical registers is less than the required number of floating-point physical registers, then integer physical registers can be selected from the expected surplus integer physical registers as temporary floating-point physical registers according to the selection ratio. The changing trend of the number of free integer physical registers can be monitored at a preset period, and the selection ratio can be adjusted based on the changing trend. The expected surplus integer physical register quantity is the sum of the first estimated release quantity and the number of free integer physical registers minus the required number of integer physical registers. If the sum of the first estimated release quantity and the number of free integer physical registers is less than the required number of integer physical registers, and the sum of the second estimated release quantity and the number of free floating-point physical registers is greater than the required number of floating-point physical registers, then floating-point physical registers can be selected from the expected surplus floating-point physical registers as temporary integer physical registers according to the selection ratio. The changing trend of the number of free floating-point physical registers can be monitored at a preset period, and the selection ratio can be adjusted based on the changing trend. The expected surplus floating-point physical register quantity is the sum of the second estimated release quantity and the number of free floating-point physical registers minus the required number of floating-point physical registers.

[0107] As can be seen, the embodiments of the present invention first determine the required number of integer physical registers and floating-point physical registers, as well as the number of idle integer physical registers and floating-point physical registers. Then, they compare the required number of integer physical registers with the number of idle integer physical registers, and the required number of floating-point physical registers with the number of idle floating-point physical registers. If the number of idle registers of a certain type cannot meet the required number, and the number of idle registers of another type is higher than the required number, a target physical register is selected from the spare physical registers of the other type for use as the physical register of the aforementioned type. In this way, different types of physical registers are scheduled according to the required number and the number of idle registers. When a large number of instructions of a certain type are executed continuously, if there are not enough registers of the same type, other types of registers can be used for execution, which can improve the efficiency of out-of-order instruction execution.

[0108] Further, see Figure 3 As shown, Figure 3This invention provides a RISC-V CPU out-of-order execution architecture diagram, applying the register resource scheduling method provided by this invention. It adds an instruction pre-analysis unit, a resource scheduling unit, a release pre-analysis unit, and corresponding operation flows. Simultaneously, it optimizes the functions of the integer instruction renaming unit and the floating-point instruction renaming unit. By predicting the expected number of integer and floating-point instructions within a certain time period and comprehensively comparing and predicting this with idle integer / floating-point physical registers and expected-to-be-released physical registers, it achieves dynamic comprehensive scheduling and management of integer and floating-point physical registers within the integer and floating-point instruction renaming units. This maximizes the fulfillment of integer instruction requirements for integer physical registers and floating-point instruction requirements for floating-point physical registers, avoiding the phenomenon of insufficient physical registers leading to out-of-order execution within a certain time period, thereby improving the performance of RISC-V CPU out-of-order execution.

[0109] See Figure 4 As shown, Figure 4 This is a schematic diagram of an instruction pre-analysis unit provided in an embodiment of the present invention. The instruction pre-analysis unit performs pre-analysis of the instructions fetched from the instruction fetch unit. Based on the estimated execution time of the instructions, it obtains the number of instructions to be sent to the integer instruction dispatch queue and the floating-point instruction dispatch queue within the time period T1 (i.e., the aforementioned first target time period), and sends this number to the resource scheduling unit. It includes an instruction execution time estimation module, an instruction identification module, an instruction quantity determination module, and an estimated time adjustment module.

[0110] The instruction execution time estimation module receives feedback signals from the integer instruction dispatch queue and the floating-point instruction dispatch queue. When the integer instruction dispatch queue completes an instruction dispatch (i.e., dispatches the instruction to the execution unit), it pulls the integer_instruction_send_end (i.e., the integer instruction dispatch queue feedback signal) high. After receiving this signal, the instruction execution time estimation module pulls the integer instruction dispatch queue low. The module then calculates the time interval between the two highs of this signal to determine the average execution time of an integer instruction under the current RISC-V CPU operating state. For greater accuracy, the total time interval T_PERIOD1 (i.e., the aforementioned first preset time interval) between the CNT1 highs of the integer_instruction_send_end signal can be set to obtain the total execution time of (CNT1 - 1) integer instructions. Therefore, under the current RISC-V CPU operating state, the estimated execution time of a single integer instruction is integer_instruction_execution_time = T_PERIOD1 / (CNT1 - 1). The execution time estimation can be updated periodically for more accurate evaluation.

[0111] Similarly, when the floating-point instruction dispatch queue completes an instruction dispatch (i.e., dispatches the instruction to the execution unit), it pulls `float_instruction_send_end` high (the aforementioned floating-point instruction dispatch queue feedback signal). Upon receiving this signal, the integer instruction dispatch queue pulls the signal low. The instruction execution time prediction module then calculates the time interval between the two highs of this signal, thus determining the average execution time of a floating-point instruction under the current RISC-V CPU operating state. For greater accuracy, the total time interval between the `float_instruction_send_end` signal highs (CNT2 times) can be set to `T_PERIOD2` (the aforementioned second preset time interval), yielding the total execution time of (CNT2 - 1) floating-point instructions. Therefore, under the current RISC-V CPU operating state, the estimated execution time of a single floating-point instruction is `float_instruction_execution_time = T_PERIOD2 / (CNT2 - 1)`. The execution time estimate can be updated periodically for more accurate evaluation.

[0112] The instruction recognition module is used to distinguish between integer instructions and floating-point instructions received from the instruction fetch unit. According to the opcode field in the RISC-V instruction, which is located in the lower 7 bits of the instruction, i.e. [6:0] of the RISC-V instruction, the opcode of the integer instruction is binary 0110011 / 0010011 / 1100011, while the opcode of the floating-point instruction is 1010011.

[0113] The instruction count determination module determines the maximum number of integer instructions and the maximum number of floating-point instructions within the time period T1. T_integer_instruction_cnt and T_float_instruction_cnt represent the number of integer instructions and the number of floating-point instructions, respectively. Calculate the maximum value of T_integer_instruction_cnt and T_float_instruction_cnt that makes the following equation true:

[0114] T_integer_instruction_cnt integer_instruction_execution_time + T_float_instruction_cnt float_instruction_execution_time = T1.

[0115] This ensures efficient out-of-order execution of T_integer_instruction_cnt integer instructions (maximum number of integer instructions) and T_float_instruction_cnt floating-point instructions (maximum number of floating-point instructions) within the T1 time period. Therefore, subsequent adjustments to T1 will modify these two variables. The first T_integer_instruction_cnt integer instructions and the first T_float_instruction_cnt floating-point instructions are selected from the read-back instructions to guarantee efficient out-of-order execution, and then this process is repeated sequentially.

[0116] The estimated time adjustment module is used to adjust the value of the time period T1. T1 initially uses a default value, such as T1 = 1ms. During system execution, this submodule receives feedback signals from the resource scheduling unit. If the resource scheduling unit can normally satisfy the execution of integer and floating-point instructions within the T1 time period, the value of T1 is increased by a step (increment size), which can be 10%. Conversely, if the resource scheduling unit cannot satisfy the normal execution of integer and floating-point instructions within the T1 time period, the value of T1 is decreased by a step (decrease size), which can be 10%. This process is a continuous feedback adjustment. The purpose of this adjustment is to ensure the normal operation of the resource scheduling unit and to ensure that integer and floating-point instructions can be executed completely out of order within the T1 time period.

[0117] See Figure 5 As shown, Figure 5 This is a schematic diagram of a resource scheduling unit provided in an embodiment of the present invention. The resource scheduling unit receives relevant signals from the instruction pre-analysis unit and releases the pre-analysis unit, and performs comprehensive scheduling and management of integer physical registers and floating-point physical registers in the RISC-V CPU. This breaks through the traditional approach where integer physical registers are only allocated to integer instructions for register renaming, and floating-point physical registers are only allocated to floating-point instructions for register renaming. It achieves comprehensive and unified scheduling and management of integer and floating-point physical registers to ensure out-of-order instruction execution, improve the efficiency of out-of-order execution in the RISC-V CPU, and enhance out-of-order execution performance. The unit includes an integer physical register demand statistics module, an integer physical register inventory statistics module, a floating-point physical register demand statistics module, a floating-point physical register inventory statistics module, a physical register overall demand analysis module, and a physical register partitioning and reclamation monitoring module.

[0118] The integer physical register requirement statistics module is used to calculate the number of integer instructions to be processed within the time period T1, T_integer_instruction_cnt, output by the instruction pre-analysis unit. It performs instruction dependency checks on these T_integer_instruction_cnt instructions, specifically checking for WAW and WAR conflicts, and determines the number of physical registers required to resolve these conflicts, denoted as T_integer_instruction_physical_register_cnt. For example, if the original instruction order is as follows: I1: ADD R1, R2, R3 / / Original instructions; I2: MUL R1, R4, R5 / / Subsequent instructions may be executed out of order. To resolve WAW (write-after-write) conflicts, the registers need to be renamed as follows: I1: ADD P1, P2, P3 / / P1 is a newly allocated physical register; I2: MUL P4, P5, P6 / / P1 is another newly allocated physical register. To resolve the WAW conflict between the two instructions and achieve parallel execution of the two instructions, the required number of physical registers is P1-P6, a total of 6.

[0119] The integer physical register stock statistics module is used to count the number of unoccupied integer physical registers in the current RISC-V CPU system, i.e., the number of free integer physical registers. For example, if the total number of physical registers in a RISC-V CPU is 32, and before the current statistics time, 10 physical registers were occupied during integer instruction renaming and were not released by the reordering buffer, meaning the integer instructions occupying these 10 physical registers did not complete the full instruction pipeline processing, then at the statistics time, the number of unoccupied integer physical registers is 32 - 10 = 22, denoted as T_integer_instruction_physical_register_stock_cnt.

[0120] The floating-point physical register requirement statistics module is used to determine the number of floating-point instructions to be processed within the T1 time period output by the instruction pre-analysis unit, T_float_instruction_cnt. It then performs instruction dependency checks on the T_float_instruction_cnt floating-point instructions to be processed, i.e., checks for WAW and WAR conflicts, and obtains the number of physical registers required to resolve these conflicts, T_float_instruction_physical_register_cnt.

[0121] The floating-point physical register stock statistics module is used to count the number of unoccupied floating-point physical registers in the current RISC-V CPU system, i.e., the number of free floating-point physical registers. For example, if a RISC-V CPU has a total of 32 floating-point registers, and before the current statistics time, 20 floating-point physical registers were occupied during instruction renaming and not released by the reordering buffer, meaning the floating-point instructions occupying these 20 registers did not complete the full instruction pipeline processing, then at the statistics time, the number of available floating-point physical registers = 32 - 20 = 12. This is denoted as T_float_instruction_physical_register_stock_cnt.

[0122] The overall physical register requirement analysis module is used to perform an overall analysis of the physical register requirement quantity T_integer_instruction_physical_register_cnt for integer instructions, the number of physical registers in stock for integer instructions T_integer_instruction_physical_register_stock_cnt, the physical register requirement quantity T_float_instruction_physical_register_cnt for floating-point instructions, and the number of physical registers in stock for floating-point instructions T_float_instruction_physical_register_stock_cnt during the T1 time period, and creates an analysis table as shown in Table 1.

[0123] Table 1

[0124]

[0125] The physical register partitioning, recycling, and monitoring module is used to dynamically partition, reclaim, and monitor integer physical registers and floating-point physical registers based on the analysis table created by the overall physical register requirement analysis module.

[0126] In Scenario 1 mode: The functions of the integer physical registers and floating-point physical registers remain unchanged; that is, the integer physical registers are used for register renaming for integer instructions, and the floating-point registers are used for register renaming for floating-point instructions.

[0127] In Scenario 2 mode: A portion of the floating-point physical registers are temporarily adjusted for use as integer physical registers. From the remaining floating-point physical registers (T_float_instruction_physical_register_stock_cnt - T_float_instruction_physical_register_cnt), an initial proportion of 50% is selected for use as integer physical registers. For example, if the remaining floating-point physical registers are 20, then 10 are selected for use as integer physical registers. That is, integer instruction renaming can use these 10 floating-point physical registers, plus the existing integer physical registers, as temporarily available integer physical registers during time period T1. The reason for setting the initial adjustment proportion to 50% is that the previous requirements for physical registers were estimated and not necessarily 100% accurate. Therefore, this embodiment of the invention designs a dynamic allocation and monitoring mechanism for the temporary allocation of physical registers. In this scenario, during instruction execution, if the value of T_integer_instruction_physical_register_stock_cnt is found to be decreasing, the allocation proportion of idle floating-point physical registers should be further increased, such as to 70%. Continuous monitoring revealed that the value of T_integer_instruction_physical_register_stock_cnt was increasing. Therefore, the allocation ratio of idle floating-point physical registers was dynamically reduced. For example, reducing it to 60% is equivalent to reclaiming another 10% of idle physical registers, achieving dynamic adjustment. The reason for not setting an initial ratio of 100% is to avoid situations where the estimated demand for floating-point physical registers is not 100% accurate, which could lead to unreliable out-of-order execution of floating-point instructions.

[0128] In Scenario 3: Some integer physical registers are temporarily used as floating-point physical registers. An initial proportion of 50% of the remaining integer physical register space (T_integer_instruction_physical_register_stock_cnt - T_integer_instruction_physical_register_cnt) is selected for use as floating-point physical registers. For example, if the remaining integer physical register space is 12, then 6 are selected as floating-point physical registers. This means that for floating-point instruction renaming, these 6 integer physical registers, plus the existing floating-point physical register space, can be used as temporarily available floating-point physical registers. The reason for setting an initial adjustment proportion of 50% is that the previous requirements for physical registers were estimated and not necessarily 100% accurate. Therefore, a dynamic allocation and monitoring mechanism is designed for the temporary allocation of physical registers. In this scenario, if the value of T_float_instruction_physical_register_stock_cnt is found to be decreasing during the execution of the instruction corresponding to time period T1, then the allocation proportion of idle integer physical registers is further increased, such as to 80%. Continuous monitoring revealed that the value of T_float_instruction_physical_register_stock_cnt was increasing. Therefore, the allocation ratio of free integer physical registers was dynamically reduced. For example, reducing it to 60% is equivalent to reclaiming another 20% of free physical registers, achieving dynamic adjustment. The reason for not setting an initial ratio of 100% is to avoid situations where the estimated demand for integer physical registers is not 100% accurate, which could lead to unreliable out-of-order execution of integer instructions.

[0129] In scenario 4 mode, the number of physical registers required for integer instructions and the data of physical registers required for floating-point instructions do not meet the requirements. At this time, the results of the release pre-analysis unit (the results are the integer physical registers and floating-point physical registers potentially released within the T2 segment (i.e., the aforementioned second target time period)) are used to comprehensively manage and schedule the physical registers. For example, if the number of integer physical registers potentially released within the T2 segment is RELEASE_CNT1 (i.e., the first estimated release quantity), and the number of floating-point physical registers potentially released within the T2 segment is RELEASE_CNT2 (i.e., the second estimated release quantity), if T_integer_instruction_physical_register_stock_cnt + RELEASE_CNT1 > T_integer_instruction_physical_register_cnt, and T_float_instruction_physical_register_stock_cnt + RELEASE_CNT2 < T_float_instruction_physical_register_cnt, then some integer physical registers can be adjusted to be used as temporary floating-point physical registers, and the initial number of adjustments is expected to be 50% of the remaining margin, that is, (T_integer_instruction_physical_register_stock_cnt + RELEASE_CNT1 - T_integer_instruction_physical_register_cnt) 50%, and as described in Scenarios 2 and 3 above, this adjustment ratio is also dynamically monitored and recycled. The control process is similar to the previous one and will not be elaborated here. If T_float_instruction_physical_register_stock_cnt + RELEASE_CNT2 > T_float_instruction_physical_register_cnt, and T_integer_instruction_physical_register_stock_cnt + RELEASE_CNT1 < T_integer_instruction_physical_register_cnt, then some floating-point physical registers can be adjusted to be used as temporary integer physical registers. The initial number of adjustments is expected to be 50% of the margin, that is, (T_float_instruction_physical_register_stock_cnt + RELEASE_CNT2 - T_float_instruction_physical_register_cnt) 50%, and as described in Scenarios 2 and 3 above, this adjustment ratio is also dynamically monitored and recycled. The control process is similar to the previous one and will not be elaborated here. At the same time, it is worth noting that the results of the release pre-analysis unit are also dynamically and real-time received. Therefore, the expected margin in the above description is also a dynamic calculation process.

[0130] The release pre-analysis unit is used to estimate the number of integer physical registers and floating-point physical registers to be released during the T2 period, and obtain RELEASE_CNT1 and RELEASE_CNT2 respectively. Its calculation process is based on the average release time of integer instructions T_integer_release (this time is the average of the release times of the first N integer instructions) and the average release time of floating-point instructions T_float_release (this time is the average of the release times of the first N floating-point instructions) during the T2 period. According to the instruction order in the reorder buffer, the following formula is used: T_integer_release Number of integer instruction releases + T_float_release Number of floating-point instruction releases = T2, to determine the maximum number of integer instruction releases and the maximum number of floating-point instruction releases that make this equation hold, and then obtain RELEASE_CNT1 and RELEASE_CNT2.

[0131] In this embodiment, a dynamic feedback mechanism is designed for parameter T2. The initial value of T2 adopts a default value, such as 100ns, etc. Then, in the scenario 4 mode, if the real integer physical instruction release time > T_integer_release and the real floating-point instruction release time > T_float_release, then T2 is shortened, and T_integer_release and T_float_release are increased. If the real integer instruction release time < T_integer_release and the real floating-point instruction release time < T_float_release, then T2 is increased, and T_integer_release and T_float_release are decreased. The purpose is to dynamically adjust the physical registers in the scenario 4 mode as accurately as possible on the basis of more accurate RELEASE_CNT1 and RELEASE_CNT2 (including adjusting integer physical registers to temporary floating-point registers and temporarily adjusting floating-point registers to temporary integer physical registers). Because the instructions are executed out of order but committed in order. After the instructions are executed out of order, they enter the reorder buffer and wait for the real execution to complete. The time in between is the release time.

[0132] In this way, by adding an instruction pre-analysis unit, a resource scheduling unit, a release pre-analysis unit and corresponding operation processes, and at the same time optimizing the functions of the integer instruction renaming unit and the floating-point instruction renaming unit, by predicting the expected number of instructions of integer instructions and floating-point instructions within the T1 time period and comprehensively comparing and predicting with the idle integer physical registers / floating-point physical registers and the expected released physical registers, the dynamic comprehensive scheduling and management of integer physical registers and floating-point physical registers in the integer instruction renaming unit and the floating-point instruction renaming unit are realized. Furthermore, it maximally ensures the demand of integer instructions for integer physical registers, meets the demand of floating-point instructions for floating-point physical registers, avoids the phenomenon that out-of-order execution cannot be performed within a certain time period due to insufficient physical registers in the traditional solution, and thus improves the out-of-order execution performance of the RISC-V CPU.

[0133] In this embodiment of the invention, each unit and module can be implemented in hardware, providing a hardware design scheme to optimize the out-of-order execution performance of RISC-V CPUs. It achieves dynamic integrated scheduling, reclamation, and management of integer and floating-point physical registers within the RISC-V CPU in the integer and floating-point instruction renaming units, breaking through the barriers of traditional schemes, improving the utilization rate of physical registers, greatly ensuring the efficiency of RISC-V out-of-order execution, and improving the execution performance of out-of-order instructions. It implements the prediction of the expected number of physical registers required by integer and floating-point instructions and designs a dynamic feedback mechanism to dynamically adjust the estimated time T1 to ensure the normal operation of the resource scheduling unit and guarantee that integer and floating-point instructions can be completely executed out of order within the T1 time period. It implements the instruction release prediction function design, maximizing the integrated scheduling function of physical registers, improving the overall utilization rate of physical registers, improving the utilization rate of internal CPU hardware resources, improving the efficiency of out-of-order execution of integer and floating-point instructions, and improving the overall performance of RISC-V CPU out-of-order execution.

[0134] See Figure 6 As shown, Figure 6 A schematic diagram of a register resource scheduling system provided in an embodiment of the present invention includes:

[0135] The requirement quantity determination module 11 is used to determine the required number of integer physical registers and the required number of floating-point physical registers;

[0136] The idle quantity determination module 12 is used to determine the number of idle integer physical registers and the number of idle floating-point physical registers;

[0137] The demand analysis module 13 is used to compare the required number of integer physical registers with the number of free integer physical registers, and the required number of floating-point physical registers with the number of free floating-point physical registers.

[0138] The register partitioning module 14 is used to select a target physical register from the remaining physical registers of the second type of physical registers as the first type of physical register when the number of free physical registers of the first type cannot meet the required number and the number of free physical registers of the second type of physical registers is higher than the required number.

[0139] Wherein, the first type of physical register is any one of the integer physical register and the floating-point physical register, and the second type of physical register is the other type of physical register among the integer physical register and the floating-point physical register.

[0140] The system further includes: a release pre-analysis module, used to determine a first estimated release quantity of the integer physical register and a second estimated release quantity of the floating-point physical register within a second target time period when the number of idle units of both the integer physical register and the floating-point physical register cannot meet the required quantity;

[0141] Correspondingly, the register partitioning module is also used to allocate idle integer physical registers and floating-point physical registers based on the first estimated release quantity, the second estimated release quantity, the number of integer physical registers required, the number of idle integer physical registers, the number of floating-point physical registers required, and the number of idle floating-point physical registers.

[0142] The register partitioning module can be a sub-module within the physical register partitioning and recycling monitoring module. The release pre-analysis module is the aforementioned release pre-analysis unit. The demand analysis module is the aforementioned overall physical register demand analysis module. The demand quantity determination module can include the aforementioned floating-point physical register demand statistics module and integer physical register demand statistics module, and the free quantity determination module can include the aforementioned integer physical register inventory statistics module and floating-point physical register inventory statistics module.

[0143] As can be seen, the embodiments of the present invention first determine the required number of integer physical registers and floating-point physical registers, as well as the number of idle integer physical registers and floating-point physical registers. Then, they compare the required number of integer physical registers with the number of idle integer physical registers, and the required number of floating-point physical registers with the number of idle floating-point physical registers. If the number of idle registers of a certain type cannot meet the required number, and the number of idle registers of another type is higher than the required number, a target physical register is selected from the spare physical registers of the other type for use as the physical register of the aforementioned type. In this way, different types of physical registers are scheduled according to the required number and the number of idle registers. When a large number of instructions of a certain type are executed continuously, if there are not enough registers of the same type, other types of registers can be used for execution, which can improve the efficiency of out-of-order instruction execution.

[0144] Figure 6 For a description of the features in the corresponding embodiments, please refer to Figure 2 The relevant descriptions of the corresponding embodiments will not be repeated here.

[0145] It is understood that if the register resource scheduling method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, and other media capable of storing program code.

[0146] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the register resource scheduling method described above.

[0147] Furthermore, embodiments of the present invention provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the aforementioned register resource scheduling method.

[0148] The foregoing has provided a detailed description of a register resource scheduling method, system, medium, and product provided by embodiments of the present invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0149] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0150] The foregoing has provided a detailed description of the register resource scheduling method, system, medium, and product provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A register resource scheduling method, characterized in that, include: Determine the required number of integer physical registers and the required number of floating-point physical registers; Determine the number of free integer physical registers and the number of free floating-point physical registers; Compare the required number of integer physical registers with the number of free integer physical registers, and compare the required number of floating-point physical registers with the number of free floating-point physical registers; If the number of free physical registers of the first type cannot meet the required number, and the number of free physical registers of the second type is higher than the required number, a target physical register shall be selected from the remaining physical registers of the second type as the first type of physical register. Wherein, the first type of physical register is any one of the integer physical register and the floating-point physical register, and the second type of physical register is the other type of physical register among the integer physical register and the floating-point physical register; Determining the required number of integer physical registers and floating-point physical registers includes: determining the maximum number of integer instructions and the maximum number of floating-point instructions that can be executed within a first target time period based on the estimated execution time of a single integer instruction and the estimated execution time of a single floating-point instruction; obtaining integer instructions and floating-point instructions based on the maximum number of integer instructions and the maximum number of floating-point instructions; and performing conflict detection on the read integer instructions and floating-point instructions to determine the required number of integer physical registers and the required number of floating-point physical registers; wherein, the estimated execution time of a single instruction is related to the time interval between issuing the instruction to the execution unit.

2. The register resource scheduling method according to claim 1, characterized in that, Also includes: Receive integer instruction dispatch queue feedback signal within the first preset time interval; The number of integer instruction dispatch queue feedback signals that are at the first preset type level is counted, and the estimated execution time of a single integer instruction is determined based on the number and the first preset time interval. The feedback signal of the integer instruction dispatch queue is a first preset type level, indicating that the integer instruction dispatch queue has completed one integer instruction issuance.

3. The register resource scheduling method according to claim 1, characterized in that, Also includes: Receive floating-point instruction dispatch queue feedback signal within the second preset time interval; The number of floating-point instruction dispatch queue feedback signals that are at the second preset level is counted, and the estimated execution time of a single floating-point instruction is determined based on the number and the second preset time interval. The floating-point instruction dispatch queue feedback signal is a second preset type level, indicating that the floating-point instruction dispatch queue has completed a floating-point instruction issuance.

4. The register resource scheduling method according to claim 1, characterized in that, Obtaining integer instructions and floating-point instructions based on the maximum number of integer instructions and the maximum number of floating-point instructions includes: The instructions fetched from the instruction fetch unit are sequentially retrieved as the number of the largest integer instructions and the number of the largest floating-point instructions.

5. The register resource scheduling method according to claim 1, characterized in that, Determine the number of free integer physical registers and the number of free floating-point physical registers, including: Determine the number of unreleased integer physical registers; The number of free integer physical registers is determined based on the number of unreleased integer physical registers and the total number of integer physical registers. Determine the number of unreleased floating-point physical registers; The number of free floating-point physical registers is determined based on the number of unreleased floating-point physical registers and the total number of floating-point physical registers.

6. The register resource scheduling method according to claim 1, characterized in that, Selecting a target physical register from the remaining physical registers of the second type of physical registers for use as a first type of physical register includes: According to the selection ratio, a target physical register is selected from the remaining physical registers of the second type of physical registers for use as a first type of physical register.

7. The register resource scheduling method according to claim 6, characterized in that, Also includes: Monitor the changing trend of the number of idle physical registers of the first type according to a preset period, and adjust the selection ratio based on the changing trend.

8. The register resource scheduling method according to any one of claims 1 to 7, characterized in that, Also includes: If the number of idle integer physical registers and floating-point physical registers cannot meet the demand, determine the first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within the second target time period. Based on the first estimated release quantity, the second estimated release quantity, the required quantity of integer physical registers, the number of free integer physical registers, the required quantity of floating-point physical registers, and the number of free floating-point physical registers, free integer physical registers and floating-point physical registers are allocated.

9. The register resource scheduling method according to claim 8, characterized in that, Determining the first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within the second target time period includes: The first estimated number of integer physical registers to be released and the second estimated number of floating-point physical registers to be released within the second target time period are determined based on the integer instruction release time and the floating-point instruction release time. The release time of the integer instruction is determined based on the release time of the historical integer instruction, and the release time of the floating-point instruction is determined based on the release time of the historical floating-point instruction.

10. The register resource scheduling method according to claim 8, characterized in that, Also includes: During execution, the first release time of integer instructions and the second release time of floating-point instructions are monitored. The second target time period is adjusted based on the first release time and the second release time.

11. A register resource scheduling system, characterized in that, include: The requirement quantity determination module is used to determine the required number of integer physical registers and the required number of floating-point physical registers; The free quantity determination module is used to determine the number of free integer physical registers and the number of free floating-point physical registers; The demand analysis module is used to compare the required number of integer physical registers with the number of free integer physical registers, and the required number of floating-point physical registers with the number of free floating-point physical registers. The register partitioning module is used to select a target physical register from the remaining physical registers of the second type of physical registers as the first type of physical register when the number of free physical registers of the first type cannot meet the required number and the number of free physical registers of the second type of physical registers is higher than the required number. Wherein, the first type of physical register is any one of the integer physical register and the floating-point physical register, and the second type of physical register is the other type of physical register among the integer physical register and the floating-point physical register; The requirement quantity determination module is specifically used for: determining the maximum number of integer instructions and the maximum number of floating-point instructions that can be executed within a first target time period based on the estimated execution time of a single integer instruction and the estimated execution time of a single floating-point instruction; obtaining integer instructions and floating-point instructions based on the maximum number of integer instructions and the maximum number of floating-point instructions; performing conflict detection on the read integer instructions and floating-point instructions to determine the required number of integer physical registers and the required number of floating-point physical registers; wherein, the estimated execution time of a single instruction is related to the time interval between issuing the instruction to the execution unit.

12. The register resource scheduling system according to claim 11, characterized in that, Also includes: The release pre-analysis module is used to determine the first estimated release quantity of the integer physical registers and the second estimated release quantity of the floating-point physical registers within a second target time period when the number of idle units of both the integer physical registers and the floating-point physical registers cannot meet the required quantity. Correspondingly, the register partitioning module is also used to allocate idle integer physical registers and floating-point physical registers based on the first estimated release quantity, the second estimated release quantity, the number of integer physical registers required, the number of idle integer physical registers, the number of floating-point physical registers required, and the number of idle floating-point physical registers.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the register resource scheduling method as described in any one of claims 1 to 10.

14. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the register resource scheduling method as described in any one of claims 1 to 10.

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