Network-on-chip atomic operation method, system and equipment for time limit perception and sequence control and medium
By introducing a time-aware and sequential control atomic operation method into the on-chip network, the problems of unpredictable latency and mutual interference of atomic operations in NoC are solved, and the predictable latency and efficient synchronization of critical atomic operations are achieved, reducing the complexity of the memory controller.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-08
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, atomic operation latency in network-on-chip (NoC) is unpredictable, susceptible to network congestion and load fluctuations, and atomic operations interfere with ordinary traffic, resulting in low synchronization efficiency and high complexity in maintaining the order of the storage controller.
An on-chip network atomic operation method with time-awareness and sequential control is adopted. By marking the criticality, deadline and address field identifier in the atomic operation request packet, and using a multi-level queue structure and deadline-driven arbitration strategy, atomic operations are isolated from ordinary traffic. Lightweight sequential management is performed at the NoC level to reduce the complexity of the storage controller.
It provides predictable latency and quality of service for critical atomic operations, reduces performance interference between atomic operations and ordinary traffic, reduces the sequential maintenance burden on the storage controller, and improves latency determinism and system performance for synchronous operations.
Smart Images
Figure CN121807769A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of Network on-Chip (NoC) technology, specifically to a method, system, device, and medium for time-sensitive and sequential control of atomic operations on a network on-chip. Background Technology
[0002] Network on-chip (NoC) is the fundamental interconnect structure in multi-core processors and systems that carries out inter-core communication and memory access. As the scale of multi-core processors continues to increase, multi-processor shared memory architectures widely adopt atomic operations as key primitives for thread synchronization, lock implementation, and lock-free data structures, such as Compare-and-Swap (CAS), Fetch-and-Add (FAA), and Fetch-and-Store.
[0003] Despite the initial progress made in supporting NoC atomic operations, the following major problems remain:
[0004] ① Unpredictable latency of atomic operations: In traditional designs, atomic requests and ordinary read / write requests typically share the same NoC resources, and the arbitration strategies for routers and links are mostly round-robin or simple priority mechanisms. Atomic operations in NoC compete for bandwidth with large-volume data transmission flows, causing their end-to-end latency to be greatly affected by network congestion and load fluctuations. It is difficult to provide a clear upper bound on latency for critical atomic operations such as locking / synchronization, which is extremely detrimental to application scenarios such as real-time tasks and those sensitive to Quality of Service (QoS).
[0005] ② Interference between atomic operations and normal traffic: When there are a large number of atomic operations in the system, they will form high-intensity read-modify-write access near hot addresses, which can easily cause congestion on the path to the same storage controller and slow down the response of normal read and write requests. Conversely, when a large volume of normal read and write operations occupy NoC resources, atomic operations may be cascaded and queued on multiple routers, which will greatly increase the lock waiting time and seriously reduce the synchronization efficiency.
[0006] ③ The order of atomic operations on the same address is difficult to control explicitly at the NoC layer: Existing designs typically rely on the storage controller to maintain the order of atomic operations at the terminal, while the NoC is only responsible for packet transmission. For NoCs with multi-hop routing, multi-path, or out-of-order forwarding support, atomic operation requests for the same memory address may experience order reversal or highly discrete arrival times in the network. The storage controller needs complex rearrangement and buffering logic to maintain atomic semantics, increasing implementation complexity and power consumption.
[0007] Therefore, how to provide predictable latency and quality of service for critical atomic operations, reduce performance interference between atomic operations and ordinary traffic, and reduce the sequential maintenance pressure on the storage controller are urgent technical problems to be solved. Summary of the Invention
[0008] The technical objective of this invention is to provide a time-sensitive and sequential control method, system, device, and medium for on-chip network atomic operations to address the problem of how to provide predictable latency and quality of service for critical atomic operations, reduce performance interference between atomic operations and ordinary traffic, and reduce the sequential maintenance pressure on the storage controller.
[0009] The technical objective of this invention is achieved as follows: a time-sensitive and sequential control method for on-chip network atomic operations, the specific method of which is as follows:
[0010] Atomic operation request packet generation and labeling: Based on the upper-layer software or hardware task requirements, the on-chip network source node generates atomic operation requests and labels the atomic operation requests according to the upper-layer software or hardware task information. The labeled atomic operation requests are then encapsulated into atomic operation request packets containing target node address, operation type, criticality level, deadline, and address field identifier fields, and sent to the source router through the network interface.
[0011] Time-limited forwarding: After receiving the atomic operation request packet, the source router implements time-limited forwarding using a time-limited forwarding strategy.
[0012] Address domain atomic order control: Lightweight order management is performed on atomic operation request packets within the same critical section using intermediate router order preservation strategy and terminal order simplification strategy;
[0013] Atomic operation execution and result feedback: The storage controller executes the corresponding atomic operation according to the address and operation type, updates the target data and generates the corresponding atomic operation result feedback packet. The atomic operation result feedback packet carries the address field identifier and sorting label of the original request and returns to the source node along the on-chip network path. After receiving the atomic operation result feedback packet, the source node matches the result to the corresponding task according to the sorting label and request identifier and resumes subsequent execution.
[0014] Atomic operation monitoring and parameter adaptation: Periodically collect the average / maximum latency of atomic operations with different criticalities, the queue length and utilization of each queue type (high-priority atoms, low-priority atoms, and ordinary data), and the number and distribution of atomic operations that fail to meet deadlines. Based on real-time monitoring information, dynamically adjust the resource allocation and scheduling strategy of the on-chip network.
[0015] As a preferred approach, atomic operation requests are annotated based on upper-layer software or hardware task information as follows:
[0016] ① Based on task requirements, determine whether the corresponding atomic operations are used in key synchronization scenarios such as lock acquisition and semaphore update, mark them as criticality levels, and extract the atomic operation types; among them, the atomic operation type field includes operation types that identify CAS, FAA, and FAS.
[0017] ② Set deadlines for atomic operations based on the latest acceptable response time for the task;
[0018] ③ Assign incremental sorting labels to atomic operations within the same critical region and generate address field identifiers.
[0019] As a preferred option, the time-limit-aware forwarding strategy is as follows:
[0020] ① Multi-level queue structure strategy: Set up high-priority queues and low-priority queues for atomic operation requests on each output port of each level of router, and set up independent queues for ordinary data read and write requests to achieve queue isolation between atomic operations and ordinary traffic;
[0021] ② Deadline-driven arbitration strategy: When multiple atomic operation request packets exist on the same output port, arbitration is carried out using the "earliest deadline priority" strategy based on the corresponding deadline field; when the priorities are the same and the deadlines are close, a round-robin arbitration strategy is used to ensure fairness and real-time performance; the "earliest deadline priority" strategy specifically means: check the deadline of requests in the high-priority atomic operation queue, and prioritize forwarding atomic operation request packets with earlier deadlines;
[0022] ③ Path selection and detour strategy: When the queuing delay of any outgoing link is predicted to cause the critical atomic operation to exceed the deadline, an alternative path is selected based on local congestion information to prioritize the time limit requirements of the critical atomic operation. Specifically, when local congestion occurs in the network, the source router selects a path that can meet the deadline of the critical atomic operation based on the queue length of each output port and the expected queuing delay. If all paths cannot meet the deadline, the path with the shortest delay is selected and the default information is recorded for subsequent parameter adjustment.
[0023] As a preferred option, the intermediate router order preservation strategy is as follows: In an on-chip network that supports out-of-order forwarding or multi-path routing, when each router forwards an atomic request, it performs order preservation for requests with the same address field identifier that are sent from the same output port to the same direction. That is, it prioritizes forwarding requests with smaller sort labels to ensure that the sending order of requests with the same address field in the corresponding output direction is consistent with their sort labels, thereby avoiding the introduction of new out-of-order requests during the routing forwarding stage.
[0024] The terminal sequence simplification strategy is as follows: the on-chip network side has already maintained the order of requests for the same address domain. When the storage controller receives atomic operation requests for the same address domain, it only needs to execute them sequentially according to the sorting label order. There is no need to configure complex rearrangement buffers and control logic, thereby significantly reducing the terminal-side buffer resource requirements and implementation complexity.
[0025] More specifically, the resource allocation and scheduling strategy for on-chip networks is as follows:
[0026] Dynamically adjust the bandwidth quota and weight of high and low criticality atomic operations on each port;
[0027] Optimize the deadline urgency classification threshold and elevate atomic operations that frequently default to higher priority;
[0028] Targeted optimization is implemented for frequently accessed address domains.
[0029] A time-limit-aware and sequential control on-chip network atomic operating system is disclosed. The system includes a source node and a storage control node. The source node identifies operations that require atomicity protection based on the needs of upper-layer software or hardware tasks, generates an atomic operation request packet, and sends it to the target storage control node through a network interface. After executing the atomic operation logic, the storage control node returns an atomic operation result feedback packet based on the sorting label and address field identifier. The source node updates its local state based on the result and continues to execute subsequent tasks.
[0030] The system comprises an atomic operation annotation module, an atomic operation monitoring and parameter adaptation module, and a source or destination router deployed on the source node. The atomic operation annotation module sends the annotated atomic operation request packets to the source or destination router through the network interface between the source node and the on-chip network router. The atomic operation monitoring and parameter adaptation module is used to collect real-time statistics on the request arrival rate, average / maximum latency, and utilization of different priority queues for atomic operations. Based on real-time monitoring information, it dynamically adjusts the atomic operation priority threshold, queue quota, and deadline urgency classification strategy. For example, when the atomic operation load is light, the high priority level is appropriately reduced to reduce the suppression of ordinary read and write traffic. When the atomic load suddenly increases or the risk of default for critical atomic operations increases, the bandwidth ratio and scheduling priority of critical atomic operations are increased accordingly to ensure their time-limit requirements.
[0031] The storage control node deploys a destination or source router and a storage controller. The storage controller is used to obtain and execute atomic operation requests and send the atomic operation result feedback packet back to the destination or source router through the network interface.
[0032] As a preferred embodiment, both the destination or source router and the source or destination router include a time-aware arbitration and routing module and an address field atomic sequence control module.
[0033] The time-limit-aware arbitration and routing module implements a time-limit-aware forwarding strategy for atomic operation request packets while ensuring the correctness of atomic semantics. Specifically, the time-limit-aware forwarding strategy includes: ① A multi-level queue structure strategy: High-priority and low-priority queues are set up on each output port of each level of router for atomic operation requests, while independent queues are set up for ordinary data read / write requests, achieving queue isolation between atomic operations and ordinary traffic. The rule for distinguishing between high-priority and low-priority queues is: if the request is of high criticality level and less than or equal to the deadline urgency classification threshold, then the corresponding request is placed in the high-priority queue. Sub-queues; if the priority level is low or greater than the deadline urgency classification threshold, the request will be placed in a low-priority atomic queue; ② Deadline-driven arbitration strategy: when there are multiple atomic operation requests on the same output port, arbitration is carried out according to the corresponding deadline field using the "earliest deadline first" strategy. When the priorities are the same and the deadlines are close, a round-robin arbitration strategy is used to ensure fairness and real-time performance; ③ Path selection and detour strategy: when it is predicted that the queuing delay of any outgoing link may cause the critical atomic operation to exceed the deadline, an alternative path is selected based on local congestion information to prioritize the time limit requirements of the critical atomic operation;
[0034] The address domain atomic sequence control module is used for lightweight sequence management of atomic operation requests targeting the same critical section. Specifically: ① Intermediate router sequence preservation strategy: In on-chip networks that support out-of-order forwarding or multi-path routing, when routers at all levels forward atomic requests, they perform sequence preservation for requests with the same address domain identifier and sent from the same output port to the same direction. That is, they prioritize forwarding requests with smaller sort labels to ensure that the sending order of requests with the same address domain in the corresponding output direction is consistent with their sort labels, thereby avoiding the introduction of new out-of-order requests during the routing forwarding stage; ② Terminal sequence simplification strategy: Since the on-chip network side has already performed sequence preservation for requests with the same address domain, when the storage controller receives atomic operation requests with the same address domain, it only needs to execute them sequentially according to the sort label order. There is no need to configure complex rearrangement buffers and control logic, thereby significantly reducing the buffer resource requirements and implementation complexity on the terminal side.
[0035] More preferably, the atomic operation annotation module explicitly annotates time-related and sequence-related information in the atomic operation request packet, as follows:
[0036] ① Atomic operation type field: identifies the CAS, FAA, and FAS operation types;
[0037] ② Atomic priority level field: distinguishes between lock acquisition atomic operations (high priority) and counting / statistical atomic operations (low priority);
[0038] ③ Deadline field: Set the deadline for atomic operations based on the real-time requirements provided by the upper-layer software or hardware tasks;
[0039] ④ Address field identifier: Assigns an incrementing sorting label to atomic operations within the same critical section to facilitate subsequent order control in NoC.
[0040] An electronic device includes: a memory and at least one processor;
[0041] The memory contains computer programs;
[0042] The at least one processor executes the computer program stored in the memory, causing the at least one processor to perform the on-chip network atomic operation method as described above, which is based on time-aware and sequential control.
[0043] A computer-readable storage medium storing a computer program that can be executed by a processor to implement the on-chip network atomic operation method with time-aware and sequential control as described above.
[0044] The time-sensitive and sequential control on-chip network atomic operation method, system, device, and medium of the present invention have the following advantages:
[0045] (i) This invention introduces information such as criticality, deadline, address field identifier and sorting label into atomic request packets, and adopts a path selection mechanism on the NoC router side that isolates atomic and ordinary traffic queues, uses deadline-driven arbitration and congestion awareness, provides clear latency constraints and quality of service guarantees for critical atomic operations, reduces the performance interference of atomic operations on ordinary read and write traffic to achieve isolation between different traffic types, and pushes some order maintenance logic down to the NoC layer to simplify the storage controller design, thereby reducing terminal reordering buffer and control logic. At the same time, combined with monitoring and parameter adaptive strategies, it achieves predictable latency service guarantees for read-modify-write atomic operations and lightweight order constraints for atomic requests in the same critical section.
[0046] (ii) This invention can fundamentally solve the problems of "unpredictable latency, mutual interference with ordinary traffic, and high complexity due to high dependence on the terminal for sequential control" in the traditional atomic operation mechanism. By reducing the uncertainty caused by congestion fluctuations through deadline-aware scheduling and queue isolation on the router side, and suppressing the mutual influence between atomic operations and ordinary read and write operations, it can maintain stable atomic operation latency.
[0047] (III) This invention can be applied to the on-chip network interconnection architecture of products such as multi-core heterogeneous chips, high-performance computing chips, and AI acceleration chips. As a key communication and scheduling mechanism to support atomic operations such as CAS / FAA / FAS, it improves the latency determinism of key synchronization / lock-type atomic operations and achieves controllable isolation from ordinary traffic. At the same time, it reduces the consumption of buffer resources and control logic of the storage controller. In addition, it can enhance the company's core technical strength in the NoC technology field and enhance its competitiveness in the multi-core heterogeneous chip market.
[0048] (iv) This invention can provide predictable latency and quality of service for critical atomic operations, reduce performance interference between atomic operations and ordinary traffic, and reduce the sequential maintenance pressure on the memory controller. It is used to provide NoC support with time constraints and priority isolation capabilities for read-modify-write atomic operations in multi-core on-chip systems.
[0049] (v) The time-aware arbitration and routing module of the present invention can provide more stable and predictable end-to-end latency for atomic operations at the NoC level, while avoiding excessive competition for resources with ordinary traffic at the link level. Attached Figure Description
[0050] The invention will be further described below with reference to the accompanying drawings.
[0051] Appendix Figure 1 A flowchart of an on-chip network atomic operation method for time-sensitive and sequential control;
[0052] Appendix Figure 2 This is a block diagram of an on-chip network atomic operating system for time-constraint awareness and sequential control. Detailed Implementation
[0053] The on-chip network atomic operation method, system, device, and medium of the present invention with time-limit awareness and sequence control are described in detail below with reference to the accompanying drawings and specific embodiments.
[0054] Example 1:
[0055] As attached Figure 1 As shown, this embodiment provides a time-sensitive and sequential control method for on-chip network atomic operations, which is as follows:
[0056] S1. Atomic Operation Request Packet Generation and Labeling: Based on the upper-layer software or hardware task requirements, the on-chip network source node generates atomic operation requests and labels the atomic operation requests according to the upper-layer software or hardware task information. The labeled atomic operation requests are then encapsulated into atomic operation request packets containing target node address, operation type, criticality level, deadline, and address field identifier fields, and sent to the source router through the network interface.
[0057] S2. Time-aware forwarding: After receiving the atomic operation request packet, the source router implements time-aware forwarding using a time-aware forwarding strategy.
[0058] S3, Address Field Atomic Sequence Control: Lightweight sequence management is performed on atomic operation request packets within the same critical section using intermediate router sequence preservation strategy and terminal sequence simplification strategy;
[0059] S4. Atomic Operation Execution and Result Feedback: The storage controller executes the corresponding atomic operation according to the address and operation type, updates the target data, and generates the corresponding atomic operation result feedback packet. The atomic operation result feedback packet carries the address field identifier and sorting label of the original request and returns to the source node along the on-chip network path. After receiving the atomic operation result feedback packet, the source node matches the result to the corresponding task according to the sorting label and request identifier and resumes subsequent execution.
[0060] S5. Atomic Operation Monitoring and Parameter Adaptation: Periodically collect the average / maximum latency of atomic operations with different criticalities, the queue length and utilization of each queue type (high-priority atoms, low-priority atoms, and ordinary data), and the number and distribution of atomic operations that fail to meet deadlines. Based on real-time monitoring information, dynamically adjust the resource allocation and scheduling strategy of the on-chip network.
[0061] In this embodiment, step S1, which involves annotating atomic operation requests based on upper-layer software or hardware task information, is as follows:
[0062] ① Based on task requirements, determine whether the corresponding atomic operations are used in key synchronization scenarios such as lock acquisition and semaphore update, mark them as criticality levels, and extract the atomic operation types; among them, the atomic operation type field includes operation types that identify CAS, FAA, and FAS.
[0063] ② Set deadlines for atomic operations based on the latest acceptable response time for the task;
[0064] ③ Assign incremental sorting labels to atomic operations within the same critical region and generate address field identifiers.
[0065] The time-limit-aware forwarding strategy in step S2 of this embodiment is as follows:
[0066] ① Multi-level queue structure strategy: Set up high-priority queues and low-priority queues for atomic operation requests on each output port of each level of router, and set up independent queues for ordinary data read and write requests to achieve queue isolation between atomic operations and ordinary traffic;
[0067] ② Deadline-driven arbitration strategy: When multiple atomic operation request packets exist on the same output port, arbitration is carried out using the "earliest deadline priority" strategy based on the corresponding deadline field; when the priorities are the same and the deadlines are close, a round-robin arbitration strategy is used to ensure fairness and real-time performance; the "earliest deadline priority" strategy specifically means: check the deadline of requests in the high-priority atomic operation queue, and prioritize forwarding atomic operation request packets with earlier deadlines;
[0068] ③ Path selection and detour strategy: When the queuing delay of any outgoing link is predicted to cause the critical atomic operation to exceed the deadline, an alternative path is selected based on local congestion information to prioritize the time limit requirements of the critical atomic operation. Specifically, when local congestion occurs in the network, the source router selects a path that can meet the deadline of the critical atomic operation based on the queue length of each output port and the expected queuing delay. If all paths cannot meet the deadline, the path with the shortest delay is selected and the default information is recorded for subsequent parameter adjustment.
[0069] The intermediate router order preservation strategy in step S3 of this embodiment is as follows: In an on-chip network that supports out-of-order forwarding or multi-path routing, when each router forwards an atomic request, it performs order preservation for requests with the same address domain identifier and sent from the same output port to the same direction. That is, it prioritizes forwarding requests with smaller sort labels to ensure that the sending order of requests with the same address domain in the corresponding output direction is consistent with their sort labels, thereby avoiding the introduction of new out-of-order requests during the routing forwarding stage.
[0070] The terminal sequence simplification strategy in step S3 of this embodiment is as follows: the on-chip network side has already maintained the order of requests for the same address domain. When the storage controller receives atomic operation requests for the same address domain, it only needs to execute them sequentially according to the sorting label order. There is no need to configure complex rearrangement buffers and control logic, thereby significantly reducing the buffer resource requirements and implementation complexity on the terminal side.
[0071] The resource allocation and scheduling strategy for the on-chip network in step S5 of this embodiment is as follows:
[0072] Dynamically adjust the bandwidth quota and weight of high and low criticality atomic operations on each port;
[0073] Optimize the deadline urgency classification threshold and elevate atomic operations that frequently default to higher priority;
[0074] Targeted optimization is implemented for frequently accessed address domains.
[0075] Example 2:
[0076] As attached Figure 2As shown, this embodiment provides an on-chip network atomic operating system with time limit awareness and sequential control. The system includes a source node and a storage control node. The source node identifies operations that require atomicity protection based on the needs of upper-layer software or hardware tasks, generates an atomic operation request packet, and sends it to the target storage control node through a network interface. After executing the atomic operation logic, the storage control node returns an atomic operation result feedback packet based on the sorting label and address field identifier. The source node updates its local state based on the result and continues to execute subsequent tasks.
[0077] The system comprises an atomic operation annotation module, an atomic operation monitoring and parameter adaptation module, and a source or destination router deployed on the source node. The atomic operation annotation module sends the annotated atomic operation request packets to the source or destination router through the network interface between the source node and the on-chip network router. The atomic operation monitoring and parameter adaptation module is used to collect real-time statistics on the request arrival rate, average / maximum latency, and utilization of different priority queues for atomic operations. Based on real-time monitoring information, it dynamically adjusts the atomic operation priority threshold, queue quota, and deadline urgency classification strategy to enhance adaptability under different load modes. For example, when the atomic operation load is light, the high priority level is appropriately reduced to reduce the suppression of ordinary read and write traffic. When the atomic load suddenly increases or the risk of default of critical atomic operations increases, the bandwidth ratio and scheduling priority of critical atomic operations are increased accordingly to ensure their time limit requirements.
[0078] The storage control node deploys a destination or source router and a storage controller. The storage controller is used to obtain and execute atomic operation requests and send the atomic operation result feedback packet back to the destination or source router through the network interface.
[0079] In this embodiment, both the destination or source router and the source or destination router include a time-aware arbitration and routing module and an address field atomic sequence control module.
[0080] The time-limit-aware arbitration and routing module implements a time-limit-aware forwarding strategy for atomic operation request packets while ensuring the correctness of atomic semantics. Specifically, the time-limit-aware forwarding strategy includes: ① A multi-level queue structure strategy: High-priority and low-priority queues are set up on each output port of each level of router for atomic operation requests, while independent queues are set up for ordinary data read / write requests, achieving queue isolation between atomic operations and ordinary traffic. The rule for distinguishing between high-priority and low-priority queues is: if the request is of high criticality level and less than or equal to the deadline urgency classification threshold, then the corresponding request is placed in the high-priority queue. Sub-queues; if the priority level is low or greater than the deadline urgency classification threshold, the request will be placed in a low-priority atomic queue; ② Deadline-driven arbitration strategy: when there are multiple atomic operation requests on the same output port, arbitration is carried out according to the corresponding deadline field using the "earliest deadline first" strategy. When the priorities are the same and the deadlines are close, a round-robin arbitration strategy is used to ensure fairness and real-time performance; ③ Path selection and detour strategy: when it is predicted that the queuing delay of any outgoing link may cause the critical atomic operation to exceed the deadline, an alternative path is selected based on local congestion information to prioritize the time limit requirements of the critical atomic operation;
[0081] The address domain atomic sequence control module is used for lightweight sequence management of atomic operation requests targeting the same critical section. Specifically: ① Intermediate router sequence preservation strategy: In on-chip networks that support out-of-order forwarding or multi-path routing, when routers at all levels forward atomic requests, they perform sequence preservation for requests with the same address domain identifier and sent from the same output port to the same direction. That is, they prioritize forwarding requests with smaller sort labels to ensure that the sending order of requests with the same address domain in the corresponding output direction is consistent with their sort labels, thereby avoiding the introduction of new out-of-order requests during the routing forwarding stage; ② Terminal sequence simplification strategy: Since the on-chip network side has already performed sequence preservation for requests with the same address domain, when the storage controller receives atomic operation requests with the same address domain, it only needs to execute them sequentially according to the sort label order. There is no need to configure complex rearrangement buffers and control logic, thereby significantly reducing the buffer resource requirements and implementation complexity on the terminal side.
[0082] In this embodiment, the atomic operation annotation module explicitly annotates information related to time limits and order in the atomic operation request packet, as follows:
[0083] ① Atomic operation type field: identifies the CAS, FAA, and FAS operation types;
[0084] ② Atomic priority level field: distinguishes between lock acquisition atomic operations (high priority) and counting / statistical atomic operations (low priority);
[0085] ③ Deadline field: Set the deadline for atomic operations based on the real-time requirements provided by the upper-layer software or hardware tasks;
[0086] ④ Address field identifier: Assigns an incrementing sorting label to atomic operations within the same critical section to facilitate subsequent order control in NoC.
[0087] The specific workflow of this system is as follows:
[0088] (I) Generation and Labeling of Atomic Operation Request Packets: On-chip network nodes generate atomic operation requests based on the requirements of upper-layer software or hardware tasks; the atomic operation labeling module labels the requests based on the following information:
[0089] ① Based on the task requirements, determine whether the atomic operation is used in key synchronization scenarios such as lock acquisition and semaphore update, mark it as high criticality level, and extract the atomic operation type (CAS, FAA, etc.);
[0090] ② Set deadlines for atomic operations based on the latest acceptable response time for the task;
[0091] ③ Assign incremental sorting labels to atomic operations within the same critical region and generate address field identifiers.
[0092] The labeled atomic operation request is encapsulated into a request packet containing fields such as target node address, operation type, criticality level, deadline, and address domain identifier, and sent to the source router through the network interface.
[0093] (ii) Time-limit-aware forwarding: After receiving the atomic operation request packet, the source router sends it to the time-limit-aware arbitration and routing module:
[0094] ① If the request is of high criticality and the deadline is tight, then the request will be placed in a high-priority atomic queue;
[0095] ② If the request is of low criticality level or has a lenient deadline, it will be placed in a low-priority atomic queue.
[0096] ③ Regular data read / write requests enter a separate data queue.
[0097] At each output port, the time-aware arbitration and routing module first checks the deadline of requests in the high-priority atomic queue and prioritizes forwarding packets with earlier deadlines. When the high-priority queue is empty, it then performs round-robin arbitration between the low-priority atomic queue and the ordinary data queue.
[0098] When local congestion occurs in the network, the router selects a path that can meet the deadline of critical atomic operations based on the queue length of each output port and the expected queuing delay. If none of the paths can meet the deadline, the router selects the path with the shortest delay and records the default information to the atomic operation monitoring and parameter adaptation module for subsequent parameter adjustment.
[0099] (iii) Address Domain Atomic Order Control: For atomic operation request packets within the same critical section, an incremental ordering label is assigned at the source node. In NoCs that support multipath or out-of-order forwarding, each router ensures at its output port that atomic requests destined for the same destination node and within the same address domain are sent from the local queue in the order of their ordering labels, thereby preventing the introduction of new out-of-order requests into the network.
[0100] After receiving an atomic request, the terminal storage controller only needs to perform atomic operations on the same address field according to the sorting label order, without needing to perform complex rearrangement for requests that arrive in any out-of-order order.
[0101] (iv) Atomic Operation Execution and Result Feedback: The storage controller executes the corresponding atomic operation based on the address and operation type, updates the target data, and generates the corresponding atomic operation result feedback packet. The result packet carries the address field identifier and sorting tag of the original request and returns to the source node along the NoC path. After receiving the result packet, the source node matches the result to the corresponding task based on the sorting tag and request identifier, and resumes subsequent execution.
[0102] (V) Atomic Operation Monitoring and Parameter Adaptation: The atomic operation monitoring and parameter adaptation module periodically collects indicators such as the average / maximum latency of atomic operations with different criticalities, the queue length and utilization of each queue type (high-priority atoms, low-priority atoms, and ordinary data), and the number and distribution of atomic operations that fail to meet deadlines. Based on the above data, this module dynamically adjusts the NoC's resource allocation and scheduling strategy: dynamically adjusts the bandwidth quota and weight of high and low-priority atomic operations on each port; optimizes the deadline urgency classification threshold, elevating frequently defaulting atomic operations to higher priority; and performs targeted optimization for hot address domains with concentrated access, such as allocating dedicated virtual channels or fixed forwarding paths, in order to maintain stable atomic operation latency characteristics and overall system performance under different load conditions.
[0103] Example 3:
[0104] This embodiment also provides an electronic device, including: a memory and a processor;
[0105] The memory stores the instructions executed by the computer.
[0106] The processor executes computer execution instructions stored in the memory, causing the processor to perform the time-aware and sequential control on-chip network atomic operation method in any embodiment of the present invention.
[0107] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor can be a microprocessor or any conventional processor.
[0108] Memory is used to store computer programs and / or modules. The processor implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory can mainly include a program storage area and a data storage area. The program storage area can store the operating system, at least one application program required for a function, etc.; the data storage area can store data created based on the use of the terminal, etc. In addition, memory can also include high-speed random access memory, and can also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart memory cards (SMC), secure digital cards (SD cards), flash memory cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.
[0109] Example 4:
[0110] This embodiment also provides a computer-readable storage medium storing multiple instructions, which are loaded by a processor to cause the processor to execute the on-chip network atomic operation method of time-aware and sequential control in any embodiment of the present invention. Specifically, a system or apparatus equipped with a storage medium may be provided, on which software program code implementing the functions of any of the above embodiments is stored, and the computer (or CPU or MPU) of the system or apparatus may read and execute the program code stored in the storage medium.
[0111] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of the present invention.
[0112] Storage media embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RYM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.
[0113] Furthermore, it should be clear that not only can the program code read by the computer be executed, but also the operating system or other components operating on the computer can be instructed based on the program code to perform some or all of the actual operations, thereby realizing the function of any of the embodiments described above.
[0114] Furthermore, it is understood that the program code read from the storage medium is written to the memory set in the expansion board inserted into the computer or to the memory set in the expansion unit connected to the computer. Then, based on the instructions of the program code, the CPU or other components installed on the expansion board or expansion unit execute some and all of the actual operations, thereby realizing the function of any of the embodiments described above.
[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A time-constraint-aware and sequential control method for on-chip network atomic operations, characterized in that, The method is as follows: Atomic operation request packet generation and labeling: Based on the upper-layer software or hardware task requirements, the on-chip network source node generates atomic operation requests and labels the atomic operation requests according to the upper-layer software or hardware task information. The labeled atomic operation requests are then encapsulated into atomic operation request packets containing target node address, operation type, criticality level, deadline, and address field identifier fields, and sent to the source router through the network interface. Time-limit-aware forwarding: After receiving the atomic operation request packet, the source router implements time-limit-aware forwarding using a time-limit-aware forwarding strategy. Address domain atomic order control: Lightweight order management is performed on atomic operation request packets within the same critical section using intermediate router order preservation strategy and terminal order simplification strategy; Atomic operation execution and result feedback: The storage controller executes the corresponding atomic operation according to the address and operation type, updates the target data and generates the corresponding atomic operation result feedback packet. The atomic operation result feedback packet carries the address field identifier and sorting label of the original request and returns to the source node along the on-chip network path. After receiving the atomic operation result feedback packet, the source node matches the result to the corresponding task according to the sorting label and request identifier and resumes subsequent execution. Atomic operation monitoring and parameter adaptation: Periodically collect the average / maximum latency of atomic operations with different criticalities, the queue length and utilization of each queue type, and the number and distribution of atomic operation deadline defaults. Based on real-time monitoring information, dynamically adjust the on-chip network resource allocation and scheduling strategy.
2. The on-chip network atomic operation method with time-limit awareness and sequential control according to claim 1, characterized in that, Based on the upper-layer software or hardware task information, the atomic operation requests are labeled as follows: ① Based on task requirements, determine whether the corresponding atomic operations are used in key synchronization scenarios such as lock acquisition and semaphore update, mark them as criticality levels, and extract the atomic operation types; among them, the atomic operation type field includes operation types that identify CAS, FAA, and FAS. ② Set deadlines for atomic operations based on the latest acceptable response time for the task; ③ Assign incremental sorting labels to atomic operations within the same critical region and generate address field identifiers.
3. The on-chip network atomic operation method with time-limit awareness and sequential control according to claim 1, characterized in that, The time-limit-aware forwarding strategy is as follows: ① Multi-level queue structure strategy: Set up high-priority queues and low-priority queues for atomic operation requests on each output port of each level of router, and set up independent queues for ordinary data read and write requests to achieve queue isolation between atomic operations and ordinary traffic; ② Deadline-driven arbitration strategy: When multiple atomic operation request packets exist on the same output port, arbitration is carried out using the "earliest deadline priority" strategy based on the corresponding deadline field; when the priorities are the same and the deadlines are close, a round-robin arbitration strategy is used to ensure fairness and real-time performance; the "earliest deadline priority" strategy specifically means: check the deadline of requests in the high-priority atomic operation queue, and prioritize forwarding atomic operation request packets with earlier deadlines; ③ Path selection and detour strategy: When the queuing delay of any outgoing link is predicted to cause the critical atomic operation to exceed the deadline, an alternative path is selected based on local congestion information to prioritize the time limit requirements of the critical atomic operation. Specifically, when local congestion occurs in the network, the source router selects a path that can meet the deadline of the critical atomic operation based on the queue length of each output port and the expected queuing delay. If all paths cannot meet the deadline, the path with the shortest delay is selected and the default information is recorded for subsequent parameter adjustment.
4. The on-chip network atomic operation method with time-limit awareness and sequential control according to claim 1, characterized in that, The intermediate router order preservation strategy is as follows: In an on-chip network that supports out-of-order forwarding or multi-path routing, when each router forwards an atomic request, it performs order preservation for requests with the same address field identifier that are sent from the same output port to the same direction. That is, it prioritizes forwarding requests with smaller sort labels to ensure that the sending order of requests with the same address field in the corresponding output direction is consistent with their sort labels. The terminal order simplification strategy is as follows: the on-chip network side has already maintained the order of requests for the same address domain. When the storage controller receives atomic operation requests for the same address domain, it only needs to execute them sequentially according to the sorting label order, without the need for additional configuration of complex rearrangement buffers and control logic.
5. The on-chip network atomic operation method with time-limit awareness and sequential control according to any one of claims 1 to 4, characterized in that, The resource allocation and scheduling strategies for on-chip networks are as follows: Dynamically adjust the bandwidth quota and weight of high and low criticality atomic operations on each port; Optimize the deadline urgency classification threshold and elevate atomic operations that frequently default to higher priority; Targeted optimization is implemented for frequently accessed address domains.
6. A time-limit-aware and sequential control on-chip network atomic operating system, characterized in that, The system includes a source node and a storage control node. The source node identifies operations that require atomicity protection based on the needs of upper-layer software or hardware tasks, generates an atomic operation request packet, and sends it to the target storage control node through the network interface. After executing the atomic operation logic, the storage control node returns an atomic operation result feedback packet based on the sorting label and address field identifier. The source node updates its local state based on the result and continues to execute subsequent tasks. The system includes an atomic operation annotation module, an atomic operation monitoring and parameter adaptation module, and a source or destination router deployed on the source node. The atomic operation annotation module sends the annotated atomic operation request packets to the source or destination router through the network interface between the source node and the on-chip network router. The atomic operation monitoring and parameter adaptation module is used to collect statistics on the request arrival rate, average / maximum latency, and utilization of different priority queues for atomic operations in real time, and dynamically adjusts the atomic operation priority threshold, queue quota, and deadline urgency classification strategy based on the real-time monitoring information. The storage control node deploys a destination or source router and a storage controller. The storage controller is used to obtain and execute atomic operation requests and send the atomic operation result feedback packet back to the destination or source router through the network interface.
7. The on-chip network atomic operating system with time-limit awareness and sequential control according to claim 6, characterized in that, Both the destination and source routers include a time-aware arbitration and routing module and an address field atomic sequence control module. The time-limit-aware arbitration and routing module implements a time-limit-aware forwarding strategy for atomic operation request packets while ensuring the correctness of atomic semantics. Specifically, the time-limit-aware forwarding strategy includes: ① A multi-level queue structure strategy: High-priority and low-priority queues are set up on each output port of each level of router for atomic operation requests, while independent queues are set up for ordinary data read / write requests, achieving queue isolation between atomic operations and ordinary traffic. The rule for distinguishing between high-priority and low-priority queues is: if the request is of high criticality level and less than or equal to the deadline urgency classification threshold, then the corresponding request is placed in the high-priority queue. Sub-queues; if the priority level is low or greater than the deadline urgency classification threshold, the request will be placed in a low-priority atomic queue; ② Deadline-driven arbitration strategy: when there are multiple atomic operation requests on the same output port, arbitration is carried out according to the corresponding deadline field using the "earliest deadline first" strategy. When the priorities are the same and the deadlines are close, a round-robin arbitration strategy is used to ensure fairness and real-time performance; ③ Path selection and detour strategy: when it is predicted that the queuing delay of any outgoing link may cause the critical atomic operation to exceed the deadline, an alternative path is selected based on local congestion information to prioritize the time limit requirements of the critical atomic operation. The address domain atomic sequence control module is used for lightweight sequence management of atomic operation requests targeting the same critical section. Specifically: ① Intermediate router sequence preservation strategy: In on-chip networks that support out-of-order forwarding or multi-path routing, when routers at all levels forward atomic requests, they perform sequence preservation for requests with the same address domain identifier and sent from the same output port to the same direction. That is, they prioritize forwarding requests with smaller sort labels to ensure that the sending order of requests with the same address domain in the corresponding output direction is consistent with their sort labels; ② Terminal sequence simplification strategy: Since the on-chip network side has already performed sequence preservation for requests with the same address domain, when the storage controller receives atomic operation requests with the same address domain, it only needs to execute them sequentially according to the sort label order, without the need for additional configuration of complex rearrangement buffers and control logic.
8. The on-chip network atomic operating system with time-limit awareness and sequential control according to claim 6 or 7, characterized in that, The atomic operation annotation module explicitly annotates time-related and sequence-related information in the atomic operation request packet, as follows: ① Atomic operation type field: identifies the CAS, FAA, and FAS operation types; ② Atomic criticality level field: distinguishes between lock acquisition atomic operations and counting / statistical atomic operations; ③ Deadline field: Set the deadline for atomic operations based on the real-time requirements provided by the upper-layer software or hardware tasks; ④ Address field identifier: Assigns an incrementing sorting label to atomic operations within the same critical section to facilitate subsequent order control in NoC.
9. An electronic device, characterized in that, include: Memory and at least one processor; The memory contains computer programs; The at least one processor executes the computer program stored in the memory, causing the at least one processor to perform the on-chip network atomic operation method of time-aware and sequential control as described in any one of claims 1 to 5.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that can be executed by a processor to implement the on-chip network atomic operation method for time-aware and sequential control as described in any one of claims 1 to 5.