Layout intelligent defect identification method and system based on hierarchical deep learning

Abstract

The invention provides an intelligent layout defect identification method and system based on hierarchical deep learning, and relates to the technical field of deep learning, and the method comprises the steps: obtaining original image data of a layout, extracting structure invariant features and sensitive change features, constructing a standard topology template, carrying out the antagonism verification of the sensitive change features and the standard template, and carrying out the recognition of the defects of the layout. And identifying an abnormal region, and determining defect position and type information. The method can effectively identify the defect damaging the layout topology connection integrity, improve the detection accuracy and reduce the omission ratio.

Description

Technical Field

[0001] This invention relates to the field of deep learning technology, and in particular to a layout intelligent defect recognition method and system based on hierarchical deep learning. Background Technology

[0002] Semiconductor integrated circuit layout design is a crucial step in modern chip manufacturing, and its quality directly impacts chip performance and yield. As integrated circuit process nodes continue to shrink, layout design rules become increasingly complex, making layout defect detection increasingly difficult. Traditional layout defect detection primarily relies on methods such as design rule checking and layout comparison verification, matching pre-defined rules and templates to identify potential defects. With the development of deep learning technology, AI-based layout defect detection methods have emerged, improving the accuracy and efficiency of defect detection by learning from large amounts of layout data.

[0003] However, existing layout defect detection technologies still have some significant shortcomings. First, existing technologies typically employ a single feature extraction path, making it difficult to simultaneously capture the geometric invariance and subtle local changes of the layout, resulting in limited ability to identify certain complex defects. Second, existing methods lack a deep understanding and modeling of the layout topology, failing to accurately represent the connectivity relationships between layout elements, leading to a high false alarm rate when identifying defects that disrupt layout integrity. Furthermore, traditional defect detection algorithms generally lack a mechanism for effectively fusing geometric and topological features, failing to establish a direct correlation between pixel-level changes and the functional impact on the layout, thus making it difficult to accurately distinguish between genuine defects and permissible design variations. Summary of the Invention

[0004] This invention provides a layout intelligent defect identification method and system based on hierarchical deep learning, which can solve the problems in the prior art.

[0005] A first aspect of this invention provides a layout intelligent defect recognition method based on hierarchical deep learning, comprising: The original image data of the map to be detected is acquired; the original image data is decomposed into multiple paths in parallel to extract structurally invariant features reflecting the geometric consistency of the map and sensitive variation features reflecting local deformation of the map. The structurally invariant features are obtained by graph structure encoding of the topological connectivity of the map, and the sensitive variation features are obtained by directional encoding of the gradient changes at the map edges. A standard topology template for the layout is constructed based on the aforementioned structural invariant features. This standard topology template is used to characterize the connectivity integrity constraints of a defect-free layout. The sensitive change features are subjected to adversarial verification against the standard topological template. By calculating the deviation vector of the sensitive change features from the standard topological template, abnormal regions that disrupt the integrity of topological connections are identified. The adversarial verification is achieved by establishing a violation metric function of the sensitive change features against the standard topological template. The violation metric function maps the connection breaks at the topological level to gradient abrupt responses at the pixel level. Based on the spatial distribution of the abnormal region and the amplitude characteristics of the deviation vector, the location and type information of the layout defect are determined; based on the location and type information, a defect identification result is generated and output.

[0006] The original image data is subjected to multi-path parallel decomposition to extract structurally invariant features reflecting the geometric consistency of the layout, and sensitive variation features reflecting local deformation of the layout are extracted, including: A spatial domain separation operation is performed on the original image data to decompose it into global spatial components and local spatial components; The connection edges between layout unit nodes in the global spatial component are abstracted to construct a graph structure describing the topological connection relationship of the layout. By vectorizing the node attributes and edge attributes of the graph structure, the structure-invariant features are obtained. Edge detection is performed on the local spatial components to extract the gradient magnitude and gradient direction of the map edges. The sensitive change features are obtained by directional encoding the gradient magnitude and gradient direction. The node attributes of the graph structure reflect the spatial position and geometry of the layout unit nodes, and the edge attributes of the graph structure reflect the connection relationship and connection strength between the layout unit nodes.

[0007] Adversarial validation of sensitive change features against standard topology templates includes: The sensitive change features are projected onto the feature space of the standard topology template to obtain the projected sensitive change feature representation; the distance metric between the projected sensitive change feature representation and the standard topology template is calculated to obtain the deviation vector. Based on the violation metric function, components in the deviation vector that exceed a preset tolerance range are identified as candidate locations for topological connection breaks; The gradient abrupt response of the sensitive change feature is extracted at the candidate location, and the abnormal region is determined by judging whether the gradient abrupt response satisfies the characteristic pattern of connection breakage. The violation metric function is constructed by establishing a mapping relationship between the connection integrity constraint vector of the standard topology template and the local change response vector of the sensitive change feature. The mapping relationship transforms node disconnection and edge loss at the topology level into gradient direction abrupt change and gradient magnitude jump at the pixel level.

[0008] The construction of the violation metric function includes: The desired connection patterns of layout unit nodes are extracted from the standard topology template, and the desired connection patterns define the connection topology constraints between nodes in a defect-free layout. The actual gradient distribution pattern of the map edges is extracted from the sensitive change features. The actual gradient distribution pattern reflects the statistical distribution of the gradient direction and gradient magnitude of the edges in the map to be detected. A cross-layer mapping operator is established to map the desired connection pattern to the actual gradient distribution pattern, wherein the cross-layer mapping operator maps connection break events at the topology level to gradient anomaly events at the pixel level; The violation metric between the desired connection pattern and the actual gradient distribution pattern is calculated using the cross-layer mapping operator.

[0009] Calculating the violation metric between the desired connectivity pattern and the actual gradient distribution pattern using the cross-layer mapping operator includes: The expected connection vectors of the layout unit nodes are extracted from the expected connection patterns. The expected connection vectors describe the expected connection direction and expected connection strength between each layout unit node and its neighboring layout unit nodes. Extract the actual gradient vectors of the map edges from the actual gradient distribution pattern. The actual gradient vectors describe the gradient direction and gradient magnitude at each pixel location. The desired connection vector is projected onto the pixel space using the cross-layer mapping operator to obtain the desired gradient vector. The desired gradient vector represents the theoretical distribution of the gradient direction and gradient magnitude that the layout edge should exhibit under defect-free conditions. The gradient deviation vector is obtained by calculating the vector difference between the actual gradient vector and the expected gradient vector. The norm of the gradient deviation vector is calculated, and the norm value of the gradient deviation vector is used as the violation metric.

[0010] Based on the spatial distribution of the abnormal region and the amplitude characteristics of the deviation vector, the location and type information of the layout defect are determined, including: Spatial clustering analysis is performed on the abnormal regions to group together the abnormal regions that are spatially adjacent and whose deviation vector magnitudes differ by less than a preset deviation threshold into the same defect candidate region, thus obtaining several defect candidate regions; Calculate the weighted average of the spatial coordinates of all abnormal regions within the defect candidate region. The weight of the weighted average is determined by the magnitude of the deviation vector corresponding to the abnormal region. Use the spatial coordinates corresponding to the weighted average as the location information. Extract the amplitude statistical features of the deviation vector corresponding to each of the defect candidate regions. The amplitude statistical features include the peak amplitude of the deviation vector, the average amplitude of the deviation vector, and the amplitude variance of the deviation vector. Based on the amplitude statistical characteristics, the morphological feature parameters of the defect candidate region are calculated. These morphological feature parameters describe the spatial distribution shape and amplitude variation trend of the deviation vector within the defect candidate region. The morphological feature parameters are matched with a preset defect type feature library, which stores feature patterns of morphological feature parameters corresponding to different defect types. By calculating the similarity between the morphological feature parameters and the feature patterns of each defect type in the defect type feature library, the defect type with the highest similarity is selected as the type information.

[0011] A second aspect of this invention provides a layout intelligent defect recognition system based on hierarchical deep learning, comprising: The first unit is used to acquire the original image data of the map to be detected; to perform multi-path parallel decomposition on the original image data, extract structurally invariant features reflecting the geometric consistency of the map, and extract sensitive change features reflecting local deformation of the map. The structurally invariant features are obtained by graph structure encoding of the topological connectivity of the map, and the sensitive change features are obtained by directional encoding of the gradient changes at the map edges. The second unit is used to construct a standard topology template for the layout based on the structurally invariant features. The standard topology template is used to characterize the connection integrity constraints of the defect-free layout. The third unit is used to perform adversarial verification between the sensitive change features and the standard topological template. By calculating the deviation vector of the sensitive change features from the standard topological template, abnormal regions that disrupt the integrity of topological connections are identified. The adversarial verification is achieved by establishing a violation metric function of the sensitive change features against the standard topological template. The violation metric function maps the connection breaks at the topological level to gradient abrupt responses at the pixel level. The fourth unit is used to determine the location and type information of the layout defect based on the spatial distribution of the abnormal area and the amplitude characteristics of the deviation vector; and to generate and output the defect identification result based on the location and type information.

[0012] A third aspect of the embodiments of the present invention, An electronic device is provided, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0013] Fourth aspect of the present invention, A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0014] The beneficial effects of this application are as follows: By employing a dual feature representation mechanism that extracts both structurally invariant and sensitive change features through multi-path parallel decomposition, the system effectively distinguishes between normal structures and abnormal deformations in the layout, thereby improving the accuracy and robustness of defect identification.

[0015] A standard topological template is constructed to represent the connectivity integrity constraints of a defect-free layout, providing a reliable reference benchmark for defect identification and solving the problem of the lack of an effective reference standard in traditional methods. By employing an adversarial verification mechanism and a violation metric function, sensitive change features are compared with the standard topological template, successfully achieving the mapping transformation from topological-level connectivity breaks to pixel-level gradient abrupt changes, significantly improving the detection capability of subtle defects.

[0016] By analyzing the spatial distribution of abnormal areas and the amplitude characteristics of deviation vectors, accurate identification of defect locations and types was achieved, significantly improving the intelligence level and practical value of layout inspection. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the layout intelligent defect recognition method based on hierarchical deep learning, as described in an embodiment of the present invention. Figure 2 A flowchart illustrating the process of determining the location and type of defects. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0020] refer to Figure 1 and Figure 2 The present invention provides a layout intelligent defect recognition method based on hierarchical deep learning, comprising: The original image data of the map to be detected is acquired; the original image data is decomposed into multiple paths in parallel to extract structurally invariant features reflecting the geometric consistency of the map and sensitive variation features reflecting local deformation of the map. The structurally invariant features are obtained by graph structure encoding of the topological connectivity of the map, and the sensitive variation features are obtained by directional encoding of the gradient changes at the map edges. A standard topology template for the layout is constructed based on the aforementioned structural invariant features. This standard topology template is used to characterize the connectivity integrity constraints of a defect-free layout. The sensitive change features are subjected to adversarial verification against the standard topological template. By calculating the deviation vector of the sensitive change features from the standard topological template, abnormal regions that disrupt the integrity of topological connections are identified. The adversarial verification is achieved by establishing a violation metric function of the sensitive change features against the standard topological template. The violation metric function maps the connection breaks at the topological level to gradient abrupt responses at the pixel level. Based on the spatial distribution of the abnormal region and the amplitude characteristics of the deviation vector, the location and type information of the layout defect are determined; based on the location and type information, a defect identification result is generated and output.

[0021] In one optional implementation, the original image data is decomposed using a multi-path parallel process to extract structurally invariant features reflecting the geometric consistency of the layout, and to extract sensitive variation features reflecting local deformation of the layout, including: A spatial domain separation operation is performed on the original image data to decompose it into global spatial components and local spatial components; The connection edges between layout unit nodes in the global spatial component are abstracted to construct a graph structure describing the topological connection relationship of the layout. By vectorizing the node attributes and edge attributes of the graph structure, the structure-invariant features are obtained. Edge detection is performed on the local spatial components to extract the gradient magnitude and gradient direction of the map edges. The sensitive change features are obtained by directional encoding the gradient magnitude and gradient direction. The node attributes of the graph structure reflect the spatial position and geometry of the layout unit nodes, and the edge attributes of the graph structure reflect the connection relationship and connection strength between the layout unit nodes.

[0022] Spatial domain separation is performed on the original image data. This operation employs a multi-scale filtering method to decompose the original image data into global and local spatial components. Specifically, a Gaussian filter is used to perform a low-pass filter on the original image, resulting in a smoothed image as the global spatial component. Then, the original image is subtracted from the global spatial component to obtain the local spatial component, which contains detailed information. The kernel size of the filter is determined based on the minimum feature size of the layout, and is typically set to three times the minimum feature size.

[0023] The global spatial components are further processed to extract structure-invariant features. First, the global spatial components are binarized using an adaptive thresholding method to convert the image into a binary image. Next, connected component analysis is used to identify map unit nodes, with each connected region considered a node. For each node, its geometric attributes are calculated, including center coordinates, area, perimeter, aspect ratio, and other geometric parameters. Then, the spatial relationships between nodes are analyzed. When the Euclidean distance between two nodes is less than a preset threshold, they are considered connected, and a connecting edge is established. The attributes of the connecting edge include its length, orientation angle, and connection strength (determined by the overlapping area or proximity of the two nodes).

[0024] Based on the node and edge information described above, a graph structure describing the topological connections of the layout is constructed. This graph structure can be represented as G=(V,E), where V is the set of nodes and E is the set of edges. To facilitate subsequent processing, the graph structure is vectorized. For each node, its geometric attributes are encoded as a fixed-length feature vector; for each edge, its attributes are similarly encoded as a feature vector. Finally, all node feature vectors and edge feature vectors are combined to form a structure-invariant feature describing the overall topological structure of the layout.

[0025] For the local spatial components, edge detection is performed to extract sensitive change features. First, the Sobel operator is used to convolve the local spatial components, obtaining the horizontal gradient Gx and the vertical gradient Gy. Based on Gx and Gy, the gradient magnitude and direction of each pixel are calculated: the gradient magnitude is equal to √(Gx / Gy). 2 +Gy 2 The gradient direction is equal to arctan(Gy / Gx). To enhance edge details, non-maximum suppression is applied to the gradient magnitude image to retain local maximum gradient points, forming clear edge contours.

[0026] Subsequently, the processed gradient information is directionally encoded. The gradient direction is divided into eight equally divided directional intervals, corresponding to 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. For each pixel, a corresponding encoding value is assigned based on the interval its gradient direction falls into and the magnitude of the gradient. This directional encoding can effectively capture minute deformations and displacements at the edges of the layout, forming sensitive change features.

[0027] In practical applications, after the above processing, a typical chip layout area retains the main structural information of the layout in its global spatial components, such as functional unit blocks and signal lines; while the local spatial components contain subtle edge textures and fine structures. The extracted structure-invariant features are represented as a multi-dimensional vector, which contains a key description of the layout topology; the change-sensitive features are represented as a directional encoding matrix, which accurately records the change characteristics of the layout edges.

[0028] Structurally invariant features and change-sensitive features complement each other, together forming a comprehensive representation of the layout. Structurally invariant features ensure accurate identification of the overall layout and main functional units, even in the presence of slight image distortion; while change-sensitive features can capture minute local deformations and defects, improving detection sensitivity. This multi-path parallel decomposition method effectively improves the accuracy and robustness of layout defect detection.

[0029] In one alternative implementation, adversarial verification of the sensitive change features against a standard topology template includes: The sensitive change features are projected onto the feature space of the standard topology template to obtain the projected sensitive change feature representation; the distance metric between the projected sensitive change feature representation and the standard topology template is calculated to obtain the deviation vector. Based on the violation metric function, components in the deviation vector that exceed a preset tolerance range are identified as candidate locations for topological connection breaks; The gradient abrupt response of the sensitive change feature is extracted at the candidate location, and the abnormal region is determined by judging whether the gradient abrupt response satisfies the characteristic pattern of connection breakage. The violation metric function is constructed by establishing a mapping relationship between the connection integrity constraint vector of the standard topology template and the local change response vector of the sensitive change feature. The mapping relationship transforms node disconnection and edge loss at the topology level into gradient direction abrupt change and gradient magnitude jump at the pixel level.

[0030] In practical applications, the projection process can be implemented using a feature transformation matrix. Specifically, a transformation matrix T is constructed such that the original feature vector F, after transformation by this matrix, aligns with the feature space of the standard topological template. The transformation process is expressed as: F' = T·F, where F' is the projected feature representation. This transformation matrix T is obtained through pre-training, with training data including the features of normal samples and their corresponding representations in the standard space.

[0031] After projection, the distance metric between the projected features and the standard template is calculated. The distance calculation uses weighted Euclidean distance, assigning different weights to feature components of different dimensions to highlight the importance of key topological nodes. For image features, the deviation at each location (i,j) can be represented as the difference between the standard template feature S(i,j) and the projected feature F'(i,j), forming the deviation vector D.

[0032] The violation metric function is constructed based on the connectivity integrity constraints of the standard topological template. This function maps topological connectivity relationships to pixel-level gradient changes. Specifically, a topological node mapping table is first established to record key nodes in the standard template and their connectivity relationships; then, a gradient response pattern dictionary is constructed, containing the gradient direction and magnitude patterns of normal connections. The violation metric function V(D) evaluates whether each element in the deviation vector D exceeds a preset tolerance range Θ. If |D(i,j)|>Θ, then position (i,j) is marked as a candidate outlier.

[0033] To improve detection accuracy, candidate locations are further analyzed. At each candidate location (i,j), abrupt gradient responses are extracted, including gradient direction changes ΔG_dir and gradient magnitude changes ΔG_mag. At normal connections, the gradient should exhibit a smooth transition; while at breaks, the gradient direction will abruptly change, and the magnitude will show a significant jump. By comparing the actual abrupt gradient responses with preset break characteristic patterns, it is determined whether it is a true topological break point.

[0034] This method can also be effectively applied in industrial defect detection scenarios. When inspecting the soldering quality of circuit boards, a standard topology template represents the normal circuit connection pattern. By projecting the features of the circuit board to be inspected onto a standard space, a deviation vector is calculated, and potential defect points are identified using a violation metric function. At these candidate points, the gradient response is further analyzed. Solder breakpoints typically exhibit drastic changes in gradient direction and abrupt changes in brightness, which helps determine the location of soldering defects.

[0035] The aforementioned anomaly detection method effectively handles complex background interference. By analyzing the topological structure rather than relying solely on pixel value comparison, this method can distinguish between normal changes caused by factors such as illumination and pose, and genuine structural anomalies. Furthermore, the gradient feature-based verification mechanism improves detection reliability and reduces the false alarm rate.

[0036] In practical deployments, parameters can be adjusted to adapt to different application scenarios. The selection of the preset tolerance range Θ should be determined based on the fault tolerance requirements of the specific task; the setting of the gradient mutation threshold needs to balance detection sensitivity and noise resistance. For scenarios with high precision requirements, the threshold can be appropriately reduced; while in noisy environments, the threshold should be increased to reduce false detections.

[0037] In one alternative implementation, the construction of the violation metric function includes: The desired connection patterns of layout unit nodes are extracted from the standard topology template, and the desired connection patterns define the connection topology constraints between nodes in a defect-free layout. The actual gradient distribution pattern of the map edges is extracted from the sensitive change features. The actual gradient distribution pattern reflects the statistical distribution of the gradient direction and gradient magnitude of the edges in the map to be detected. A cross-layer mapping operator is established to map the desired connection pattern to the actual gradient distribution pattern, wherein the cross-layer mapping operator maps connection break events at the topology level to gradient anomaly events at the pixel level; The violation metric between the desired connection pattern and the actual gradient distribution pattern is calculated using the cross-layer mapping operator.

[0038] Extracting the desired connection patterns of layout cell nodes from a standard topology template is crucial in integrated circuit layout design, where each functional module has specific topology requirements. By analyzing a defect-free standard layout, a node connection relationship library can be established, containing the correct connection methods between various layout cells. Specifically, graph structure analysis is performed on the standard template, representing layout cells as a set of nodes V and connections between nodes as a set of edges E, forming a graph G=(V,E). For each node vi, its adjacent node set Ni and connection type Ti are extracted, thus obtaining the desired connection pattern Pi=(vi,Ni,Ti). For example, for conductor nodes in a metal layer, the desired connection pattern might require maintaining a certain spacing with adjacent conductors in a specific direction, or maintaining electrical connection with via nodes in the lower layer. These connection patterns constitute the basic criteria for judging whether there are defects in the layout.

[0039] Extracting the actual gradient distribution patterns of layout edges from sensitive variation features: Layout images acquired by scanning electron microscopy (SEM) or optical inspection equipment contain rich edge information, and the gradient features of these edges can effectively reflect the manufacturing quality of the layout. Specifically, the gradient operator is first applied to the acquired layout image I(x,y) to calculate the gradient vector field G(x,y)=(Gx,Gy), where Gx and Gy are the gradient components in the x and y directions, respectively. Then, the gradient magnitude M(x,y) and gradient direction θ(x,y) of each pixel are calculated. Based on this information, a gradient statistical histogram H(R) is constructed for each edge region R in the layout, recording the distribution of gradient direction and magnitude within that region. Normal edge regions typically exhibit consistent gradient directions and moderate magnitudes; while defective regions may exhibit chaotic gradient directions or abnormal magnitudes. These actual gradient distribution patterns provide pixel-level characterization of layout quality.

[0040] Establishing a cross-layer mapping operator from the desired connection pattern to the actual gradient distribution pattern is crucial for establishing the association between topological and pixel-level information. The mapping operator F is defined as a function that takes the connection pattern P at the topological level and the gradient distribution H at the pixel level as input, and outputs the consistency score S = F(P, H). In practical implementation, the spatial correspondence between topological nodes and image regions is first established, mapping the layout unit node vi to the region Ri in the image. For each pair of connected nodes (vi, vj), the edge region Rij at the connection should exhibit specific gradient characteristics. For example, for normally connected metal lines, the gradient direction of the edge region should be consistent with the design direction, and the gradient magnitude should be within a reasonable range. A mapping matrix W is constructed, where the element wij represents the expected relationship between the topological connection (i, j) and the gradient feature pattern H(Rij). When the actual gradient distribution deviates from the expectation, it may indicate defects such as breaks or short circuits in the connection.

[0041] A violation metric between the desired connection pattern and the actual gradient distribution pattern is calculated using a cross-layer mapping operator. For each node vi in ​​the layout, the degree of violation of all its connections is calculated. Let Pi be the desired connection pattern of node vi and Hi be the observed gradient distribution, then the violation metric Di of this node can be expressed as Di = D(Pi, Hi), where D is a metric function used to quantify the difference between the expected and actual patterns. In the multilayer structure of integrated circuits, different types of defects manifest as different modes of violation. For example, open-circuit defects typically manifest as abrupt disappearance of gradients at connections; short-circuit defects manifest as abrupt gradient changes at unexpected locations. By comprehensively considering the violation metrics of all nodes in the layout, a defect score for the overall layout can be obtained. When the violation metric of a certain region exceeds a preset threshold, the region is marked as a potential defect region, requiring further manual verification or automatic repair.

[0042] In practical applications, this cross-layer mapping violation metric function can effectively detect minute defects, which is particularly important for design verification at advanced process nodes. By continuously accumulating defect samples and optimizing the mapping operator, the detection accuracy of this method can be continuously improved, providing strong support for quality control in integrated circuit manufacturing.

[0043] In one optional implementation, calculating the violation metric between the desired connectivity pattern and the actual gradient distribution pattern using the cross-layer mapping operator includes: The expected connection vectors of the layout unit nodes are extracted from the expected connection patterns. The expected connection vectors describe the expected connection direction and expected connection strength between each layout unit node and its neighboring layout unit nodes. Extract the actual gradient vectors of the map edges from the actual gradient distribution pattern. The actual gradient vectors describe the gradient direction and gradient magnitude at each pixel location. The desired connection vector is projected onto the pixel space using the cross-layer mapping operator to obtain the desired gradient vector. The desired gradient vector represents the theoretical distribution of the gradient direction and gradient magnitude that the layout edge should exhibit under defect-free conditions. The gradient deviation vector is obtained by calculating the vector difference between the actual gradient vector and the expected gradient vector. The norm of the gradient deviation vector is calculated, and the norm value of the gradient deviation vector is used as the violation metric.

[0044] The expected connection vectors of layout cell nodes are extracted from the expected connection patterns. The expected connection vector is a data structure used to describe the expected connection direction and strength between each layout cell node and its neighboring layout cell nodes. Specifically, for each cell node in the layout, a multi-dimensional vector is established, where the direction component of the vector represents the connection direction between the node and its neighboring nodes, and the magnitude component represents the connection strength. For example, for a gate node in the chip layout, its expected connection vector may point towards both the source and drain directions, and the connection strength is determined according to design rules.

[0045] The actual gradient vectors of the map edges are extracted from the actual gradient distribution pattern. These actual gradient vectors describe the gradient direction and magnitude at each pixel location in the scanning electron microscope image. By applying gradient operators (such as the Sobel operator, Prewitt operator, or Canny edge detection operator) to the image, the horizontal and vertical gradients at each pixel location can be calculated, and then the gradient direction and magnitude can be synthesized. For example, the Sobel operator can be used to calculate the x-axis gradient Gx and y-axis gradient Gy, respectively. The gradient magnitude can then be obtained by calculating the square root of the sum of squares, and the gradient direction can be calculated using the arctangent function.

[0046] The desired gradient vector is obtained by projecting the desired connection vector onto the pixel space using a cross-layer mapping operator. The cross-layer mapping operator acts as a bridge between the layout design domain and the image measurement domain, taking into account factors such as optical imaging systems, electron beam scattering effects, and material response characteristics. In practice, the mapping relationship can be constructed based on physical models or data-driven methods. For example, the point spread function of an optical system can be simulated through convolution operations, or a trained neural network can be used to achieve the transformation from the layout domain to the image domain. The desired gradient vector characterizes the theoretical distribution of the gradient direction and magnitude that the layout edges should exhibit under defect-free conditions.

[0047] After obtaining the actual gradient vector and the expected gradient vector, the difference between them is calculated to obtain the gradient bias vector. For each location (x, y) in the image, the actual gradient vector is G_actual(x, y), and the expected gradient vector is G_expected(x, y). Then, the gradient bias vector D(x, y) can be expressed as the difference between the two: D(x, y) = G_actual(x, y) - G_expected(x, y). This step essentially quantifies the difference between the observed edge features and the theoretical expectations.

[0048] Finally, the norm of the gradient bias vector is calculated, and the norm value of the gradient bias vector is used as the violation metric. Norm calculation can be performed in various ways, such as L1 norm (Manhattan distance), L2 norm (Euclidean distance), or other norms suitable for specific application scenarios. Specifically, the norm can be calculated over the gradient bias vector across the entire image region, for example, using the L2 norm: Violation = √(∑∑|D(x,y)| 2 Different weights can be assigned to different regions as needed, or only the deviations within a specific region of interest can be considered.

[0049] In practical applications, a region-based processing strategy can be adopted to improve computational efficiency. For example, the chip layout can be divided into multiple sub-regions, the violation metric of each sub-region can be calculated separately, and then the overall evaluation result can be obtained by combining them. In addition, different weights can be assigned to gradient direction deviation and gradient magnitude deviation according to the sensitivity of different types of defects.

[0050] The violation metric calculated through the above steps can effectively quantify the degree of defects in actual images, and can then be used for subsequent tasks such as defect detection, classification, and localization. It is worth noting that a larger violation metric indicates a more severe deviation between the observed edge features and theoretical expectations, and a higher probability of defects.

[0051] In one optional implementation, determining the location and type information of the layout defect based on the spatial distribution of the abnormal region and the amplitude characteristics of the deviation vector includes: Spatial clustering analysis is performed on the abnormal regions to group together the abnormal regions that are spatially adjacent and whose deviation vector magnitudes differ by less than a preset deviation threshold into the same defect candidate region, thus obtaining several defect candidate regions; Calculate the weighted average of the spatial coordinates of all abnormal regions within the defect candidate region. The weight of the weighted average is determined by the magnitude of the deviation vector corresponding to the abnormal region. Use the spatial coordinates corresponding to the weighted average as the location information. Extract the amplitude statistical features of the deviation vector corresponding to each of the defect candidate regions. The amplitude statistical features include the peak amplitude of the deviation vector, the average amplitude of the deviation vector, and the amplitude variance of the deviation vector. Based on the amplitude statistical characteristics, the morphological feature parameters of the defect candidate region are calculated. These morphological feature parameters describe the spatial distribution shape and amplitude variation trend of the deviation vector within the defect candidate region. The morphological feature parameters are matched with a preset defect type feature library, which stores feature patterns of morphological feature parameters corresponding to different defect types. By calculating the similarity between the morphological feature parameters and the feature patterns of each defect type in the defect type feature library, the defect type with the highest similarity is selected as the type information.

[0052] Spatial clustering analysis is performed on the anomalous regions to group spatially adjacent anomalous regions whose deviation vector magnitude differences are less than a preset deviation threshold into the same defect candidate region, resulting in several defect candidate regions. In practical applications, density-based clustering algorithms such as DBSCAN can be used to cluster the anomalous regions. During the algorithm, two key parameters are set: a distance threshold ε and a minimum number of points MinPts. When the spatial Euclidean distance between two anomalous regions is less than ε and the difference in their deviation vector magnitudes is less than a preset deviation threshold δ (e.g., set as a percentage of the standard deviation), these two anomalous regions are considered to belong to the same cluster. For each anomalous region, if the number of points in its ε-neighborhood exceeds MinPts, it is considered a core point, and a cluster is formed starting from that point. In this way, all anomalous regions are clustered into several defect candidate regions, each of which may represent an independent layout defect.

[0053] Next, the weighted average of the spatial coordinates of all abnormal regions within the defect candidate region is calculated. The weight of the weighted average is determined by the magnitude of the deviation vector corresponding to the abnormal region. The spatial coordinates corresponding to the weighted average are used as the location information.

[0054] With this weighting method, abnormal areas with larger deviation amplitudes contribute more to the location of defects, which helps to locate the defect center more accurately, since the deviation amplitude is usually positively correlated with the severity of the defect.

[0055] The amplitude statistical features of the deviation vector corresponding to each candidate defect region are extracted. These amplitude statistical features include the peak amplitude, the average amplitude, and the amplitude variance of the deviation vector. For each candidate defect region, the maximum amplitude of the deviation vectors of all abnormal regions within it is calculated as the peak amplitude `max_m`, the arithmetic mean of all amplitudes is calculated as the average amplitude `avg_m`, and the amplitude variance is calculated as the amplitude variance `var_m`. These three statistics together describe the distribution characteristics of the deviation vector amplitudes within the defect region, providing an important basis for subsequent defect type identification.

[0056] Based on the amplitude statistical characteristics, morphological feature parameters of the defect candidate region are calculated. These morphological feature parameters describe the spatial distribution and amplitude variation trend of the deviation vector within the defect candidate region. The morphological feature parameters include, but are not limited to: the spatial extent of the defect region (obtainable by calculating the minimum bounding box containing all anomalous regions); the shape characteristics of the defect region (e.g., obtained by calculating the principal axis direction and anisotropy of the anomalous region distribution); and the radial distribution characteristics of the deviation vector amplitude (obtained by calculating the amplitude variation gradient from the defect center outwards). Spatial correlation of amplitude variations and directional consistency of the deviation vector can also be calculated.

[0057] For example, point defects typically exhibit a circular distribution of abnormal areas, with the largest amplitude at the center and gradually decreasing outwards; line defects often extend along a certain direction, exhibiting a clear linear characteristic; and area defects may present a large, uniformly distributed area with relatively gentle amplitude changes. These different types of defect morphological characteristics can be quantified mathematically to form feature vectors.

[0058] The morphological feature parameters are matched with a preset defect type feature library, which stores feature patterns of morphological feature parameters corresponding to different defect types. The similarity between the morphological feature parameters and the feature patterns of each defect type in the feature library is calculated, and the defect type with the highest similarity is selected as the type information. In practical applications, cosine similarity, Euclidean distance, or Mahalanobis distance can be used to calculate the similarity between the morphological feature vector of the current defect candidate region and the templates of each type in the feature library. Assuming the morphological feature vector of the current defect is F, and the feature vector of a certain type of defect in the feature library is Ti, their cosine similarity can be calculated: similarity = (F·Ti) / (|F|×|Ti|); Where F·Ti represents the dot product of two vectors, and |F| and |Ti| represent the magnitudes of the vectors. The similarity between the current defect and all types in the feature library is calculated, and the type with the highest similarity is selected as the type identification result for the defect. To improve recognition accuracy, a similarity threshold can be set. When the highest similarity is below this threshold, the defect is marked as "unknown type" and awaits further manual analysis.

[0059] Through the above steps, precise location and automatic identification of layout defects are achieved, providing an important basis for subsequent defect repair and quality control. Defect location information is represented using weighted coordinates, while defect type information is determined based on the matching results of morphological feature parameters and a preset feature library. Together, they constitute a complete description of the layout defect.

[0060] This invention provides a layout intelligent defect recognition system based on hierarchical deep learning, comprising: The first unit is used to acquire the original image data of the map to be detected; to perform multi-path parallel decomposition on the original image data, extract structurally invariant features reflecting the geometric consistency of the map, and extract sensitive change features reflecting local deformation of the map. The structurally invariant features are obtained by graph structure encoding of the topological connectivity of the map, and the sensitive change features are obtained by directional encoding of the gradient changes at the map edges. The second unit is used to construct a standard topology template for the layout based on the structurally invariant features. The standard topology template is used to characterize the connection integrity constraints of the defect-free layout. The third unit is used to perform adversarial verification between the sensitive change features and the standard topological template. By calculating the deviation vector of the sensitive change features from the standard topological template, abnormal regions that disrupt the integrity of topological connections are identified. The adversarial verification is achieved by establishing a violation metric function of the sensitive change features against the standard topological template. The violation metric function maps the connection breaks at the topological level to gradient abrupt responses at the pixel level. The fourth unit is used to determine the location and type information of the layout defect based on the spatial distribution of the abnormal area and the amplitude characteristics of the deviation vector; and to generate and output the defect identification result based on the location and type information.

[0061] A third aspect of the present invention provides an electronic device, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0062] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0063] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A layout intelligent defect recognition method based on hierarchical deep learning, characterized in that, include: The original image data of the map to be detected is acquired; the original image data is decomposed into multiple paths in parallel to extract structurally invariant features reflecting the geometric consistency of the map and sensitive variation features reflecting local deformation of the map. The structurally invariant features are obtained by graph structure encoding of the topological connectivity of the map, and the sensitive variation features are obtained by directional encoding of the gradient changes at the map edges. A standard topology template for the layout is constructed based on the aforementioned structural invariant features. This standard topology template is used to characterize the connectivity integrity constraints of a defect-free layout. The sensitive change features are subjected to adversarial verification against the standard topological template. By calculating the deviation vector of the sensitive change features from the standard topological template, abnormal regions that disrupt the integrity of topological connections are identified. The adversarial verification is achieved by establishing a violation metric function of the sensitive change features against the standard topological template. The violation metric function maps the connection breaks at the topological level to gradient abrupt responses at the pixel level. Based on the spatial distribution of the abnormal region and the amplitude characteristics of the deviation vector, the location and type information of the layout defect are determined; based on the location and type information, a defect identification result is generated and output.

2. The method according to claim 1, characterized in that, The original image data is subjected to multi-path parallel decomposition to extract structurally invariant features reflecting the geometric consistency of the layout, and sensitive variation features reflecting local deformation of the layout are extracted, including: A spatial domain separation operation is performed on the original image data to decompose it into global spatial components and local spatial components; The connection edges between layout unit nodes in the global spatial component are abstracted to construct a graph structure describing the topological connection relationship of the layout. By vectorizing the node attributes and edge attributes of the graph structure, the structure-invariant features are obtained. Edge detection is performed on the local spatial components to extract the gradient magnitude and gradient direction of the map edges. The sensitive change features are obtained by directional encoding the gradient magnitude and gradient direction. The node attributes of the graph structure reflect the spatial position and geometry of the layout unit nodes, and the edge attributes of the graph structure reflect the connection relationship and connection strength between the layout unit nodes.

3. The method according to claim 1, characterized in that, Adversarial validation of sensitive change features against standard topology templates includes: The sensitive change features are projected onto the feature space of the standard topology template to obtain the projected sensitive change feature representation; the distance metric between the projected sensitive change feature representation and the standard topology template is calculated to obtain the deviation vector. Based on the violation metric function, components in the deviation vector that exceed a preset tolerance range are identified as candidate locations for topological connection breaks; The gradient abrupt response of the sensitive change feature is extracted at the candidate location, and the abnormal region is determined by judging whether the gradient abrupt response satisfies the characteristic pattern of connection breakage. The violation metric function is constructed by establishing a mapping relationship between the connection integrity constraint vector of the standard topology template and the local change response vector of the sensitive change feature. The mapping relationship transforms node disconnection and edge loss at the topology level into gradient direction abrupt change and gradient magnitude jump at the pixel level.

4. The method according to claim 3, characterized in that, The construction of the violation metric function includes: The desired connection patterns of layout unit nodes are extracted from the standard topology template, and the desired connection patterns define the connection topology constraints between nodes in a defect-free layout. The actual gradient distribution pattern of the map edges is extracted from the sensitive change features. The actual gradient distribution pattern reflects the statistical distribution of the gradient direction and gradient magnitude of the edges in the map to be detected. A cross-layer mapping operator is established to map the desired connection pattern to the actual gradient distribution pattern, wherein the cross-layer mapping operator maps connection break events at the topology level to gradient anomaly events at the pixel level; The violation metric between the desired connection pattern and the actual gradient distribution pattern is calculated using the cross-layer mapping operator.

5. The method according to claim 4, characterized in that, Calculating the violation metric between the desired connectivity pattern and the actual gradient distribution pattern using the cross-layer mapping operator includes: The expected connection vectors of the layout unit nodes are extracted from the expected connection patterns. The expected connection vectors describe the expected connection direction and expected connection strength between each layout unit node and its neighboring layout unit nodes. Extract the actual gradient vectors of the map edges from the actual gradient distribution pattern. The actual gradient vectors describe the gradient direction and gradient magnitude at each pixel location. The desired connection vector is projected onto the pixel space using the cross-layer mapping operator to obtain the desired gradient vector. The desired gradient vector represents the theoretical distribution of the gradient direction and gradient magnitude that the layout edge should exhibit under defect-free conditions. The gradient deviation vector is obtained by calculating the vector difference between the actual gradient vector and the expected gradient vector. The norm of the gradient deviation vector is calculated, and the norm value of the gradient deviation vector is used as the violation metric.

6. The method according to claim 1, characterized in that, Based on the spatial distribution of the abnormal region and the amplitude characteristics of the deviation vector, the location and type information of the layout defect are determined, including: Spatial clustering analysis is performed on the abnormal regions to group together the abnormal regions that are spatially adjacent and whose deviation vector magnitudes differ by less than a preset deviation threshold into the same defect candidate region, thus obtaining several defect candidate regions; Calculate the weighted average of the spatial coordinates of all abnormal regions within the defect candidate region. The weight of the weighted average is determined by the magnitude of the deviation vector corresponding to the abnormal region. Use the spatial coordinates corresponding to the weighted average as the location information. Extract the amplitude statistical features of the deviation vector corresponding to each of the defect candidate regions. The amplitude statistical features include the peak amplitude of the deviation vector, the average amplitude of the deviation vector, and the amplitude variance of the deviation vector. Based on the amplitude statistical characteristics, the morphological feature parameters of the defect candidate region are calculated. These morphological feature parameters describe the spatial distribution shape and amplitude variation trend of the deviation vector within the defect candidate region. The morphological feature parameters are matched with a preset defect type feature library, which stores feature patterns of morphological feature parameters corresponding to different defect types. By calculating the similarity between the morphological feature parameters and the feature patterns of each defect type in the defect type feature library, the defect type with the highest similarity is selected as the type information.

7. A layout intelligent defect recognition system based on hierarchical deep learning, used to implement the method as described in any one of claims 1-6, characterized in that, include: The first unit is used to acquire the original image data of the map to be detected; to perform multi-path parallel decomposition on the original image data, extract structurally invariant features reflecting the geometric consistency of the map, and extract sensitive change features reflecting local deformation of the map. The structurally invariant features are obtained by graph structure encoding of the topological connectivity of the map, and the sensitive change features are obtained by directional encoding of the gradient changes at the map edges. The second unit is used to construct a standard topology template for the layout based on the structurally invariant features. The standard topology template is used to characterize the connection integrity constraints of the defect-free layout. The third unit is used to perform adversarial verification between the sensitive change features and the standard topological template. By calculating the deviation vector of the sensitive change features from the standard topological template, abnormal regions that disrupt the integrity of topological connections are identified. The adversarial verification is achieved by establishing a violation metric function of the sensitive change features against the standard topological template. The violation metric function maps the connection breaks at the topological level to gradient abrupt responses at the pixel level. The fourth unit is used to determine the location and type information of the layout defect based on the spatial distribution of the abnormal area and the amplitude characteristics of the deviation vector; and to generate and output the defect identification result based on the location and type information.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

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