Cascade multi-level energy storage converter topology and control method thereof

Abstract

The invention discloses a cascade multi-level energy storage converter topology and a control method thereof, the DC input side of the topology adopts half-bridge sub-modules powered by independent batteries to be connected in series in groups, and the AC output side adopts multiple groups of H-bridge inversion units to be connected in series to form a secondary cascade structure. According to the topology, by flexibly configuring the number of battery packs and the number of half-bridge sub-modules in each group, the optimal balance between the number of switching devices and the voltage stress of the devices is realized, and the topology has the advantages of a cascaded H-bridge topology and a cascaded half-bridge topology. In the control method level, a switching device is controlled based on carrier stacking modulation and zero crossing point modulation, a double-closed-loop quasi-proportional resonance controller is adopted to carry out closed-loop control on an output voltage waveform, an equalization algorithm based on battery state parameter sorting is combined, high-quality multi-level output is achieved, and meanwhile battery online energy equalization is completed. The problems that a multi-level energy storage converter is large in traditional topology device number, high in cost, large in high-voltage device stress, poor in expansibility, difficult in battery management and the like are solved.

Description

Technical Field

[0001] This invention relates to a cascaded multilevel energy storage converter topology and its control method, belonging to the field of power electronic converter technology. Background Technology

[0002] Driven by the global energy transition and the "dual carbon" goal, the penetration rate of renewable energy sources, represented by photovoltaics and wind power, in the power system continues to increase. However, the inherent intermittency, volatility, and uncertainty of renewable energy pose serious challenges to the frequency stability, power balance, and power quality of the power grid. Against this backdrop, energy storage systems, especially electrochemical energy storage, have become a key technological support for smoothing renewable energy output, participating in grid frequency regulation, and achieving peak shaving and valley filling, due to their flexible adjustment capabilities, rapid response speed, and modular deployment characteristics.

[0003] The core objective of energy storage systems is to achieve efficient, controllable, and reliable energy management. Traditional electrochemical energy storage system integration schemes often use battery packs connected in series and parallel to provide DC bus voltage, followed by two-level or multi-level inverters to complete energy conversion. Although this approach is simple in structure, it has several drawbacks: First, the operation of a large number of batteries in series and parallel limits the overall system performance to the worst-performing battery cell, significantly reducing the system's usable capacity and cycle life; second, system capacity expansion relies on simple battery stacking, but increasing the number of batteries exacerbates problems caused by inconsistent battery parameters; and third, energy requires multiple stages of conversion before being connected to the grid, resulting in low system cycle efficiency.

[0004] To overcome the aforementioned bottlenecks, cascaded multilevel converter topologies have emerged. As a feasible solution for achieving high-voltage, high-capacity power conversion, cascaded multilevel converters have been widely researched and applied. The core idea of ​​this topology is to synthesize a high-voltage, low-harmonic-distortion stepped waveform using low-voltage switching devices through the series connection of multiple power units. This overcomes many bottlenecks of traditional multilevel converters in high-voltage applications, such as electromagnetic interference and the large requirements for output filters. This type of converter has demonstrated irreplaceable advantages in medium- and high-voltage motor drives, active power filters, and large-scale renewable energy storage system grid connection scenarios.

[0005] In cascaded topologies, the cascaded H-bridge (CHB) converter is one of the most widely used topologies due to its high modularity and relatively simple control. However, the CHB topology requires each H-bridge unit to be powered by an independent, voltage-isolated DC power supply. When applied to battery energy storage systems, each individual battery pack or battery array requires an H-bridge as an output inverter. To obtain higher AC output voltages, dozens or even hundreds of H-bridge units need to be connected in series. This results in a linear increase in the number of switching devices with the output voltage level, significantly increasing system cost, control complexity, and size. To address the problem of excessive switching requirements under high voltage in the CHB topology, the academic community has proposed a cascaded half-bridge converter with opposite outputs on both arms and a cascaded half-bridge converter that shares an H-bridge for inverter on the output side. The cascaded half-bridge converter with opposite outputs on both arms generates positive and negative levels by connecting two arms with opposite output polarities in series. Although its submodule structure is simpler than that of the H-bridge (containing only 2 switches), and it has greater energy storage capacity and energy management capabilities with the same number of switching devices, it requires twice as many submodules to generate the same number of output levels as the CHB, resulting in no reduction in the total number of switching devices. The cascaded half-bridge converter topology, which shares an H-bridge inverter on the output side, connects the DC-side outputs of all half-bridge submodules in series and inverts them through a shared H-bridge. This structure does reduce the number of switching devices for the same number of output levels, making it very attractive in terms of cost; however, the switching devices of its H-bridge must withstand the sum of the DC voltages of all the series-connected half-bridge submodules. Therefore, the H-bridge devices must use high-voltage devices, which are expensive, have high switching losses, and are generally less reliable than mature medium- and low-voltage devices. Furthermore, the voltage level expansion capability of the entire system is limited by the withstand voltage level of the single H-bridge. Upgrades and expansions often require redesigning the H-bridge unit, resulting in poor scalability and limiting the application of this topology in complex scenarios.

[0006] Therefore, the industry urgently needs a new topology and control solution that can achieve breakthroughs in cost, reliability, and scalability at the same time. Summary of the Invention

[0007] The technical problem to be solved by this invention is to provide a cascaded multilevel energy storage converter topology and its control method, which solves the problems of large number of switching devices, high cost, high stress of high voltage devices, and limited system scalability in the application of existing cascaded multilevel converters in the field of battery energy storage.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A cascaded multilevel energy storage converter topology includes a DC input side and an AC output side, wherein the DC input side includes first to M battery packs connected in series, and the m-th battery pack includes... A series of half-bridge submodules connected in series, 1≤m≤M, M and All are integers not less than 2; The AC output side includes the first to the Mth H-bridge inverter units connected in series. Each H-bridge inverter unit corresponds to a battery pack. The DC input terminal of the mth H-bridge inverter unit is directly connected to the output terminal of the mth battery pack. The mth H-bridge inverter unit is responsible for the power conversion of the mth battery pack. The input terminal of an LC low-pass filter is connected to the AC output side, and the output terminal of the LC low-pass filter is connected to a load in parallel. The LC low-pass filter is used to smooth the voltage waveform on the AC output side to the required load voltage waveform.

[0009] A control method based on the above-mentioned cascaded multilevel energy storage converter topology is divided into a switching transistor control strategy, a voltage closed-loop control strategy, and a battery energy balancing strategy. For the switching transistor control strategy, the converter employs a carrier stacked modulation strategy to control each half-bridge switching device on the input side and a zero-crossing modulation strategy to control each H-bridge switching device on the output side. For the voltage closed-loop control strategy, the converter uses a dual-closed-loop quasi-proportional resonant controller to perform closed-loop control of the converter output, ensuring high output waveform quality and dynamic characteristics. For the battery energy balancing strategy, the converter adopts a balancing algorithm based on battery state parameters, synchronously achieving online battery energy balancing during normal converter operation, without requiring an additional balancing circuit.

[0010] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects: 1. The topology of this invention can achieve an optimal balance between the number of devices and voltage stress. The topology parameters can be flexibly configured according to the application environment, effectively controlling system cost, while taking into account the scalability of energy storage capacity and efficient battery management performance.

[0011] 2. When the number of battery packs is not less than 2, the topology H-bridge unit does not need to bear the full DC voltage, and medium- and low-voltage high-reliability devices can be used.

[0012] 3. The control method of the topology of this invention is suitable for high-level inverter scenarios, and the output waveform has low harmonic content. Furthermore, the energy balancing strategy, based on a sorting algorithm, achieves automatic and lossless battery energy balancing during converter operation, which can improve battery life and requires no additional hardware circuitry. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating the structure and principle of a cascaded multilevel energy storage converter system topology and its control method according to the present invention; Figure 2 This is a schematic diagram of the topology of a cascaded multilevel energy storage converter system according to an embodiment of the present invention; Figure 3This is a schematic diagram of the LSPWM modulation method applied to the half-bridge submodule in an embodiment of the present invention; Figure 4 This is a schematic diagram of the zero-crossing modulation method applied to the H-bridge in an embodiment of the present invention; Figure 5 This is a diagram showing the relationship between the control signal of the half-bridge submodule and the DC output voltage in an embodiment of the present invention; Figure 6 This is a diagram showing the relationship between the H-bridge modulation signal and the AC output voltage in an embodiment of the present invention; Figure 7 This is a block diagram of the dual closed-loop QPR control in an embodiment of the present invention; Figure 8 This is a logic block diagram of the online battery energy balancing algorithm based on SOC sorting in an embodiment of the present invention. Detailed Implementation

[0014] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0015] This invention provides a novel cascaded multilevel energy storage converter topology and its control method. The core of the cascaded multilevel energy storage converter topology lies in a "secondary cascading" structure. Based on the cascading of the AC output side of a traditional topology (such as CHB), a second layer of cascading is introduced on the input side, namely, the series connection of half-bridge submodules. This topology adopts a cascading mode on both the input and output sides. By flexibly combining the grouped series half-bridge submodules with the H-bridge inverter unit, an optimal balance is achieved between the number of switching devices, device voltage stress, system cost, and scalability.

[0016] like Figure 1 As shown, the DC input side of the topology system consists of M battery packs. The m-th (1≤m≤M) battery pack consists of... The system consists of N half-bridge submodules connected in series. The entire topology has N half-bridge submodules, all powered by independent batteries. N represents the total number of independently controllable energy storage units in the system, and M ≤ N. M is an integer not less than 2, representing the number of groups in the system. Also an integer not less than 2, representing the number of half-bridge submodules contained in the m-th battery pack. For different battery packs, The value of can be different, which provides great flexibility for system design and allows for customized design based on actual battery configuration and voltage requirements.

[0017] Each half-bridge submodule contains an independent energy storage battery (with... This indicates the battery voltage of the i-th submodule within the m-th battery pack, where 1 ≤ i ≤ 1. It uses a half-bridge structure with two power switches (such as IGBTs or MOSFETs) and can optionally connect a filter capacitor in parallel with the battery to filter out high-frequency harmonics. This structure allows each submodule to operate in two basic states: when the upper switch is on and the lower switch is off, the submodule outputs its battery voltage; when the lower switch is on and the upper switch is off, the submodule is short-circuited and the output voltage is zero.

[0018] The amplitude of the input DC voltage of the topology is the sum of the voltages of all energy storage batteries, that is: , If we assume that the rated voltage of each battery is E, and the number of submodules in all battery packs is equal (i.e., Then the total DC input voltage can be simplified to: , This input-side series configuration can generate the high DC bus voltage required by the system.

[0019] The topology output side consists of M H-bridge inverter units connected in series on the AC side. Each H-bridge inverter unit independently withstands the DC voltage of its corresponding battery pack and completes the DC-to-AC power conversion. Each H-bridge inverter unit is a standard full-bridge circuit, consisting of four power switches and their anti-parallel diodes. The DC input terminal of the m-th (1≤m≤M) H-bridge inverter unit is directly connected to the output terminal of the m-th battery pack. Therefore, each H-bridge inverter unit only withstands the DC voltage of its corresponding battery pack, not the total DC voltage of the entire system. Assume the m-th battery pack contains... The battery voltage of the i-th submodule is At that time, the voltage stress borne by the H-bridge inverter unit corresponding to the battery pack is: , If the rated voltage of each battery is E, then the above formula is: , This significantly reduces the voltage stress requirements on individual H-bridge switching devices.

[0020] The system's total AC output voltage waveform is formed by superimposing the AC voltages output from M H-bridge inverter units. An LC low-pass filter is connected to the output side of the topology to smooth the output voltage waveform to the desired load voltage waveform. The maximum number of output levels is determined solely by the number of submodules N, and is independent of the number of H-bridges. A system consisting of N submodules and M H-bridge units can generate (2N+1) output voltage levels. The total number of switching devices in the system is 4M+2N, where 4M represents the total number of switches in all H-bridge units, and 2N represents the total number of switches in all half-bridge submodules.

[0021] Given a fixed total capacity for the energy storage system, by rationally configuring M and The value of M allows system designers to weigh various performance metrics such as system reliability and complexity: by increasing the number of groups M and reducing the number of modules within each group. This significantly reduces the DC voltage across each H-bridge unit, allowing the system to utilize more mature low- and medium-voltage power devices, improving reliability and maintainability, and facilitating redundant design; by reducing the number of groups M and increasing the number of modules within each group... This can reduce the number of switching devices without changing the maximum output voltage, which helps to reduce system cost and complexity.

[0022] This invention employs a Level-Shifted Pulse Width Modulation (LSPWM) strategy based on carrier stacking to generate the switching signals for all half-bridge submodules. For a system containing N half-bridge submodules, the controller pre-generates N sets of triangular carriers that are in phase and continuously stacked in amplitude. The value range of the nth set of carriers (1≤n≤N) is [n-1,n], so the amplitude of all carriers covers the range [0,N]. The modulation wave is a half-sine wave, obtained by taking the absolute value of a reference sine wave. According to the principle of PWM modulation, the frequency and phase of the controller's modulation wave are consistent with the output. The modulation wave signal is compared with the N sets of carriers to obtain N sets of complementary PWM signals, which are used to drive all the preceding half-bridge submodules. For the nth half-bridge submodule, when the carrier amplitude is less than the instantaneous value of the modulation wave, the upper transistor is turned on and the lower transistor is turned off, and the submodule outputs the battery voltage; when the carrier amplitude is greater than the instantaneous value of the modulation wave, the upper transistor is turned off and the lower transistor is turned on, the submodule is short-circuited, and the output is zero.

[0023] This invention employs a zero-crossing modulation strategy to generate the switching signals for all H-bridge inverter units. By detecting the zero-crossing point of a reference sine wave, a square wave signal with the same frequency and phase as the reference sine wave and a constant duty cycle of 0.5 is generated. When the square wave signal is high, transistors S1 and S4 of all H-bridge inverter units are turned on, while transistors S2 and S3 are turned off, and the topology output side outputs v. b This is the positive half-axis voltage waveform; when the control signal is low, all H-bridge transistors S1 and S4 are turned off, while transistors S2 and S3 are turned on, and the topology output side outputs v. b This is the voltage waveform of the negative half-axis.

[0024] In closed-loop control mode, this invention employs a dual-loop quasi-proportional resonant control strategy for output voltage control, ensuring high output waveform quality and dynamic characteristics. The outer loop voltage control uses a quasi-proportional resonant (QPR) controller, which generates the inner loop current reference signal by detecting the difference between the reference voltage and the actual output voltage. Setting the resonant frequency of the QPR controller at the power frequency provides extremely high gain for that frequency component, thereby achieving zero steady-state error tracking of the output voltage to the reference value. The inner loop current control also uses a QPR controller, generating the final modulated wave signal by detecting the difference between the sum of the outer loop reference and the load current, and the inductor current. The fast response characteristics of the current loop effectively suppress harmonic components near the switching frequency, improving output waveform quality.

[0025] This invention employs a control strategy based on battery state parameters for battery energy balancing, achieving online battery energy balancing synchronously during normal converter operation without the need for additional balancing circuitry. The balancing control operates at preset balancing time intervals. Execute periodically. The value can be adjusted according to battery characteristics to ensure balancing effect while avoiding excessive computation. Taking the converter discharging the load as an example, at the balancing trigger moment, the controller has collected and calculated the real-time state parameters of all energy storage batteries and sorted them in descending order. Taking the battery discharge condition as an example, using SOC as the state parameter, the strategy allocates the carrier with the lowest amplitude to the submodule corresponding to the battery with the highest SOC, and the remaining batteries are assigned carriers with amplitudes from low to high in order of SOC. The high SOC battery is allocated a longer discharge time in one cycle, thus undertaking more discharge power, and after a period of operation, the energy of all batteries is finally dynamically balanced. When the converter is charged by an external power supply, the above logic is reversed. The carriers allocated to each submodule in the entire balancing cycle... The internal balance remains constant, and when the next equalization trigger arrives, it is updated according to the latest SOC sorting result. Due to the inherent characteristics of carrier stacked modulation, the amplitude of a carrier with a lower amplitude is less than the instantaneous value of the modulation wave for a longer period within a modulation wave cycle. Consequently, the corresponding submodule output is zero for a shorter period, resulting in a larger rate of change in battery power. After a period of operation, the converter can achieve automatic battery energy equalization without the need for additional equalization circuitry.

[0026] The following will describe in detail the implementation of the present invention using a symmetric parametric topology with M=2 and N=8 as an example.

[0027] like Figure 2 As shown, a converter topology example with M=2 and N=8 is analyzed, where the converter operates in a load discharge state. The AC output side of the converter consists of two H-bridges connected in series, namely switches S...11 -S 14 With S 21 -S 24 The DC input side contains two battery packs, each with four half-bridge submodules. Each half-bridge submodule has identical parameters, including an independent energy storage battery (voltage E) and a half-bridge circuit (two switches K1 and K2). To filter out potential high-frequency interference, each battery is also connected in parallel with a filter capacitor C. The AC output side is connected to a purely resistive load after an LC low-pass filter. powered by.

[0028] like Figure 3 As shown, the carrier signal generator pre-generates 8 sets of triangular carriers with the same frequency and phase, a peak-to-peak value of 1, and continuously stacked amplitudes. The amplitudes of all carriers are between [0, 8]. First, the amplitude U of the reference sine wave is scaled to between [-8, 8] to obtain a new sine wave signal with an amplitude of The scaling formula is: , in, This is the sum of the voltages of the eight battery groups. The signal is then converted into a sine half-wave by an absolute value module, which serves as the modulation wave for the PWM. Controller A, responsible for controlling the front-end half-bridge, compares the two signals to generate eight PWM signals (PWM1-PWM8), which are then output and distributed to the eight half-bridge sub-modules.

[0029] like Figure 4 As shown, controller B, responsible for controlling the subsequent H-bridge, determines the zero-crossing point of the reference sine wave. When the amplitude of the reference sine wave is greater than zero, the controller outputs a positive level; when the amplitude of the reference sine wave is less than zero, the controller outputs a zero level. Through the above control logic, the output of controller B is a square wave signal S with the frequency of the reference sine wave.

[0030] like Figure 5 As shown, when the modulation signal of the half-bridge submodule is high, the upper half-bridge switch K1 is turned on and the lower half-bridge switch K2 is turned off, and the submodule output voltage is the battery voltage E; when the modulation signal is low, the upper half-bridge switch K1 is turned off and the lower half-bridge switch K2 is turned on, the submodule is short-circuited, and the output voltage is zero.

[0031] like Figure 6 As shown, when the H-bridge modulation signal is high, all S1 and S4 transistors of the H-bridge are turned on, and S2 and S3 transistors are turned off, resulting in an AC output voltage of V. b This is the positive half-axis voltage waveform; when the control signal is low, all H-bridge transistors S1 and S4 are turned off, while transistors S2 and S3 are turned on, and the AC output side outputs V. b This is the voltage waveform of the negative half-axis.

[0032] like Figure 7As shown, in this embodiment of the invention, a dual-closed-loop QPR control strategy is adopted when using closed-loop control. The controller samples the load voltage v. o The input signal to the voltage loop is obtained by subtracting the reference voltage from the input signal. After passing through the QPR controller of the voltage loop, the reference current signal of the current loop is output. Considering that filters often adopt an integrated design, capacitor current acquisition is relatively difficult. Therefore, the controller acquires the inductor current and the load current, and the difference between the two yields the capacitor current. The input signal to the current loop is obtained by subtracting the reference current from the capacitor current. After passing through the QPR controller of the current loop, the final closed-loop modulated wave signal is obtained. This signal is used to replace... Figure 3 , Figure 4 The closed-loop control can be completed using the reference sine wave of the modulation strategy shown.

[0033] like Figure 8 As shown, this embodiment of the invention uses a method based on SOC sorting and carrier reallocation to achieve battery energy balancing. Before the balancing time arrives, the controller estimates the SOC parameters of all eight batteries and sorts them in descending order. Based on the sorting result, a carrier-submodule signal reallocation is performed: the submodule corresponding to the battery with the highest SOC is assigned to the carrier with the lowest amplitude, while the battery with the lowest SOC is assigned to the carrier with the highest amplitude. The remaining batteries are assigned to the remaining carriers in descending order of SOC. High SOC batteries bear more discharge power in one balancing cycle, and after a period of operation, the converter achieves automatic energy balancing for all batteries.

[0034] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A cascaded multilevel energy storage converter topology, characterized in that, The converter topology includes a DC input side and an AC output side, wherein the DC input side includes the first to the Mth battery packs connected in series, and the mth battery pack includes... A series of half-bridge submodules connected in series, 1≤m≤M, M and All are integers not less than 2; The AC output side includes the first to the Mth H-bridge inverter units connected in series. Each H-bridge inverter unit corresponds to a battery pack. The DC input terminal of the mth H-bridge inverter unit is directly connected to the output terminal of the mth battery pack. The mth H-bridge inverter unit is responsible for the power conversion of the mth battery pack. The input terminal of an LC low-pass filter is connected to the AC output side, and the output terminal of the LC low-pass filter is connected to a load in parallel. The LC low-pass filter is used to smooth the voltage waveform on the AC output side to the required load voltage waveform.

2. The cascaded multilevel energy storage converter topology according to claim 1, characterized in that, The half-bridge submodule includes an energy storage battery and two power switching transistors, an upper one and a lower one. The half-bridge submodule operates in two states: when the upper power switching transistor is turned on and the lower power switching transistor is turned off, the half-bridge submodule outputs the corresponding energy storage battery voltage; when the upper power switching transistor is turned off and the lower power switching transistor is turned on, the half-bridge submodule is short-circuited and the output voltage is zero.

3. The cascaded multilevel energy storage converter topology according to claim 1, characterized in that, The H-bridge inverter unit is a full-bridge circuit, including the first to fourth power switches, with a diode connected in anti-parallel to each power switch.

4. The cascaded multilevel energy storage converter topology according to claim 1, characterized in that, The AC voltage output from the AC output side is the sum of the AC voltages output from M H-bridge inverter units. The maximum number of output levels in the topology is 2N+1, where N is the number of all half-bridge submodules in the M battery packs, and M≤N.

5. A control method based on the cascaded multilevel energy storage converter topology according to any one of claims 1-4, characterized in that, The control method is as follows: At each moment, a pulse width modulation strategy based on carrier stacking is used to generate switching signals to control all half-bridge submodules, a zero-crossing modulation strategy is used to generate switching signals to control all H-bridge inverter units, and a dual-closed-loop quasi-proportional resonant control strategy is used to perform closed-loop control of the output voltage; wherein, The pulse width modulation strategy based on carrier stacking is as follows: N sets of triangular carriers, in phase and continuously stacked in amplitude, are pre-generated. N is the number of all half-bridge submodules in the M battery packs. The value range of the nth triangular carrier is [n-1, n]. Therefore, the amplitude of all triangular carriers is between [0, N], where 1 ≤ n ≤ N. At the initial moment, the absolute value of the externally provided reference voltage sine wave is taken to obtain the modulation signal. The modulation signal at other moments is the modulation signal generated by the dual-closed-loop quasi-proportional resonant control strategy at the previous moment. The voltage amplitude when all half-bridge submodules are in use is... Based on the required load voltage amplitude U, the amplitude of the modulated wave signal is... for: ， N sets of triangular carrier waves are compared with the modulation wave signal to obtain N sets of complementary PWM signals to drive all half-bridge sub-modules. For the nth half-bridge module, when the carrier wave amplitude is less than the modulation wave signal amplitude, the upper power switch is turned on and the lower power switch is turned off, and the nth half-bridge module outputs the corresponding energy storage battery voltage. When the carrier amplitude is greater than the modulation signal amplitude, the upper power switch is turned off and the lower power switch is turned on, the nth half-bridge submodule is short-circuited, and the output is 0. The zero-crossing modulation strategy is as follows: at the initial moment, the zero-crossing point of the reference voltage sine wave is detected, and a square wave signal with the same frequency and phase as the reference voltage sine wave and a constant duty cycle of 0.5 is generated to control the switching state of all H-bridge inverter units; at other moments, the zero-crossing point of the modulation wave signal generated by the dual closed-loop quasi-proportional resonant control strategy in the previous moment is detected, and a square wave signal with the same frequency and phase as the reference voltage sine wave and a constant duty cycle of 0.5 is generated to control the switching state of all H-bridge inverter units. When the square wave signal is high, the first and fourth power switches of all H-bridge inverter units are turned on, and the second and third power switches are turned off, resulting in an AC output voltage v on the AC output side. b This is the positive half-axis voltage waveform; when the square wave signal is low, the first and fourth power switches of all H-bridge inverter units are turned off, and the second and third power switches are turned on, resulting in an AC output voltage v on the AC output side. b This is the voltage waveform of the negative half-axis; The dual-loop quasi-proportional resonant control strategy specifically includes outer-loop voltage control and inner-loop current control. The outer-loop voltage control uses a first quasi-proportional resonant controller, whose resonant frequency is set at the power frequency. At each moment, the difference between the externally provided reference voltage and the actual output voltage of the converter topology is detected, and the difference is used by the first quasi-proportional resonant controller to generate the inner-loop current reference signal. The inner-loop current control uses a second quasi-proportional resonant controller. The inner-loop current reference signal is added to the load current, and then the difference is calculated with the inductor current of the LC low-pass filter. The difference is used by the second quasi-proportional resonant controller to generate the modulation wave signal for the current moment.

6. The control method according to claim 5, characterized in that, When the converter topology is operating normally, a preset equalization time interval is used. A battery energy balancing strategy based on battery state parameters is periodically executed. At the balancing trigger time, the real-time state parameters of all energy storage batteries are obtained and sorted in descending order. Based on the sorting results, a mapping relationship between carriers and half-bridge sub-modules is established: when the converter topology is working in the discharge state, the carrier amplitudes are sorted in ascending order. The ascending carrier amplitudes are assigned one-to-one with the descending real-time state parameters. The carrier with the lowest amplitude is assigned to the half-bridge sub-module corresponding to the energy storage battery with the highest real-time state parameter, and the carrier with the highest amplitude is assigned to the half-bridge sub-module corresponding to the energy storage battery with the lowest real-time state parameter. When the converter topology is in charging state, the carrier amplitude is sorted in descending order. The carrier amplitude sorted in descending order is assigned one-to-one with the real-time state parameters sorted in descending order. The carrier with the lowest amplitude is assigned to the half-bridge sub-module corresponding to the energy storage battery with the lowest real-time state parameter, and the carrier with the highest amplitude is assigned to the half-bridge sub-module corresponding to the energy storage battery with the highest real-time state parameter. The carrier allocated to each half-bridge submodule during the entire equalization cycle The internal state remains constant, and when the next equilibrium trigger time arrives, it is updated according to the latest real-time state parameter sorting results.

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