Low-power-consumption high-precision digital temperature compensation frequency control chip and method

Abstract

The embodiment of the invention discloses a low-power-consumption high-precision digital temperature compensation frequency control chip and method, and relates to the technical field of integrated circuits, the low-power-consumption high-precision digital temperature compensation frequency control chip comprises a temperature sensing and quantification module, a digital compensation control module and a crystal oscillator module; the digital compensation control module is respectively coupled with the temperature sensing and quantifying module and the crystal oscillator module, and the crystal oscillator module and the digital compensation control module form closed-loop connection; the crystal oscillator module comprises a quartz crystal resonator, a driving circuit and a variable capacitor array, the variable capacitor array is connected to an oscillation circuit of the crystal oscillator module, and the driving circuit is a stacked phase inverter. And meanwhile, the precision is improved from a full link of temperature acquisition, frequency compensation and oscillation control, and a digital temperature compensation frequency control chip of a high-capacity lookup table is not needed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power, high-precision digital temperature-compensated frequency control chip and method. Background Technology

[0002] With the rapid development of the Internet of Things, wearable medical devices, and industrial automation control technologies, electronic systems are placing stringent demands on the frequency stability and power consumption of time reference modules such as real-time clocks. The 32.768kHz fork-type quartz crystal resonator has become the mainstream clock source due to its frequency characteristics, but its frequency-temperature characteristics are parabolic, with frequency deviations exceeding 150ppm under extreme temperatures. Existing digital temperature-compensated crystal oscillators (DTCXOs) mostly use lookup tables for compensation, requiring large-capacity on-chip non-volatile memory, which not only occupies chip area and increases manufacturing costs but also suffers from static leakage power consumption. Traditional crystal oscillator drive circuits use standard CMOS inverters, which have overdrive problems for low-frequency crystals, resulting in dynamic power consumption waste and accelerating crystal aging. At the same time, the on-resistance of the sampling switch of traditional analog-to-digital converters varies with the signal amplitude, introducing nonlinear distortion, limiting the effective number of bits for temperature acquisition, and affecting frequency compensation accuracy, making it difficult to simultaneously meet the design requirements of low power consumption, high precision, and small area. Summary of the Invention

[0003] The technical problem to be solved by the embodiments of the present invention is that existing digital temperature-compensated crystal oscillators require large-capacity lookup tables, making it difficult to simultaneously meet the requirements of low power consumption, high precision, and small area.

[0004] To address the aforementioned issues, this invention discloses a low-power, high-precision digital temperature compensation frequency control chip. This chip improves accuracy across the entire process from temperature acquisition and frequency compensation to oscillation control, and eliminates the need for a large-capacity lookup table.

[0005] This invention provides a low-power, high-precision digital temperature-compensated frequency control chip, which includes a temperature sensing and quantization module, a digital compensation control module, and a crystal oscillator module. The digital compensation control module is coupled to both the temperature sensing and quantization module and the crystal oscillator module, forming a closed-loop connection. The crystal oscillator module includes a quartz crystal resonator, a driving circuit, and a variable capacitor array. The variable capacitor array is connected to the oscillation circuit of the crystal oscillator module. The driving circuit is a stacked inverter, which consists of a first conductivity type transistor group and a second conductivity type transistor group connected in series between the power supply and ground. The first conductivity type transistor group consists of at least three PMOS transistors connected in series, and the second conductivity type transistor group consists of at least three NMOS transistors connected in series.

[0006] A further technical solution is that the output terminal of the driving circuit is coupled to the quartz crystal resonator through a current-limiting resistor, and the crystal oscillator module also includes two cascaded conventional inverters, which are connected to the output side of the driving circuit as an output buffer stage.

[0007] A further technical solution is that the temperature sensing and quantization module includes a temperature sensor front end, a successive approximation analog-to-digital converter, and a bias generation circuit. The successive approximation analog-to-digital converter is coupled to the temperature sensor front end, and the bias generation circuit is electrically connected to the temperature sensor front end and the successive approximation analog-to-digital converter, respectively. The front end of the temperature sensor includes a bipolar transistor and a high-gain operational amplifier, and the high-gain operational amplifier and the bipolar transistor form a closed-loop feedback connection. The successive approximation analog-to-digital converter includes a sample-and-hold circuit and a dynamic latch comparator. The sample-and-hold circuit is coupled to the dynamic latch comparator, and the sampling switch of the sample-and-hold circuit is a gate voltage bootstrap switch.

[0008] A further technical solution is that the bias generation circuit is a beta-multiply self-biasing structure, and the dynamic latch comparator is connected to the clock signal transmission link.

[0009] A further technical solution is that the digital compensation control module includes a time-division multiplexing logic circuit and an arithmetic unit. The arithmetic unit is coupled to the time-division multiplexing logic circuit, and the time-division multiplexing logic circuit is connected to the signal output terminal of the temperature sensing and quantization module and the control terminal of the variable capacitor array, respectively.

[0010] A further technical solution is that the successive approximation analog-to-digital converter is a 12-bit successive approximation analog-to-digital converter, and the gate voltage bootstrap switch structure includes a pre-charge capacitor, which is connected in series between the gate and source of the switching transistor.

[0011] A further technical solution is that the variable capacitor array is a binary weighted capacitor array, and the capacitance values ​​of the multiple capacitor branches are distributed in a binary weighted manner.

[0012] A further technical solution is that the crystal oscillator module is a Pierce topology structure, and the quartz crystal resonator is a 32.768kHz tuning fork type quartz crystal.

[0013] This invention provides a low-power, high-precision digital temperature compensation frequency control method. This method is implemented based on the low-power, high-precision digital temperature compensation frequency control chip described in any of the above embodiments, and includes the following steps: S1. The stacked inverter of the crystal oscillator module drives the quartz crystal resonator to start oscillation, and the oscillation circuit forms the initial oscillation signal. S2. The temperature sensor front end of the temperature sensing and quantization module collects the ambient temperature and converts it into a voltage signal. After closed-loop feedback by a high-gain operational amplifier, it is input to a successive approximation analog-to-digital converter. After sampling by a gate voltage bootstrap switch, it is quantized into a digital temperature code by a dynamic latch comparator and transmitted to the digital compensation control module. S3. The digital compensation control module drives the arithmetic unit through time-division multiplexing logic circuit, calculates and outputs the load capacitance control word to the variable capacitor array of the crystal oscillator module according to the digital temperature code. S4. The variable capacitor array adjusts the number of capacitor branches connected to the oscillation circuit according to the load capacitance control word, changes the load capacitance value of the oscillation circuit, pulls the frequency of the oscillation signal to the nominal value, and completes one frequency compensation. S5. Repeat steps S2-S4 to form a closed-loop digital temperature compensation frequency control.

[0014] A further technical solution is that, in step S3, the arithmetic unit executes a polynomial compensation algorithm to generate a load capacitance control word that matches the temperature drift of the quartz crystal resonator based on the digital temperature code.

[0015] Compared with the prior art, the technical effects achieved by the embodiments of the present invention include: A stacked inverter consisting of at least three PMOS and at least three NMOS transistors connected in series is used as the driving circuit. The equivalent long channel effect of the multi-transistor series connection is used to limit the transconductance of the driving circuit, so that the circuit operates in the subthreshold region. This not only suppresses the static leakage current under deep submicron process, but also avoids the overdrive problem of low-frequency quartz crystal resonator, realizing low power consumption design from the bottom layer of the driving circuit. Through the coupling and closed-loop connection of the digital compensation control module with the temperature sensing and quantization module and the crystal oscillator module, a full-link control architecture of temperature acquisition-digital quantization-frequency compensation is constructed, providing a hardware foundation for high-precision frequency stability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a low-power, high-precision digital temperature-compensated frequency control chip framework provided in an embodiment of the present invention; Figure 2 A schematic diagram of a crystal oscillator circuit is provided for an embodiment of the present invention; Figure 3 A schematic diagram of a temperature sensor front-end circuit is provided for an embodiment of the present invention; Figure 4 A schematic diagram of a high-gain operational amplifier circuit provided in an embodiment of the present invention; Figure 5 A schematic diagram of a SAR ADC architecture provided in an embodiment of the present invention; Figure 6 A schematic diagram of a gate voltage bootstrap switch circuit provided in an embodiment of the present invention; Figure 7 A schematic diagram of a load capacitor array circuit provided in an embodiment of the present invention; Figure 8 A flowchart of a low-power, high-precision digital temperature-compensated frequency control method provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used in this specification of embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. As used in this specification of embodiments of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] See Figure 1This invention provides a low-power, high-precision digital temperature-compensated frequency control chip. The chip includes a temperature sensing and quantization module, a digital compensation control module, and a crystal oscillator module. The digital compensation control module is coupled to both the temperature sensing and quantization module and the crystal oscillator module, forming a closed-loop connection. The crystal oscillator module includes a quartz crystal resonator, a driving circuit, and a variable capacitor array. The variable capacitor array is connected to the oscillation circuit of the crystal oscillator module. The driving circuit is a stacked inverter, which consists of a first conductivity type transistor group and a second conductivity type transistor group connected in series between the power supply and ground. The first conductivity type transistor group consists of at least three PMOS transistors connected in series, and the second conductivity type transistor group consists of at least three NMOS transistors connected in series.

[0022] In this embodiment, the low-power, high-precision digital temperature-compensated frequency control chip of the present invention adopts a mixed-signal architecture. Its core consists of a temperature sensing and quantization module, a digital compensation control module, and a crystal oscillator module. These three modules form a closed-loop control link, realizing ambient temperature acquisition, digital quantization, frequency deviation calculation, and dynamic adjustment of the load capacitance, ultimately achieving frequency stability over a wide temperature range. The first conductivity type transistor group is composed of P-type metal-oxide-semiconductor (PMOS) transistors, exhibiting high-level cutoff and low-level conduction characteristics. The second conductivity type transistor group is composed of N-type metal-oxide-semiconductor (NMOS) transistors, exhibiting low-level cutoff and high-level conduction characteristics. The variable capacitor array consists of multiple capacitor branches connected in parallel. The total capacitance value can be changed by adjusting the number of capacitor branches connected to the circuit, and it is connected to the crystal oscillator oscillation circuit to adjust the oscillation frequency.

[0023] This stacked inverter has dual technological advantages: Reduced static leakage current: The series connection of multiple transistors effectively increases the equivalent channel length of the transistor, which significantly suppresses the subthreshold leakage current under deep submicron technology. Limiting drive current: Through stacking, the equivalent transconductance (g) of the inverter is limited. m This causes the driving transistor to operate in the subthreshold region. At this time, the subthreshold leakage current I of the MOSFET is... D It can be approximated by formula (1):

[0024] Among them, V GS The gate-source voltage of a field-effect transistor (FET), i.e., the voltage difference between the gate and source of the FET, is a key electrical parameter that determines the FET's conduction state, on-resistance, and operating region. In this embodiment, V GSDesigned to be a constant value to eliminate nonlinear distortion caused by variations in the sampling switch's on-resistance as the input signal changes. W is the channel width, L... eff V is the equivalent channel length formed by the stacked structure. th V is the threshold voltage, m is the subthreshold slope factor, and V T =kT / q is the thermal voltage. From formula (1), it can be seen that connecting three transistors in series significantly increases L. eff This effectively suppresses leakage current, ensuring nanoampere-level static power consumption, thereby avoiding overdrive of the 32.768kHz low-frequency crystal and reducing the current consumption of the oscillation core to the nanoampere (nA) level. Figure 2 As shown, the output of the stacked inverter is connected to a current-limiting resistor R. S (Approximately 277Ω resistance) Connected to one end of the quartz crystal, further increasing the output impedance and isolating high-frequency noise. The oscillator output is shaped into a square wave clock after passing through a buffer stage composed of two conventional inverters, to enhance load driving capability and isolate subsequent interference.

[0025] A stacked inverter consisting of at least three PMOS and at least three NMOS transistors connected in series is used as the driving circuit. The equivalent long channel effect of the multi-transistor series connection is used to limit the transconductance of the driving circuit, so that the circuit operates in the subthreshold region. This not only suppresses the static leakage current under deep submicron process, but also avoids the overdrive problem of low-frequency quartz crystal resonator, realizing low power consumption design from the bottom layer of the driving circuit. Through the coupling and closed-loop connection of the digital compensation control module with the temperature sensing and quantization module and the crystal oscillator module, a full-link control architecture of temperature acquisition-digital quantization-frequency compensation is constructed, providing a hardware foundation for high-precision frequency stability.

[0026] In this embodiment, the output of the driving circuit is coupled to the quartz crystal resonator through a current-limiting resistor. The crystal oscillator module also includes two cascaded conventional inverters, which are connected to the output side of the driving circuit as an output buffer stage.

[0027] Specifically, the current-limiting resistor is a resistor connected in series between the output terminal of the drive circuit and the quartz crystal resonator. It is used to increase the output impedance, limit the loop current, and isolate high-frequency noise. The output buffer stage consists of two cascaded conventional inverters connected to the output side of the drive circuit. It is a circuit unit used to shape the oscillation waveform, improve the load driving capability, and isolate the load interference of the subsequent stage.

[0028] The output of the drive circuit is coupled to the quartz crystal resonator through a current-limiting resistor, which effectively increases the output impedance, isolates high-frequency noise in the circuit, avoids noise interference to the oscillation circuit, and improves the stability of the oscillation signal. Two cascaded conventional inverters serve as the output buffer stage, shaping the oscillation waveform into a standard square wave clock signal, while isolating the influence of the subsequent load on the oscillation circuit, ensuring the stability of the oscillation frequency, and improving the chip's load driving capability.

[0029] Furthermore, the temperature sensing and quantization module includes a temperature sensor front-end, a successive approximation analog-to-digital converter (ADC), and a bias generation circuit. The successive approximation ADC is coupled to the temperature sensor front-end, and the bias generation circuit is electrically connected to both the temperature sensor front-end and the successive approximation ADC. The temperature sensor front-end includes a bipolar transistor and a high-gain operational amplifier, with the high-gain operational amplifier and the bipolar transistor forming a closed-loop feedback connection. The successive approximation ADC includes a sample-and-hold circuit and a dynamic latch comparator, with the sample-and-hold circuit coupled to the dynamic latch comparator. The sampling switch of the sample-and-hold circuit is a gate voltage bootstrap switch.

[0030] Specifically, the temperature sensor front-end is the core unit in the temperature sensing and quantization module that realizes temperature-to-voltage conversion, consisting of a bipolar transistor and a high-gain operational amplifier; the successive approximation analog-to-digital converter is an analog-to-digital conversion circuit that converts analog voltage signals into digital signals through successive comparisons, featuring high accuracy and low power consumption; the bias generation circuit is a circuit unit that provides constant operating current for the temperature sensor front-end and the successive approximation analog-to-digital converter; the gate voltage bootstrap switch is a sampling switch that raises and maintains the gate-source voltage of the switching transistor through a pre-charge capacitor, which can eliminate the nonlinearity of the on-resistance changing with the input signal; the dynamic latch comparator is a comparator controlled by a clock signal that performs voltage comparison and latches the result only at the clock edge, with no static current consumption during the reset phase.

[0031] The workflow is as follows: The power management module converts the external battery voltage into a stable internal voltage to power all analog and digital modules. After power-on, the crystal oscillator module starts oscillating and outputs a 32.768kHz clock signal. The digital compensation control module periodically wakes up the temperature sensing and quantization module; the temperature sensor collects the current chip temperature and converts it into a 12-bit digital temperature code through the SAR ADC (the digital temperature code is a digital signal obtained by the temperature sensing and quantization module after quantizing the analog voltage signal output by the temperature sensor through the analog-to-digital converter (ADC), used to characterize the current ambient temperature, and is the core input parameter for the digital compensation control module to perform frequency compensation calculation). The digital compensation control module receives the temperature code, uses the built-in polynomial to calculate the frequency deviation of the crystal at the current temperature, and derives the load capacitance control word required to offset the deviation according to formula (2) (the load capacitance control word is a digital control signal generated by the digital compensation control module according to the digital temperature code, used to control the on / off of each capacitor branch in the variable capacitor array, thereby adjusting the total load capacitance value connected to the oscillation circuit, and realizing the pulling and compensation of the crystal oscillation frequency). Formula (2) is as follows:

[0032] Among them, f osc This is the actual oscillation frequency of the crystal oscillator module, reflecting the actual output oscillation frequency generated by the quartz crystal resonator driven by the stacked inverter under the current ambient temperature and load capacitance conditions. s C0 is the nominal resonant frequency / series resonant frequency of the quartz crystal resonator. C1 is the inherent parasitic capacitance of the quartz crystal, generated by the crystal's electrodes, packaging, and other structures. It is a fixed capacitance value and affects the correlation between the crystal's actual oscillation frequency and the load capacitance. C1 is the dynamic series capacitance (motion capacitance) of the quartz crystal resonator, reflecting the crystal's electromechanical conversion characteristics. It is a fixed capacitance value and, together with C0, determines how the crystal's oscillation frequency changes with the external load capacitance. L The actual load capacitance value connected to the crystal oscillator oscillation circuit refers to the total load capacitance value actually connected to the oscillation circuit by the variable capacitor array (CDAC) in the crystal oscillator module according to the control word output by the digital compensation control module. It is an adjustable parameter used for frequency compensation in this invention. By adjusting C... L Tractionable f osc up to nominal value f s .

[0033] The control word is fed back to the variable capacitor array (CDAC) in the crystal oscillator module, which pulls the output frequency back to the nominal value (32.768kHz) by changing the load capacitance of the oscillation circuit, thereby achieving frequency stability over the entire temperature range.

[0034] Temperature sensor front end such as Figure 3As shown, the circuit mainly consists of seven core sub-modules: bandgap core, CTAT current generation stage, PTAT current generation stage, zero-temperature drift reference voltage generation stage, zero-temperature drift reference current generation stage, ADC differential voltage generation stage, and reference voltage drive enhancement stage.

[0035] The bandgap core module consists of bipolar transistors Q0 and Q1, resistor R0, and operational amplifier OA. 11 The configuration is as follows: The emitter junction area ratio of Q1 to Q0 is set to n:1 (n=8 in this embodiment). Due to the operational amplifier OA... 11 The virtual short effect of node V P The voltage feedback forces the collector potentials of Q1 and Q0 to be the same, thereby generating a base-emitter voltage difference ΔV across resistor R0. BE This voltage difference has a positive temperature coefficient, expressed as:

[0036] Among them, V BE1 This refers to the base-emitter voltage of the first bipolar transistor (such as a PNP transistor), which decreases linearly with increasing temperature and has a negative temperature coefficient; V BE2 This refers to the base-emitter voltage of the second bipolar transistor, and its relationship with V. BE1 They have the same temperature characteristics; k is the Boltzmann constant; q is the electron charge; T is the absolute temperature.

[0037] PTAT current generating stage, such as Figure 3 As shown, resistor R0 will reduce ΔV BE Converted into a current I proportional to the absolute temperature. PTAT At the same time, resistor R2 also generates an auxiliary PTAT voltage V. PTAT The expression for PTAT current is:

[0038] The high-gain operational amplifier used in the circuit constructs a closed-loop feedback, such as Figure 4 As shown, this forces the voltages of the current mirror nodes to be equal, thereby ensuring the accuracy of PTAT current generation.

[0039] CTAT current generation stage, such as Figure 3 As shown, using operational amplifier OA 12 The base-emitter voltage V of transistor Q1 BE1 It is applied across resistor R1. Because V BE With a negative temperature coefficient (approximately -2mV / °C), the resistor R1 branch generates a current I that is inversely proportional to the absolute temperature. CTAT The voltage V it generates CTAT The expression is:

[0040] Zero-temperature-drift reference voltage generation stage, such as Figure 3 As shown, this stage utilizes a current mirror to... PTAT Injecting a resistor network and combining it with the V of transistor Q2 BE Voltage, through operational amplifier OA 21 Closed-loop regulation. The circuit weighted sums the voltages with positive and negative temperature coefficients to generate two zero-temperature-drift reference voltages V across the resistor chain R4, R5, and R6. REF_3P0 (3.0V) and V REF_1P5 (1.5V). Zero temperature drift conditions must be met:

[0041] Among them, V REF The reference voltage is a reference voltage generated internally by the chip, characterized by high stability and a low temperature coefficient. It is used to provide a precise voltage reference for circuits such as analog-to-digital converters and comparators, ensuring the accuracy and stability of temperature acquisition, signal quantization, and frequency compensation. K is the multiplier set by the resistor network.

[0042] Zero-temperature-drift reference current generation stage, such as Figure 3 As shown, operational amplifier OA 22 The generated zero temperature drift voltage V REF_3P0 A constant, temperature-independent reference current I is generated when applied across resistor R8. REF It is used for biasing subsequent circuits.

[0043] ADC differential voltage generation stage, such as Figure 3 As shown, this module uses a current mirror to... PTAT and I CTAT Inject resistors R9 and R respectively 10 In the network, a pair of differential voltage signals V are generated through resistor voltage division and level shifting. COMPP and V COMPN This ensures high linearity in temperature-to-voltage conversion because the signal changes linearly with temperature and the common-mode level matches the input range of the subsequent ADC.

[0044] Reference voltage drive enhancement stage such as Figure 3 As shown, to prevent switching noise during the switching of the internal capacitor array of the SAR ADC from interfering with the reference voltage of the preceding stage, this design uses V COMPP and V COMPN The output terminals are respectively equipped with operational amplifiers OA 32 OA 31 and output transistor M 24 M 23This is a unity-gain buffer. This buffer stage provides low output impedance, significantly enhancing the driving capability of the reference voltage and ensuring rapid voltage build-up and stabilization during ADC sampling.

[0045] Low-power SAR ADCs such as Figure 5 As shown, the analog-to-digital converter employs a 12-bit successive approximation architecture. Its key innovation lies in the use of a gate voltage bootstrap switch in the sample-and-hold circuit. The gate voltage bootstrap switch is as follows: Figure 6 As shown. This bootstrap switching circuit includes a pre-charge capacitor (C0). In the sampling phase, the capacitor is pre-charged to the supply voltage; in the holding phase, the capacitor is connected in series between the gate and source of the switching transistor. This mechanism allows the gate-source voltage (V0) of the switching transistor to remain constant during conduction. gs The on-resistance remains constant and does not fluctuate with changes in the input signal amplitude. This effectively eliminates the nonlinearity of the on-resistance of traditional MOS switches, significantly improves the total harmonic distortion (THD) and effective number of bits (ENOB) of the ADC under full-swing input, and ensures high linearity of temperature measurement.

[0046] In addition, the comparator inside the ADC adopts a dynamic latch structure, which only performs comparison operations and consumes dynamic current on the rising edge of the clock signal (CLK), and is in a reset state at other times. There is no static DC path, which further reduces power consumption.

[0047] Load capacitor array such as Figure 7 As shown, the variable capacitor array (CDAC) consists of a fixed base capacitor (C). fix ) and multiple (e.g., n) binary-weighted parallel capacitors (C1 to C n (Branch)

[0048] Whether each capacitor branch is connected or not is determined by the control word output by the digital compensation control module. <n:0>The total equivalent capacitance C of the array is determined. array It has a linear relationship with the input digital control word D:

[0049] Among them, C fix The base is a fixed capacitor, C unit For the smallest unit capacitance, b i This is the i-th binary value (0 or 1) of the control word. This structure ensures monotonic adjustment of the load capacitance.

[0050] To ensure a high Q value, each branch switch employs a transmission gate structure, consisting of an NMOS transistor and a PMOS transistor connected in parallel and driven by complementary signals. This structure ensures that the switch exhibits low on-resistance across the entire operating voltage range, reducing the impact of switch parasitic resistance on the crystal oscillator's quality factor and thus guaranteeing the oscillator's phase noise performance.

[0051] The temperature sensor front end adopts a closed-loop feedback structure with bipolar transistors and high-gain operational amplifiers to ensure the linearity of temperature-to-voltage conversion, laying the foundation for high-precision temperature acquisition. The sampling switch of the successive approximation analog-to-digital converter uses a gate voltage bootstrap switch, eliminating the nonlinear distortion of traditional sampling switches and increasing the effective number of bits of the analog-to-digital conversion. The dynamic latch comparator is coupled with the sample-and-hold circuit, reducing the power consumption of the analog-to-digital conversion module. The bias generation circuit provides a stable operating current for each unit of the temperature sensing and quantization module, ensuring the stability of the module under different operating conditions. This improves the overall compensation accuracy from the temperature acquisition and signal quantization stages, while also ensuring low power consumption.

[0052] Furthermore, the bias generation circuit is a beta-multiply self-biased structure, and the dynamic latch comparator is connected to the clock signal transmission link.

[0053] Specifically, the beta-multiply self-biased structure is a circuit structure that achieves self-biasing through the current amplification factor (β) of the transistor, which can generate a constant bias current independent of the power supply voltage; the clock signal transmission link is the circuit path that provides the clock signal for each timing circuit of the chip, and the dynamic latch comparator is controlled synchronously by the clock signal after being connected.

[0054] The bias generation circuit adopts a beta-multiply self-biasing structure, which can generate a constant bias current independent of the power supply voltage, ensuring that the temperature sensor front end and the successive approximation analog-to-digital converter can still work stably when the power supply voltage fluctuates, thus improving the chip's immunity to power supply noise. The dynamic latch comparator is connected to the clock signal transmission link and performs voltage comparison operation only at the clock edge. There is no static current consumption during the reset phase, which further reduces the power consumption of the successive approximation analog-to-digital converter and achieves a balance between accuracy and power consumption.

[0055] Furthermore, the digital compensation control module includes a time-division multiplexing logic circuit and an arithmetic unit. The arithmetic unit is coupled to the time-division multiplexing logic circuit, which is connected to the signal output terminal of the temperature sensing and quantization module and the control terminal of the variable capacitor array, respectively.

[0056] Specifically, the time-division multiplexing logic circuit is a logic circuit that allocates the same circuit link to different signal transmission tasks according to time slices to realize link multiplexing; the arithmetic unit is the core circuit unit in the digital compensation control module that executes the polynomial compensation algorithm and calculates the frequency deviation and load capacitance control word.

[0057] The digital compensation control module employs time-division multiplexing logic circuits to achieve link multiplexing of digital temperature code reception and load capacitor control word output, simplifying the circuit structure and reducing chip area. The time-division multiplexing logic circuits are connected to the temperature sensing and quantization module and the variable capacitor array, respectively, to construct a fast signal transmission link and ensure the real-time performance of frequency compensation. The arithmetic unit is coupled with the time-division multiplexing logic circuits and can calculate the frequency deviation in real time based on the digital temperature code, providing the hardware foundation for algorithm execution for accurate frequency compensation.

[0058] Furthermore, the successive approximation analog-to-digital converter is a 12-bit successive approximation analog-to-digital converter, and the gate voltage bootstrap switch structure includes a pre-charge capacitor connected in series between the gate and source of the switching transistor.

[0059] Specifically, a 12-bit successive approximation analog-to-digital converter refers to a successive approximation analog-to-digital converter with a conversion accuracy of 12 bits, which can convert analog voltage signals into 12-bit digital signals and has high conversion accuracy; the precharge capacitor is a capacitor element inside the gate voltage bootstrap switch, connected in series between the gate and source of the switch, used for precharging and keeping the gate-source voltage of the switch constant.

[0060] A 12-bit successive approximation analog-to-digital converter is used to improve the digital accuracy of temperature-to-voltage signal conversion, providing a high-precision digital temperature code for accurate calculation of subsequent frequency compensation. The pre-charge capacitor in the gate voltage bootstrap switch is connected in series between the gate and source of the switching transistor, so that the gate-source voltage of the switching transistor remains constant during conduction, completely eliminating the nonlinear distortion caused by the change of on-resistance with the amplitude of the input signal, further improving the linearity and accuracy of the analog-to-digital conversion, and ensuring the accuracy of frequency compensation from the signal quantization stage.

[0061] Furthermore, the variable capacitor array is a binary weighted capacitor array, and the capacitance values ​​of the multiple capacitor branches are distributed in a binary weighted manner.

[0062] Specifically, a binary weighted capacitor array is a capacitor array composed of multiple capacitor branches, with the capacitance value of each capacitor branch distributed according to binary weights, which can realize fine binary adjustment of the capacitance value.

[0063] The variable capacitor array is a binary weighted capacitor array, with the capacitance values ​​of each capacitor branch distributed in a binary weighted manner. It can achieve monotonic and fine adjustment of the load capacitance according to the load capacitance control word, which greatly improves the adjustment accuracy of the load capacitance, thereby achieving precise control of the oscillation frequency, effectively offsetting the frequency temperature drift of the quartz crystal resonator, and improving the accuracy of frequency compensation.

[0064] Furthermore, the crystal oscillator module is a Pierce topology, and the quartz crystal resonator is a 32.768kHz tuning fork quartz crystal.

[0065] Specifically, the Pierce topology is a crystal oscillator topology based on an inverter, characterized by its simple structure and stable oscillation; the 32.768kHz tuning fork quartz crystal is a tuning fork quartz crystal resonator with a resonant frequency of 32.768kHz, which is the mainstream clock source for devices such as real-time clocks and IoT nodes, and is characterized by its stable frequency and small size.

[0066] The crystal oscillator module adopts a Pierce topology, which ensures the structural simplicity and oscillation stability of the oscillation circuit and reduces the complexity of circuit design. The quartz crystal resonator uses a 32.768kHz tuning fork quartz crystal, which is suitable for typical application scenarios such as real-time clocks and IoT nodes, improving the practicality and adaptability of the chip. It can meet the needs of mainstream low-power clock applications without the need for additional frequency conversion circuits.

[0067] This invention also provides a low-power, high-precision digital temperature compensation frequency control method, implemented based on the low-power, high-precision digital temperature compensation frequency control chip described in any of the above embodiments, including steps S1-S5: S1. The stacked inverter of the crystal oscillator module drives the quartz crystal resonator to start oscillation, and the oscillation circuit forms the initial oscillation signal. S2. The temperature sensor front end of the temperature sensing and quantization module collects the ambient temperature and converts it into a voltage signal. After closed-loop feedback by a high-gain operational amplifier, it is input to a successive approximation analog-to-digital converter. After sampling by a gate voltage bootstrap switch, it is quantized into a digital temperature code by a dynamic latch comparator and transmitted to the digital compensation control module. S3. The digital compensation control module drives the arithmetic unit through time-division multiplexing logic circuit, calculates and outputs the load capacitance control word to the variable capacitor array of the crystal oscillator module according to the digital temperature code. S4. The variable capacitor array adjusts the number of capacitor branches connected to the oscillation circuit according to the load capacitance control word, changes the load capacitance value of the oscillation circuit, pulls the frequency of the oscillation signal to the nominal value, and completes one frequency compensation. S5. Repeat steps S2-S4 to form a closed-loop digital temperature compensation frequency control.

[0068] Specifically, the digital temperature code is a digital signal obtained by converting the temperature-voltage analog signal into a digital signal by the temperature sensing and quantization module, and it is a digital quantity reflecting the ambient temperature; the load capacitance control word is a digital control signal calculated and generated by the digital compensation control module, used to control the variable capacitor array to adjust the load capacitance value; the closed-loop digital temperature compensation frequency control is a real-time, dynamic frequency control link formed by repeated temperature acquisition, digital quantization, and frequency compensation steps, which can adjust the oscillation frequency in real time according to changes in ambient temperature.

[0069] This frequency control method is implemented based on the chip hardware structure of this application. It uses a stacked inverter to drive oscillation, a temperature sensing and quantization module to achieve high-precision temperature acquisition, a digital compensation control module to calculate frequency deviation, and a variable capacitor array to achieve precise frequency traction. The steps work together to form a closed-loop digital temperature-compensated frequency control, which can adjust the oscillation frequency in real time and dynamically according to changes in ambient temperature, effectively offsetting the frequency temperature drift of the quartz crystal resonator. The entire method requires no manual intervention, achieving fully automated frequency compensation and improving the ease of use of the chip. At the same time, each step is implemented based on a low-power hardware structure, ensuring the low power consumption characteristics of the control process.

[0070] Furthermore, in step S3 above, the arithmetic unit executes a polynomial compensation algorithm to generate a load capacitance control word that matches the temperature drift of the quartz crystal resonator based on the digital temperature code.

[0071] Specifically, the polynomial compensation algorithm is an algorithm that uses polynomial fitting to fit the frequency-temperature characteristics of a quartz crystal resonator, calculates the frequency deviation based on the digital temperature code, and generates a load capacitance control word, eliminating the need for a large-capacity lookup table to store calibration data.

[0072] The arithmetic unit executes a polynomial compensation algorithm, which fits the frequency-temperature characteristics of the quartz crystal resonator using a polynomial. It can accurately calculate the frequency deviation of the quartz crystal resonator based on the digital temperature code, and generate a load capacitance control word that is highly matched to the temperature drift, thus achieving precise cancellation of frequency and temperature drift. It abandons the traditional lookup table compensation method, eliminating the need for a large-capacity on-chip non-volatile memory to store calibration data, significantly reducing chip area, manufacturing costs, and static leakage power consumption. At the same time, the real-time calculation characteristics of the polynomial compensation algorithm improve the real-time performance and adaptability of frequency compensation, making it suitable for quartz crystal resonators with different characteristics.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0074] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0076] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0077] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0078] In the description of this specification, the references to "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0079] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0080] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-power, high-precision digital temperature-compensated frequency control chip, characterized in that, It includes a temperature sensing and quantization module, a digital compensation control module, and a crystal oscillator module; The digital compensation control module is coupled to the temperature sensing and quantization module and the crystal oscillator module respectively, and the crystal oscillator module and the digital compensation control module form a closed loop connection. The crystal oscillator module includes a quartz crystal resonator, a driving circuit, and a variable capacitor array. The variable capacitor array is connected to the oscillation circuit of the crystal oscillator module. The driving circuit is a stacked inverter. The stacked inverter consists of a first conductivity type transistor group and a second conductivity type transistor group connected in series between the power supply and ground. The first conductivity type transistor group consists of at least three PMOS transistors connected in series, and the second conductivity type transistor group consists of at least three NMOS transistors connected in series.

2. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 1, characterized in that, The output of the driving circuit is coupled to the quartz crystal resonator through a current-limiting resistor. The crystal oscillator module also includes two cascaded conventional inverters, which are connected to the output side of the driving circuit as an output buffer stage.

3. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 1, characterized in that, The temperature sensing and quantization module includes a temperature sensor front end, a successive approximation analog-to-digital converter (ADC), and a bias generation circuit. The successive approximation ADC is coupled to the temperature sensor front end, and the bias generation circuit is electrically connected to both the temperature sensor front end and the successive approximation ADC. The front end of the temperature sensor includes a bipolar transistor and a high-gain operational amplifier, and the high-gain operational amplifier and the bipolar transistor form a closed-loop feedback connection. The successive approximation analog-to-digital converter includes a sample-and-hold circuit and a dynamic latch comparator. The sample-and-hold circuit is coupled to the dynamic latch comparator, and the sampling switch of the sample-and-hold circuit is a gate voltage bootstrap switch.

4. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 3, characterized in that, The bias generation circuit is a beta-multiply self-biased structure, and the dynamic latch comparator is connected to the clock signal transmission link.

5. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 1, characterized in that, The digital compensation control module includes a time-division multiplexing logic circuit and an arithmetic unit. The arithmetic unit is coupled to the time-division multiplexing logic circuit, which is connected to the signal output terminal of the temperature sensing and quantization module and the control terminal of the variable capacitor array, respectively.

6. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 3, characterized in that, The successive approximation analog-to-digital converter is a 12-bit successive approximation analog-to-digital converter, and the gate voltage bootstrap switch includes a pre-charge capacitor connected in series between the gate and source of the switching transistor.

7. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 1, characterized in that, The variable capacitor array is a binary weighted capacitor array, and the capacitance values ​​of the multiple capacitor branches are distributed in a binary weighted manner.

8. The low-power, high-precision digital temperature-compensated frequency control chip according to claim 1, characterized in that, The crystal oscillator module is a Pierce topology, and the quartz crystal resonator is a 32.768kHz tuning fork quartz crystal.

9. A low-power, high-precision digital temperature-compensated frequency control method, implemented based on the low-power, high-precision digital temperature-compensated frequency control chip according to any one of claims 1-8, characterized in that, Includes the following steps: S1. The stacked inverter of the crystal oscillator module drives the quartz crystal resonator to start oscillation, and the oscillation circuit forms the initial oscillation signal. S2. The temperature sensor front end of the temperature sensing and quantization module collects the ambient temperature and converts it into a voltage signal. After closed-loop feedback by a high-gain operational amplifier, it is input to a successive approximation analog-to-digital converter. After sampling by a gate voltage bootstrap switch, it is quantized into a digital temperature code by a dynamic latch comparator and transmitted to the digital compensation control module. S3. The digital compensation control module drives the arithmetic unit through time-division multiplexing logic circuit, calculates and outputs the load capacitance control word to the variable capacitor array of the crystal oscillator module according to the digital temperature code. S4. The variable capacitor array adjusts the number of capacitor branches connected to the oscillation circuit according to the load capacitance control word, changes the load capacitance value of the oscillation circuit, pulls the frequency of the oscillation signal to the nominal value, and completes one frequency compensation. S5. Repeat steps S2-S4 to form a closed-loop digital temperature compensation frequency control.

10. The low-power, high-precision digital temperature-compensated frequency control method according to claim 9, characterized in that, In step S3, the arithmetic unit executes a polynomial compensation algorithm to generate a load capacitance control word that matches the temperature drift of the quartz crystal resonator based on the digital temperature code.

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