Semiconductor structure and preparation method of semiconductor structure
By designing the structure of substrate, buffer layer, P-type barrier layer and barrier layer in gallium nitride HEMT device, and combining it with delta doping technology, the problem of dynamic on-resistance being greater than static on-resistance was solved, thereby optimizing device performance and improving efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-04-07
AI Technical Summary
The dynamic on-resistance of existing gallium nitride HEMT devices is greater than that of static on-resistance, which affects the device's performance.
A semiconductor structure was designed, including a substrate, a buffer layer, a P-type barrier layer, a channel layer, and a barrier layer. A preset barrier is formed between the channel layer and the buffer layer by the P-type barrier layer to prevent two-dimensional electron gas from migrating into the buffer layer. Combined with the delta doping process, the magnesium ion doping concentration is controlled to prevent electrons from being trapped.
It effectively reduces the dynamic on-resistance of the device during switching, optimizes the crystal morphology, avoids excessive diffusion of doped ions affecting device performance, and improves the device's operating efficiency.
Smart Images
Figure CN121815704A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology
[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) are advanced power semiconductor devices based on gallium nitride materials, characterized by high electron mobility, high power density, small size, and high integration.
[0003] However, the dynamic on-resistance of current gallium nitride HEMT devices is greater than that of static on-resistance, sometimes even equal to 3-8 times the static on-resistance, which affects the operating performance of HEMT devices. Therefore, how to reduce the dynamic on-resistance of HEMT devices has become one of the urgent technical problems to be solved.
[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure and a method for fabricating the semiconductor structure, so as to solve the problem that the dynamic on-resistance of gallium nitride HEMT devices is greater than the static on-resistance in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a semiconductor structure comprising:
[0007] Substrate;
[0008] A buffer layer is located on the substrate;
[0009] A P-type barrier layer is located on the buffer layer; wherein the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers;
[0010] The channel layer is located on the P-type barrier layer;
[0011] A barrier layer is located on the channel layer;
[0012] The channel layer contains a two-dimensional electron gas; the P-type barrier layer forms a preset barrier between the channel layer and the buffer layer, and the preset barrier is used to prevent the two-dimensional electron gas in the channel layer from migrating to the buffer layer.
[0013] In some embodiments, the doped ions of the P-type barrier layer include magnesium ions; the material of the P-type barrier layer includes gallium nitride.
[0014] In some embodiments, the magnesium ion doping concentration is 1E18cm⁻³-3E19cm⁻³.
[0015] In some embodiments, the semiconductor structure further includes a cap layer located on a portion of the barrier layer.
[0016] In some embodiments, the cap layer is made of P-type gallium nitride.
[0017] In some embodiments, the semiconductor structure further includes:
[0018] A passivation layer is applied to the surface of the barrier layer, excluding the area where the cap layer is located.
[0019] In some embodiments, the semiconductor structure further includes a gate electrode, a source electrode, and a drain electrode; wherein the gate electrode is located on the cap layer; the source electrode penetrates the passivation layer and the barrier layer and contacts the channel layer; the drain electrode penetrates the passivation layer and the barrier layer and contacts the channel layer.
[0020] Secondly, this application also provides a method for preparing a semiconductor structure, the method comprising:
[0021] Provide substrate;
[0022] A buffer layer is formed on the substrate;
[0023] A P-type barrier layer is formed on the buffer layer; wherein the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers;
[0024] A channel layer is formed on the P-type barrier layer;
[0025] A barrier layer is formed on the channel layer;
[0026] The channel layer contains a two-dimensional electron gas; the P-type barrier layer forms a preset barrier between the channel layer and the buffer layer, and the preset barrier is used to prevent the two-dimensional electron gas in the channel layer from migrating to the buffer layer.
[0027] In some embodiments, the doped ions of the P-type barrier layer include magnesium ions; the material of the P-type barrier layer includes gallium nitride.
[0028] In some embodiments, the magnesium ion doping concentration is 1E18cm⁻³-3E19cm⁻³.
[0029] As described above, the semiconductor structure and its preparation method of the present invention have the following beneficial effects:
[0030] The semiconductor structure and its fabrication method of the present invention include: a substrate, a buffer layer, a P-type barrier layer, a channel layer, and a barrier layer. The buffer layer is located on the substrate and is used to promote crystal growth of the P-type barrier layer and the channel layer, optimizing the crystal morphology. The P-type barrier layer is located on the buffer layer, the channel layer is located on the P-type barrier layer, and the barrier layer is located on the channel layer. The channel layer contains a two-dimensional electron gas. The P-type barrier layer forms a preset barrier between the channel layer and the buffer layer. This preset barrier prevents the two-dimensional electron gas in the channel layer from migrating to the buffer layer, thereby preventing the two-dimensional electron gas from being injected into the buffer layer and trapped by the buffer layer under the strong electric field of the drain. This reduces the concentration of the two-dimensional electron gas in the channel layer during the device transition from an off-state to an on-state, thus reducing the dynamic on-resistance. Furthermore, the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers. The relatively small thickness of the P-type barrier layer prevents excessive diffusion of P-type doped ions into the channel layer or buffer layer, which could affect device performance. Attached Figure Description
[0031] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.
[0032] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment of this application;
[0033] Figure 2 This is a schematic diagram of a semiconductor structure provided in another embodiment of this application;
[0034] Figure 3 This is a schematic diagram of a semiconductor structure provided in another embodiment of this application;
[0035] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment of this application;
[0036] Figure 5 This is a schematic diagram of the energy levels of a semiconductor structure provided in one embodiment of this application;
[0037] Figure 6 This is a schematic diagram of the energy levels of a semiconductor structure provided in another embodiment of this application. Detailed Implementation
[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0040] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0041] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0042] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0043] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0044] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0045] As mentioned in the background section, due to the heteroepitaxial process, HEMT devices contain numerous internal traps, inevitably leading to charge trapping during switching. This results in a dynamic on-resistance that is significantly greater than the static on-resistance, leading to substantial conduction losses. (Reference) Figure 1 Charge trapping in HEMT devices mainly occurs in two forms: First, when the device is in a high-voltage off-state, the strong electric field between the drain and gate traps electrons on the gate surface or excites them into high-energy hot electrons, which are then trapped by the barrier layer 40. Second, when the device transitions from a high-voltage off-state to an on-state, a strong vertical electric field is generated below the drain. Under the influence of this strong electric field, the two-dimensional electron gas 310 in the channel layer 30 is injected into the buffer layer 20 and trapped by traps within the buffer layer 20. Since the trapped charges cannot be released in time, the concentration of the two-dimensional electron gas in the channel layer 30 decreases, leading to an increase in dynamic on-resistance. Dynamic on-resistance refers to the instantaneous equivalent resistance between the source and drain during the switching transition, while static on-resistance refers to the equivalent resistance between the drain and source when the device is in a stable on-state.
[0046] For the reasons mentioned above, please refer to Figure 2 This application provides a semiconductor structure, including: a substrate 10, a buffer layer 20, a P-type barrier layer 100, a channel layer 30, and a barrier layer 40. The buffer layer 20 is located on the substrate 10; the P-type barrier layer 100 is located on the buffer layer 20; the thickness of the P-type barrier layer 100 is greater than 0 nanometers and less than or equal to 100 nanometers; the channel layer 30 is located on the P-type barrier layer 100; the barrier layer 40 is located on the channel layer 30; wherein the channel layer 30 contains a two-dimensional electron gas 310; the P-type barrier layer 100 forms a predetermined barrier between the channel layer 30 and the buffer layer 20, the predetermined barrier being used to prevent the two-dimensional electron gas 310 in the channel layer 30 from migrating to the buffer layer 20.
[0047] As an example, the material of substrate 10 may include semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 10 may be a single-layer structure or a multi-layer structure. For example, the material of substrate 10 may include silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 10 may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of substrate 10 should not limit the scope of protection of this disclosure.
[0048] As an example, the material of the buffer layer 20 may include at least one of aluminum nitride and gallium nitride.
[0049] As an example, the thickness of the P-type barrier layer 100 may include 5 nanometers, 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers, 50 nanometers, 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers, 100 nanometers, etc.
[0050] As an example, the material of the channel layer 30 may include gallium nitride, and the material of the barrier layer 40 may include aluminum gallium nitride.
[0051] In the above embodiments, the semiconductor structure includes: a substrate, a buffer layer, a P-type barrier layer, a channel layer, and a barrier layer. The buffer layer is located on the substrate and is used to promote crystal growth of the P-type barrier layer and the channel layer, optimizing the crystal morphology. The P-type barrier layer is located on the buffer layer, the channel layer is located on the P-type barrier layer, and the barrier layer is located on the channel layer. The channel layer contains a two-dimensional electron gas. The P-type barrier layer forms a preset barrier between the channel layer and the buffer layer. This preset barrier prevents the two-dimensional electron gas in the channel layer from migrating to the buffer layer. The barrier height is related to the material and dopant ions of the P-type barrier layer, thereby preventing the two-dimensional electron gas from being injected into the buffer layer and trapped by the buffer layer under the strong electric field of the drain. This reduces the concentration of the two-dimensional electron gas in the channel layer during the device transition from an off-state to an on-state, thus reducing the dynamic on-resistance. Furthermore, the thickness of the P-type barrier layer is 0 nm to 100 nm. The relatively small thickness of the P-type barrier layer prevents excessive diffusion of P-type dopant ions into the channel layer or buffer layer, which could affect device performance.
[0052] In some embodiments, the doping ions of the P-type barrier layer include magnesium ions; the material of the P-type barrier layer includes gallium nitride.
[0053] In some embodiments, the magnesium ion doping concentration is 1E18cm⁻³-3E19cm⁻³.
[0054] For example, the magnesium ion doping concentrations are 1E18cm⁻³, 5E18cm⁻³, 9E18cm⁻³, 1E19cm⁻³, 2E19cm⁻³, 3E19cm⁻³, etc.
[0055] In the above embodiments, by controlling the magnesium ion doping concentration to be 1E18cm⁻³-3E19cm⁻³, the memory effect of magnesium is avoided, and magnesium ions are prevented from diffusing into the buffer layer or channel layer. The diffusion of magnesium ions into the buffer layer or channel layer will lead to a decrease in the concentration of two-dimensional electron gas and an increase in static on-resistance.
[0056] In some embodiments, please refer to Figure 3 The semiconductor structure also includes a cap layer 50, which is located on a portion of the barrier layer 40.
[0057] In some embodiments, the cap layer is made of P-type gallium nitride.
[0058] In the above embodiments, by making the cap layer material include P-type gallium nitride, electrons in the two-dimensional electron gas are prevented from being trapped by the barrier layer, thereby avoiding an increase in the dynamic on-resistance of the HEMT device.
[0059] In some embodiments, please refer to Figure 3 The semiconductor structure also includes a passivation layer 60, which covers the surface of the barrier layer 40 except for the area where the cap layer 50 is located.
[0060] As an example, the material of the passivation layer 60 includes aluminum nitride, silicon nitride, silicon dioxide, etc., thereby mitigating the influence of the surface states of the barrier layer 40 and increasing the barrier height, further reducing the probability of electrons being trapped.
[0061] In some embodiments, please refer to Figure 3 The semiconductor structure also includes a gate electrode 70, a source electrode 80, and a drain electrode 90; wherein, the gate electrode 70 is located on the cap layer 50; the source electrode 80 penetrates the passivation layer 60 and the barrier layer 40 and contacts the channel layer 30; the drain electrode 90 penetrates the passivation layer 60 and the barrier layer 40 and contacts the channel layer 30.
[0062] As an example, the materials of the gate electrode 70, source electrode 80, and drain electrode 90 may include one or more combinations of metals such as nickel, platinum, gold, titanium, and tungsten.
[0063] In some embodiments, please refer to Figure 4 This application also provides a method for preparing a semiconductor structure, including: steps S402-S410.
[0064] Step S402: Provide a substrate.
[0065] Step S404: Form a buffer layer on the substrate.
[0066] Step S406: Form a P-type barrier layer on the buffer layer; wherein the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers.
[0067] Step S408: Form a channel layer on the P-type barrier layer.
[0068] Step S410: A barrier layer is formed on the channel layer; wherein the channel layer contains a two-dimensional electron gas; a P-type barrier layer forms a preset barrier between the channel layer and the buffer layer, the preset barrier being used to prevent the two-dimensional electron gas in the channel layer from migrating to the buffer layer.
[0069] In some embodiments, step S106, forming a P-type barrier layer on the buffer layer, includes: performing doping using a delta doping process.
[0070] In the above embodiments, by employing a delta doping process for P-type ion doping, the memory effect of magnesium ion doping can be avoided, thereby improving device performance.
[0071] In some embodiments, the doping ions of the P-type barrier layer include magnesium ions; the material of the P-type barrier layer includes gallium nitride.
[0072] In some embodiments, the magnesium ion doping concentration is 1E18cm⁻³-3E19cm⁻³.
[0073] In some embodiments, the method for fabricating a semiconductor structure further includes the step of forming a cap layer on a portion of the barrier layer.
[0074] As an example, the cap material includes P-type gallium nitride.
[0075] In some embodiments, the method for fabricating a semiconductor structure further includes the step of forming a passivation layer on the surface of the barrier layer, excluding the region where the cap layer is located.
[0076] In some embodiments, the method for fabricating a semiconductor structure further includes the steps of forming a gate electrode, a source electrode, and a drain electrode; wherein the gate electrode is located on a cap layer; the source electrode penetrates the passivation layer and the barrier layer and contacts the channel layer; and the drain electrode penetrates the passivation layer and the barrier layer and contacts the channel layer.
[0077] In summary, the semiconductor structure and its fabrication method of the present invention include: a substrate, a buffer layer, a P-type barrier layer, a channel layer, and a barrier layer; wherein, the buffer layer is located on the substrate and is used to promote the crystal growth of the P-type barrier layer and the channel layer, and optimize the crystal morphology; the P-type barrier layer is located on the buffer layer, the channel layer is located on the P-type barrier layer, and the barrier layer is located on the channel layer; wherein, the channel layer contains a two-dimensional electron gas. Please refer to [reference needed]. Figure 5 and Figure 6In this diagram, the horizontal axis represents the film depth in micrometers, and the vertical axis represents the energy level height in electron volts. The 0-point mark on the vertical axis represents the Fermi level. Energy level lines greater than 0 on the vertical axis represent the conduction band bottom, and energy level lines less than 0 represent the valence band top. The 0-point mark on the horizontal axis represents the depth of the interface between the barrier layer and the channel layer. Dashed line ① represents the depth of the top surface of the cap layer, dashed line ② represents the depth of the interface between the barrier layer and the cap layer, dashed line ③ represents the depth of the interface between the barrier layer and the channel layer, and dashed line ④ represents the depth of the side of the buffer layer facing away from the substrate. The P-type barrier layer forms a preset barrier between the channel layer and the buffer layer. The preset barrier is used to prevent the two-dimensional electron gas in the channel layer from migrating to the buffer layer, thereby preventing the two-dimensional electron gas from being injected into the buffer layer and trapped by the buffer layer under the strong electric field of the drain. This results in a decrease in the concentration of two-dimensional electron gas in the channel layer during the transition of the device from the off state to the on state, thereby reducing the dynamic on-resistance. Furthermore, the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers. The relatively small thickness of the P-type barrier layer prevents excessive diffusion of P-type doped ions into the channel layer or buffer layer, thus avoiding impact on device performance. Therefore, this invention effectively overcomes various shortcomings of the prior art and has high industrial applicability. The above embodiments are merely illustrative of the principles and effects of this invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of this invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this invention.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A buffer layer is located on the substrate; A P-type barrier layer is located on the buffer layer; wherein the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers; The channel layer is located on the P-type barrier layer; A barrier layer is located on the channel layer; The channel layer contains a two-dimensional electron gas; the P-type barrier layer forms a preset barrier between the channel layer and the buffer layer, and the preset barrier is used to prevent the two-dimensional electron gas in the channel layer from migrating to the buffer layer.
2. The semiconductor structure according to claim 1, characterized in that, The doped ions of the P-type barrier layer include magnesium ions; the material of the P-type barrier layer includes gallium nitride.
3. The semiconductor structure according to claim 2, characterized in that, The magnesium ion doping concentration is 1E18cm⁻³-3E19cm⁻³.
4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a cap layer located on a portion of the barrier layer.
5. The semiconductor structure according to claim 4, characterized in that, The cap layer is made of P-type gallium nitride.
6. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: A passivation layer is applied to the surface of the barrier layer, excluding the area where the cap layer is located.
7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes a gate electrode, a source electrode, and a drain electrode; wherein the gate electrode is located on the cap layer; the source electrode penetrates the passivation layer and the barrier layer and contacts the channel layer; the drain electrode penetrates the passivation layer and the barrier layer and contacts the channel layer.
8. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; A buffer layer is formed on the substrate; A P-type barrier layer is formed on the buffer layer; wherein the thickness of the P-type barrier layer is greater than 0 nanometers and less than or equal to 100 nanometers; A channel layer is formed on the P-type barrier layer; A barrier layer is formed on the channel layer; The channel layer contains a two-dimensional electron gas; the P-type barrier layer forms a preset barrier between the channel layer and the buffer layer, and the preset barrier is used to prevent the two-dimensional electron gas in the channel layer from migrating to the buffer layer.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The doped ions of the P-type barrier layer include magnesium ions; the material of the P-type barrier layer includes gallium nitride.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The magnesium ion doping concentration is 1E18cm⁻³-3E19cm⁻³.