Data processing system and method thereof

Abstract

The data processing system described herein can be implemented with reference to or as shown in drawings. The data processing system includes a plurality of RAM blocks, a configuration selector, and a switch fabric. The configuration selector is used for identifying an active pipeline from a plurality of data processing pipelines, wherein each data processing pipeline carries a data set to be processed. Each data processing pipeline includes a multi-stage processing unit. The switch fabric is used for dynamically routing a request stage from each stage of an active pipeline to a group of RAM blocks corresponding to the request stage so as to perform read-write operation. Also described herein are data processing methods as shown in the drawings or reference drawings.

Description

This application claims priority to the filing date of earlier Singapore patent application No. 10202302927Q, entitled "Switching Shared Memory Data Processing System," filed with the Intellectual Property Office of Singapore (IPOS) on October 16, 2023. All contents and / or relevant subject matter of the prior application are incorporated herein by reference in their entirety and / or, where appropriate. Invention Field

[0001] This application relates to a data processing system, and more particularly to a data processing system and a method for implementing a switching structure, for dynamically routing request stages of an active data pipeline to RAM blocks to perform read and write operations. Background of the Invention

[0002] In image and video processing applications, such as in mobile phones, data processing is typically organized into a pipeline structure, where data enters from one end, is processed through a series of different stages, and is output from the other end. For example, in the case of image processing, data may be processed pixel by pixel, with each pixel requiring a certain amount of time, often referred to as a clock cycle. Furthermore, pixels in an image may be arranged in a grid, with adjacent pixels forming a row, and subsequent rows making up the entire image.

[0003] Each stage in this processing pipeline typically includes storage components for various purposes, including temporary storage of data. This storage is crucial for performing computations that require access to specific portions of the image, as some operations depend on information from neighboring pixels in the current row and adjacent rows.

[0004] Therefore, devices (such as mobile phones) typically contain multiple data processing pipelines, each specializing in handling different types of data. The operation of these pipelines may not interfere with each other. For example, one pipeline might handle photos, while another handles videos. While the phone may need to perform both tasks simultaneously, it doesn't need to process photos and videos at the same time. Similarly, pipelines may be dedicated to specific types of photography, such as low-light or slow-motion shooting, in which case only one operation is performed at a time.

[0005] This traditional data processing pipeline approach leads to inefficient use of storage resources because only a portion of the available storage is used at any given time. Reducing the amount of storage required by these pipelines will enable more cost-effective designs, reduce the silicon area required for device chips, and lower overall power consumption—important considerations in mobile device design.

[0006] Therefore, there is a need for a cost-effective solution to optimize the utilization of storage resources in data processing pipelines, minimize the storage required by these pipelines, and reduce the silicon area occupied on device chips, thereby reducing overall power consumption. Invention Summary

[0007] In one embodiment, a data processing system is disclosed. The data processing system may include multiple RAM blocks, a configuration selector, and a switching structure. The configuration selector is used to identify an active pipeline from multiple pipelines. Each pipeline may carry a dataset to be processed. Furthermore, each pipeline may implement multiple stages. The switching structure can dynamically route a requested stage in the active pipeline from multiple stages to a set of RAM blocks corresponding to the requested stage to perform read and write operations.

[0008] In one embodiment, the dataset associated with the active pipeline may be written as a subset to a set of RAM blocks corresponding to the requested stage. For example, in an image processing scenario, the subset may include a set of pixels written as rows to the corresponding RAM blocks in that set. Subsequently, the subset in that set of RAM blocks can be read simultaneously.

[0009] In one embodiment, writing a subset of data into the corresponding RAM block in the set of RAM blocks may include writing a predefined number of data elements to each RAM block within a single clock cycle. For example, in an image processing scenario, a data element may refer to a single pixel.

[0010] In one embodiment, after a subset of data is read from the set of RAM blocks, the set of RAM blocks can be reused to receive a new subset of data associated with the request phase.

[0011] In one embodiment, the data processing system may further include a buffer for storing response outputs to reading a subset of data from the set of RAM blocks. This buffer may be implemented as a temporary buffer.

[0012] In one embodiment, the data processing system may also implement a RequesterWrite Sequencer (RWS) configured to generate write addresses and write bank addresses for RAM blocks for each request phase, for writing subsets associated with those RAM blocks. The switching structure can dynamically route request phases by selecting a RAM block from this set of RAM blocks for each subset, based on the write RAM address and write bank address. Each subset can be written to the RAM block selected for that subset. Furthermore, the switching structure can dynamically route request phases by multicasting the write RAM address, write bank address, and subset to multiple RAM blocks. Each RAM block may be pre-configured with an associated bank address. Additionally, each subset can be written to the RAM block according to the write bank address generated by the RWS and the pre-configured bank address mapping of the RAM block.

[0013] In one embodiment, the data processing system may further include a RequesterRead Sequencer (RRS) for generating read addresses for RAM blocks for each request stage to read the dataset associated with each request stage. A switching structure can multicast the read RAM addresses to multiple RAM blocks. Each subset of the dataset can be read from the corresponding RAM block according to the read RAM addresses generated by the RRS and a pre-configured RAM address mapping between the RAM blocks.

[0014] In one embodiment, after reading a subset of data from the set of RAM blocks, the exchange structure can loop the subset back to its respective request phase via associated paths.

[0015] In one embodiment, the group of RAM blocks may include one or more additional RAM blocks besides the RAM block corresponding to the request phase. These one or more additional RAM blocks allow write and read operations to be performed independently within a single clock cycle. In this embodiment, under a dual-port emulation configuration, for read operations, the switching structure can switch subsets between the group of RAM blocks and one or more additional RAM blocks. Furthermore, under a dual-port emulation configuration, for read operations, the switching structure can reorder request phases by routing subsets associated with the requester phase to multiple RAM blocks. In one example scenario, the multiple RAM blocks may have different capacities, allowing the switching structure to switch subsets between the RAM block and one or more additional RAM blocks with capacities smaller than a predefined capacity for read operations. In another example scenario, when the size of a subset is larger than the capacity of any RAM block in the group, for write operations, the switching structure can route the subset to two or more RAM blocks in the group.

[0016] Furthermore, in another scenario, when the storage requirements of one or more request phases are less than the storage capacity of a single RAM block, the switching structure can route these request phases sequentially to a single RAM block. To this end, the switching structure can implement an arbitrator function to assign priorities when multiple request phases arrive simultaneously. Priorities can be based on a first-in, first-out (FIFO) principle, taking into account previously stored requests.

[0017] In one embodiment, when the size of the RAM block is known at the request stage, for cases where the RAM block size is not an integer multiple of the data elements, the write operation may include accumulating one or more data elements in a secondary buffer until the total memory space of these data elements matches or is close to the RAM block size. When the size of the RAM block is unknown at the request stage, for cases where the RAM block size is not an integer multiple of the data elements, the write operation may include sending a signal instructing the RAM block to write a portion of the data elements at the end of a sequential write batch.

[0018] In one embodiment, the switching structure may include a set of crosspoints for selectively connecting inputs to outputs, wherein the set of crosspoints is implemented by a multiplexer for each output to select which input the output is connected to.

[0019] In another embodiment, a data processing method is disclosed. The method may include: identifying active pipelines among multiple pipelines by a configuration selector, each pipeline carrying a dataset to be processed. Each pipeline may include multiple stages. The method may further include: dynamically routing a requested stage in the active pipeline from among the multiple stages to a set of RAM blocks corresponding to the requested stage from among multiple RAM blocks by a switching structure to perform read / write operations.

[0020] Therefore, this invention relates to the field of efficient data processing within devices, and is particularly applicable to scenarios such as image and video processing in mobile phones. This invention aims to provide an architecture in which a memory consisting of multiple RAM blocks is logically centralized and connected to a data processing pipeline via a switching structure. This switching structure routes requests from each stage in the active pipeline to RAM blocks pre-allocated for specific stages during the design process. Each stage in the pipeline can generate multiple RAM requests; therefore, each stage can be considered a requester to the switching structure.

[0021] This invention proposes a novel architecture in which a memory consisting of multiple RAM blocks is logically centralized and connected to a data processing pipeline via a switching structure. This switching structure routes requests from each stage in the active pipeline to RAM blocks pre-allocated for specific stages during the design process. Each stage in the pipeline can generate multiple RAM requests; therefore, each stage can be considered a requester to the switching structure.

[0022] This architecture offers significant advantages in memory utilization, power efficiency, and overall design cost, making it well-suited for modern mobile devices and other data-intensive applications. Brief description of the attached diagram

[0023] The accompanying drawings illustrate embodiments of the present invention and serve to explain the principles of the disclosed embodiments. However, it should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of the related invention.

[0024] Figure 1 illustrates a traditional data processing technique that uses multiple data processing pipelines.

[0025] Figure 2 shows a block diagram of a data processing system according to some embodiments of the present disclosure.

[0026] Figures 3 and 4A-4C show block diagrams of the data processing system of Figure 2, illustrating the process by which the switching structure routes the request phase to RAM blocks, according to some embodiments of this disclosure.

[0027] Figure 5 shows a schematic representation of an input image and an output image composed of multiple pixels, according to some embodiments of this disclosure.

[0028] Figures 6-7 show schematic representations of input and output images composed of multiple pixels, illustrating the process of writing data into RAM blocks according to some embodiments of this disclosure.

[0029] Figure 8 shows a block diagram of a data processing system and illustrates the process of writing data onto a RAM block, according to some embodiments of this disclosure.

[0030] Figure 9 shows a block diagram of a data processing system and illustrates the process of reading data from a RAM block, according to some embodiments of this disclosure.

[0031] Figures 10-13 show block diagrams of a data processing system implemented to simulate a dual-port configuration, according to some embodiments of this disclosure.

[0032] Figure 14 shows a block diagram of a data processing system that implements dynamic RAM sharing, according to some embodiments of this disclosure.

[0033] Figures 15-17 show block diagrams of a data processing system, illustrating different data packing scenarios according to some embodiments of this disclosure.

[0034] Figure 18 shows a schematic diagram of the switching structure according to some embodiments of the present disclosure.

[0035] Figure 19 shows a schematic diagram of a multiplexer according to some embodiments of the present disclosure.

[0036] Figure 20 illustrates a schematic diagram of a switching structure including multiple cross points implemented using multiple multiplexers, according to some embodiments of this disclosure.

[0037] Figure 21 illustrates an alternative architecture block diagram including a data processing system and a data pipeline, according to some embodiments of this disclosure.

[0038] Figure 22 shows a schematic block diagram of a switching structure divided into multiple stages, according to some embodiments of the present disclosure.

[0039] Figure 23 shows a flowchart of a data processing method according to some embodiments of the present disclosure.

[0040] Figure 24 illustrates an example computing system (e.g., as a SIMD device, client device, server device, one or more processors or similar devices) that can be used to implement the processing functions of various embodiments, according to some embodiments of this disclosure. Detailed Description of Examples

[0041] Exemplary and non-limiting embodiments of this application will now be described with reference to the accompanying drawings.

[0042] Figure 1 illustrates a conventional data processing technique that uses multiple data processing pipelines (also referred to simply as pipelines). Specifically, Figure 1 shows a block diagram of a conventional data processing technique using a first pipeline 102 and a second pipeline 104, which carry data to be processed. As mentioned above, data processing can be broken down into multiple independent pipelines. Each pipeline can carry one dataset to be processed. Furthermore, each pipeline can include multiple stages. Each pipeline can carry different types of data for processing. Moreover, in some cases, the activities of multiple pipelines may be mutually exclusive; for example, one pipeline in a mobile phone may be dedicated to processing photos, while another pipeline is dedicated to processing videos. It should be understood that a mobile phone may be able to capture photos and videos simultaneously, but not concurrently. In other cases, a mobile phone may have pipelines dedicated to specific types of photography, such as low-light or slow-motion shooting. The activities corresponding to these specific types of photography may be mutually exclusive.

[0043] For example, as shown in Figure 1, in the image and video processing process in a mobile phone, image and video processing can be broken down into independent pipelines—a first pipeline 102 and a second pipeline 104. In the first and second pipelines 102 and 104, a dataset can be input from one end, processed through several different stages, and output from the other end. As shown in Figure 1, the first pipeline 102 may include stages 102-1, 102-2, 102-3, 102-4, and 102-5, and the second pipeline 104 may include stages 104-1, 104-2, 104-3, 104-4, and 104-5. The dataset can be passed through the first and second pipelines 102 and 104 in various ways. For example, when processing an image, the data may appear pixel by pixel, and each pixel requires a certain amount of time to process, called a clock cycle. Furthermore, when processing images, pixels can be arranged into a grid, with several consecutive pixels forming a row of the grid, and subsequent pixels forming the next row, and so on.

[0044] Each stage of each pipeline 102, 104 may have an associated memory for various purposes, including storing data segments for performing calculations that require access to these image segments. It should be noted that these calculations require storing pixel streams, as the calculations involve knowing the uplink and downlink pixel values.

[0045] It should also be understood that building a pipeline can lead to wasted storage, as only a portion of the storage is used at any given time. Therefore, it is desirable to reduce the amount of storage required, thereby making the overall system cost-effective in terms of required silicon chip area and overall power consumption.

[0046] Referring now to FIG2, a block diagram of a data processing system 200 is shown according to some embodiments of the present disclosure. The data processing system 200 may receive data to be processed via multiple pipelines 102, 104. In one embodiment, the data processing system 200 may include multiple storage blocks (also referred to as random access memory (RAM) blocks) 202. In other words, the memory of the data processing system 200 may include multiple RAM blocks 202. In one embodiment, these RAM blocks 202 may be implemented as independent physical storage blocks. Alternatively, in some embodiments, these RAM blocks 202 may be implemented by creating soft partitions in the memory of the data processing system 200.

[0047] The data processing system 200 may also include a switching structure 204. The switching structure 204 is configurable to dynamically route request stages from multiple stages of an active pipeline (from pipelines 102, 104) to a set of RAM blocks pre-allocated to these request stages within multiple RAM blocks 202 to perform read / write operations. The multiple RAM blocks 202 may be logically centralized and connected to pipelines 102, 104 via the switching structure 204. This set of RAM blocks may be pre-allocated to the request stages required by each pipeline 102, 104. When the pipeline is running, the switching structure 204 can dynamically route request stages (or simply "requests") to the pre-allocated set of RAM blocks, thereby enabling simultaneous writes and reads.

[0048] The data processing system 200 may also include a configuration selector (not shown in Figure 2; see Figures 4B, 4C) for identifying active pipelines among the multiple pipelines 102, 104. It should be noted that at any given time, multiple pipelines may be active. Therefore, the configuration selector can be configured to identify one or more active pipelines from all available pipelines.

[0049] In some embodiments, the configuration selector may be integrated into the switching structure 204; alternatively, the configuration selector may be implemented as a standalone module. It should be noted that an active pipeline may refer to a series of interconnected stages currently processing data. Therefore, an active pipeline may refer to the pipeline (102 or 104) currently processing data. Therefore, the configuration selector may select between an active first pipeline 102 and an active second pipeline 104. Furthermore, it should be noted that one or more stages associated with an active pipeline may request processing of the dataset associated with that stage (the stage requesting data processing may be referred to as a "requesting stage").

[0050] Referring now to Figures 3 and 4A-4C, a block diagram of the data processing system 200 is shown, illustrating the process by which a switching structure 204 routes a request stage to RAM blocks, according to some embodiments. As shown in Figures 3 and 4A, the switching structure 204 can be configured to dynamically route a request stage from among multiple stages of an active pipeline to a set of RAM blocks corresponding to the request stage to perform read and write operations. In other words, the switching structure 204 can connect a set of multiple RAM blocks 202 to the request stage in different modes depending on pipeline activity. As described above, this set of RAM blocks can be pre-allocated to the request stage, and the switching structure 204 can dynamically route the request stage to the pre-allocated set of RAM blocks to perform simultaneous write and read operations.

[0051] As described above, the data processing system 200 may include a configuration selector 402 for identifying one or more active pipelines from a plurality of pipelines 102, 104. For example, as shown in Figures 3 and 4B, the configuration selector 402 may identify pipeline 102 as an active pipeline. Therefore, when pipeline 102 is active and stage 102-5 is a requested stage, the switching structure 204 may connect a set of RAM blocks, including RAM blocks 202-1, 202-2, 202-3, 202-4, and 202-5, to the requested stage 102-5. Similarly, as shown in Figures 3 and 4C, the configuration selector 402 may identify pipeline 104 as an active pipeline. Therefore, when pipeline 104 is active and stage 104-4 is a requested stage, switching structure 204 can connect a set of RAM blocks, including RAM blocks 202-3, 202-4, 202-5, 202-6, and 202-7, to the requested stage 104-4. Furthermore, as shown in Figures 3 and 4C, when pipeline 104 is active and stage 104-5 is a requested stage, switching structure 204 can connect a set of RAM blocks, including RAM blocks 202-1 and 202-2, to the requested stage 104-5. Thus, in a particular selected configuration, switching structure 204 can perform a switch to connect the requested stage to the pre-allocated RAM blocks associated with that requested stage.

[0052] Referring to Figure 5, a schematic representation 500 of an input image consisting of multiple input pixels 502 and an output image consisting of multiple output pixels 504 is shown according to some embodiments of the present disclosure. As shown in Figure 5, in an example operation of the data processing system 200, a stage in a pipeline may require computation to be performed on a 5x5 block of input pixels 502A in the input image to generate each corresponding output pixel 504A in the output image. As shown in Figure 5, the input pixels of the input image can arrive row by row. Furthermore, the output pixels 504 of the output image can be generated row by row by sliding a 5x5 window over the input image. Therefore, a particular output pixel (e.g., output pixel 504A) may require corresponding input pixels (e.g., the 5x5 block 502A of input pixels 502) from five rows of pixels that have arrived and been stored to allow computation. This can be achieved by writing the input pixels into RAM blocks in arrival order, with each pixel stored at an incrementing address in RAM, and each RAM storing one row of pixels.

[0053] Figures 6-7 illustrate schematic representations 600 and 700 of an input and output image composed of multiple pixels, demonstrating the process of writing data into RAM blocks according to some embodiments of this disclosure. A dataset associated with an active pipeline can be written to a set of RAM blocks corresponding to a requested stage as a subset of the dataset. The subset of the dataset in this set of RAM blocks can be read simultaneously.

[0054] As described above, input pixels arrive row by row, and output pixels are generated row by row by sliding a 5x5 window across the input image. A specific output pixel requires that the corresponding input pixels from the five rows have arrived and been stored for computation. Therefore, input pixels can be written to RAM blocks upon arrival. For example, as shown in Figure 6, pixels associated with the input image (i.e., the dataset) can be written to corresponding RAM blocks 602-1, 602-2, 602-3, 602-4, and 602-5 (collectively referred to as RAM block 602; corresponding to RAM block 202) as a subset of the dataset. Pixels (i.e., the dataset) can be written to RAM blocks 602 in incrementing addresses, such that each RAM block 602 stores (i.e. writes) one row of pixels (i.e., the subset) of the input image pixels (i.e., the dataset), as shown in Figure 6.

[0055] Once enough input pixels arrive, a subset of data written to a set of (five) RAM blocks 602 can be read simultaneously. After reading a subset of data from the set of RAM blocks 602, the set of RAM blocks 602 can receive a new subset of data associated with the request phase, thereby enabling reuse of RAM blocks 602.

[0056] The data processing system 200 may also include a buffer 604 (also called a "temporary buffer") for storing the output generated from reading a subset of data from RAM block 602. Specifically, the output of reading a subset of data may be stored in buffer 604 until a 5x5 pixel block is obtained for computation. Buffer 604 may be configured such that newly read data is appended to one side, while previously read data is shifted down. In this way, a 5x5 buffer advances one pixel to the right each clock cycle.

[0057] Once a pixel at a specific location is read, that pixel may no longer be needed and can be replaced by a new input pixel. In this way, each RAM block 602 can be reused for the next row. Therefore, in the example shown in Figure 6, only five RAM blocks are needed to process the entire image, regardless of how many rows the input pixels contain.

[0058] In some embodiments, writing a subset of data into an associated RAM block within a set of RAM blocks may involve writing a predefined number of data elements to each RAM block within a single clock cycle. As shown in Figures 6-7, each RAM block 602 can write and read two pixels per clock cycle. This satisfies the required pixel throughput within a specific clock cycle. Therefore, if two pixels are read per cycle, calculations for two pixels can be performed within each cycle, resulting in two output pixels 606.

[0059] In some cases, the RAM block 202 used may only be able to perform a single read or a single write operation within one clock cycle. Therefore, a read operation cannot be performed on a RAM block that is currently being written to. To overcome this challenge, the number of RAM blocks 202 used can be increased by one. In other words, in addition to the RAM block corresponding to the request phase, the group of RAM blocks may include one or more additional RAM blocks to perform both write and read operations simultaneously within a single clock cycle. As understood, using additional RAM blocks may result in an additional row of output generation latency. As shown in Figure 7, five RAM blocks 602-1, 602-2, 602-3, 602-4, and 602-5 can perform five read operations within one clock cycle, while the sixth RAM block 702 (i.e., the sixth row 702) can perform one write operation.

[0060] Referring now to FIG8, a block diagram 800 of a data processing system 200 is shown, illustrating the process of writing data to RAM blocks 202 according to some embodiments. As shown, data can be provided via pipeline 802 (corresponding to pipelines 102, 104) through request stage 804. In some embodiments, the data processing system 200 may include a Requester Write Sequencer (RWS) 806, which is configured to generate write RAM addresses and write bank addresses for RAM blocks (from multiple RAM blocks 202) for each request stage (i.e., request stage 804) to write the dataset associated with that request stage. In some embodiments, as shown in FIG8, the RWS 806 may be implemented in the request stage 804 of pipeline 802. The RWS 806 may select RAM blocks from multiple RAM blocks 202 based on the generated write RAM addresses and write bank addresses for writing a row of pixels of an input image. The RWS 806 can generate a write RAM address, which increments once after each pair of pixels is written.

[0061] In some embodiments, as shown in FIG8, the switching structure 204 may implement a switching function 808 for routing data of the request stage 804 and its bank address to the corresponding RAM block. To this end, in one embodiment, the switching structure 204 may dynamically route the request stage to a set of RAM blocks by selecting a RAM block from a set of RAM blocks for each subset based on the write RAM address and the write bank address. Each subset may be written to the RAM block selected for that subset. As shown in FIG8, the switching structure 204 may dynamically route the request stage 804 to a set of RAM blocks including RAM blocks 202-1, 202-2, 202-3, 202-4, and 202-5. Therefore, a subset (i.e., pixel rows) may be written to the corresponding RAM block in the set of RAM blocks including 202-1 to 202-5. The switching structure 204 may select a RAM block for each subset based on the write RAM address and the write bank address so that the subset is written to the selected RAM block.

[0062] In another embodiment, the switching structure 204 can dynamically route the request phase by multicasting the write RAM address, write bank address, and subset to multiple RAM blocks. Each RAM block can be pre-configured with an associated bank address (i.e., a register storing its specific bank address), so that each subset can be written to that RAM block according to the write bank address mapping generated by RWS 806 and the pre-configured bank address of the RAM block. As shown in FIG8, the switching function 808 of the switching structure 204 can multicast the write RAM address, write bank address, and subset to multiple RAM blocks 202. Since each RAM block has its associated bank address pre-configured, the RAM block matching the bank address is selected to perform the write operation. The RAM address can refer to the address of the pixel (subset) in the corresponding RAM block. For example, as shown in FIG7, when a pixel is written to the sixth row 702, each pair of pixels can be written with the RAM address associated with that pixel pair.

[0063] Referring to Figure 9, a block diagram 900 of a data processing system 200 is shown, along with the process of reading data from RAM block 202, according to some embodiments. As shown, data can be provided via pipeline 902 (corresponding to pipelines 102, 104) through request stage 904. In some embodiments, the data processing system 200 may include a Requester Read Sequencer (RSS) 906, which can be configured to generate read RAM addresses for each request stage to read the dataset associated with that request stage. The RRS 906 may be synchronized with an RWS 806. The switching structure 204 of the data processing system 200 may implement a switching function 808 for dynamically routing request stages to a set of RAM blocks. In one embodiment, the switching function 808 can dynamically route the request phase (i.e., 804) to a set of RAM blocks including RAM blocks 202-1, 202-2, 202-3, 202-4, and 202-5 by multicasting the read RAM addresses to the set of RAM blocks. Each subset can be read from the RAM blocks according to the read RAM address and RAM block pre-configured RAM address mapping relationship generated by RRS 906.

[0064] In one embodiment, as shown in FIG9, RRS 906 may be implemented in request phase 904. Alternatively, RRS 906 may also be implemented in switching structure 204 or as a standalone module. RRS 906 may not require any bank selection logic. Instead, the RAM address may be multicast to a set of RAM blocks including RAM blocks 202-1, 202-2, 202-3, 202-4, and 202-5. Once the read operation is complete, the data can be returned to request phase 904 via switching structure 204 through five independent paths associated with RAM blocks 202-1, 202-2, 202-3, 202-4, and 202-5.

[0065] Referring to Figure 10, a block diagram of a data processing system 200 for simulating a dual-port configuration is shown, according to some embodiments. As described above, and as shown in Figures 8-9, the switching structure 204 can implement a switching function 808 for dynamically routing request phases to a set of RAM blocks.

[0066] In some embodiments, as shown in FIG10, the data processing system 200 simulating a dual-port configuration can implement multiple switching functions, such as a first switching function 1004A, a second switching function 1004B, etc. (hereinafter, the switching functions can be collectively referred to as switching functions 1004). Specifically, the switching structure 204 of the data processing system 200 can implement multiple switching functions 1004. The dataset can be provided by the request phase of pipeline 1002 (corresponding to pipelines 102, 104). To perform a read operation, the switching function 1004 can switch a subset of the dataset between a set of RAM blocks and one or more additional RAM blocks. Therefore, when simulating a dual-port memory configuration using additional RAM blocks, the switching structure 204 (i.e., multiple switching functions) can perform additional functions such as switching between adjacent RAM block pairs.

[0067] For example, as shown in Figure 10, six RAM blocks 202-1 to 202-6 (adding one extra RAM block to the existing five) can be used. The switching structure 204 can perform an additional function of switching between adjacent RAM block pairs to select five RAM blocks from 202-1 to 202-6 for reading in one clock cycle. Therefore, when using the extra RAM block, although only five RAM blocks need to be read and returned (instead of six), the switching function 1004 can return only five data outputs from the six RAM blocks 202-1 to 202-6. For example, the above function can be implemented using five dual-input switches. As can be understood, the number of switching functions (i.e., switches) is equal to the number of data reading ports. The number of switching functions can vary depending on the number of data ports (here, data reading port 0 corresponds to the first switching function 1004A).

[0068] In some embodiments, switching function 1004 can multicast the read RAM address to five RAM blocks to read a subset of data from the RAM blocks according to the read RAM address mapping generated by RRS 906 and the RAM block's pre-configured RAM address mapping. For each read data port, a switch (i.e., one of the multiple switching functions 1004) can select a subset of RAM read data to return.

[0069] Referring to Figure 11, another block diagram of a data processing system 200 for simulating a dual-port configuration is shown, according to some embodiments. As described in Figure 10, the data processing system 200 for simulating a dual-port configuration may implement multiple switching functions 1004. Data sets may be provided by the request phase of pipeline 1002 (corresponding to pipelines 102, 104).

[0070] In the above configuration, the rows (i.e., subsets) returned to the read data port may be in different orders depending on their position in the image. For example, at one location, the top row may appear at read data port 0, while at another location, the top row may appear at read data port 1. Since computation may require different processing based on the relative position of the rows, pipeline stages may require additional processing to rearrange the rows in the correct order before performing computation. To avoid additional complexity in stages, this rearrangement can be done internally within the switching structure 204. To this end, in a dual-port simulation configuration, for read operations, the switching structure 204 can reorder (i.e., rearrange) the request stage to the set of RAM blocks by routing the subsets associated with the request stage to multiple RAM blocks. As shown in Figure 11, the switching function 1004 can select among all six RAM blocks to route the read data from the top RAM block to read data port 0. To simplify computation, the switching structure 204 can rearrange the rows (i.e., subsets) so that the rows appear in a top-to-bottom order on the read data ports. As mentioned above, the number of switching functions implemented can be equal to the number of data reading ports.

[0071] Referring to Figure 12, another block diagram of the data processing system 200 is shown, according to some embodiments. As described in Figure 10, the data processing system 200, configured to simulate a dual-port setup, can implement multiple switching functions 1004. Data sets can be provided by the request phase of pipeline 1002 (corresponding to pipelines 102, 104).

[0072] To perform a write operation, when the size of the subset is larger than the size of any single RAM block in the RAM block set, the switching structure 204 can route the subset to two or more RAM blocks in the RAM block set. In other words, when a single row (i.e., the subset) cannot fit into any RAM block in the RAM block set, multiple RAM blocks (e.g., two RAM blocks) may be required. In this case, as shown in Figure 12, the switching structure 204 can multicast the RAM address to all relevant RAM blocks in either the first group (represented by "A" in the figure) or the second group (represented by "B" in the figure). Furthermore, the switching structure 204 can perform a switching function to return read data to the correct group; the routing can be determined by the bank address. It should be noted that the first and second groups ("A", "B") may be part of the configuration and can be determined based on how the switching structure 204 routes RAM addresses and data.

[0073] Referring to Figure 13, another block diagram of the data processing system 200 is shown, according to some embodiments. As described in Figure 10, the data processing system 200, configured to simulate a dual-port setup, can implement multiple switching functions 1004. Data sets can be provided by the request phase of pipeline 1002 (corresponding to pipelines 102, 104).

[0074] To perform a write operation, when the size of the subset is larger than the size of any single RAM block in the RAM block set, the switching structure 204 can route the subset to two or more RAM blocks in the RAM block set. Specifically, when the RAM block set contains RAM blocks of different sizes, some RAM blocks may be able to hold the entire subset (i.e., the entire row), while others may not. In this case, for high-capacity RAM blocks, data reading may not require switching functionality. However, a portion of the bank address can be routed to the high-capacity RAM block as part of the read address. Therefore, for high-capacity RAM blocks, certain bank addresses (i.e., certain bits) may be added to the RAM address. It is important to note that the read data paths for different RAM blocks may differ.

[0075] In some implementations, one or more portions of the RWS 806 and RRS 906 may be replicated within the switching structure 204 or a RAM block. Replicating the RWS 806 and RRS 906 helps avoid long-distance address transmissions. The RWS 806 and RRS 906 (or copies thereof) can be placed close to each RAM block and addresses can be generated locally, thus eliminating the need to send long-distance addresses from the (central) RWS 806 and RRS 906. The copies of the RWS 806 and RRS 906 can be synchronized with the RWS 806 within the pipeline stage via a signal between the original and copy locations.

[0076] Referring to Figure 14, a block diagram of a data processing system 200 implementing dynamic RAM sharing is shown according to some embodiments. When the memory requirements of one or more request stages are less than the memory capacity of a single RAM block, the switching structure 204 can route these request stages one by one to the single RAM block. As shown in Figure 14, the total size and bandwidth of the dataset 1406 associated with the first request stage 1402 and the dataset 1408 associated with the second request stage 1404 may be less than the memory capacity of a single RAM block 202-2. In this case, the switching structure 204 can route the datasets 1406 and 1408 associated with request stages 1402 and 1404 one by one to the single RAM block 202-2. Therefore, when the memory requirements of multiple request stages 1402 and 1404 are less than the capacity and bandwidth of a single RAM (i.e., 202-2), these request stages 1402 and 1404 can share that single RAM. Sharing can be done sequentially, that is, by ordering access to each request stage 1402, 1404 so that they are not requested at the same time.

[0077] However, ordering access to each request stage 1402, 1404 can present certain challenges in terms of sequence. To address this, the switching structure 204 can implement an arbitration function to assign priorities to request stages when they arrive simultaneously, thereby controlling access to the shared RAM block. In other words, when two requests arrive simultaneously, the arbitration function can choose which request stage to allow access first. In some embodiments, priorities can be based on a First-In-First-Out (FIFO) criterion, i.e., the order is determined based on previously stored requests. Therefore, the arbitration function can be performed based on priority or the fullness of the FIFO storage. To implement arbitration, unsuccessful requests can be stored for later completion. The storage of unsuccessful requests can be implemented by using a FIFO criterion for each request stage; the request is stored until it can be processed. In some embodiments, the arbitration function can be sensitively controlled based on the number of storage requests associated with the FIFO criterion to prevent request overflow. Furthermore, the switching structure 204 can apply offsets to ensure that requests do not overlap.

[0078] In some embodiments, the switching structure 204 can also manage addressing within a RAM block by using a base address for each request stage. Using a base address ensures that a request stage can only access the RAM block region allocated to that request stage.

[0079] Referring now to Figures 15-17, a block diagram of the data processing system 200 under different data packing scenarios is shown, according to some embodiments. As shown in Figure 15, in some embodiments, it may be necessary to write a data element (e.g., a pixel) to each of RAM blocks 202-1, 202-2, and 202-3 to obtain sufficient RAM block bandwidth. Furthermore, this can improve efficiency because some RAM blocks may be more efficient than others. For example, tall and narrow RAM blocks may be less efficient in terms of area usage and / or power consumption.

[0080] As shown in Figure 15, the image processing pipeline may carry pixels (i.e., data elements), each pixel being 8, 10, 12, 14, or 16 bits. It should be noted that different request stages may use different pixel sizes. For example, if request stage 1502 uses 14-bit pixels, these pixels can be stored in a 28-bit wide RAM block, with each word storing two pixels. In one example technique, request stage 1502 may transmit 28 bits of pixels at once via exchange structure 204. In another example technique, request stage 1502 may send pixels one by one via exchange structure 204. Furthermore, logic within the RAM block can pack each pair of pixels into a RAM word. In some cases, it may be simpler for request stage 1502 to always send an even number of pixels so that the RAM block always has enough pixels to write a word. However, the two example techniques described above can be used in combination, with some packing occurring in the request stage and further packing occurring within the RAM block.

[0081] In some scenarios, complex situations may arise when RAM blocks allow data words (such as pixels) to be packed into RAM words, but the RAM size is not an integer multiple of the data word size. As shown in Figures 16-17, to efficiently pack data into RAM words, one or more data words can be accumulated in an auxiliary buffer until enough data is written to a complete RAM word. However, this packing technique is only effective when data is written sequentially. When the request stage (e.g., request stage 1602) knows the RAM block size (e.g., RAM block 202-1) and the RAM block size is not an integer multiple of the data element (i.e., pixel), one or more data elements can be accumulated in the auxiliary buffer until the total memory space of these data elements approaches the RAM block size. In other words, if request stage 1602 knows the size of RAM block 202-1, request stage 1602 can ensure that the number of pixels written always corresponds to a complete RAM word. Therefore, when the request stage knows the packing information, the request stage can send pairs of pixels, as shown in Figure 16. It should be noted that the ports and memory widths of the switching structure 204 may be heterogeneous.

[0082] When the RAM block size is unknown during the request phase (e.g., request phase 1602) and the RAM block size is not an integer multiple of the data elements, a signal can be sent to instruct the RAM block to write a portion of the data elements at the end of a sequential write batch. Therefore, when request phase 1602 does not know the RAM word size, this signal can be used to instruct RAM block 202-1 to write a portion of the word at the end of a sequential write batch. Alternatively, the write can be triggered by an out-of-order write address. Reads can be non-sequential, provided the read frequency allows for additional access when the data word spans two RAM words. Sequential reads can be handled by loading RAM words into a temporary buffer and removing data words one by one.

[0083] Referring now to FIG18, a schematic diagram of the switching structure 204 is shown according to some embodiments of the present disclosure. For example... Figure 18 As shown, the switching structure 204 can be implemented via a set of cross points 1802 configured to selectively connect inputs to outputs. This set of cross points 1802 can be implemented via a multiplexer, where each output selects the input to which it is connected.

[0084] Figure 19 shows a schematic diagram of a multiplexer 1900, according to some embodiments. As is generally known, a multiplexer 1900 (also known as a "mux" or "data selector") is a device that selects one input from multiple analog or digital input signals and forwards the selected input to a single output. The selection is controlled by a set of digital inputs called select lines.

[0085] Figure 20 illustrates a schematic diagram 2000 of a switching structure 204, including an example implemented using multiplexers 1900 with multiple crosspoints 1802, according to some embodiments. As shown in Figure 20, the switching structure 204 is logically composed of a set of crosspoints 1802 for selectively connecting inputs 2002 to outputs 2004. This structure is also referred to as a crossbar. In some configurations, the crossbar can be implemented using multiplexers 1900 for each output, allowing each multiplexer to select which input the output is connected to. In embodiments of this disclosure, it may be advantageous to construct the switching structure 204 using multiple smaller switching structures. For example, one embodiment of the switching structure 204 may include a 3-layer switching structure (which may be referred to as a Clos network).

[0086] In some embodiments, in addition to connecting pipeline stages to RAM blocks, the switching structure 204 may also connect other functions. For example, if the RAM blocks are used as lookup tables (LUTs) storing tables mapping pixel values ​​to pre-configured values, the switching structure 204 can provide a path for an external entity (such as a central processing unit, CPU) to write pre-configured data into the RAM blocks. Furthermore, providing the CPU with read access to all RAM blocks may be advantageous for debugging purposes. Additionally, another function can route the connection of a built-in self-test (BIST) unit to the RAM block group during manufacturing testing.

[0087] In some embodiments, it may be advantageous to divide the switching structure into multiple stages and the RAM blocks into several groups based on the physical layout of the various circuit elements constituting the pipeline stages, switching structure, and RAM blocks. This is illustrated in Figures 21-22.

[0088] Figure 21 shows a block diagram of an alternative architecture including a data processing system 2100 and data pipelines 2102 and 2104, according to some embodiments. As shown in Figure 21, pipelines 2102 and 2104 provide datasets to a switching structure 2106, which routes requests from pipelines 2102 and 2104 to multiple RAM blocks 2108. In the current implementation, the switching structure 2106 can be divided into three stages—2106A, 2106B, and 2106C. Furthermore, pipelines 2102 and 2104 can be divided into four groups—2102A, 2102B, 2104A, and 2104B. Further, the RAM blocks can be divided into four groups—2108A, 2108B, 2108C, and 2108D. The four groups 2102A, 2102B, 2104A, and 2104B of pipelines 2102 and 2104 can be distributed around the three stages 2106A, 2106B, and 2106C of switching structure 2106. Figure 22 shows a schematic block diagram of switching structure 2106 divided into multiple stages, according to some embodiments. Dividing switching structure 2106 into multiple stages and RAM blocks into groups 2108A, 2108B, 2108C, and 2108D can offer advantages in terms of the total number of switching elements required.

[0089] Referring now to FIG. 23, a flowchart of a data processing method 2300 is shown, according to some embodiments of the present disclosure. For example, the method 2300 may be performed by the data processing system 200 shown in FIG. 2. As described above, the data processing system 200 may include a plurality of RAM blocks 202, and the data processing system 200 may implement modules such as a switching structure 204 and a configuration selector 402.

[0090] In step 2302, a configuration selector 402 can be used to identify an active pipeline from among multiple pipelines. As described above, multiple data processing pipelines (e.g., pipelines 102, 104) can carry the dataset to be processed. Furthermore, each pipeline may include multiple stages (102-1, 102-2... and 104-1, 104-2... etc.).

[0091] In step 2304, a request stage from the active pipeline can be dynamically routed by the switching structure 204 to a set of RAM blocks corresponding to the request stage in RAM block 202 to perform read / write operations. In some embodiments, the dataset associated with the active pipeline can be written to a set of subsets (i.e., a row) of RAM blocks for each corresponding request stage. The subsets in this set of RAM blocks can be read simultaneously. Furthermore, writing a subset of data into the relevant RAM block can include writing a predefined number of data elements (i.e., pixels) to each RAM block of the set of RAM blocks within a single clock cycle.

[0092] In some embodiments, method 2300 may include an additional step of receiving a new subset of data related to the request phase into the set of RAM blocks after reading a subset of data from the set of RAM blocks; this allows the set of RAM blocks to be reused.

[0093] In some embodiments, method 2300 may include an additional step of storing the output generated by reading a subset of data from the RAM block group in a buffer. This buffer may be implemented as a temporary buffer.

[0094] In some embodiments, method 2300 may include an additional step in which the request write sequencer (RWS) 806 generates a write RAM address and a write bank address for a RAM block for each request stage. The write RAM address and write bank address can be used to write a subset of the dataset into the RAM block.

[0095] In some embodiments, the step of the dynamic routing request phase of switching structure 204 to a set of RAM blocks may include: selecting a RAM block from the set of RAM blocks for each subset based on a write RAM address and a write bank address. Each subset may be written to the selected RAM block. Alternatively, the step of the dynamic routing request phase of switching structure 204 to a set of RAM blocks may include: multicasting the write RAM address, the write bank address, and the subset to multiple RAM blocks. Each RAM block may be pre-configured with its associated bank address. Furthermore, each subset may be written to the RAM block according to the mapping between the write bank address generated by RWS and the pre-configured bank addresses of the RAM block.

[0096] In some embodiments, method 2300 may include an additional step in which the request read sequencer (RRS) 906 generates read RAM addresses for RAM blocks for each request phase, for reading the dataset associated with each request phase. The read RAM addresses may be multicast to multiple RAM blocks 202 by the switching structure 204. Each subset of the dataset may be read from the RAM block according to the mapping between the read RAM addresses generated by RRS 906 and the pre-configured RAM addresses of the RAM blocks.

[0097] In some embodiments, method 2300 may include an additional step of routing the subset of data back to its respective request phase via its associated path by the switching structure 204 after reading the subset of data from the RAM block group.

[0098] In some embodiments, the group of RAM blocks may include one or more additional RAM blocks besides the RAM block corresponding to the requested phase, so that write and read operations can be performed independently within a single clock cycle. When configuring a dual-port emulation and performing a read operation, method 2300 may further include switching a subset of data between the RAM block group and one or more additional RAM blocks by the switching structure 204. When configuring a dual-port emulation and performing a read operation, method 2300 may further include reordering the requested phase by the switching structure 204 by routing the subset of data associated with the requested phase to multiple RAM blocks.

[0099] In some embodiments, when multiple RAM blocks 202 have different capacities, method 2300 may include switching a subset of RAM blocks between one or more additional RAM blocks with capacities smaller than a predefined capacity in order to perform a read operation. This switching may be performed by a switching structure 204.

[0100] In some embodiments, to perform a write operation, when the size of the subset is greater than the capacity of any one of the RAM blocks in the group of RAM blocks, the switching structure 204 can route the subset to two or more RAM blocks in the group of RAM blocks.

[0101] In some embodiments, when the memory requirements of one or more request stages are less than the memory capacity of a single RAM block, method 2300 may include the step of routing one or more request stages one by one to a single RAM block by switching structure 204. To this end, in some embodiments, switching structure 204 may implement an arbitrator function to assign priorities to request stages that arrive simultaneously. For example, the priority may be based on a first-in, first-out (FIFO) criterion, allocated according to previously stored requests.

[0102] In some embodiments, for performing a write operation, when the size of the RAM block is known at the request stage and the size of the RAM block is not an integer multiple of the data elements, method 2300 may further include accumulating one or more data elements in a secondary buffer until the combined memory space of these data elements approaches the size of the RAM block. When the size of the RAM block is unknown at the request stage and the size of the RAM block is not an integer multiple of the data elements, method 2300 may further include sending a signal indicating the RAM block to write a portion of the data elements at the end of the sequential write batch.

[0103] Referring now to Figure 24, an example computing system 2400 is shown, which can be used to implement processing functions in various embodiments (e.g., as a Single Instruction Multiple Data (SIMD) device, a client device, a server device, one or more processors, etc.). Those skilled in the art will also be able to understand how to implement the invention using other computer systems or architectures. The computing system 2400 may represent, for example, a user device such as a desktop device, laptop, mobile phone, personal entertainment device, DVR, or any other type of dedicated or general-purpose computing device, which may be implemented as needed for a particular application or environment. The computing system 2400 may include one or more processors, such as processor 2402, which may be connected via bus 2404 or other communication media. Processor 2402 may be implemented using a general-purpose or dedicated processing engine, such as a microprocessor, microcontroller, or other control logic. In this example, processor 2402 may also be an artificial intelligence (AI) processor, which may be implemented as a Tensor Processing Unit (TPU), a Graphics Processing Unit (GPU), or a custom programmable solution (FPGA).

[0104] The computing system 2400 may also include a memory 2406, such as random access memory (RAM) or other dynamic memory, for storing instructions and information executed by the processor 2402. The memory 2406 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by the processor 2402. The computing system 2400 may also include a read-only memory (“ROM”) or other static storage device coupled to the bus 2404 for storing static information and instructions of the processor 2402.

[0105] The computing system 2400 may also include a storage device 2408, such as a media drive 2410 and a removable storage interface. The media drive 2410 may include a drive or other mechanism for supporting fixed or removable storage media, such as a hard disk drive, floppy disk drive, tape drive, SD card interface, USB interface, Micro-USB, optical disc drive, CD or DVD drive (R or RW), or other removable or fixed media drive. The storage medium 2412 may include, for example, a hard disk, magnetic tape, flash memory, or other fixed or removable media, read from and written to by the media drive 2410. As these examples illustrate, the storage medium 2412 may include a computer-readable storage medium in which specific computer software or data is stored.

[0106] In other embodiments, storage device 2408 may include other similar means to allow computer programs or other instructions or data to be loaded into computing system 2400. These means may include, for example, removable storage unit 2414 and storage unit interface 2416, such as program cartridges and cartridge interfaces, removable memory (e.g., flash memory or other removable storage modules) and storage slots, as well as other removable storage units and interfaces for transferring software and data from removable storage unit 2414 to computing system 2400.

[0107] The computing system 2400 may also include a communication interface 2418. The communication interface 2418 allows software and data to be transferred between the computing system 2400 and external devices. Examples of the communication interface 2418 may include a network interface (e.g., Ethernet or other network interface card), a communication port (e.g., a USB port, a Micro-USB port), near-field communication (NFC), etc. Software and data transmitted through the communication interface 2418 exist in the form of signals, which may be electronic signals, electromagnetic signals, optical signals, or other signals that can be received by the communication interface 2418. Signals are provided to the communication interface 2418 via a channel 2420. The channel 2420 can transmit signals and may be implemented via wireless media, wires or cables, optical fibers, or other communication media. Examples of the channel 2420 include telephone lines, cellular telephone links, radio frequency links, Bluetooth links, network interfaces, local or wide area networks, and other communication channels.

[0108] The computing system 2400 may also include an input / output (I / O) device 2422. Examples include, but are not limited to, a display, keyboard, microphone, audio speaker, vibration motor, LED light, etc. The I / O device 2422 may receive user input and display the output of calculations performed by the processor 2402. In this document, "computer program product" and "computer-readable medium" may generally be used to refer to storage media, such as memory 2406, storage device 2408, removable storage unit 2414, or signals on channel 2420. These and other forms of computer-readable media may be used to provide the processor 2402 with one or more sequences of instructions for execution. These instructions are generally referred to as "computer program code" (which may constitute a computer program or other grouping) and, when executed, enable the computing system 2400 to perform the functions or features of embodiments of the present invention.

[0109] In embodiments using software-implemented elements, the software may be stored in a computer-readable medium and loaded into the computing system 2400 via a removable storage unit 2414, a media drive 2410, or a communication interface 2418. Control logic (in this example, software instructions or computer program code) causes the processor 2402 to perform the functions described in this invention when executed by the processor 2402.

[0110] In this application, unless otherwise stated, the terms “comprising,” “including,” and their grammatical variations are intended to mean “open” or “inclusive” language, that is, including not only the listed elements but also other elements not explicitly listed.

[0111] Here, the term “about”, in the context of formulation component concentration, usually means ±5%, more usually ±4%, more usually ±3%, more usually ±2%, even more usually ±1%, and more commonly ±0.5%.

[0112] In this disclosure, some embodiments may be described in a range format. This range format is used for convenience and brevity only and should not be construed as a strict limitation of the disclosed range. Therefore, a description of a range should be considered as explicitly disclosing all possible subranges and the individual values ​​within that range. For example, describing a range from 1 to 6 should be considered as explicitly disclosing subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual values ​​within that range, such as 1, 2, 3, 4, 5, and 6. This principle applies regardless of the width of the range.

[0113] Various other modifications and adaptations to this application will be apparent to those skilled in the art upon reading the foregoing disclosure, without departing from the spirit and scope of this application, and it is intended that all such modifications and adaptations be included within the scope of protection of the appended claims. Reference number 102 First production line 102-1, 102-2, 102-3, 102-4, 102-5 Stages associated with the first production line 104 Second production line 104-1, 104-2, 104-3, 104-4, 104-15 Stages associated with the second production line 200 Data processing system 202 RAM block 204 Exchange structure 402 Configuration Selector 502 Input pixels 502A 5×5 input pixel block 504 Output pixels 504A Output pixels 602A, 602B, 602C, 602D, 602E, 602F RAM block 604 Buffer 606 Output pixels 802 assembly line 804 Request phase 806 Request to write to the sequencer (RWS) 902 assembly line 904 Request phase 906 Request Read Sequencer (RRS) 1002 assembly line 1004A, 1004B Switch function 1402 First request phase 1404 Second Request Phase 1406, 1408 Dataset 1502 Request phase 1602 Request phase 1802 Intersection 1900 Multiplexer 2000 Schematic diagram of the exchange structure 2002 enter 2004 Output 2100 Data processing system 2102, 2104 Data pipeline 2102A, 2102B, 2104A, 2104B Assembly line grouping 2106 Exchange structure 2106A, 2106B, 2106C Exchange structure stage 2108 RAM block 2108A, 2108B, 2108C, 2108D RAM block 2400 Computing System 2402 processor 2404 bus 2406 memory 2408 storage devices 2410 Media Driver 2412 storage media 2414 Removable storage unit 2416 Storage unit interface 2418 Communication interface 2420 aisle 2422 Input / output (I / O) devices

Claims

1. A data processing system, comprising: Multiple RAM blocks; A configuration selector for identifying an active pipeline from multiple pipelines, where each pipeline carries a dataset to be processed and each pipeline includes multiple stages; as well as A switching structure for dynamically routing request stages from multiple stages of the activity pipeline to a pre-allocated set of RAM blocks corresponding to the request stage to perform read and write operations.

2. The data processing system of claim 1, wherein the dataset associated with the activity pipeline is written to a subset of a pre-allocated RAM block set corresponding to the request phase, and the subset of the RAM block set can be read simultaneously.

3. The data processing system of claim 2, wherein writing a subset of data in a RAM block associated with the set of RAM blocks comprises writing a predefined number of data elements in each RAM block within a single clock cycle.

4. The data processing system of claim 2, wherein after reading a subset of data from the RAM block set, the RAM block set is reused to receive a new subset of data related to the request phase.

5. The data processing system of claim 2, further comprising a buffer for storing output generated from reading a subset of data from the set of RAM blocks.

6. The data processing system of claim 2, further comprising a request write sequencer (RWS) for generating a write RAM address and a write bank address for each request phase, so as to write a subset of data associated with the RAM block.

7. The data processing system of claim 6, wherein the switching structure dynamically routes the request phase to a pre-allocated set of RAM blocks by selecting a RAM block from a set of RAM blocks for each subset based on the write RAM address and the write bank address, and each subset is written to the selected RAM block.

8. The data processing system according to claim 6, wherein the switching structure dynamically routes the request phase to a set of RAM blocks by multicasting the write RAM address, the write bank address and the subset to multiple RAM blocks, wherein each RAM block is pre-configured with an associated bank address, and each subset is written to the corresponding RAM block according to the write bank address generated by RWS and the bank address pre-configured in the RAM block.

9. The data processing system of claim 2, further comprising a request read sequencer (RRS) for generating read addresses for RAM blocks for each request phase to read datasets associated with each request phase, wherein the switching structure multicasts the read RAM addresses to multiple RAM blocks, and each subset of datasets is read from the RAM blocks according to a pre-configured address mapping between the read RAM addresses generated by the RRS and the RAM blocks.

10. The data processing system of claim 2, wherein after reading a subset of data from the set of RAM blocks, the exchange structure returns the subset of data to its respective request stage via an associated path.

11. The data processing system of claim 2, wherein the set of RAM blocks includes one or more additional RAM blocks besides the RAM block corresponding to the request phase, so as to perform write and read operations respectively in a single clock cycle.

12. The data processing system of claim 11, wherein, in a dual-port simulation configuration, for a read operation, the switching structure switches a subset of data between the RAM block set and one or more additional RAM blocks.

13. The data processing system of claim 12, wherein, in a dual-port simulation configuration, for a read operation, the switching structure reorders the request phase to the RAM block set by routing a subset of data sets associated with the request phase to multiple RAM blocks.

14. The data processing system of claim 12, wherein the plurality of RAM blocks have different capacities, and in a read operation, the switching structure switches a subset of data between RAM blocks and one or more additional RAM blocks with capacities less than a predefined capacity.

15. The data processing system of claim 12, wherein during a write operation, when the size of the subset is greater than the size of any RAM block in the RAM block set, the switching structure routes the subset to two or more RAM blocks in the RAM block set.

16. The data processing system of claim 12, wherein when the storage requirements of one or more request phases are less than the storage capacity of a single RAM block, the switching structure routes one or more request phases to a single RAM block at once.

17. The data processing system of claim 16, wherein the switching structure implements an arbitrator function to assign priorities to request phases when they arrive simultaneously, and the priorities are based on a first-in-first-out criterion based on previous stored requests.

18. The data processing system according to claim 2, wherein the write operation includes: When the size of the RAM block is known during the request phase, for cases where the RAM block size is not an integer multiple of the data element size, one or more data elements are accumulated in an auxiliary buffer until the combined memory space of one or more data elements approaches the size of the RAM block, or When the size of the RAM block is unknown at the request stage, and the RAM block size is not an integer multiple of the data element, a signal indicating the RAM block is sent to write a portion of the data element at the end of the sequential batch write.

19. The data processing system according to claim 1, wherein the switching structure comprises: A set of crosspoints for selectively connecting inputs to outputs, where each output uses a multiplexer to implement the crosspoints to select the inputs to which the output is connected.

20. A data processing method, the method comprising: The configuration selector identifies active pipelines from multiple pipelines, each carrying a dataset to be processed, and each pipeline includes multiple stages; as well as The switching structure dynamically routes request stages from multiple stages of the active pipeline to multiple sets of RAM blocks corresponding to the request stages to perform read and write operations.

21. The method of claim 20, wherein the dataset associated with the activity pipeline is written as a subset of a set of RAM blocks corresponding to a requested phase, and the subset of RAM blocks can be read simultaneously. Writing a subset of data into a relevant RAM block of the RAM block set includes writing a predefined number of data elements into each RAM block within a single clock cycle.

22. The method of claim 21, further comprising: After reading a subset of data from the RAM block set, a new subset of data related to the request phase is received into the RAM block set, thereby reusing the RAM block set.

23. The method of claim 21, further comprising: The output generated in response to reading a subset of data from a set of RAM blocks is stored in a buffer.

24. The method of claim 21, further comprising: The request write sequencer generates RAM write addresses and RAM bank addresses for each request stage, which are used to write the subset of data associated with the RAM block.

25. The method of claim 24, wherein the dynamic routing request phase from the switching structure to the RAM block set comprises one of the following: RAM blocks are selected from the set of RAM blocks for each subset, based on the RAM write address and RAM bank address, where each subset is written to the selected RAM block; and The RAM write address, RAM bank address, and subset are multicast to multiple RAM blocks, each RAM block having an associated bank address pre-configured, and each subset is written to the RAM block based on the mapping between the RAM bank address generated by RWS and the pre-configured bank address of the RAM block.

26. The method of claim 21, further comprising: The request read sequencer generates read addresses for RAM blocks for each request stage, used to read the dataset associated with each request stage. The read RAM address is multicast to multiple RAM blocks by a switching structure, and each subset is read from the RAM block according to the mapping between the read RAM address generated by the RRS and the RAM address pre-configured in the RAM block.

27. The method of claim 21, further comprising: After reading a subset of data from the set of RAM blocks, the exchange structure routes the subset of data back to its respective request phase via associated paths.

28. The method of claim 22, wherein the set of RAM blocks includes one or more additional RAM blocks besides the RAM blocks corresponding to the request phase, so that write operations and read operations can be performed separately in a single clock cycle.

29. The method of claim 28, further comprising: In a dual-port emulation configuration, for read operations, a subset of data is switched between the RAM block set and one or more additional RAM blocks by a switching structure.

30. The method of claim 28, further comprising: In a dual-port emulation configuration, for read operations, the request phase is reordered to the RAM block set by the switching structure by routing the subset of data associated with the request phase to multiple RAM blocks.

31. The method of claim 28, wherein the multiple RAM blocks have different capacities, and for a read operation, a switching structure switches a subset of the data between the RAM blocks and one or more additional RAM blocks with capacities smaller than a predefined capacity.

32. The method of claim 28, wherein for a write operation, when the size of the subset is greater than the capacity of any one RAM block in the RAM block set, the subset is routed to two or more RAM blocks in the RAM block set by a switching structure.

33. The method of claim 28, further comprising: When the memory requirements of one or more request stages are less than the capacity of a single RAM block, the switching structure routes one or more request stages to a single RAM block at a time.

34. The method of claim 33, wherein the exchange structure implements an arbitration function to allocate priority of request phases when request phases arrive simultaneously, and the priority is based on a first-in-first-out criterion based on previous stored requests.

35. The method of claim 21, wherein the write operation comprises: When the size of the RAM block is known during the request phase, if the RAM block size is not an integer multiple of the data element, one or more data elements are accumulated into the secondary buffer until the total memory space of one or more data elements is close to the size of the RAM block; or When the size of the RAM block is unknown during the request phase, and the RAM block size is not an integer multiple of the data elements, a signal is sent to indicate that the RAM block writes a portion of the data elements at the end of the sequential write batch.

36. The data processing system according to claim 21, wherein the switching structure comprises: A set of crosspoints for selectively connecting inputs to outputs, where each output uses a multiplexer to implement the crosspoints to select the inputs to which the output is connected.

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