Synchronous full-duplex daisy chain communication system

Abstract

A communication system includes a plurality of nodes connected in a daisy chain via respective bus links, wherein the plurality of nodes are configured for full duplex synchronous communication via a carrier-based modulation scheme on the bus links. The node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receiving an upstream synchronization response header (UpSRH) from the downstream node; measuring the delay between the DnSCH and the UpSRH; transmitting the delay information to a downstream node in the DnSCH; receiving the UpSRH of which the time is adjusted; and communicating with the downstream node and any upstream node through a frame based on the delay information. The frame may include a header; a flexible payload defined by a stream map that allocates byte locations within the flexible payload to the stream; and reporting.

Description

[0001] Priority data and related applications

[0002] This patent application claims priority to U.S. Non-Provisional Application No. 18 / 464,512, filed September 11, 2023, entitled “Synchronous Full-Duplex Daisy-Chained Communication System,” which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to wired communication systems, and more specifically to synchronous full-duplex daisy-chain communication systems. Background Technology

[0004] In-vehicle audio communication has shifted from analog signals (each signal having one or two analog lines) to digital communication (multiple audio streams on a single line or line pair). Example digital audio communication technologies can use a unidirectional loop topology. Other technologies (such as Ethernet) use point-to-point technology, which requires Ethernet switching between links and expensive audio clock regeneration at each node.

[0005] A2B is a true low-latency daisy-chain network because it eliminates the need for storage and forwarding between nodes. A2B uses line coding and is based on time-division multiplexing. While A2B is currently the most mature low-latency audio communication technology in automobiles, improvements in bandwidth could help support future applications. Summary of the Invention

[0006] The following presents a simplified overview of one or more aspects to provide a basic understanding of such aspects. This content is not a broad overview of all contemplated aspects, nor is it intended to identify key or decisive elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that follows.

[0007] In some aspects, the techniques described herein relate to a node daisy-chained to one or more other nodes on a full-duplex link, the node being configured to: transmit a Downstream Synchronization Control Header (DnSCH) to a downstream node; receive an Upstream Synchronization Response Header (UpSRH); measure the delay between the DnSCH and the UpSRH; send delay information in the DnSCH to the downstream node; receive a time-adjusted UpSRH; and communicate with the downstream node and any upstream node via frames based on the delay information.

[0008] In some aspects, the technology described herein relates to a method for operating a node daisy-chained to one or more other nodes on a full-duplex link, the method comprising: transmitting a Downstream Synchronization Control Header (DnSCH) to a downstream node; receiving an Upstream Synchronization Response Header (UpSRH); measuring the delay between the DnSCH and the UpSRH; sending delay information in the DnSCH to the downstream node; receiving a time-adjusted UpSRH; and communicating with the downstream node and any upstream node via frames based on the delay information.

[0009] In some aspects, the technology described herein relates to a communication system comprising: a plurality of nodes daisy-chained together via a respective bus, wherein the plurality of nodes are configured for full-duplex synchronous communication on the bus via a carrier-based modulation scheme, wherein, in order to synchronize the nodes, a master node transmits a downstream synchronization header at the beginning of a superframe, and each child node among the plurality of nodes transmits an uplink synchronization header at a timing adjusted based on the delay in receiving the downstream synchronization header and the delay in the upstream synchronization header arriving at the first node at the end of the superframe.

[0010] To accomplish the foregoing and related purposes, one or more aspects include features fully described below and specifically pointed out in the claims. Certain illustrative features of one or more aspects are described below and elaborated in detail with the accompanying drawings. However, these features indicate only a few of the various ways in which the principles of each aspect may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0011] To provide a more complete understanding of this disclosure and its features and advantages, reference may be made to the following description in conjunction with the accompanying drawings, wherein the same component symbols denote the same parts, wherein:

[0012] Figure 1 A diagram of nodes in a daisy chain according to one aspect of this disclosure;

[0013] Figure 2 A timing diagram for synchronous communication of nodes in a daisy chain, according to one aspect of this disclosure;

[0014] Figure 3 A diagram of a synchronization procedure for nodes in a daisy chain, according to one aspect of this disclosure;

[0015] Figure 4 A diagram illustrating an example of a frame structure according to one aspect of this disclosure;

[0016] Figure 5 A diagram illustrating general-purpose input / output (GPIO) processing according to one aspect of this disclosure;

[0017] Figure 6Aand Figure 6B A diagram illustrating an example of flexible node sorting based on one aspect of this disclosure;

[0018] Figure 7 A diagram of an example stream mapping for flexible payloads according to one aspect of this disclosure;

[0019] Figure 8 A flowchart of an example method performed by nodes in a daisy chain according to one aspect of this disclosure;

[0020] Figure 9 A diagram illustrating an example of a remote interrupt operation using a daisy chain of interrupt request bytes, according to one aspect of this disclosure. Detailed Implementation

[0021] Current daisy-chain communication systems provide discovery of nodes within the chain. Generally, daisy chains follow a fixed frame schedule. One problem with daisy chains, which have a flexible number of nodes and unknown cable lengths, involves timing relative to the frame schedule. For example, A2B discovery does not automatically adjust response times and does not automatically phase-align nodes.

[0022] In one aspect, this disclosure describes a daisy-chain communication system that uses a novel frame structure optimized for bidirectional synchronous communication. The daisy-chain communication system supports flexible payloads (not fixed time slots as in A2B) capable of carrying both synchronous and asynchronous communication.

[0023] Instead of line coding schemes, daisy-chain communication systems use carrier-based modulation (e.g., Quadrature Phase Shift Keying (QPSK)) and full-duplex communication (replacing the half-duplex ping-pong communication scheme within the audio sample period in A2B) to achieve 4 times the bandwidth and better electromagnetic compatibility (EMC). A novel mechanism is used to automatically align the phase of audio samples across all nodes. During downstream node discovery, the upstream node measures the response time of the downstream node. This measurement, or the resulting adjustment, is relayed back to the downstream node. From then on, the downstream node responds with time-adjusted (delayed) upstream information. This adjustment ensures that all nodes sample audio in the same phase, maximizing the number of daisy-chain nodes that can communicate within the same fixed time window. The unique frame structure of the data is optimized for full-duplex communication, which can carry clock-synchronized data streams (e.g., digital audio) as well as asynchronous communication and interrupt communication.

[0024] Figure 1Figure 100 shows the nodes in a daisy chain 102. In the daisy chain 102, each node is connected to subsequent nodes via a bus link 104. For example, the bus link 104 can be a twisted pair cable. As shown, the daisy chain 102 includes a master node 110, one or more intermediate child nodes 120, and a terminal child node 130. In some embodiments, each node is a device including one or more modems.

[0025] Each node 110, 120, and 130 includes a corresponding frame buffer 112, 122, and 132. Frame buffers 112, 122, and 132 are configured to store information for one or more frames transmitted via bus link 104 in the downstream direction (from master node 110 to end child node 130) and the upstream direction (from end child node 130 to master node 110). For example, frame buffer 112 of master node 110 may include an upstream receive buffer (US RX Buff) and a downstream transmit buffer (DS TX Buff). Frame buffer 122 of intermediate child node 120 may include a US RX Buff and a DS TX Buff, as well as a downstream receive buffer (DS RX Buff) and an upstream transmit buffer (US TX Buff). Frame buffer 132 of end child node 130 may include a DS RX Buff and a US TX Buff.

[0026] Each node 110, 120, 130 further includes one or more transceivers 106 (TX / RX). Each transceiver 106 is configured to generate a signal on a corresponding bus link 104 based on the contents of a corresponding frame buffer 112 or 132 or based on an input signal from another link in an intermediate child node, the input signal having contents that will be selectively replaced by the location of the corresponding frame buffer 122. In one aspect, the transmission on the bus link 104 is full-duplex. That is, the bus link 104 can carry both downstream and upstream signals simultaneously. In some embodiments, the communication utilizes a carrier-based modulation scheme with echo cancellation to achieve full-duplexity. For example, the signal may use binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), or quadrature amplitude modulation (QAM).

[0027] In one aspect, the daisy chain 102 provides low latency because there is no storage and forwarding at each node. Data from the direction of the master node 110 is immediately forwarded to the end child node 130. Data from the direction of the end child node 130 is immediately forwarded to the master node. As data passes through the nodes, each node selectively reads the data. Each node also selectively modifies the data without storing and forwarding the entire frame or a portion of the frame. For example, at child node 120, transceiver 106a receives downstream signal 150 and selectively reads data into the DS RX buffer. Transceiver 106b selectively modifies the data in downstream signal 150 (e.g., based on the DS TX buffer) and immediately forwards downstream signal 150 to end child node 130. Simultaneously, transceiver 106b receives uplink signal 152 and selectively reads data into the US RX buffer. Transceiver 106a selectively modifies the data in upstream signal 152 and immediately forwards upstream signal 152 to master node 110. Therefore, frame buffer 122 does not store the entire frame before forwarding it to the next node, thus providing low-latency communication. For example, data can be forwarded from master node 110 to end child node 130 in less than half a sampling period, which can be, for example, 10.4 microseconds (µs).

[0028] In one aspect, communication is synchronized according to a superframe structure. For example, superframes can be transmitted over a period of 48 kHz, where each superframe is 20.82 µs. For a data rate of 98.304 Mbps, the payload in each frame can be 256 bytes. Further details of synchronization and frame structure are described below.

[0029] Additionally, each node may include corresponding memories 114, 124, 134 for storing configuration information of the node. In some embodiments, memories 114, 124, 134 are addressable registers, one-time programmable (OTP) memories, or electrically erasable programmable (EEPROM) memories that store node identifiers. In some embodiments, the order of the nodes is flexible, and the position of a node within the daisy chain 102 can be determined during the discovery process based on the stored identifiers.

[0030] In some implementations, one or more nodes may include or be connected to a corresponding microcontroller, microprocessor, or DSP (MCU) 116, 126, 136. For example, MCUs 116, 126, 136 may be connected to the nodes via time-division multiplexing (I2S / TDM), inter-integrated circuit (I2C), or serial peripheral interface (SPI). MCUs 116, 126, 136 may configure the corresponding nodes and communicate with other nodes via daisy-chain 102. For example, in an audio system, the audio source may originate from the DSP (MCU) in node 110. Some sub-nodes 120, such as intelligent amplifiers, may include MCUs, but other nodes, such as subwoofers or microphone nodes, may not include MCUs.

[0031] Figure 2 This is a timing diagram for synchronous communication between nodes in daisy chain 102. Communication can be transmitted using superframes within sample periods including the first sample period 202, the second sample period 204, the third sample period 206, and the fourth sample period 208. For example, the nodes include a master node 110, intermediate child nodes 120, and a terminal child node 130. The downstream and upstream signals of each node are divided into headers (e.g., synchronization control header (SCH) or synchronization response header (SRH)), flexible payload bytes, and trailer (FTR) in each superframe.

[0032] In some implementations, one or more nodes (e.g., master node 110 and end child node 130) may include other node components connected via a time-division multiplexing (TDM) interface 210, such as I2S / TDM. For example, if a node is an audio node such as a microphone or speaker, audio signals may be input to or output to the daisy chain 102 via the I2S / TDM interface. I2S / TDM interface pins or other pins on the chip may alternatively be used as general-purpose input / output (GPIO) pins at the node. The daisy chain 102 may also be synchronized with the I2S / TDM interface 210 at the master node and provide synchronization to the child nodes at the respective I2S / TDM interfaces 210.

[0033] In one aspect, the master node 110 I2S / TDM samples can be synchronized with superframes. For example, the master node 110 can transmit SCH 220 at the beginning of each sample period. Due to transmission delays and processing at each node, subsequent nodes can transmit the corresponding SCH slightly later within the sample period. The end child node 130 can receive a superframe ending with FTR 230 within the same sample period and transmit an upstream frame starting with SRH 240. The upstream frame can be transmitted upstream at each node, such that SRH 240 is received at the master node 110 within the same sample period. Thus, synchronization can provide control and response within a single sample period.

[0034] Communication with the TDM interface can be synchronized and uses additional superframes. For example, as shown, the master node 110 can load the contents of the transport frame buffer with the I2S / TDM data stream sample 212 during the first audio sample period 202 to construct a new superframe. The master node 110 can transmit a new downstream frame with an audio stream sample as part of the flexible payload 222 during the second sample period 204. The daisy chain 102 can load the flexible payload 222 to the end child node 130 during the second sample period 204 and the third sample period 206. Then, the end child node 130 can transmit the audio stream within the flexible payload 222 as an I2S / TDM frame 232 during the fourth sample period 208.

[0035] In one aspect, all nodes sample data at the same time (in the same phase) based on the received timing information. Using the timing information, each node is fully aware of the start 250 of the sampling period (which can be determined from the midpoint between dnSCH and upSRF – ½ tsf). During the sampling period, each node can sample data from the source to the TX buffer for use in flexible payloads. For example, an audio device can sample the audio signal of an audio stream. In one aspect, flexible payloads can support other types of data, such as control of pulse width modulation (PWM) signals or data from analog-to-digital converters (ADCs), which, for example, can provide sensor data.

[0036] In implementations, the PWM duty cycle can be controlled by a flexible payload byte. For example, a flexible payload for controlling the PWM duty cycle allows, for instance, an I2S / TDM interface from an audio DSP in one node to directly control the PWM duty cycle on another node. If the PWM is used for audio-affected lighting effects (e.g., an audio light organ), the audio DSP can directly control the LED with low latency based on its native processing, without having to use asynchronous communication over I2C or SPI. PWM can also be used to control the output voltage of voltage regulators, such as those supplying power to the power rails of a Class D amplifier. When a low-level audio signal is expected, the PWM can be set to create a low supply voltage, and when a high-level audio output is expected, a high supply voltage can be created (look-ahead control by the DSP). The PWM duty cycle can be asynchronously controlled from the same node or another node's I2C (from the master node) or SPI (from any other node) interface, or synchronously controlled with low latency from another node over I2S / TDM.

[0037] Figure 3This is a diagram of a discovery procedure 300 used for nodes in a daisy chain 302. For example, the discovery procedure 300 can be used to establish the timing of the header, flexible payload bytes, and trailer at each node. In the example shown, the daisy chain 302 includes a total of four nodes (e.g., with two intermediate child nodes 120), but may include additional nodes. Signals corresponding to probe points on each bus are shown.

[0038] Master node 110 may optionally perform line diagnostics and provide bus power to downstream child node 0. Master node 110 begins sending downstream data in the form of DnSCH 310 including a downstream locking pattern. When child node 0 is locked, it begins responding with UpSRH 312 including an upstream locking pattern. Master node 110 measures the delay time t1 and sends DnSCH 320 with delay information 322 to child node 0. The delay time t1 represents the cable delay of bus link 104 plus the receive and transmit path delay between nodes. Child node 0 responds with a time-adjusted UpSRH 324. For example, the time-adjusted UpSRH 324 is synchronized to end at the end of the master node's superframe before the next DnSCH 330 from master node 110. For example, t1 may be received at child node 0 after DnSCH 320. SF - t1 - t upSRH UpSRH324 with transmission time adjustment. SF It is the duration of the superframe, and t upSRH This is the duration of the time-adjusted UpSRH. Child node 0 locks in downstream signals arriving from autonomous node 110.

[0039] The master node or child node 0 optionally performs line diagnostics and provides bus power to downstream child node 1. If everything is normal, child node 0 begins sending data downstream, including DnSCH 340. When child node 1 is locked, it begins responding with UpSRH 342. Child node 0 measures the delay time t2 and sends DnSCH 350 with delay information 352 to child node 1. Child node 1 responds with a time-adjusted UpSRH 354. The UpSRH 354 used for time adjustment by child node 1 is synchronized to the end t1 + t2 before DnSCH 330 arrives at child node 0. For example, after receiving DnSCH 350 at child node 0, t... SF - t1 - t2 - t upSRH The time-adjusted UpSRH 354 can be transmitted from child node 1. Therefore, child node 0 can receive UpSRH 354 and retransmit it as a time-adjusted UpSRH 324. Now the master node 110 can communicate with child node 1.

[0040] For each child node in daisy chain 302, the same procedure is used at each node to continue discovery procedure 300. It should be understood that the discovery procedure can be performed over multiple superframes. In one aspect, the number of nodes in daisy chain 302 can be based on a time budget. For example, the time budget can be expressed as:

[0041] t 预算 = t SF - t SCH - t SRH - 2 × (t) 电缆 + #Subs × t 程序 >0

[0042] Assuming a processing latency of 1 µs and 80 bits each for SCH and SRH at 98.304 Mbit / s, a maximum total distance of 50 m is allowed for 9 child nodes. Assuming a cable delay of t... 电缆 It is 6.5 ns / m. For example, 9 child nodes can be used in vehicle entertainment systems that include microphones and speakers.

[0043] Figure 4 Figure 400 shows an example of a frame structure. Figure 400 includes examples of a downstream superframe 410 and an upstream superframe 450.

[0044] The downstream superframe 410 includes a downstream synchronization header 412, a downstream flexible payload 414, and a downstream trailer 416. The downstream synchronization header 412 includes a downstream synchronization byte 420 with a modal frame counter, a command field 422, a data field 424, a data or address field 426, a long-distance GPIO byte 428, a retry bit, and a CRC 429. The downstream flexible payload 414 includes multiple bytes that can be flexibly configured to carry data streams. For example, a stream map can indicate which bytes of the downstream flexible payload 414 carry each stream. (About...) Figure 7 Further details of the flexible payload 414 are described. The downstream trailer 416 includes a CRC 430 for the downstream flexible payload 414 and a frame validity indication 432 with its own CRC.

[0045] Downstream synchronization byte 420 indicates the start of a frame and includes a modal frame counter value. Command field 422 provides control signaling and addresses the node. Data field 424 and data or address field 426 depend on command field 422. Long-distance GPIO byte 428 indicates as per [reference to...]. Figure 5 The states of one or more virtual GPIO pins are discussed in further detail. CRC 429 is the CRC of the downstream header 412, which includes retry bits and a 15-bit CRC. CRC 430 in the downstream trailer 416 provides the CRC for the downstream flexible payload 414.

[0046] Frame validity indication 432 is an indication with an independent CRC bit that indicates whether a downstream frame was valid upon arrival at the preceding node. For example, a child node might check CRC 430 and determine that the received flexible payload is invalid. However, a child node might have data to transmit on the flexible payload and calculate a new CRC 430. Therefore, a frame transmitted by the child node could have a correct CRC 430, but frame validity indication 432 could indicate that other data in the flexible payload is invalid.

[0047] The upstream superframe 450 includes an upstream header 452, an upstream flexible payload 454, and an upstream trailer 456. The upstream header 452 includes an upstream synchronization byte 460, a response / request field 462, a data field 464, and a header CRC 466. Similar to the downstream flexible payload 414, the upstream flexible payload 454 includes multiple bytes that can be flexibly configured to carry a data stream. The upstream flexible payload 454 can be defined by the same or different stream mappings regarding the downstream stream mapping, and the stream mappings between nodes can be different. The upstream trailer 456 includes an interrupt request (IRQ) byte 470, a GPIO byte 472, a CRC 474 for the upstream flexible payload 454, and a frame validity indicator 476 with its own CRC.

[0048] Upstream synchronization byte 460 indicates the start of upstream superframe 450. Response / request field 462 is a response to command field 422 or a request for control signaling. Data field 464 is defined based on response / request field 462. Header CRC 466 is calculated based on the contents of upstream header 452. Interrupt request byte 470 indicates an interrupt request detected at the downstream node. GPIO byte 472 indicates the state of one or more virtual GPIO pins at the downstream node. CRC 474 is calculated based on upstream flexible payload 454. Frame valid indication 476 operates in the same manner as frame valid indication 432, but for the upstream direction. In some cases, a node may not receive upstream header 452 from the downstream node (e.g., if the downstream node becomes disconnected). A node may generate an upstream frame including a new UpSRH even if no UpSRH is received from the downstream node.

[0049] Figure 5This is a diagram of GPIO processing in daisy-chain 102. Each node in daisy-chain 102 can be associated with multiple virtual GPIO pins. Remote GPIO bytes 428 and 472 can indicate updates to the state of virtual GPIO pins. Each node can be configured to output virtual pin information on its GPIO output pins. In some cases, logical operations such as inversion, logical AND, and logical OR can be applied to the states of virtual GPIO pins and local GPIO pins. For example, when inversion is applied to a local GPIO pin, a logical AND operation can be applied to combine the states of the virtual GPIO pin and the local GPIO pin. If no inversion is applied, a logical OR operation can be applied to combine the states of the virtual GPIO pin and the local GPIO pin. The combined states of the virtual GPIO pins are included in the transmitted remote GPIO bytes 428 and 472. More than eight virtual GPIO pins are supported when GPIO bytes are associated with alternating groups of virtual GPIO pins, for example, by alternating between even and even frame counter values.

[0050] For example, during the first sample period 202, both the master node 110 and the end child node 130 can detect GPIO state updates on their GPIO input pins. The end child node 130 can indicate the GPIO state update 510 in the long-distance GPIO byte 472 in the tail 456 transmitted in the second sample period 204. Other child nodes can contribute by combining their GPIO input pin states with the upstream GPIO byte using a logical OR and forwarding the updated GPIO byte upstream. The tail can reach the master node 110 in the second sample period 204. At the end of the second sample period 204, the master node 110 can perform a logical operation (e.g., logical OR) on its GPIO input pin states during the first sample period to determine the updated state of the virtual GPIO pins. In the third sample period 206, the master node 110 can indicate the state 530 of the virtual GPIO pins in the header (e.g., the result of the logical OR). Therefore, each node can receive virtual GPIO state buffer updates in the third sample period 206 to update the GPIO output pins simultaneously with the start of the fourth sample period 208.

[0051] Therefore, within three superframes of a change in the input GPIO pin, a state is received at any node to be output on the GPIO pin. For example, the end child node 130 may output state 530 in the fourth sample period 208. Alternate virtual GPIO bytes and associated GPIO pin groups may be sampled at the end of the second sample period 204 to be output at the beginning of the fifth sample period.

[0052] Figure 6A and Figure 6B This is a diagram illustrating an example of flexible node sorting. Figure 6AFor example, master node 610 can be daisy-chained to second node 620, third node 630, fourth node 640, and fifth node 650. Third node 630 can be a microphone. Second node 620 and fifth node 650 can utilize microphone signals. In one aspect, third node 630 can transmit microphone signals in both upstream and downstream directions. Second node 620 and fifth node 650 can be configured to listen in both upstream and downstream directions.

[0053] exist Figure 6B In this configuration, nodes can be connected in different orders. For example, the master node 610 can be connected to the fifth node 650, the fourth node 640, the third node 630, and then to the second node 620. The third node 630 can transmit microphone signals in both upstream and downstream directions. The second node 620 and the fifth node 650 can be configured to listen in both upstream and downstream directions. Therefore, the second node 620 and the fifth node 650 can receive microphone signals within a superframe, regardless of the node order.

[0054] Figure 7 Figure 700 shows an example flexible payload stream mapping 710, where stream mapping 710a is a superset of different subsets 710b, 710c, 710d for different vehicle models or implementations. In one aspect, the flexible payload carries multiple streams transmitted by different nodes. Depending on the bandwidth of the streams, each stream can be allocated several bytes in the flexible payload. Nodes contributing one or more streams to the flexible payload write data to the allocated flexible payload byte positions. Nodes using one or more streams can read bytes from the allocated flexible payload byte positions.

[0055] In some implementations, such as vehicle audio systems, the stream may include one or more of an audio stream, a Serial Peripheral Interface (SPI) tunnel, an Ethernet tunnel, or a mailbox tunnel. For example, the audio stream may use 16-bit words, 24-bit words, or 32-bit words. In some implementations, the flexible payload may carry 239 bytes. Therefore, multiple audio streams (e.g., mic FL, mic FR, sub1, sub2 mic center, spkr FL, and spkr FR) can be carried in the flexible payload. In some implementations, the stream mappings 710 are identical at each node. For example, each node may follow a stream mapping 710a that includes all streams. A node may simply ignore data from streams that are not relevant to it. In other implementations, additional bandwidth may be available if the stream mappings for adjacent nodes reuse one or more bytes that are not used by adjacent nodes, or if different mappings are used between upstream and downstream. However, multiple stream mappings increase the complexity of the communication system and may reduce sequencing flexibility.

[0056] A 10 Mbit / s SPI or Ethernet tunnel can utilize 30 bytes of flexible payload upstream and downstream. A mailbox tunnel may occupy 10 bytes upstream and downstream. Not every node needs to participate in the tunnel. For example, a node configured with a 710a mapping may not participate in the SPI tunnel. Multiple SPI, Ethernet, and mailbox tunnels can exist mapped to flexible payloads, and a node's participation in these tunnels may be limited by the interface of the transceiver chip in the node. A mailbox tunnel provides simple information exchange between nodes by providing communication between a transmit mailbox on one node and a receive mailbox on an addressed node, and vice versa.

[0057] In some implementations, the stream mapping 710 can be the same in all directions. In some implementations, for example, if the master node 110 or the end child node 130 only needs to transmit in one direction, it is possible to use different stream mappings in each direction to optimize bandwidth. For example, if the master node 110 is the only source of the output audio stream and no feedback is required, the upstream payload can carry a different stream than that of the end child node 130.

[0058] Figure 8 This is a flowchart of an example method 800 performed by nodes in daisy chain 102 (e.g., master node 110 or child node 120). Method 800 can synchronize nodes in daisy chain 102 for communication. Method 800 can also be performed by communicating with another node in daisy chain 102 (e.g., child node 120 or end child node 130).

[0059] In block 810, method 800 may optionally include storing a node identifier indicating the position of a node in the daisy chain. For example, in some embodiments, master node 110 may store a node identifier indicating the position of a node in memory 114. The node identifier may be enumerated during the discovery process.

[0060] In block 815, method 800 includes transmitting DnSCH to a downstream node. For example, in some embodiments, master node 110 may transmit DnSCH 310 to a downstream node (e.g., child node 120).

[0061] At block 820, method 800 includes receiving UpSRH from a downstream node. For example, in some embodiments, master node 110 may receive UpSRH 312 from a downstream node (e.g., child node 120).

[0062] At block 825, method 800 includes measuring the delay between DnSCH and UpSRH. For example, in some embodiments, master node 110 may measure the delay (t1) between DnSCH 310 and UpSRH 312.

[0063] In block 830, method 800 includes sending delay information to a downstream node in DnSCH. For example, in some implementations, master node 110 may send delay information 322 to downstream node 120 in DnSCH 320.

[0064] At box 835, method 800 includes receiving a time-adjusted UpSRH. For example, in some implementations, master node 110 may receive a time-adjusted UpSRH 324.

[0065] In block 840, method 800 includes communicating with downstream nodes and any upstream nodes via frames based on latency information. For example, in some embodiments, master node 110 may communicate with downstream nodes (e.g., child node 120) on superframe 410 or 450 based on latency information. As another example, child node 120 may communicate with end child node 130 and master node 110 on superframe 410 or 450 based on latency information. In some embodiments, at sub-block 842, block 840 may optionally include sampling data of the flexible payload at the same time as other nodes based on latency information. For example, each node may sample data at the beginning 250 of the sampling period. In some embodiments, at sub-block 844, block 840 may optionally include generating an upstream frame including an UpSRH in the absence of received UpSRH from downstream nodes.

[0066] In block 850, method 800 may optionally include performing logical operations on the uplink receive state of the virtual GPIO pin and the local state of the GPIO pin. For example, in some embodiments, master node 110 may perform logical operations (e.g., inversion, logical AND, logical OR) on the uplink receive state of the virtual GPIO pin indicated in GPIO byte 470 in the header of the uplink frame (e.g., GPIO state update 510).

[0067] In box 855, method 800 may optionally include the result of a logical operation in a long-range GPIO byte in the trailer of a forwarded uplink frame. For example, a child node may forward a long-range GPIO byte 472, including the result of the logical operation, to the upstream node in trailer 456.

[0068] In box 860, method 800 may optionally include sending updated virtual GPIO information from the master node to all child nodes downstream in the long-distance GPIO byte in the header of the downstream frame. For example, master node 110 may use downstream long-distance GPIO byte 428 in header 412 to send updated virtual GPIO information downstream to all child nodes.

[0069] In block 865, method 800 may optionally include outputting virtual GPIO pin information on the GPIO output pin. For example, in some embodiments, master node 110 may output virtual GPIO pin information on the GPIO output pin.

[0070] Figure 9 Figure 900 shows an example of remote interrupt operation in a daisy chain 102 using IRQ byte 470. 128 interrupt requests can be enabled and prioritized on each node with two priorities. Node interrupts support one of eight priorities on the master node and local interrupt selection via IRQ pins is supported on all child nodes. The host only needs to access the master node's INTSTAT buffer 910 to determine the node and source of the highest priority interrupt. Once a pending interrupt is selected as the highest priority interrupt, it is automatically cleared, resulting in minimal "on-deck" interrupt latency once the host processes the master interrupt.

[0071] All nodes share eight wired OR bus interrupt request (BIRQ) bytes 920. The BIRQ value is sent in the payload portion of the upstream response frame (e.g., in IRQ byte 470 of the tail 456) and is protected by a payload CRC 474. Each node ORs its node interrupt request bits to obtain the bits of the foreign BIRQ value; the bit positions are specified by the BIRQ_PRIO[2:0] field in the NINT_CTL buffer at the node. The combined BIRQ value is transmitted upstream in the payload portion of the upstream superframe 450 (e.g., IRQ byte 470).

[0072] Child node 120 is configured to send a node interrupt request to master node 110 by setting a bit of the specified bus interrupt request priority (BPRIO) field value 930 (a three-bit field) in the NINTCTL register in the IRQ byte 470 of the upstream response frame. The local BIRQ is ORed with the external IRQ byte 470 from downstream child node 120 before being sent out in the upstream superframe 450. When master node 110 receives a valid external IRQ byte 470 (both payload and frame are valid), the master node ORs the external IRQ byte 470 with the local BIRQ byte. If any bits are set in the merged BIRQ byte, the master node first checks whether its BPRIO value 930 matches the highest priority interrupt request bit and whether the master NIRQ bit is set. If so, the master node's NINTSTAT value 940 is loaded into the INTSTAT register 910, and the IRQ pin is set to notify the external host of the pending interrupt. This will also clear the INTPND[N].pndN bit that caused the interrupt request.

[0073] If the master node 110 is not the source of the highest priority interrupt, it will broadcast a SCH BIRQ query (e.g., in command field 422) to all child nodes, requesting more information about the highest priority interrupt request bit (0 is the highest and bit 7 is the lowest). A child node 120 with an active interrupt request set in NINTSTAT buffer 940 and matching its BPRIO priority with the SCH BIRQ query will respond with an SRH packet (e.g., in response / request field 462) containing data from NINTSTAT buffer 940. If multiple child nodes have matching BPRIO priorities and pending interrupt requests, the node closest to the master node (including the master node) will have priority. Note that all matching child nodes will respond with an SRH, but the SRH from the nearest node will override the downstream SRH.

[0074] When master node 110 receives a valid SRH response, it locally stores the returned NINTSTAT information in INTSTAT buffer 910 and sets its IRQ pin to notify the external host of the pending interrupt. Next, the master node reads NINTSTAT buffer 940 on the responding node to clear the NINTSTAT.IRQ bit. This also clears the INTPND[N].pndN bit that caused the interrupt request. The master node ignores incoming BIRQ bytes until the external host has read its INTSTAT buffer 910. At this point, it will respond to any active interrupt request bits through the above procedure.

[0075] Example aspects are described in the following numbered clauses:

[0076] Clause 1. A node daisy-chained to one or more other nodes on a full-duplex link, the node being configured to: transmit a Downstream Synchronization Control Header (DnSCH) to a downstream node; receive an Upstream Synchronization Response Header (UpSRH); measure the delay between the DnSCH and the UpSRH; send delay information in the DnSCH to the downstream node; receive a time-adjusted UpSRH; and communicate with the downstream node and any upstream node via frames based on the delay information.

[0077] Clause 2. The node as described in Clause 1, wherein communication on the full-duplex link uses full-duplex carrier-based modulation for upstream and downstream signals.

[0078] Clause 3. A node as described in Clause 1 or 2, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to sample data of the flexible payload at the same time as the other nodes based on the latency information.

[0079] Clause 4. A node according to any one of Clauses 1 to 3, wherein each frame includes: a header; a flexible payload defined by a stream map that allocates byte positions within the flexible payload to the stream; and a trailer.

[0080] Clause 5. The node as described in Clause 4, wherein for a downstream frame, the header is the DnSCH and includes: a synchronization byte with a modal frame counter, a command field, a data field, a data or address field, a long-distance general-purpose input / output (GPIO) byte, and a cyclic redundancy check for the header; and the trailer includes: a cyclic redundancy check (CRC) byte for the flexible payload and a frame validity indication with independent CRC bits.

[0081] Clause 6. A node as described in Clause 4 or 5, wherein for an upstream frame, the header is the UpSRH and includes a synchronization byte, a response / request field, a data field, and a cyclic redundancy check for the header, and the trailer includes an interrupt request (IRQ) byte, a general purpose input / output (GPIO) byte, a CRC byte for the flexible payload, and a frame validity indication with independent CRC bits.

[0082] Clause 7. The node as described in Clause 6, wherein the remote GPIO byte indicates an update to the state of a virtual GPIO pin, wherein the node is configured to output virtual GPIO pin information on a GPIO output pin.

[0083] Clause 8. The node as described in Clause 7, wherein the node is configured to: perform logical operations on the uplink receive state and local state of the virtual GPIO pin; forward the result of the logical operations in the long-distance GPIO byte in the tail of the uplink frame; and send updated virtual GPIO information from the master node to all child nodes in the long-distance GPIO byte in the header of the downstream frame.

[0084] Clause 9. The node described in Clause 7 or 8, wherein the long-distance GPIO byte changes between multiple sets of virtual GPIO pins per frame to support more than 8 virtual GPIO pins.

[0085] Clause 10. A node as described in Clause 9, wherein the frame validity indicator with cyclic redundancy check indicates whether the frame was valid when it was received at the previous node.

[0086] Clause 11. A node as described in Clause 9 or 10, wherein the IRQ byte indicates an interrupt request detected at a downstream node.

[0087] Clause 12. The node as described in Clause 11, wherein the node is configured to select the location of the IRQ byte to indicate the local interrupt based on the priority of the local interrupt.

[0088] Clause 13. A node according to any one of Clauses 9 to 12, wherein the node is configured to generate an upstream frame including an UpSRH in the absence of an UpSRH received from the downstream node.

[0089] Clause 14. A node according to any one of Clauses 4 to 13, wherein the flexible payload includes one or more of the following: an audio stream; control for the pulse width modulation duty cycle; a stream from an analog-to-digital converter (ADC) at the node; a serial peripheral interface (SPI) tunnel; an Ethernet tunnel; or a mailbox tunnel.

[0090] Clause 15. A node pursuant to any one of Clauses 4 to 14, wherein if there is no source, the flexible payload byte is zero.

[0091] Clause 16. A node according to any one of Clauses 4 to 15, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to transmit streams simultaneously at the same flexible payload location upstream and downstream.

[0092] Clause 17. A node according to any one of Clauses 4 to 16, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to apply a logical OR operation between upstream and downstream flows at the same location in the flexible payload.

[0093] Clause 18. A node according to any one of Clauses 1 to 17, wherein the node is configured to store a node identifier indicating the position of the node in the daisy chain.

[0094] Clause 19. A node according to any one of Clauses 1 to 18, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to: immediately forward information received in a downstream frame to the downstream node; immediately forward information received in an upstream frame to the upstream node; and selectively read or write data to the upstream frame or the downstream frame.

[0095] Clause 20. A method of operating a node daisy-chained to one or more other nodes on a full-duplex link, comprising: transmitting a Downstream Synchronization Control Header (DnSCH) to a downstream node; receiving an Upstream Synchronization Response Header (UpSRH); measuring a delay between the DnSCH and the UpSRH; sending delay information in the DnSCH to the downstream node; receiving a time-adjusted UpSRH; and communicating with the downstream node and any upstream node via frames based on the delay information.

[0096] Clause 21. The method according to Clause 20, wherein the communication uses full-duplex carrier-based modulation for upstream and downstream signals on the full-duplex link.

[0097] Clause 22. The method according to Clause 20 or 21, wherein communication with the downstream node and any upstream node includes sampling the data of the flexible payload at the same time as the other nodes based on the latency information.

[0098] Clause 23. The method according to any one of Clauses 20 to 22, wherein each frame includes: a header; a flexible payload defined by a stream mapping that allocates byte positions within the flexible payload to the stream; and a trailer.

[0099] Clause 24. The method according to Clause 23, wherein for a downstream frame, the header is the DnSCH and includes: a synchronization byte with a modal frame counter, a command field, a data field, a data or address field, a long-distance general-purpose input / output (GPIO) byte, and a cyclic redundancy check for the header; and the trailer includes: a cyclic redundancy check (CRC) byte for the flexible payload and a frame validity indication with independent CRC bits.

[0100] Clause 25. The method according to Clause 23 or 24, wherein for an upstream frame, the header is the UpSRH and includes a synchronization byte, a response / request field, a data field, and a cyclic redundancy check for the header, and the trailer includes an interrupt request (IRQ) byte, a long-distance general-purpose input / output (GPIO) byte, a CRC byte for the flexible payload, and a frame validity indication with independent CRC bits.

[0101] Clause 26. The method according to Clause 25, wherein the remote GPIO byte indicates an update to the state of a virtual GPIO pin, the method further comprising outputting virtual GPIO pin information on a GPIO output pin.

[0102] Clause 27. The method according to Clause 26 further includes: performing a logical operation on the uplink receive state of the virtual GPIO pin and the local state of the GPIO pin; forwarding the result of the logical operation in the long-distance GPIO byte in the tail of the uplink frame; and including the result of the logical operation in the long-distance GPIO byte in the downstream node.

[0103] Clause 28. The method according to any one of Clauses 25 to 27, wherein the frame validity indicator having an independent CRC bit indicates whether the frame was valid when it was received at the previous node.

[0104] Clause 29. The method according to any one of Clauses 25 to 28, wherein the IRQ byte indicates the priority of an interrupt request detected at a downstream node.

[0105] Clause 30. The method according to any one of Clauses 25 to 29, wherein the communication includes generating an upstream frame including an UpSRH in the absence of an UpSRH received from the downstream node.

[0106] Clause 31. The method according to any one of Clauses 23 to 30, wherein the flexible payload comprises one or more of the following: an audio stream; control of the pulse width modulation duty cycle; a stream from an analog-to-digital converter (ADC) at the node; a serial peripheral interface (SPI) tunnel; an Ethernet tunnel; or a mailbox tunnel.

[0107] Clause 32. The method according to any one of Clauses 20 to 32 further includes storing a node identifier indicating the position of the node in the daisy chain.

[0108] Clause 33. A communication system comprising: a plurality of nodes daisy-chained together via respective bus links, wherein the plurality of nodes are configured for full-duplex synchronous communication over the bus links via a carrier-based modulation scheme, wherein, in order to synchronize the nodes, a master node transmits a downstream synchronization header at the beginning of a superframe, and each child node among the plurality of nodes transmits the upstream response header at a timing adjusted based on a delay in receiving the downstream synchronization header and a delay in the upstream response header arriving at the master node at the end of the superframe.

[0109] Clause 34. The communication system pursuant to Clause 33, wherein the order of the plurality of nodes is enumerated during the discovery process.

[0110] Clause 35. A communication system pursuant to Clause 33 or 34, wherein the number of nodes in the communication system is limited based on a time budget for the length of a superframe, the time budget including time for the downstream synchronization header, time for the upstream response header, cable delay, and time for processing at each child node in each direction.

[0111] As an example, a component, any part of a component, or any combination of components may be implemented using a "processing system" comprising one or more processors. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in the processing system can execute software. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, scripts, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, programs, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description languages, or otherwise.

[0112] Therefore, in one or more aspects, one or more of the described functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the function may be stored or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. As used herein, disks and floppy disks include optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), and floppy disks, wherein disks typically magnetically reproduce data, while floppy disks optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Non-transitory computer-readable media excludes transient signals.

Claims

1. A node that is daisy-chained to one or more other nodes on a full-duplex link, said node being configured to: Transmit the downstream synchronization control header (DnSCH) to the downstream node; Receive the upstream synchronization response header (UpSRH); Measure the delay between the DnSCH and the UpSRH; The delay information is sent to the downstream node in DnSCH; UpSRH for receiving time adjustment; and Based on the latency information, communication is conducted with the downstream node and any upstream node via frames.

2. The node of claim 1, wherein communication on the full-duplex link uses full-duplex carrier-based modulation for upstream and downstream signals.

3. The node of claim 1, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to sample data of the flexible payload at the same time as the other nodes based on the latency information.

4. The node according to claim 1, wherein each frame comprises: Header; A flexible payload defined by a stream mapping, which allocates byte positions within the flexible payload to a stream; as well as End of report.

5. The node of claim 4, wherein for a downstream frame, the header is the DnSCH and includes: It includes a synchronization byte with a frame counter, a command field, a data field, a data or address field, a long-range general-purpose input / output (GPIO) byte, and a cyclic redundancy check for the header; and The trailer includes: a Cyclic Redundancy Check (CRC) byte for the flexible payload and a frame validity indicator with independent CRC bits.

6. The node of claim 4, wherein for an upstream frame, the header is the UpSRH and includes a synchronization byte, a response / request field, a data field, and a cyclic redundancy check for the header, and the trailer includes an interrupt request (IRQ) byte, a general purpose input / output (GPIO) byte, a CRC byte for the flexible payload, and a frame validity indicator with independent CRC bits.

7. The node of claim 6, wherein the remote GPIO byte indicates an update to the state of a virtual GPIO pin, wherein the node is configured to output virtual GPIO pin information on a GPIO output pin.

8. The node of claim 7, wherein the node is configured to: Perform logical operations on the uplink receive state and local state of the virtual GPIO pin; The result of the logical operation in the long-distance GPIO byte in the tail of the forwarded uplink frame; and The updated virtual GPIO information is sent from the master node to all child nodes in the long-distance GPIO byte in the header of the downstream frame.

9. The node of claim 7, wherein the long-distance GPIO byte changes between multiple sets of virtual GPIO pins per frame to support more than 8 virtual GPIO pins.

10. The node of claim 9, wherein the frame validity indicator having cyclic redundancy check indicates whether the frame was valid when it was received at the previous node.

11. The node of claim 9, wherein the IRQ byte indicates an interrupt request detected at a downstream node.

12. The node of claim 11, wherein the node is configured to select the location of the IRQ byte to indicate the local interrupt based on the priority of the local interrupt.

13. The node of claim 9, wherein the node is configured to generate an upstream frame including an UpSRH in the absence of an UpSRH received from the downstream node.

14. The node of claim 4, wherein the flexible payload comprises one or more of the following: Audio stream; Control of the duty cycle of pulse width modulation; The stream from the analog-to-digital converter (ADC) at the node; Serial Peripheral Interface (SPI) tunnel; Ethernet tunnel; or Email tunnel.

15. The node of claim 4, wherein if there is no source, the flexible payload byte is zero.

16. The node of claim 4, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to transmit streams simultaneously at the same flexible payload location upstream and downstream.

17. The node of claim 4, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to apply a logical OR operation between upstream and downstream flows at the same location in the flexible payload.

18. The node of claim 1, wherein the node is configured to store a node identifier indicating the position of the node in the daisy chain.

19. The node of claim 1, wherein, in order to communicate with the downstream node and any upstream node, the node is configured to: The information received in the downstream frame will be immediately forwarded to the downstream node; The information received in the upstream frame will be immediately forwarded to the upstream node; as well as Data may be selectively read from or written to the upstream frame or the downstream frame.

20. A method of operating a node daisy-chained to one or more other nodes on a full-duplex link, comprising: Transmit the downstream synchronization control header (DnSCH) to the downstream node; Receive the upstream synchronization response header (UpSRH); Measure the delay between the DnSCH and the UpSRH; The delay information is sent to the downstream node in DnSCH; UpSRH for receiving time adjustment; and Based on the latency information, communication is conducted with the downstream node and any upstream node via frames.

21. The method of claim 20, wherein the communication uses full-duplex carrier-based modulation for the upstream and downstream signals on the full-duplex link.

22. The method of claim 20, wherein communicating with the downstream node and any upstream node includes sampling data of the flexible payload at the same time as the other nodes based on the latency information.

23. The method of claim 20, wherein each frame comprises: Header; A flexible payload defined by a stream mapping, which allocates byte positions within the flexible payload to a stream; as well as End of report.

24. The method of claim 23, wherein for a downstream frame, the header is the DnSCH and includes: It includes a synchronization byte with a frame counter, a command field, a data field, a data or address field, a long-range general-purpose input / output (GPIO) byte, and a cyclic redundancy check for the header; and The trailer includes: a Cyclic Redundancy Check (CRC) byte for the flexible payload and a frame validity indicator with independent CRC bits.

25. The method of claim 23, wherein for an upstream frame, the header is the UpSRH and includes a synchronization byte, a response / request field, a data field, and a cyclic redundancy check for the header, and the trailer includes an interrupt request (IRQ) byte, a long-distance general-purpose input / output (GPIO) byte, a CRC byte for the flexible payload, and a frame validity indication with independent CRC bits.

26. The method of claim 25, wherein the remote GPIO byte indicates an update to the state of the virtual GPIO pin, the method further comprising outputting virtual GPIO pin information on a GPIO output pin.

27. The method of claim 26, further comprising: Perform logical operations on the uplink receive state and local state of the virtual GPIO pin; The result of the logical operation in the long-distance GPIO byte in the tail of the forwarded uplink frame; and The result of the logical operation in the long-distance GPIO byte is included in the downstream node.

28. The method of claim 25, wherein the frame validity indicator having an independent CRC bit indicates whether the frame was valid when it was received at the previous node.

29. The method of claim 25, wherein the IRQ byte indicates the priority of an interrupt request detected at a downstream node.

30. The method of claim 25, wherein the communication includes generating an upstream frame including an UpSRH in the absence of an UpSRH received from the downstream node.

31. The method of claim 23, wherein the flexible payload comprises one or more of the following: Audio stream; Control of the duty cycle of pulse width modulation; The stream from the analog-to-digital converter (ADC) at the node; Serial Peripheral Interface (SPI) tunnel; Ethernet tunnel; or Email tunnel.

32. The method of claim 20, further comprising storing a node identifier indicating the position of the node in the daisy chain.

33. A communication system, comprising: Multiple nodes are daisy-chained via corresponding bus links, wherein the multiple nodes are configured for full-duplex synchronous communication over the bus links via a carrier-based modulation scheme, wherein, in order to synchronize the nodes, the master node transmits a downstream synchronization header at the beginning of a superframe, and each child node among the multiple nodes transmits the upstream response header at a timing adjusted based on the delay in receiving the downstream synchronization header and the delay in the upstream response header arriving at the master node at the end of the superframe.

34. The communication system of claim 33, wherein the order of the plurality of nodes is enumerated during the discovery process.

35. The communication system of claim 33, wherein the number of nodes in the communication system is limited based on a time budget for the length of a superframe, the time budget including time for the downstream synchronization header, time for the upstream response header, cable delay, and time for processing at each child node in each direction.

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