Embedded data processing and transmission optimization method and system based on ARM-RISCV dual-core architecture

Abstract

The embodiment of the invention provides an embedded data processing and transmission optimization method and system based on an ARM-RISCV dual-core architecture, and belongs to the technical field of signal processing of embedded systems. The method comprises the following steps: acquiring a digital signal needing to be processed; receiving the digital signal by using a UART end; under the condition that the data volume of the digital signal received by the UART end is greater than or equal to a preset first threshold value, carrying the received digital signal to a current buffer area by adopting a DMA controller; under the condition that the current data volume stored in the buffer area is greater than or equal to a preset second threshold value, adopting the DMA controller to send an interrupt signal to the CPU controller; under the condition that the CPU controller receives the interrupt signal, switching the carrying address of the DMA controller to a new buffer area; and under the condition that the data volume of any buffer area is greater than or equal to the second threshold value, performing data packaging operation on the correspondingly stored digital signal by adopting the CPU controller to form a data frame.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing of embedded systems, and in particular to an embedded data processing and transmission optimization method and system based on an ARM-RISCV dual-core architecture. BACKGROUND

[0002] With the rapid development of Internet of Things, artificial intelligence and 5G technology, embedded systems are evolving from traditional single-function execution units to intelligent, real-time and efficient ones. As the "nerve endings" connecting the physical and digital worlds, embedded systems play an increasingly important role in key fields such as industrial control, intelligent vehicles, medical devices and aerospace. However, as application scenarios demand higher real-time, reliability and energy efficiency for data processing, traditional embedded system architectures face severe challenges.

[0003] In embedded system design, resource constraints (limited CPU power, memory and storage), real-time requirements (tasks need to be completed within strict time limits), low-power operation (especially suitable for battery-powered scenarios) and high reliability (industrial, medical and other critical fields cannot be interrupted) are its core features. These features pose special requirements for system design, especially in data acquisition and processing. Currently, most embedded systems use single-core or homogeneous multi-core architectures, which are difficult to meet the dual demands of high-performance computing and real-time data processing.

[0004] Multi-core collaborative processing technology has become a key path to solving the performance bottleneck of embedded systems. However, existing technical solutions still have significant limitations. First, most embedded systems use homogeneous multi-core architectures, which can improve parallel computing capabilities but cannot effectively distinguish between real-time tasks and non-real-time tasks, resulting in a lack of real-time guarantees. Second, traditional multi-core collaboration solutions often rely on software-level scheduling mechanisms, lack hardware-level optimization support, and have low data transmission efficiency, making it difficult to meet the needs of high real-time scenarios. In industrial Internet of Things applications, the bursty nature of sensor data streams causes CPU utilization to fluctuate by more than 300%, and if data transmission delays exceed 50μs, the system will trigger a frequency reduction protection mechanism, resulting in a 22% loss of throughput.

[0005] In existing technologies, ARM and RISC-V heterogeneous multi-core architectures have been proposed, but most are limited to single-system or single-task scenarios. For example, some solutions use RISC-V cores for specific real-time tasks, but lack efficient communication mechanisms with Linux systems. Other solutions use DMA transmission, but do not fully utilize the characteristics of heterogeneous cores for task allocation, resulting in low resource utilization. In addition, serial communication methods become a bottleneck in high-data-rate scenarios, and traditional serial communication methods cannot meet real-time data acquisition requirements.

[0006] Meanwhile, the real-time requirement of embedded systems is increasing. In the fields of industrial automation, medical monitoring, intelligent driving, etc., the real-time performance of data acquisition directly affects the system performance and safety. For example, the ABS control system of a car must respond to sensor signals and execute braking logic within milliseconds, and any delay in data transmission can have serious consequences. The current embedded system lacks coordination efficiency in the data acquisition and processing link, and cannot fully exploit the potential of heterogeneous multi-core architecture. SUMMARY

[0007] The purpose of the embodiment of the application is to provide an embedded data processing and transmission optimization method and system based on ARM-RISCV dual-core architecture, which can improve the data processing efficiency of embedded systems.

[0008] In order to achieve the above purpose, the embodiment of the application provides an embedded data processing and transmission optimization method based on ARM-RISCV dual-core architecture, comprising: acquiring digital signals that need to be processed; receiving the digital signals at the UART end; if the data amount of the digital signals received at the UART end is greater than or equal to a preset first threshold, using a DMA controller to transfer the received digital signals to the current buffer; if the data amount stored in the current buffer is greater than or equal to a preset second threshold, using the DMA controller to send an interrupt signal to the CPU controller; if the CPU controller receives the interrupt signal, switching the transfer address of the DMA controller to a new buffer; if the data amount in any buffer is greater than or equal to the second threshold, using the CPU controller to perform data packing operation on the corresponding stored digital signals to form a data frame; using the CPU controller to wake up the ARM core and sending the data frame to the ARM core through the rpmsg mechanism for data processing.

[0009] Optionally, acquiring digital signals that need to be processed comprises: acquiring analog signals of the physical world; sampling and converting the analog signals according to a preset timer; unpacking the sampling and conversion results into UART communication frame format to obtain the digital signals.

[0010] Optionally, the number of buffers is 2, and the first threshold is 1 byte.

[0011] Optionally, the CPU controller is used to wake up the ARM core, and the data frame is sent to the ARM core through an rpmsg mechanism for data processing, including: triggering an inter-core interrupt to wake up the ARM core.

[0012] Optionally, the CPU controller is used to wake up the ARM core, and the data frame is sent to the ARM core through an rpmsg mechanism for data processing, including: the data frame is sent to the ARM core by writing an inter-core shared memory; the ARM core is used to strip an rpmsg protocol header to obtain the digital signal.

[0013] In another aspect, the application also provides an embedded data processing and transmission optimization system based on an ARM-RISCV dual-core architecture, which comprises a preprocessing interface, a UART end, a DMA controller, at least two buffer zones, a CPU controller and an ARM core. The preprocessing interface is used to obtain a digital signal to be processed. The UART end is used to receive the digital signal. When the data amount of the digital signal received by the UART end is greater than or equal to a preset first threshold, the DMA controller is used to carry the received digital signal to a current buffer zone. When the data amount stored in the current buffer zone is greater than or equal to a preset second threshold, the DMA controller sends an interrupt signal to the CPU controller. When the CPU controller receives the interrupt signal, the carrying address of the DMA controller is switched to a new buffer zone. When the data amount of any buffer zone is greater than or equal to the second threshold, the CPU controller performs a data packing operation on the corresponding stored digital signal to form a data frame. The CPU controller wakes up the ARM core, and the data frame is sent to the ARM core through an rpmsg mechanism for data processing.

[0014] Optionally, the preprocessing interface is used to: obtain an analog signal of a physical world; sample and convert the analog signal according to a preset timer; unpack the sampling and conversion result into a UART communication frame format to obtain the digital signal.

[0015] Optionally, the number of buffer zones is 2, and the first threshold is 1 byte.

[0016] Optionally, the CPU controller is configured to: trigger an inter-core interrupt to wake up the ARM core.

[0017] Optionally, the CPU controller is configured to send the data frame to the ARM core by writing to an inter-core shared memory. The ARM core is configured to strip the rpmsg protocol header to obtain the digital signal.

[0018] By the above technical solution, the embodiment of the present application provides an embedded data processing and transmission optimization method and system based on an ARM-RISCV dual-core architecture. The method and system realize efficient use of the DMA controller and the CPU controller in different stages of receiving data and processing data by dynamically mobilizing the DMA controller and the CPU controller, and improve the data processing efficiency of the embedded system.

[0019] Other features and advantages of the present application will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used together with the following specific implementation to explain the embodiments of the present application, but do not constitute a limitation on the embodiments of the present application. In the drawings: Figure 1 is a flow chart of an embedded data processing and transmission optimization method based on an ARM-RISCV dual-core architecture according to an embodiment of the present application; Figure 2 is a structural block diagram of an embedded data processing and transmission optimization system based on an ARM-RISCV dual-core architecture according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] The specific implementation of the embodiments of the present application will be described in detail below in combination with the drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiments of the present application, and does not limit the embodiments of the present application.

[0022] It should be noted that the acquisition, transmission, storage, use, processing, etc. of data in the technical solution of the present application comply with the relevant provisions of laws and regulations. In the embodiments of the present application, some industry existing solutions, components, models, etc. may be mentioned, which should be considered as exemplary, and the purpose is only to illustrate the feasibility of the implementation of the technical solution of the present application, but does not mean that the applicant has or will necessarily use the solution.

[0023] As Figure 1The diagram shows a flowchart of an embedded data processing and transmission optimization method based on an ARM-RISC dual-core architecture according to an embodiment of the present invention. Figure 1 In this method, the steps may include: In step S10, the digital signal to be processed is acquired; In step S11, digital signals are received using a UART terminal; In step S12, if the amount of data of the digital signal received at the UART terminal is greater than or equal to a preset first threshold, the DMA controller is used to move the received digital signal to the current buffer. In step S13, if the amount of data stored in the current buffer is greater than or equal to a preset second threshold, the DMA controller sends an interrupt signal to the CPU controller. In step S14, when the CPU controller receives an interrupt signal, the DMA controller's transfer address is switched to a new buffer. In step S15, if the amount of data in any buffer is greater than or equal to the second threshold, the CPU controller performs a data packing operation on the corresponding stored digital signal to form a data frame. In step S16, the CPU controller wakes up the ARM core and sends the data frame to the ARM core through the rpmsg mechanism for data processing.

[0024] In such Figure 1 In the method shown, step S10 can be used to acquire the digital signal to be processed. Specifically, step S11 can involve first acquiring an analog signal from the physical world, then sampling and converting the analog signal according to a preset timer, and finally, to facilitate signal transmission, packaging the sampling and conversion result into a UART communication frame format to obtain a digital signal. Furthermore, this digital signal can be transmitted bit by bit through the UART's transmit pin at a rate of 115200bps. The data exists on the transmission line in the form of an asynchronous serial signal.

[0025] Step S11 can be used to receive digital signals via a UART. Step S11 involves using a DMA controller to move the received digital signal to the current buffer when the amount of data in the digital signal received by the UART is greater than or equal to a preset first threshold. The first threshold can be any of several values ​​known to those skilled in the art. In one example of this invention, the first threshold can be 1 byte (bit). Since CPU controller intervention is not required at this time, excessive CPU controller usage can be avoided, thereby improving CPU controller utilization.

[0026] Step S13 can be used to send an interrupt signal to the CPU controller using the DMA controller when the amount of data stored in the current buffer is greater than or equal to the preset second threshold. When the CPU controller receives the interrupt signal, the carrying address of the DMA controller can be switched (transmitted through the serial port) to the new buffer (step S14). At the same time, since the amount of data stored in the buffer reaches the second threshold, the CPU can start working, that is, the corresponding stored digital signal is subjected to a data packing operation to form a data frame. Finally, after forming the data frame, the CPU controller can be used to wake up the ARM core, and the data frame is sent to the ARM core through the rpmsg mechanism for data processing. The method of waking up the ARM core can be achieved by triggering an inter-core interrupt. The data frame can be sent to the ARM core by writing the inter-core shared memory. The ARM core can obtain the digital signal (original waveform data) by stripping the rpmsg protocol header.

[0027] It should be noted that since the ARM core also includes a CPU, in order to avoid early calling of the ARM core, in the embodiment, the CPU controller is a riscv core.

[0028] In addition, in order to save the memory of the processing core of the embedded system, the number of buffers can be 2, so that the two buffers can work alternately when receiving data, thereby maximizing the utilization of the system.

[0029] On the other hand, the present application also provides an embedded data processing and transmission optimization system based on ARM-RISCV dual-core architecture, as shown in Figure 2 The system can include a preprocessor interface 1, a UART end 2, a DMA controller 3, at least two buffers 4, a CPU controller 5, and an ARM core 6. The preprocessor interface 1 can be used to obtain the digital signal to be processed. The preprocessor interface 1, the UART end 2, the DMA controller 3, the at least two buffers 4, the CPU controller 5, and the ARM core 6 can be used to work cooperatively to execute the method shown in Figure 1 Specifically, the system can be used to execute the following steps: In step S10, the digital signal to be processed is obtained; In step S11, the UART end 2 is used to receive the digital signal; In step S12, when the amount of data of the digital signal received by the UART end 2 is greater than or equal to the preset first threshold, the received digital signal is carried to the current buffer 4 using the DMA controller 3; In step S13, in the case that the amount of data stored in the current buffer 4 is greater than or equal to a preset second threshold value, the DMA controller 3 sends an interrupt signal to the CPU controller 5; In step S14, in the case that the CPU controller 5 receives the interrupt signal, the carrying address of the DMA controller 3 is switched to a new buffer 4; In step S15, in the case that the amount of data in any buffer 4 is greater than or equal to the second threshold value, the CPU controller 5 performs a data packing operation on the corresponding stored digital signal to form a data frame; In step S16, the CPU controller 5 wakes up the ARM core 6 and sends the data frame to the ARM core 6 through the rpmsg mechanism for data processing.

[0030] In the method shown in FIG. 1, Figure 1 In the method shown in FIG. 1,

[0031] Step S11 can be used to receive the digital signal by the UART end 2. Step S11 is used to carry the received digital signal to the current buffer 4 by the DMA controller 3 in the case that the amount of data of the digital signal received by the UART end 2 is greater than or equal to a preset first threshold value. The first threshold value can be a plurality of values known by those skilled in the art. In an example of the present application, the first threshold value can be 1 Bit. Since the CPU controller 5 does not need to intervene at this time, it can avoid excessive calling of the CPU controller 5, thereby improving the utilization rate of the CPU controller 5.

[0032] Step S13 can be used to send an interrupt signal to the CPU controller 5 by the DMA controller 3 in the case that the amount of data stored in the current buffer 4 is greater than or equal to the preset second threshold. In the case that the CPU controller 5 receives the interrupt signal, the carrying address of the DMA controller 3 can be switched (transmitted through a serial port) to the new buffer 4 at this time (step S14). At the same time, since the amount of data stored in the buffer 4 reaches the second threshold, the CPU can start working at this time, that is, the data packet operation is performed on the corresponding stored digital signal to form a data frame. Finally, after the data frame is formed, the ARM core 6 can be awakened by the CPU controller 5, and the data frame is sent to the ARM core 6 through the rpmsg mechanism for data processing. The method of awakening the ARM core 6 can be achieved by triggering an inter-core interrupt. The data frame can be sent to the ARM core 6 by writing an inter-core shared memory. The ARM core 6 can obtain the digital signal (original waveform data) by stripping the rpmsg protocol header.

[0033] It should be noted that since the ARM core also includes a CPU, in order to avoid early calling of the ARM core, the CPU controller is a riscv core in the embodiment.

[0034] In addition, in order to save the memory of the processing core of the embedded system, the number of buffers 4 can be 2, so that the two buffers 4 can work alternately when receiving data, thereby maximizing the utilization of the system.

[0035] Through the above technical solution, the embodiment of the application provides an embedded data processing and transmission optimization method and system based on an ARM-RISCV dual-core architecture. The method and system achieve efficient use of the DMA controller and the CPU controller in different stages of receiving data and processing data by dynamically mobilizing the DMA controller and the CPU controller, and improve the data processing efficiency of the embedded system.

[0036] Those skilled in the art should understand that the embodiments of the application can be provided as a method, a system, or a computer program product. Therefore, the application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0037] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof.

[0038] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof.

[0039] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof.

[0040] In one typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0041] The memory can include non-persistent memory and / or volatile memory, such as a random access memory (RAM) including a cache area for the temporary storage of data. A

[0042] Computer-readable media includes permanent and non-permanent, movable and non-movable media that can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer-readable media does not include transitory media such as modulated data signals and carriers.

[0043] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or apparatus that includes a list of elements does not only include those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0044] The above only is an embodiment of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. An embedded data processing and transmission optimization method based on an ARM-RISC dual-core architecture, characterized in that, include: Acquire the digital signal that needs to be processed; The digital signal is received using a UART terminal; If the amount of data of the digital signal received at the UART terminal is greater than or equal to a preset first threshold, the DMA controller is used to move the received digital signal to the current buffer. If the amount of data stored in the current buffer is greater than or equal to a preset second threshold, the DMA controller sends an interrupt signal to the CPU controller. When the CPU controller receives an interrupt signal, the DMA controller's transfer address is switched to a new buffer. If the amount of data in any buffer is greater than or equal to the second threshold, the CPU controller is used to perform data packaging operation on the corresponding stored digital signals to form a data frame; The CPU controller is used to wake up the ARM core, and the data frame is sent to the ARM core through the rpmsg mechanism for data processing.

2. The method according to claim 1, characterized in that, Acquire the digital signal to be processed, including: Acquire analog signals from the physical world; The analog signal is sampled and converted according to a preset timer; The sampling conversion result is packaged into a UART communication frame format to obtain the digital signal.

3. The method according to claim 1, characterized in that, The number of buffers is 2, and the first threshold is 1 byte.

4. The method according to claim 1, characterized in that, The CPU controller is used to wake up the ARM core, and the data frame is sent to the ARM core via the rpmsg mechanism for data processing, including: An inter-core interrupt is triggered to wake up the ARM core.

5. The method according to claim 1, characterized in that, The CPU controller is used to wake up the ARM core, and the data frame is sent to the ARM core via the rpmsg mechanism for data processing, including: The data frame is sent to the ARM core by writing to the inter-core shared memory; The ARM core is used to strip the rpmsg protocol header to obtain the digital signal.

6. An embedded data processing and transmission optimization system based on an ARM-RISC dual-core architecture, characterized in that, The system includes a preprocessing interface, a UART terminal, a DMA controller, at least two buffers, a CPU controller, and an ARM core. The preprocessing interface is used to acquire the digital signal that needs to be processed. The UART terminal is used to receive the digital signal; If the amount of data of the digital signal received at the UART terminal is greater than or equal to a preset first threshold, the DMA controller is used to move the received digital signal to the current buffer. If the amount of data stored in the current buffer is greater than or equal to a preset second threshold, the DMA controller sends an interrupt signal to the CPU controller; When the CPU controller receives an interrupt signal, the DMA controller's transfer address is switched to a new buffer. If the amount of data in any buffer is greater than or equal to the second threshold, the CPU controller will perform a data packing operation on the corresponding stored digital signal to form a data frame; The CPU controller wakes up the ARM core and sends the data frame to the ARM core via the rpmsg mechanism for data processing.

7. The system according to claim 6, characterized in that, The preprocessing interface is used for: Acquire analog signals from the physical world; The analog signal is sampled and converted according to a preset timer; The sampling conversion result is packaged into a UART communication frame format to obtain the digital signal.

8. The system according to claim 6, characterized in that, The number of buffers is 2, and the first threshold is 1 byte.

9. The system according to claim 6, characterized in that, The CPU controller is used for: An inter-core interrupt is triggered to wake up the ARM core.

10. The system according to claim 6, characterized in that, The CPU controller is used to send the data frame to the ARM core by writing inter-core shared memory; The ARM core is used to strip the rpmsg protocol header to obtain the digital signal.

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