Neutral atom array parallel execution-oriented physical perception compiling method and related device

Abstract

The invention discloses a physical perception compiling method for parallel execution of a neutral atom array and a related device, and belongs to the field of quantum computation.The physical perception compiling method comprises the steps that a hardware plane is divided into two or more hardware subareas capable of being operated in parallel according to the physical independence of an acousto-optic deflector array; converting a to-be-compiled quantum circuit into a graph model, dividing all vertexes in the graph model into communities corresponding to the number of the sub-regions, and performing iterative optimization to generate a local sub-circuit and a global sub-circuit corresponding to the sub-regions; all the sub-lines are input into a solver to be compiled, mathematical constraints are applied in the compiling process, and executable compiling results are output; according to the method, a hardware calculation plane is divided into two or more hardware sub-regions capable of being operated in parallel according to the physical independence of the acousto-optic deflector array, and a global problem is decomposed into a local problem of parallel processing, so that the calculation complexity is greatly reduced, and the compiling speed is increased in order of magnitude.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum computing, and in particular to a physical perception compiling method for parallel execution of a neutral atom array and a related device. BACKGROUND

[0002] Quantum computing is a new computing mode that regulates quantum information units to perform calculations according to the laws of quantum mechanics. It can provide powerful computing power beyond classical computing when dealing with certain computing problems by using basic principles such as quantum superposition, entanglement, and interference. In order to apply abstract quantum algorithms to actual physical systems, a quantum computer must be used. Among the many quantum computing hardware solutions, neutral atom quantum computing has great potential for expansion in the number of qubits, high-fidelity quantum operations, and unique dynamic reconfigurability, making it a promising technology platform. In this platform, individual neutral atoms are laser-cooled and trapped in an array of optical tweezers, with each atom serving as a qubit. A spatial light modulator (SLM) can generate static optical traps, while an acousto-optic deflector (AOD) can dynamically move the optical traps, thereby transporting atomic qubits to designated locations. When two atoms are moved close enough (i.e., within the Rydberg blockade radius , they can be excited into high-energy states by a Rydberg laser, enabling high-fidelity two-qubit entangling gate operations, which are the core of building general quantum circuits.

[0003] Any quantum algorithm must go through the key process of "compiling" before it is executed on hardware. Quantum compilation aims to convert a theoretical, abstract quantum circuit into a specific sequence of operation instructions that can be physically executed on a specific quantum hardware. The compilation process must strictly follow the physical constraints of the hardware. For the neutral atom platform, these constraints are particularly special and complex, including: 1) AOD intersection constraint: the AOD beam array used to move atoms cannot intersect in any two rows or any two columns on the plane, which limits the movement path of the atoms. 2) Parallel execution constraint: when a pair of qubits is executing a two-qubit gate, no third qubit is allowed to exist within their interaction region (usually defined by the Rydberg blockade radius) to avoid crosstalk and errors. 3) Rydberg interaction constraint: entangling gate operations can only be effectively performed when the distance between two qubits is less than the Rydberg blockade radius . These physical constraints collectively define an extremely large and complex solution space, making neutral atom quantum compilation a significant challenge.

[0004] With the rapid expansion of the hardware scale of neutral atoms (e.g., from 16x16 arrays to larger scales), existing compilation techniques, especially those that pursue optimal compilation quality, solver-based methods, gradually expose their inherent limitations, mainly in the following aspects: 1. "Dimensional disaster" of compilation efficiency: Existing methods usually solve the entire hardware array and the entire quantum circuit as a single, huge optimization problem. Since this problem is essentially NP-Hard, its computational complexity increases exponentially with the number of qubits and the number of gates. This leads to a dramatic expansion of compilation time, which for medium-sized circuits of several dozen qubits, takes thousands of seconds, or even fails to timeout. This "compilation bottleneck" greatly limits the effective utilization and practical application value of neutral atom quantum computers.

[0005] 2. Core contradiction between compilation efficiency and hardware flexibility: One of the biggest advantages of neutral atom platforms is their "reconfigurability", i.e., the ability to flexibly move atoms to realize connections between any qubits. However, existing compilation methods fail to effectively utilize this feature. They often transform the problem into a global static layout or scheduling problem to simplify the model, which creates an irreconcilable contradiction between compilation efficiency and hardware flexibility. On the one hand, heuristic algorithms that pursue high efficiency may not fully utilize the flexibility of the hardware, leading to a decline in compilation quality; on the other hand, precise solution methods that pursue high quality become impractical and inefficient due to the huge search space.

[0006] 3. Lack of deep utilization of physical characteristics: There is a fundamental flaw in the methodology of existing techniques, which mainly views the compilation problem as an abstract, purely computational challenge, ignoring its deep roots in physical reality. For example, the non-crossing nature of AOD arrays naturally provides physical boundaries for the division of hardware regions, which can be physically operated in parallel and without interference. However, existing methods solve the entire plane together, artificially introducing unnecessary computational complexity, and failing to utilize this "natural parallelism" to decompose the problem and speed up the solution.

[0007] In summary, existing techniques have serious performance bottlenecks in the field of neutral atom quantum compilation, and cannot meet the growing hardware scale and application requirements. Therefore, there is an urgent need for a new compilation paradigm that can fundamentally solve the contradiction between efficiency and flexibility. SUMMARY

[0008] The purpose of the present application is to overcome the problems of the prior art and provide a physical-aware compilation method for parallel execution of neutral atom arrays and related devices.

[0009] The object of the present application is achieved by the following technical solution: a physical-aware compilation method for neutral atom array parallel execution, comprising the following steps: According to the physical independence of the acousto-optic deflector array of the neutral atom quantum processor, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions capable of parallel operation; Convert the quantum circuit to be compiled into a graph model, where the vertices are qubits and the edges are gate operations. Divide all vertices in the graph model into communities corresponding to the number of hardware sub-regions, and perform iterative optimization based on an improved graph partitioning algorithm to generate local sub-circuits corresponding to each hardware sub-region and a global sub-circuit. The improved graph partitioning algorithm is used to minimize a physical-aware loss function, and the optimization goal of the loss function is to reduce the number of active qubits and the number of cross-region gates that need to be operated across regions; Input the local sub-circuit and the global sub-circuit into the solver for compilation. Apply local stage final state constraints in the local stage of compiling the local sub-circuit, and apply global stage spatial light modulator position constraints and global stage initial state connection constraints in the global stage of compiling the global sub-circuit. Output the final executable compilation result. The local stage final state constraint is used to make all resolved qubits that have completed all operations in the local stage be in a spatial light modulator trapped state at the end of the local compilation. The global stage spatial light modulator position constraint is used to prevent active qubits in the global stage from colliding with resolved qubits in the local stage in the spatial light modulator plane. The global stage initial state connection constraint is used to ensure spatial light modulator coordinate consistency and acousto-optic deflector channel relative order consistency. Spatial light modulator coordinate consistency means that the spatial light modulator coordinates of all active qubits at the beginning of the global stage are consistent with their final spatial light modulator coordinates at the end of the local stage. Acousto-optic deflector channel relative order consistency means that the acousto-optic deflector channel allocation at the beginning of the global stage needs to maintain the relative order of active qubits at the end of the local stage.

[0010] In an example, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions capable of parallel operation according to the physical independence of the acousto-optic deflector array of the neutral atom quantum processor, comprising: According to the array resources of the acousto-optic deflector, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions capable of parallel operation.

[0011] In an example, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions capable of parallel operation according to the array resources of the acousto-optic deflector, comprising: The row and column resources of the acousto-optic deflector array are divided in two, dividing the hardware computing plane of the neutral atom quantum processor into two hardware sub-regions.

[0012] In one example, the loss function The expression is: ; in, This indicates the number of active qubits that need to interact with qubits in other communities; This represents the number of edges connecting the two communities; This represents the weighting parameter.

[0013] In one example, the local stage final state constraint is represented as: in, It is a universal quantifier; Indicates the first The set of active qubits within a hardware sub-region k , n All are hardware sub-region indexes, and k < n ; Representing a quantum bit The state of confinement is a binary variable. Representing a quantum bit Trapped in a spatial light modulator state Representing a quantum bit It is trapped in the state of being imprisoned by the acousto-optic deflector; This indicates the final moment of the local compilation phase.

[0014] In one example, the global stage spatial light modulator position constraint is represented as: in, It is a universal quantifier; Defined as the set of spatial optical modulator coordinates occupied by all resolved qubits after the local phase ends. ; Indicates the first The set of active qubits within a hardware sub-region; and Representing a quantum bit i At any moment t Spatial light modulation coordinates; Representing a quantum bit The state of confinement is a binary variable. Representing a quantum bit Trapped in a spatial light modulator state Representing a quantum bit It is trapped in the state of the acousto-optic deflector.

[0015] In one example, the spatial light modulator coordinate consistency is represented as: in, It is a universal quantifier; Indicates the first The set of active qubits within a hardware sub-region; This represents the spatial optical modulator coordinates of the active quantum bit q at the initial moment of the global phase; Represents the final spatial optical modulator coordinates of the active qubit q at the end of the local phase; The relative order consistency of the acousto-optic deflector channels is represented as follows: in, For qubits The final acousto-optic deflector column index in the local phase; Representing a quantum bit The index of the acousto-optic deflector column at the initial moment of this global phase.

[0016] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.

[0017] The present invention also includes a computer program product comprising a computer program that, when executed by a processor, implements the steps of the physical-aware compilation method for parallel execution of a neutral atom array formed by any or a combination of the above examples.

[0018] The present invention also includes a storage medium storing computer instructions that, when executed, perform the steps of the physical awareness compilation method for parallel execution of a neutral atom array formed by any or more of the above examples.

[0019] The present invention also includes a terminal comprising a memory and a processor, the memory storing computer instructions executable on the processor, wherein the processor, when executing the computer instructions, performs the steps of the physical-aware compilation method for parallel execution of neutral atom arrays formed by any or more of the above examples.

[0020] Compared with the prior art, the beneficial effects of the present invention are: 1. A huge leap in compilation efficiency: Based on the physical independence of the acousto-optic deflector array, the hardware computing plane is divided into two or more hardware sub-regions that can operate in parallel (physically aware hardware partitions), decomposing the global problem into local problems that are processed in parallel, which greatly reduces the computational complexity and enables a compilation speed increase of orders of magnitude.

[0021] 2. Acceleration without sacrificing compilation quality: The physically-aware hardware partitioning step distributes the gate operations that were originally executed serially to different regions for simultaneous execution, shortening the total execution time and thus reducing the depth of the final circuit. This process does not introduce additional noise or error. Combined with quantum circuit partitioning and optimization, it can maximize the parallelism of the local stage, thereby improving compilation efficiency without sacrificing compilation quality.

[0022] 3. Superior scalability to adapt to future hardware development: Unlike existing technologies where efficiency drops sharply with scale, the performance advantages of this invention become increasingly significant with the increase in hardware scale. For the same quantum circuit, the compilation time of this method is actually reduced on larger arrays, demonstrating excellent forward scalability. This characteristic ensures that this invention is not only applicable to the present but can also effectively support the compilation needs of future larger-scale and more powerful neutral atom quantum computers. Attached Figure Description

[0023] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0024] Figure 1 A flowchart illustrating a method provided as an example of the present invention; Figure 2 A method framework diagram provided for a preferred example of the present invention; Figure 3 A schematic diagram of hardware plane partitioning and mapping provided as a preferred example of the present invention; Figure 4 This is a schematic diagram of the initial partitioning and iterative optimization provided as an example of the present invention; Figure 5 A schematic diagram of an acousto-optic deflector (AOD), a spatial light modulator (SLM) qubit, and a spatial light modulator (SLM) trap provided as an example of the present invention. Detailed Implementation

[0025] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] In one example, such as Figure 1 As shown, a physical awareness compilation method for parallel execution of neutral atom arrays is applied to neutral atom quantum processors. Its core idea is to no longer treat compilation as a single, massive global optimization task, but rather, starting from the physical characteristics of the hardware, intelligently decompose the complex global problem into multiple smaller, parallelizable local optimization problems. This fundamentally solves the bottleneck of compilation efficiency and fully unleashes the parallel potential of neutral atom hardware. The method includes the following steps: S10: Physically-aware hardware plane partitioning: Based on the physical independence of the acousto-optic deflector array of the neutral atom quantum processor, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions that can operate in parallel.

[0028] First, the physical structure and constraints of the neutral atom hardware are analyzed, particularly the row / column independent control and non-intersecting characteristics of the acousto-optic deflector array. Based on this, the entire two-dimensional hardware plane (e.g., an N x N acousto-optic deflector array) is strategically divided into two or more physically independent, parallel-operable regions. This division is not arbitrary but strictly based on the hardware physical boundaries, ensuring that atomic movements and gate operations within one region do not have any physical impact on other regions. In this way, the solution space is effectively trimmed at the hardware level, decomposing a global, highly coupled compilation environment into multiple independent, decoupled compilation sub-environments, creating the prerequisites for subsequent parallel processing.

[0029] S20: Parallel Quantum Circuit Partitioning: The quantum circuit to be compiled is converted into a graph model, where vertices are logical qubits and edges are gate operations. All vertices in the graph model are partitioned into communities corresponding to the number of hardware sub-regions, and iterative optimization is performed based on an improved graph partitioning algorithm to generate local sub-circuits and a global sub-circuit corresponding to each hardware sub-region. The improved graph partitioning algorithm is used to minimize a physical sensing loss function, the optimization objective of which is to reduce the number of active qubits and cross-region gates that require cross-region operations.

[0030] Based on the hardware partitioning in step S10, step S20 is used to intelligently decompose the input quantum circuit to maximize the matching with the parallel structure of the hardware. This invention employs an improved graph partitioning algorithm, abstracting the quantum circuit to be compiled into a graph model. Through optimized partitioning, the vast majority of gate operations (edges) fall within a single hardware region (community), while minimizing the number of gate operations requiring cross-region interaction (cross-community edges). This optimization process is guided by a physically-aware loss function that simultaneously considers the number of active qubits requiring cross-region operations and the number of cross-region gates, thereby ensuring that the partitioning result is physically optimal.

[0031] S30: The local and global sub-circuits are input into the solver for compilation. Local stage final state constraints are applied during the local stage of compiling the local sub-circuits, and global stage spatial light modulator position constraints and global stage initial state connection constraints are applied during the global stage of compiling the global sub-circuits. The final executable compilation result is output. Further, control instructions are generated based on the compilation result and applied to the acousto-optic deflector array, spatial light modulator, and excitation laser system of the neutral atom quantum processor to execute quantum computing tasks in parallel on the hardware plane.

[0032] The local stage final state constraint ensures that all resolved qubits that have completed all operations are in a spatial optical modulator (SOP) confinement state at the final moment of local compilation. The global stage SOP position constraint prevents spatial position conflicts between active qubits in the global stage and resolved qubits in the local stage on the SOP plane. The global stage initial state connection constraint ensures consistency of SOP coordinates and relative order of acousto-optic deflector channels. SOP coordinate consistency means that the SOP coordinates of all active qubits at the initial moment of the global stage are consistent with their final SOP coordinates at the end of the local stage. Relative order consistency of acousto-optic deflector channels means that the allocation of acousto-optic deflector channels at the initial moment of the global stage must maintain the relative order of the active qubits at the end of the local stage. Furthermore, when compiling the local and global sub-circuits into the solver, the compilation process is divided into a local stage and a global stage based on hardware partitioning. In the local stage, two or more hardware sub-regions process quantum gate operations that can be completed entirely within their local regions. After the local stage, the global stage performs unified compilation across the entire hardware plane for the remaining quantum gate operations that require interaction between qubits across different regions.

[0033] This invention, through the aforementioned physically-aware hardware plane partitioning and parallel quantum circuit partitioning steps, successfully transforms a previously difficult-to-handle global compilation task into two or more more manageable parts: two or more local sub-circuits that can be compiled in parallel locally, and a significantly reduced-size global sub-circuit responsible for handling cross-region interactions. This method not only drastically shortens compilation time through parallelization but also, because the size of each subproblem is much smaller than the original problem, enables the solver to find high-quality solutions in a shorter time, thus systematically resolving the contradiction between efficiency and quality.

[0034] Meanwhile, this invention proposes a novel "physically-aware" compilation paradigm, a successful practice of the co-design concept of quantum software (compilation) and hardware (physical constraints). It abandons the traditional approach of treating hardware as a black-box constraint set, instead deeply utilizing the physical characteristics of the hardware to guide and simplify the compilation algorithm itself. This shift in perspective, from a "purely computational challenge" to a "physical scenario problem," opens a highly promising new path for solving performance bottlenecks in quantum compilation and even the broader field of quantum computing.

[0035] In one example, based on the physical independence of the acousto-optic deflector array of the neutral atom quantum processor, the hardware computation plane of the neutral atom quantum processor is divided into two or more hardware sub-regions capable of parallel operation, including: Based on the array resources of the acousto-optic deflectors, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions that can operate in parallel.

[0036] Preferably, for a given N x N neutral atom array, the row and column resources of the acousto-optic deflector array are divided in half, and the hardware computing plane is divided into two hardware sub-regions. and Since the acousto-optic deflector (AOD) drive systems in different regions are independent of each other, atomic movement operations performed in one region (such as hardware sub-region 1) will not physically interfere with other regions (such as hardware sub-region 2), which makes it possible to execute compilation tasks in parallel in different regions.

[0037] In one example, based on hardware partitioning, the goal of parallel quantum circuit partitioning is to intelligently partition the input quantum circuits to match the parallel structure of the hardware, thereby maximizing the parallelism of the local stage and minimizing the computational load of the global stage. This includes: (1) Graph model transformation and initial partitioning: First, the quantum circuit to be compiled is transformed into a graph model. (in A collection of qubits The set of two-qubit gates is transformed into a graph model, where vertices represent qubits and edges represent gate operations. Subsequently, all vertices (qubits) are randomly and equally divided into two or more communities, meaning that all vertices are mapped to two or more hardware sub-regions respectively.

[0038] (2) Iterative Optimization: To achieve optimal partitioning, i.e., the most tightly connected internal nodes and the fewest external nodes, this invention employs an improved graph partitioning algorithm for iterative optimization. The core of the optimization is to minimize a physical sensing loss function L, which aims to simultaneously reduce the number of "active qubits" requiring cross-region operations and the number of "cross-region gates." This loss function is expressed as: ; in, This indicates the number of active qubits that need to interact with qubits in other communities; This represents the number of edges connecting the two communities; The weight parameter represents the importance of balancing the two optimization objectives of minimizing the number of active qubits and minimizing the number of cross-gates. The improved graph partitioning algorithm obtains the optimal partitioning scheme by iteratively swapping qubit pairs in two communities and selecting the swap operation that minimizes the loss function L to the greatest extent until L converges or reaches a preset iteration limit.

[0039] In one example, the local phase final state constraint is represented as: in, Indicates the first The set of active qubits within a hardware sub-region; Representing a quantum bit The state of confinement is a binary variable. Representing a quantum bit Trapped in a spatial light modulator state Representing a quantum bit It is trapped in the state of being imprisoned by the acousto-optic deflector; This indicates the final moment of the local compilation phase.

[0040] In one example, the global stage spatial light modulator position constraint is represented as: in, Defined as the set of spatial optical modulator coordinates occupied by all resolved qubits after the local phase ends. ; Indicates the first The set of active qubits within a hardware sub-region; and Representing a quantum bit i At any moment t Spatial light modulation coordinates; In one example, the spatial light modulator coordinate consistency is represented as: in, This represents the spatial optical modulator coordinates of the active quantum bit q at the initial moment of the global phase; Represents the final spatial optical modulator coordinates of the active qubit q at the end of the local phase; The relative order consistency of the acousto-optic deflector channels is represented as follows: in, For qubits The final acousto-optic deflector column index in the local phase; Representing a quantum bit The index of the acousto-optic deflector column at the initial moment of this global phase.

[0041] Combining the above examples yields the optimal example of the present invention. This is illustrated by dividing the hardware computing plane of the neutral atom quantum processor into two hardware sub-regions. Figure 2 As shown, the method includes the following steps: S1: As Figure 3 As shown, for a given N x N neutral atom array of a neutral atom quantum processor, based on the array resources of dynamically movable acousto-optic deflectors, the row and column resources of the array are divided in two to form... and Two sub-arrays, that is, dividing the hardware computing plane into two hardware sub-regions that can operate in parallel; S2: As Figure 4 As shown, the quantum circuit to be compiled is first converted into a graph model. All vertices in the graph model are randomly and equally divided into two communities, Q1 and Q2. These two communities, Q1 and Q2, are then mapped to two hardware sub-regions, A1 and A2, respectively. Based on an improved graph partitioning algorithm, iterative optimization is performed to generate two local sub-circuits, QC1 and QC2, and one global sub-circuit, QC3. The improved graph partitioning algorithm is used to minimize a physical sensing loss function. The optimization objective of the loss function is to reduce the number of active qubits requiring cross-region operations and the number of cross-region gates, expressed as: in, and These represent the number of active qubits (i.e., bits that need to interact with qubits in the other community) in communities Q1 and Q2, respectively. This represents the number of edges connecting the two communities; The weight parameter represents the importance of balancing the two optimization objectives: minimizing the number of active qubits and minimizing the number of cross-gates.

[0042] S3: Input the two local sub-circuits QC1 and QC2 and the global sub-circuit QC3 into the solver for compilation. The compilation process is divided into a local stage and a global stage. In the local stage, the two hardware sub-regions process the quantum gate operations that can be completed entirely within them in parallel. After the local stage is completed, the global stage compiles the remaining quantum gate operations that require interaction between qubits across regions in a unified manner across the entire hardware plane, thereby obtaining the final executable compilation result.

[0043] To ensure a correct and seamless transition between each stage and to further narrow the search space during the solution process, this invention introduces a series of key mathematical constraints.

[0044] Before defining constraints, first define the relevant variables: and Representing a quantum bit i At any moment t Spatial light modulator coordinates; and Represents the column and row indices of its acousto-optic deflector; binary variable Indicate its state, This is the spatial light modulator's trapped state. This is the AOD trapping state of the acousto-optic deflector. and These are the sets of active qubits in two regions. and These are the sets of resolved qubits in two regions, respectively. The relationship between the acousto-optic deflector (AOD), the spatial light modulator (SLM) qubits, and the SLM trap in this example is as follows: Figure 5 As shown. Based on the above hardware architecture and resource allocation, key physical constraints are introduced during the solution phase of compilation to ensure the correctness and efficiency of parallel compilation. Specifically, local stage final state constraints are applied in the local stage of compiling local sub-circuits, and global stage spatial light modulator position constraints and global stage initial state connection constraints are applied in the global stage of compiling global sub-circuits. The mathematical constraints are expressed as follows: 1. Local phase final state constraint: The final moment of compilation during the local phase. All resolved qubits Qr1 and Qr2 that have completed all operations must be forcibly moved to an SLM well that does not occupy AOD resources to avoid them physically hindering the movement of "active qubits" in the global phase. This constraint is expressed as: 2. Global Phase SLM Position Constraints: After the global phase begins, any "active qubit" (whose set is...) is subject to the following constraints: None of them can be placed on the SLM positions already occupied by resolved qubits in the local phase. Let F be the set of SLM coordinates occupied by all resolved qubits after the local phase ends. Then the constraint is: .

[0045] 3. Initial state connection constraint of global phase: The initial state of the global phase must strictly inherit the final state of the local phase to ensure the continuity of compilation.

[0046] SLM coordinate consistency: The SLM coordinates of all active qubits q at the initial moment (t=0) of the global phase must be consistent with their final SLM coordinates at the end of the local phase. Totally consistent.

[0047] AOD Channel Relative Order Consistency: To maintain the physical state continuity of the AOD array, the AOD channel allocation at the initial moment of the global phase must maintain the relative order of the active qubits at the end of the local phase. Let... For the final AOD column index of qubit q in the local phase, then for any two active qubits... and The following conditions must be met: Through the aforementioned phased and constrained implementation method, this invention transforms a large-scale compilation problem that is difficult to solve directly into a series of smaller, parallelizable, and mutually constrained subproblems, thereby achieving a fundamental improvement in compilation efficiency while ensuring solution quality. Experimental data shows that on a medium-sized 16x16 array, this invention achieves a compilation speed improvement of up to 78.5 times compared to the current state-of-the-art DPQA method, with an average speedup of 53.5 times. This means that a compilation task that originally took several hours can now be completed in minutes, greatly improving the efficiency of quantum computers and the speed of algorithm iteration. For the same quantum circuit, the compilation time of this method is actually shortened on larger arrays. Experiments have shown that on a larger 64x64 array, the peak speedup of this invention can reach 139.16 times.

[0048] Meanwhile, this invention achieves acceleration without sacrificing compilation quality. Specifically, compilation quality is typically measured by the depth of the final quantum circuit; a shallower depth means shorter execution time and higher fidelity. This invention, through physically-aware hardware partitioning, distributes gate operations that were originally executed serially to different regions for simultaneous execution, shortening the overall execution time and thus reducing the depth of the final circuit. Extensive benchmark results demonstrate that the circuit depth generated by this method is comparable to, and in some cases even superior to, existing state-of-the-art methods. This indicates that this invention successfully achieves an ideal balance between the two key metrics of compilation speed and compilation quality.

[0049] This invention proposes a novel physical-aware compilation paradigm, a successful practice of the co-design concept of quantum software (compilation) and hardware (physical constraints). It abandons the traditional approach of treating hardware as a black-box constraint set, instead deeply utilizing the physical characteristics of the hardware to guide and simplify the compilation algorithm itself. This shift in perspective, from a "purely computational challenge" to a "physical scenario problem," opens a highly promising new path for solving performance bottlenecks in quantum compilation and even the broader field of quantum computing.

[0050] The present invention also provides a computer program product, comprising a computer program that, when executed by a processor, implements the steps of the physical awareness compilation method for parallel execution of a neutral atom array formed by any or a combination of the above examples. The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement the present invention.

[0051] The present invention also provides a storage medium having the same inventive concept as a physics-aware compilation method for parallel execution of a neutral atom array formed by any or more of the above examples, wherein computer instructions are stored thereon, which, when executed, perform the steps of the physics-aware compilation method for parallel execution of a neutral atom array formed by any or more of the above examples.

[0052] Based on this understanding, the technical solution of this embodiment, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0053] This invention also provides a terminal having the same inventive concept as any or a combination of examples corresponding to the aforementioned physical awareness compilation method for parallel execution of neutral atom arrays, including a memory and a processor. The memory stores computer instructions executable on the processor, which, when executing the computer instructions, performs the steps of the aforementioned physical awareness compilation method for parallel execution of neutral atom arrays. The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement this invention.

[0054] In one example, the terminal, i.e., the electronic device, is represented in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one processing unit (processor) mentioned above, at least one storage unit mentioned above, and a bus connecting different system components (including storage units and processing units).

[0055] The storage unit stores program code that can be executed by the processing unit, causing the processing unit to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit can execute the aforementioned physical-aware compilation method for parallel execution of neutral atom arrays.

[0056] The storage unit may include a readable medium in the form of a volatile storage unit, such as a random access memory (RAM) 3201 and / or a cache storage unit, and may further include a read-only memory (ROM).

[0057] The storage unit may also include a program / utility having a set (at least one) of program modules, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0058] A bus can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus that uses any of the various bus structures.

[0059] The electronic device can also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., routers, modems, etc.). This communication can be performed via input / output (I / O) interfaces. Furthermore, the electronic device can communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter. The network adapter communicates with other modules of the electronic device via a bus. It should be understood that other hardware and / or software modules can be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0060] Through the above description, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to this exemplary embodiment can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method of the exemplary embodiment of this application.

[0061] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A physically-aware compilation method for parallel execution of neutral atom arrays, characterized in that, Includes the following steps: Based on the physical independence of the acousto-optic deflector array of the neutral atom quantum processor, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions that can operate in parallel. The quantum circuit to be compiled is converted into a graph model, where vertices are qubits and edges are gate operations. All vertices in the graph model are divided into communities corresponding to the number of hardware sub-regions, and iterative optimization is performed based on an improved graph partitioning algorithm to generate local sub-circuits and a global sub-circuit corresponding to each hardware sub-region. The improved graph partitioning algorithm is used to minimize a physical sensing loss function, the optimization objective of which is to reduce the number of active qubits and the number of cross-region gates that require cross-region operations. The local and global sub-circuits are input into the solver for compilation. Local stage final state constraints are applied during the local stage of compiling the local sub-circuits, and global stage spatial light modulator position constraints and global stage initial state connection constraints are applied during the global stage of compiling the global sub-circuits. The final executable compilation result is output. The local stage final state constraints are used to ensure that all resolved qubits that have completed all operations are in a spatial light modulator trapped state at the last moment of local compilation. The global stage spatial optical modulator position constraint is used to prevent spatial position conflicts between active qubits in the global stage and resolved qubits in the local stage on the spatial optical modulator plane. The global phase initial state connection constraint is used to ensure the consistency of spatial light modulator coordinates and the consistency of the relative order of acousto-optic deflector channels. Spatial light modulator coordinate consistency means that the spatial light modulator coordinates of all active qubits at the initial moment of the global phase are consistent with their final spatial light modulator coordinates at the end of the local phase. Acousto-optic deflector channel relative order consistency means that the acousto-optic deflector channel allocation at the initial moment of the global phase must maintain the relative order of each active qubit at the end of the local phase.

2. The physically-aware compilation method for parallel execution of neutral atom arrays according to claim 1, characterized in that, Based on the physical independence of the acousto-optic deflector array of the neutral atom quantum processor, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions capable of parallel operation, including: Based on the array resources of the acousto-optic deflectors, the hardware computing plane of the neutral atom quantum processor is divided into two or more hardware sub-regions that can operate in parallel.

3. The physically-aware compilation method for parallel execution of neutral atom arrays according to claim 2, characterized in that, The method of dividing the hardware computing plane of the neutral atom quantum processor into two or more hardware sub-regions capable of parallel operation based on the array resources of the acousto-optic deflectors includes: The row and column resources of the acousto-optic deflector array are divided in two, dividing the hardware computing plane of the neutral atom quantum processor into two hardware sub-regions.

4. The physically-aware compilation method for parallel execution of neutral atom arrays according to claim 1, characterized in that, The loss function The expression is: ； in, This indicates the number of active qubits that need to interact with qubits in other communities; This represents the number of edges connecting the two communities; This represents the weighting parameter.

5. The physically-aware compilation method for parallel execution of neutral atom arrays according to claim 1, characterized in that, The local stage final state constraint is expressed as follows: in, It is a universal quantifier; Indicates the first The set of active qubits within a hardware sub-region k , n All are hardware sub-region indexes, and k < n ; Representing a quantum bit The state of confinement is a binary variable. Representing a quantum bit Trapped in a spatial light modulator state Representing a quantum bit It is trapped in the state of being imprisoned by the acousto-optic deflector; This indicates the final moment of the local compilation phase.

6. The physically-aware compilation method for parallel execution of neutral atom arrays according to claim 1, characterized in that, The position constraint of the global stage spatial light modulator is expressed as follows: in, It is a universal quantifier; Defined as the set of spatial optical modulator coordinates occupied by all resolved qubits after the local phase ends. ; Indicates the first The set of active qubits within a hardware sub-region; and Representing a quantum bit i At any moment t Spatial light modulation coordinates; Representing a quantum bit The state of confinement is a binary variable. Representing a quantum bit Trapped in a spatial light modulator state Representing a quantum bit It is trapped in the state of the acousto-optic deflector.

7. The physically-aware compilation method for parallel execution of neutral atom arrays according to claim 1, characterized in that, The coordinate consistency of the spatial light modulator is represented as follows: in, It is a universal quantifier; Indicates the first The set of active qubits within a hardware sub-region; This represents the spatial optical modulator coordinates of the active quantum bit q at the initial moment of the global phase; Represents the final spatial optical modulator coordinates of the active qubit q at the end of the local phase; The relative order consistency of the acousto-optic deflector channels is represented as follows: in, For qubits The final acousto-optic deflector column index in the local phase; Representing a quantum bit The index of the acousto-optic deflector column at the initial moment of this global phase.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the physical awareness compilation method for parallel execution of neutral atom arrays as described in any one of claims 1-7.

9. A storage medium storing computer instructions thereon, characterized in that, The computer instructions execute the steps of the physical awareness compilation method for parallel execution of neutral atom arrays as described in any one of claims 1-7.

10. A terminal comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, characterized in that, When the processor executes the computer instructions, it performs the steps of the physical awareness compilation method for parallel execution of neutral atom arrays as described in any one of claims 1-7.

Images