Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device.The display panel comprises a plurality of pixel circuits, each pixel circuit at least comprises a data writing module and a first module, the control end of each data writing module is electrically connected with a first scanning signal, and the control end of each first module is electrically connected with a second scanning signal; the driving circuit comprises a first driving circuit and a second driving circuit; the first driving circuit receives a first type of clock signal and outputs a first scanning signal; the second driving circuit receives a second type clock signal and outputs a second scanning signal; and the cut-off time of the effective pulse of the first type of clock signals does not coincide with the cut-off time of the effective pulse of the second type of clock signals. The display device comprises the display panel. According to the invention, the possibility of brightness drift of the light-emitting element controlled by the pixel circuit is reduced, the obvious degree of mura display is improved, and the display effect is effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of science and technology, more and more display devices are being widely used in people's daily lives and work, becoming indispensable tools. Moreover, in recent years, consumers' demands for displays have been constantly increasing, leading to a proliferation of various display technologies, such as mini LED (submillimeter light-emitting diode) and micro LED (micro light-emitting diode). Micro LED features miniaturization, high photoelectric conversion efficiency, and short response time. Micro LED displays are expected to become the next major technology alongside OLED (Organic Light Source). The next generation of display technology after organic light-emitting diode (OLED).

[0003] In current display panels, the light-emitting elements used for image display are connected to pixel circuits, which in turn are connected to driving circuits. The pixel circuits respond to the control of the driving circuits, controlling the light-emitting elements to display images; that is, the control signals generated by the driving circuits directly affect the pixel circuits' control over the light-emitting elements. However, in existing driving circuits, there is a problem of mutual interference between signals, which can easily affect the driving circuits' control over the pixel circuits, leading to brightness drift of the light-emitting elements, causing display mura, and affecting the display effect. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display panel and a display device to solve the problem of poor display performance in existing display devices.

[0005] This disclosure provides a display panel, including: a plurality of pixel circuits, each pixel circuit including at least a data writing module and a first module, wherein the control terminal of the data writing module is electrically connected to a first scan signal, and the control terminal of the first module is electrically connected to a second scan signal; It also includes a driving circuit, which includes a first driving circuit and a second driving circuit; the first driving circuit receives a first type of clock signal and outputs a first scan signal; the second driving circuit receives a second type of clock signal and outputs a second scan signal. The cutoff time of the effective pulse of the first type of clock signal does not coincide with the cutoff time of the effective pulse of the second type of clock signal.

[0006] Optionally, the cutoff time of the effective pulse of the first type of clock signal is later than the cutoff time of the effective pulse of the second type of clock signal.

[0007] Optionally, the start time of the effective pulse of the first type of clock signal does not coincide with the start time of the effective pulse of the second type of clock signal.

[0008] Optionally, the start time of the effective pulse of the first type of clock signal is later than the start time of the effective pulse of the second type of clock signal.

[0009] Optionally, the pixel circuitry includes an amplitude adjustment circuit and a pulse width adjustment circuit that are electrically connected; The amplitude adjustment circuit receives amplitude data voltage and controls the amplitude of the driving current of the pixel circuit driving the light-emitting element; the pulse width adjustment circuit receives pulse width data voltage and controls the pulse width of the driving current. The data writing module includes an amplitude data writing module and / or a pulse width data writing module; the amplitude adjustment circuit includes an amplitude data writing module; and the pulse width adjustment circuit includes a pulse width data writing module. The control terminal of the amplitude data writing module is electrically connected to the first sub-scan signal, and the control terminal of the pulse width data writing module is electrically connected to the second sub-scan signal. The first scan signal includes a first sub-scan signal and / or a second sub-scan signal.

[0010] Further optionally, the first driving circuit includes a plurality of cascaded first shift registers, and the second driving circuit includes a plurality of cascaded second shift registers; The output of the first shift register is electrically connected to the control terminal of the pulse width data writing module, and the output of the second shift register is electrically connected to the control terminal of the amplitude data writing module. The second shift register receives the first clock signal and outputs the first sub-scan signal; the first shift register receives the second clock signal and outputs the second sub-scan signal. The first type of clock signal includes the second clock signal, and the second type of clock signal includes the first clock signal.

[0011] Further optionally, the second scan signal includes a third sub-scan signal and a fourth sub-scan signal; The amplitude adjustment circuit also includes an amplitude driving module and an amplitude reset module. The first terminal of the amplitude reset module is electrically connected to the amplitude reset voltage, the second terminal of the amplitude reset module is electrically connected to the amplitude driving module, and the control terminal of the amplitude reset module is electrically connected to the third sub-scan signal. The pulse width adjustment circuit also includes a pulse width driving module and a pulse width reset module. The first terminal of the pulse width reset module is electrically connected to the pulse width reset voltage, the second terminal of the pulse width reset module is electrically connected to the pulse width driving module, and the control terminal of the pulse width reset module is electrically connected to the fourth sub-scan signal. The first driving circuit includes multiple cascaded first shift registers, the second driving circuit includes a first sub-driving circuit, a second sub-driving circuit, and a third sub-driving circuit. The first sub-driving circuit includes multiple cascaded second shift registers, the second sub-driving circuit includes multiple cascaded third shift registers, and the third sub-driving circuit includes multiple cascaded fourth shift registers. The output of the first shift register is electrically connected to the control terminal of the pulse width data writing module, the output of the second shift register is electrically connected to the control terminal of the amplitude data writing module, the output of the third shift register is electrically connected to the control terminal of the amplitude reset module, and the output of the fourth shift register is electrically connected to the control terminal of the pulse width reset module. The second shift register receives the first clock signal and outputs the first sub-scan signal; The first shift register receives the second clock signal and outputs the second sub-scan signal; The third shift register receives the third clock signal and outputs the third sub-scan signal; The fourth shift register receives the fourth clock signal and outputs the fourth sub-scan signal; The first type of clock signal includes the second clock signal, and the second type of clock signal includes the first clock signal, the third clock signal, and the fourth clock signal.

[0012] Optionally, the cutoff time of the effective pulse of the second clock signal is later than the cutoff time of the effective pulse of the fourth clock signal, the cutoff time of the effective pulse of the fourth clock signal is later than the cutoff time of the effective pulse of the first clock signal, and the cutoff time of the effective pulse of the first clock signal is later than the cutoff time of the effective pulse of the third clock signal.

[0013] Optionally, the start time of the effective pulse of the second clock signal coincides with the start time of the effective pulse of the fourth clock signal, and the start time of the effective pulse of the first clock signal coincides with the start time of the effective pulse of the third clock signal. The start time of the effective pulse of the second clock signal is later than the start time of the effective pulse of the first clock signal.

[0014] Optionally, the start times of the effective pulses of the second clock signal, the fourth clock signal, the first clock signal, and the third clock signal coincide.

[0015] Optionally, the effective pulse duration of the second clock signal covers the effective pulse duration of the fourth clock signal, the effective pulse duration of the fourth clock signal covers the effective pulse duration of the first clock signal, and the effective pulse duration of the first clock signal covers the effective pulse duration of the third clock signal.

[0016] Optionally, the effective pulse width of the second clock signal is greater than the effective pulse width of the fourth clock signal, the effective pulse width of the fourth clock signal is greater than the effective pulse width of the first clock signal, and the effective pulse width of the first clock signal is greater than the effective pulse width of the third clock signal.

[0017] Optionally, the cutoff time of the effective pulse of the second clock signal is later than the cutoff time of the effective pulse of the first clock signal, the cutoff time of the effective pulse of the first clock signal is later than the cutoff time of the effective pulse of the fourth clock signal, and the cutoff time of the effective pulse of the fourth clock signal is later than the cutoff time of the effective pulse of the third clock signal.

[0018] Optionally, the start time of the effective pulse of the second clock signal is earlier than the start time of the effective pulse of the first clock signal, the start time of the effective pulse of the first clock signal is earlier than the start time of the effective pulse of the fourth clock signal, and the start time of the effective pulse of the fourth clock signal is earlier than the start time of the effective pulse of the third clock signal.

[0019] Optionally, the effective pulse duration of the second clock signal covers the effective pulse duration of the first clock signal, the effective pulse duration of the first clock signal covers the effective pulse duration of the fourth clock signal, and the effective pulse duration of the fourth clock signal covers the effective pulse duration of the third clock signal.

[0020] Optionally, the effective pulse width of the second clock signal is greater than the effective pulse width of the first clock signal, the effective pulse width of the first clock signal is greater than the effective pulse width of the fourth clock signal, and the effective pulse width of the fourth clock signal is greater than the effective pulse width of the third clock signal.

[0021] Optionally, the start time of the effective pulse of the second clock signal is later than the start time of the effective pulse of the fourth clock signal, the start time of the effective pulse of the fourth clock signal is later than the start time of the effective pulse of the first clock signal, and the start time of the effective pulse of the first clock signal is later than the start time of the effective pulse of the third clock signal.

[0022] Optionally, the effective pulse durations of at least some of the first, second, third, and fourth clock signals overlap at least partially.

[0023] Optionally, at least some of the clock signals, including the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, have effective pulse durations that do not overlap.

[0024] Optionally, at least some of the clock signals among the first, second, third, and fourth clock signals have equal effective pulse widths.

[0025] Optionally, the start time of the effective pulse of the first clock signal coincides with the start time of the effective pulse of the third clock signal, and the end time of the effective pulse of the first clock signal coincides with the end time of the effective pulse of the third clock signal. The start time of the effective pulse of the second clock signal coincides with the start time of the effective pulse of the fourth clock signal, and the end time of the effective pulse of the second clock signal coincides with the end time of the effective pulse of the fourth clock signal. The start time of the effective pulse of the first clock signal is earlier than the start time of the effective pulse of the second clock signal; The cutoff time of the effective pulse of the first clock signal is earlier than the cutoff time of the effective pulse of the second clock signal.

[0026] Optionally, the display panel includes a display area, which includes multiple pixel circuits; The driving circuit is located in the display area.

[0027] Further optionally, the driving circuit is electrically connected to the clock control signal line, which includes a first type of clock control signal line and a second type of clock signal line. The first type of clock control signal line is used to provide a first type of clock signal to the first driving circuit, and the second type of clock control signal line is used to provide a second type of clock signal to the second driving circuit. The clock control signal line is located in the display area, and multiple pixel circuits form a pixel circuit row along the first direction; The clock control signal line is located between two adjacent pixel circuits in a pixel circuit row; or, A pixel circuit row includes multiple pixel circuit groups, and each pixel circuit group includes at least two pixel circuits. Each pixel circuit group controls multiple light-emitting elements of different colors to emit light, and a clock control signal line is located between two adjacent pixel circuit groups.

[0028] Optionally, within a line time, the cutoff time of the effective pulse of the first type of clock signal does not coincide with the cutoff time of the effective pulse of the second type of clock signal; wherein, the line time represents the time required for the display panel to drive one line of pixel circuitry during the line-by-line scanning process.

[0029] Based on the same inventive concept, this disclosure also provides a display device, which includes the above-described display panel.

[0030] The technical solution provided in this disclosure has the following advantages compared with the prior art: The display panel disclosed herein includes multiple pixel circuits, each pixel circuit including at least a data writing module and a first module. The control terminal of the data writing module is electrically connected to a first scan signal, and the control terminal of the first module is electrically connected to a second scan signal. The driving circuit of the display panel includes a first driving circuit and a second driving circuit. The first driving circuit receives a first type of clock signal and outputs a first scan signal; the second driving circuit receives a second type of clock signal and outputs a second scan signal. This disclosure sets the clock signals input to the first and second driving circuits to clock signals whose effective levels do not completely overlap. Specifically, the first driving circuit receives a first type of clock signal and outputs a first scan signal to the control terminal of the data writing module, while the second driving circuit receives a second type of clock signal and outputs a second scan signal to the control terminal of the first module. Furthermore, the cutoff time of the effective pulse of the first type of clock signal does not coincide with the cutoff time of the effective pulse of the second type of clock signal; that is, the cutoff time of the effective pulse of the first type of clock signal avoids the cutoff time of the effective pulse of the second type of clock signal. This avoids mutual interference between the first scan signal output by the first driving circuit and the second scan signal output by the second driving circuit. The effective pulse time of the first scan signal generated by the first driving circuit after receiving the first type of clock signal also avoids the effective pulse time of the second scan signal generated by the second driving circuit after receiving the second type of clock signal. Because the switching timings of the transistors in the different driving circuits are staggered, the signal coupling caused by the simultaneous conduction of transistors in different driving circuits when receiving clock signals with completely overlapping effective levels in the prior art is eliminated. It also eliminates the charge mutation caused by the simultaneous cutoff of transistors in different driving circuits when receiving clock signals with completely overlapping effective levels in the prior art. In this disclosure, the first driving circuit and the second driving circuit use different clock signals to generate the waveforms of the scanning signals of different modules in the pixel circuit. This allows the writing of the data voltage signal controlled by the first scanning signal and the writing of other signals (such as the reset voltage signal) controlled by the second scanning signal to be mutually independent. For example, the writing of other signals controlled by the second scanning signal will not affect the transmission of the data voltage signal to the data writing module in the pixel circuit. This helps to ensure the stability of the data voltage signal writing, reduces the possibility of brightness drift of the light-emitting element controlled by the pixel circuit, improves the visibility of the display mura, and effectively enhances the display effect. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure; Figure 2 yes Figure 1 A schematic diagram of a connection structure for a mid-pixel circuit; Figure 3 This is a schematic diagram of the structure of a display panel provided in related technologies; Figure 4 yes Figure 3 Timing diagram of the driving circuit; Figure 5 This is a timing diagram of a first type of clock signal and a second type of clock signal provided in an embodiment of this disclosure; Figure 6 This is another timing diagram of the first type of clock signal and the second type of clock signal provided in the embodiments of this disclosure; Figure 7 yes Figure 1 A schematic diagram of another connection structure for the mid-pixel circuit; Figure 8 yes Figure 1 A schematic diagram of another connection structure for the mid-pixel circuit; Figure 9 yes Figure 1 A schematic diagram of another connection structure for the mid-pixel circuit; Figure 10 yes Figure 1 A schematic diagram of another connection structure for the mid-pixel circuit; Figure 11 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure; Figure 12 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure; Figure 13 yes Figure 9 and Figure 12 A simplified schematic diagram of the electrical connection between the drive circuit and the pixel circuit; Figure 14 yes Figure 12 A timing diagram of the first and second type of clock signals received by the driving circuit; Figure 15 yes Figure 12 The driving circuit in the middle adopts Figure 14Timing diagram of the scan signal generated by the clock signal timing; Figure 16 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit; Figure 17 yes Figure 12 The driving circuit in the middle adopts Figure 16 Timing diagram of the scan signal generated by the clock signal timing; Figure 18 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit; Figure 19 yes Figure 12 The driving circuit in the middle adopts Figure 18 Timing diagram of the scan signal generated by the clock signal timing; Figure 20 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit; Figure 21 yes Figure 12 The driving circuit in the middle adopts Figure 20 Timing diagram of the scan signal generated by the clock signal timing; Figure 22 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit; Figure 23 yes Figure 12 The driving circuit in the middle adopts Figure 22 Timing diagram of the scan signal generated by the clock signal timing; Figure 24 yes Figure 1 A schematic diagram of another connection structure for the mid-pixel circuit; Figure 25 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure; Figure 26 yes Figure 24 and Figure 25 A simplified schematic diagram of the electrical connection between the drive circuit and the pixel circuit; Figure 27 yes Figure 25 A timing diagram of the first and second type of clock signals received by the driving circuit; Figure 28 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure; Figure 29 yes Figure 28A simplified schematic diagram of the clock control signal lines and pixel circuit arrangement in the central display area; Figure 30 yes Figure 28 Another simplified schematic diagram of the clock control signal lines and pixel circuit arrangement in the central display area; Figure 31 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure; Figure 32 This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure; Figure 33 This is another planar structural schematic diagram of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0034] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0035] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0036] In the structure of existing display panels, a typical display panel includes multiple pixel circuits. These pixel circuits are electrically connected to light-emitting elements (LEDs) to control the LEDs and create a display image. Display panels also generally include driving circuits, which may include cascaded multi-stage shift registers. The output signals (scan control signals) of each shift register can control the corresponding transistors in the pixel circuits to turn on or off, thus controlling the on-time of the transistors required to control the LEDs and enabling the pixel circuits to control the LEDs to display light. For example, a pixel circuit typically includes a data writing module, a reset module, and an LED control module. The scan control signals controlling the data writing module and the reset module can be generated by different driving circuits. However, all driving circuits use clock signals with completely overlapping effective voltage levels to generate the waveforms of the scan control signals for different modules. The transistors in different driving circuits controlled by clock signals whose effective levels completely overlap will inevitably turn on and off simultaneously. This can easily cause mutual interference when transistors in different driving circuits are turned on at the same time, which in turn affects the generated scanning control signal. Ultimately, this affects the light-emitting effect of the pixel circuit on the light-emitting element, and the brightness drift of the light-emitting element causes uneven display brightness (i.e., display mura, which refers to the phenomenon of various brightness and darkness and blurred boundaries in the display screen of the display device, which will not be explained further).

[0037] To address the aforementioned problems, this application proposes a display panel and display device that can improve display mura caused by brightness drift of the light-emitting element and enhance display performance. Specific embodiments of the display panel and display device proposed in this application are described in detail below.

[0038] Please refer to the reference. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure. Figure 2 yes Figure 1 A schematic diagram of a connection structure of a pixel circuit. The display panel 000 provided in this embodiment includes: a plurality of pixel circuits 10. Each pixel circuit 10 includes at least a data writing module 101 and a first module 102. The control terminal of the data writing module 101 is electrically connected to a first scan signal scan1, and the control terminal of the first module 102 is electrically connected to a second scan signal scan2. It also includes a driving circuit 00, which includes a first driving circuit 00-1 and a second driving circuit 00-2; the first driving circuit 00-1 receives a first type of clock signal CK-1 and outputs a first scan signal scan1; the second driving circuit 00-2 receives a second type of clock signal CK-2 and outputs a second scan signal scan2. The cutoff time of the effective pulse of the first type of clock signal CK-1 does not coincide with the cutoff time of the effective pulse of the second type of clock signal CK-2.

[0039] Specifically, the display panel 000 provided in this embodiment includes multiple pixel circuits 10. Optionally, the pixel circuits 10 are electrically connected to light-emitting elements 20. In this embodiment, the light-emitting element 20 can be a light-emitting diode (LED), such as a mini light-emitting diode (mini LED) or a micro light-emitting diode (micro LED). The design can be tailored to the specific implementation. In this embodiment, the pixel circuits 10 are electrically connected to the light-emitting elements 20. By adjusting the driving current supplied to the pixel circuits 10, the brightness of the light-emitting elements 20 connected to the pixel circuits 10 is controlled, thereby realizing the image display function of the display panel 000.

[0040] It is understood that in this embodiment Figure 1 The multiple light-emitting elements 20 included in the display panel 000 are illustrated using an array arrangement as an example. In actual implementation, the arrangement of the multiple light-emitting elements 20 in the display panel 000 can be selected and set according to actual needs. This embodiment Figure 1 The pixel circuit 10 is represented by a block diagram. In specific implementation, the pixel circuit 10 can be a structure that includes multiple modules electrically connected. For example, the pixel circuit 10 can be an electrical connection structure that includes multiple thin-film transistors and capacitors. The thin-film transistors and capacitors can be made using the film layer structure of the display panel 000. This embodiment will not be described in detail here. For details, please refer to the subsequent embodiments for understanding.

[0041] The pixel circuit 10 of this embodiment includes at least a data writing module 101 and a first module 102. The control terminal of the data writing module 101 is electrically connected to a first scan signal scan1, and the control terminal of the first module 102 is electrically connected to a second scan signal scan2. The first scan signal scan1 is electrically connected to the control terminal of the data writing module 101 and is used to provide a scan control signal to control the on and off states of the data writing module 101. For example, the first scan signal scan1 can be provided to the gate of the thin-film transistor included in the data writing module 101 to control the on and off states of the thin-film transistor, thereby controlling the writing time of the data voltage signal. This allows the pixel circuit 10 to control the light-emitting element 20 to emit light according to the written data voltage signal. The first module 102 can be other modules included in the pixel circuit 10 besides the data writing module 101, such as a reset module. The second scan signal scan2 is electrically connected to the control terminal of the first module 102 and is used to provide a scan control signal to control the conduction and shutdown of the first module 102. If the first module 102 is a reset module, then the first scan signal scan1 can be provided to the gate of the thin film transistor included in the first module 102 to control the conduction and shutdown of the thin film transistor, so as to control the writing time of the reset voltage signal, so that the pixel circuit 10 can be initialized according to the written reset voltage signal.

[0042] It is understood that this embodiment does not limit the function implemented by the first module 102. It only needs to satisfy that the first module 102 is a module other than the data writing module 101 included in the pixel circuit 10, and that the scan control signal (second scan signal scan2) controlling the first module 102 to be turned on or off is a different control signal from the scan control signal (first scan signal scan1) controlling the data writing module 101 to be turned on or off.

[0043] It should be noted that in this embodiment... Figure 1 and Figure 2 This illustration only demonstrates the structure of the display panel. In actual implementation, the display panel may also include other structures besides the driving circuit 00, pixel circuit 10, and light-emitting element 20, such as various signal lines. Figure 2 This illustration only shows the electrical connection structure of the pixel circuit 10 and the light-emitting element 20. In a specific implementation, the pixel circuit 10 may also include other functional modules besides the data writing module 101 and the first module 102, such as... Figure 2 The structure includes the drive module 103, etc. In specific implementation, it can be designed according to actual needs, and will not be described in detail in this embodiment.

[0044] The display panel 000 in this embodiment further includes a driving circuit 00, which includes a first driving circuit 00-1 and a second driving circuit 00-2. That is, the display panel 000 may include at least two sets of driving circuits, namely the first driving circuit 00-1 and the second driving circuit 00-2. The first driving circuit 00-1 can be used to generate a scan control signal to control the data writing module 101 to be turned on or off. That is, the first driving circuit 00-1 is used to generate a first scan signal scan1. Optionally, the output terminal of the first driving circuit 00-1 can be electrically connected to the control terminal of the data writing module 101 of the pixel circuit 10 through the first scan line. The second driving circuit 00-2 can be used to generate a scan control signal to control the first module 102 (such as the reset module generally included in the pixel circuit 10) to be turned on or off. That is, the second driving circuit 00-2 is used to generate a second scan signal scan2. Optionally, the output terminal of the second driving circuit 00-2 can be electrically connected to the control terminal of the first module 102 of the pixel circuit 10 through the second scan line.

[0045] It should be noted that the circuit structure of the first driving circuit 00-1 and the second driving circuit 00-2 is not described in detail in this embodiment. The circuit structure of the first driving circuit 00-1 and the second driving circuit 00-2 can each include a structure of multiple cascaded shift registers. In specific implementation, the structure of the scan driving circuit in related technologies can be referred to for understanding. This embodiment does not limit it here.

[0046] It should be noted that in this embodiment... Figure 1 In the accompanying drawings of the following embodiments, the illustration shows an example where the light-emitting element 20 and the pixel circuit 10 do not overlap along the thickness direction of the display panel 000. In some other alternative embodiments, the light-emitting element 20 may overlap with the pixel circuit 10 along the thickness direction of the display panel 000. It is also understood that... Figure 1 The light-emitting element 20 shown in the diagram is located on the right side of the pixel circuit 10. This is only for illustration. In actual implementation, it is not limited to the light-emitting element 20 being located on the right side of the pixel circuit 10. Other reasonable arrangements are also acceptable.

[0047] like Figure 3 and Figure 4 As shown, Figure 3 This is a structural diagram of a display panel provided in related technologies. Figure 4 yes Figure 3 Timing diagram of the driving circuit. Figure 3The intermediate pixel circuit 10' includes a data writing module 101' and a reset module 102', etc. The first scan control signal scan1' that controls the data writing module 101' to conduct and the second scan control signal scan2' that controls the reset module 102' to conduct are generated by different driving circuits (first driving circuit 00-1' and second driving circuit 00-2'), such as... Figure 4 As shown in the figure, STV' is the start trigger signal of the drive circuit. The output terminal OUT1' of the first drive circuit 00-1' outputs scan1', and the output terminal OUT2' of the second drive circuit 00-2' outputs scan2'. However, all drive circuits use a clock signal CK' with completely overlapping effective level durations as input to generate the waveforms of the scan control signals for different modules. The transistors in different driving circuits controlled by the clock signal CK' (which can be understood as the inverted clock signal CKB' being the inverse of the clock signal CK' and also one of the clock signals required by the driving circuit) with the effective level durations completely overlapping will simultaneously turn on and off. This can easily cause mutual coupling interference in the signal paths of adjacent driving circuits when the transistors of different driving circuits are synchronously turned on, such as voltage fluctuations and current crosstalk, resulting in distortion of the effective pulses of the generated scan signals, such as affecting the generated first scan control signal scan1' and second scan control signal scan2'. During the synchronous cut-off phase of the transistors of different driving circuits, the simultaneous interruption of the scan signals of different modules in the pixel circuit 10' and their transformation into invalid pulses will cause charge mutations within the pixel circuit 10', leading to instability in the driving current of the light-emitting element 20'. This ultimately manifests as brightness drift (such as the brightness difference between adjacent light-emitting elements 20' exceeding the threshold that the human eye can perceive) and display mura (such as striped or spot-like unevenness), ultimately affecting the light-emitting effect of the light-emitting element 20' controlled by the pixel circuit 10', resulting in poor display quality.

[0048] To solve the above problems, such as Figure 1 , Figure 2 and Figure 5 As shown, Figure 5This is a timing diagram of a first type of clock signal and a second type of clock signal provided in an embodiment of this disclosure. In this embodiment, the clock signals input to the first driving circuit 00-1 and the second driving circuit 00-2 are clock signals whose effective levels do not completely overlap. Specifically, the first driving circuit 00-1 receives the first type of clock signal CK-1 and outputs a first scan signal scan1 to the control terminal of the data writing module 101. The second driving circuit 00-2 receives the second type of clock signal CK-2 and outputs a second scan signal scan2 to the control terminal of the first module 102. Furthermore, the cutoff time of the effective pulse of the first type of clock signal CK-1 does not coincide with the cutoff time of the effective pulse of the second type of clock signal CK-2, that is, the cutoff time of the effective pulse of the first type of clock signal CK-1 avoids the second type of clock signal CK-2. When the effective pulse cutoff time is determined, the first scan signal scan1 output by the first driving circuit 00-1 and the second scan signal scan2 output by the second driving circuit 00-2 can avoid mutual interference. The effective pulse time of the first scan signal scan1 generated by the first driving circuit 00-1 after receiving the first type of clock signal CK-1 can also avoid the effective pulse time of the second scan signal scan2 generated by the second driving circuit 00-2 after receiving the second type of clock signal CK-2. The switching timing of the transistors of different driving circuits is staggered, which eliminates the signal coupling when the duration of the received effective level completely coincides with the clock signal, causing the transistors of different driving circuits to be turned on at the same time. It also eliminates the charge change when the duration of the received effective level completely coincides with the clock signal, causing the transistors of different driving circuits to be turned off at the same time. In this embodiment, the first driving circuit 00-1 and the second driving circuit 00-2 use different clock signals to generate the waveforms of the scanning signals of different modules in the pixel circuit 10. This allows the writing of the data voltage signal controlled by the first scanning signal scan1 and the writing of other signals (such as the reset voltage signal) controlled by the second scanning signal scan2 to be mutually independent. For example, the writing of other signals controlled by the second scanning signal scan2 will not affect the transmission of the data voltage signal to the data writing module 101 in the pixel circuit 10. This helps to ensure the stability of the data voltage signal writing, reduces the possibility of brightness drift of the light-emitting element 20 controlled by the pixel circuit 10, improves the visibility of the display mura, and effectively enhances the display effect.

[0049] It should be noted that the illustration in this embodiment uses the example of the effective pulses of the first type of clock signal CK-1 and the second type of clock signal CK-2 being at a low level. That is, the transistors controlled by the first type of clock signal CK-1 and the second type of clock signal CK-2 are P-type transistors, which are turned on at a low level and turned off at a high level. In some other optional embodiments, the effective pulses of the first type of clock signal CK-1 and the second type of clock signal CK-2 can also be at a high level, and this embodiment does not limit this.

[0050] It is understood that in this embodiment, the first type of clock signal CK-1 corresponds to the first type of inverted clock signal CKB-1, which is also the clock signal that the first driving circuit 00-1 needs to receive. The second type of clock signal CK-2 corresponds to the second type of inverted clock signal CKB-2, which is also the clock signal that the second driving circuit 00-2 needs to receive.

[0051] Optionally, in this embodiment, when the effective pulses of the first type of clock signal CK-1 and the second type of clock signal CK-2 are low, the first driving circuit 00-1 receives the first type of clock signal CK-1, and the effective pulse of the first scan signal scan1 it outputs is also low. That is, the thin-film transistor included in the data writing module 101 can be a P-type transistor. When the first scan signal scan1 is low, the data writing module 101 is turned on, and when the first scan signal scan1 is high, the data writing module 101 is turned off. The second driving circuit 00-2 receives the second type of clock signal CK-2, and the effective pulse of the second scan signal scan2 it outputs is also low. That is, the thin-film transistor included in the first module 102 can also be a P-type transistor. When the second scan signal scan2 is low, the first module 102 is turned on, and when the second scan signal scan2 is high, the first module 102 is turned off.

[0052] It should be further explained that, in this embodiment, the first driving circuit 00-1 receives a first type of clock signal CK-1 and outputs a first scan signal scan1. At least within one line time, there exists a time when the cutoff time of the effective pulse of the first type of clock signal CK-1 corresponds to the start time of the effective pulse of the first scan signal scan1. The second driving circuit 00-2 receives a second type of clock signal CK-2 and outputs a second scan signal scan2. At least within one line time, there exists a time when the cutoff time of the effective pulse of the second type of clock signal CK-2 corresponds to the start time of the effective pulse of the second scan signal scan2. This allows different driving circuits to receive different clock signals to generate scan signals that control the conduction of different modules in the pixel circuit 10.

[0053] It is understood that the line time (1H) in this embodiment and in other subsequent embodiments can be understood as the time required for the display panel 000 to drive one line of pixel circuit 10 during the progressive scan driving process. The line time of the display panel can also be calculated using 1H = 1s / refresh rate / V_total. Here, refresh rate represents the basic refresh frequency of the display panel (e.g., 60Hz or 120Hz), and V_total is the total number of transmissions driving the display panel. V_total is the sum of the vertical display lines and the vertical blanking lines. The vertical display lines refer to the actual number of pixel circuit lines in the vertical direction of the display panel. For example, if the resolution of the display panel is 1920×1080, then 1080 in the resolution represents the vertical display lines. The vertical blanking lines refer to the number of lines in the time between the end of the last pixel circuit line scan transmission in one frame and the beginning of the first valid scan pixel circuit line in the next frame. These blank lines have multiple functions, such as ensuring the reset of the drive circuit, to ensure the normal operation of the display system. For example, in a 1920×1080 resolution, the vertical blanking lines are 45, so V_total = 1080 + 45 = 1125. If the display panel has a refresh rate of 60Hz, a resolution of 1920×1080, and 45 vertical blanking lines, then 1H is approximately 1 / 60 / 1125 = 14.81μs, meaning the time required to complete the scanning drive of one line of pixel circuitry is 14.81μs. This embodiment does not specifically limit the line time; in actual implementation, it can be calculated based on the actual display panel settings.

[0054] It should be noted that in the above description of this embodiment and the description of the subsequent embodiments, the cutoff time of the effective pulse of the first type of clock signal CK-1 and the cutoff time of the effective pulse of the second type of clock signal CK-2 do not coincide. This can be understood as follows: when an effective pulse of the first type of clock signal CK-1 and an effective pulse of the second type of clock signal CK-2 are adjacent or partially overlapped in time within a row time, the two effective pulses are compared, and the cutoff time of the effective pulse of the first type of clock signal CK-1 and the cutoff time of the effective pulse of the second type of clock signal CK-2 do not coincide.

[0055] Optional, such as Figures 1-2 , Figure 5 As shown, in this embodiment, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is (e.g.) Figure 5 t1 in the middle is later than the cutoff time of the effective pulse of the second type clock signal CK-2 (e.g., Figure 5 (t2 in the text).

[0056] This embodiment explains that the first driving circuit 00-1 receives the first type of clock signal CK-1 and generates the first scan signal scan1. The first scan signal scan1 is transmitted to the control terminal of the data writing module 101 in the pixel circuit 10. That is, the first scan signal scan1 controls the data writing module 101 to be turned on and off. During the process of the pixel circuit 10 controlling the light-emitting element 20 to emit light, the time period during which the data voltage signal is written to the pixel circuit 10 through the data line is generally after the reset and before the light-emitting element 20 emits light. That is, the last working period before the light-emitting element 20 emits light is when the first scan signal scan1 controls the data writing module 101 to be turned on, so that the data voltage signal is written. Therefore, in this embodiment, the cutoff time of the effective pulse of the first type of clock signal CK-1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2. That is, the effective pulse time of the first scan signal scan1 generated by the first driving circuit 00-1 after receiving the first type of clock signal CK-1 is also later than the effective pulse time of the second scan signal scan2 generated by the second driving circuit 00-2 after receiving the second type of clock signal CK-2. So when the first scan signal scan1 controls the data writing module 101 to be turned on, it is only controlled by the first scan signal scan1. The second scan signal scan2 has ended the control of the first module 102 before the data voltage signal transmission is completed. This can effectively avoid other interference signals from interfering with the process of writing the data voltage signal to the data writing module 101, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0057] In some alternative embodiments, please refer to the references. Figures 1-2 , Figure 6 , Figure 6 This is another timing diagram of the first type of clock signal and the second type of clock signal provided in this disclosure embodiment. In this embodiment, the start time of the effective pulse of the first type of clock signal CK-1 (e.g.) Figure 6 The start time of the effective pulse of the second type of clock signal CK-2 (e.g., t3 in the middle) and t3 in the middle) Figure 6 The t4 in the middle does not overlap.

[0058] This embodiment explains that when the driving circuit 00 of the display panel 000 includes a first driving circuit 00-1 and a second driving circuit 00-2, the first driving circuit 00-1 and the second driving circuit 00-2 receive clock signals whose effective levels do not completely overlap in duration. These signals are used to generate their respective scan control signals to different modules in the pixel circuit 10. For example, when the first driving circuit 00-1 receives a first type of clock signal CK-1 to generate a first scan signal scan1, and the second driving circuit 00-2 receives a second type of clock signal CK-2 to generate a second scan signal scan2, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is set (e.g., ...). Figure 6 t1 in the middle is later than the cutoff time of the effective pulse of the second type clock signal CK-2 (e.g., Figure 6 (t2 in the text), and the start time of the effective pulse of the first type of clock signal CK-1 (e.g., t2 ... in the text). Figure 6 The start time of the effective pulse of the second type of clock signal CK-2 (e.g., t3 in the middle) and t3 in the middle) Figure 6 The t4 in the first type of clock signal CK-1 does not overlap, meaning that the start time of the effective pulse of the first type of clock signal CK-1 avoids the start time of the effective pulse of the second type of clock signal CK-2. Therefore, the first drive circuit 00-1 starts outputting the first scan signal scan1 and the second drive circuit 00-2 starts outputting the second scan signal scan2, which can further avoid mutual interference. This can effectively stagger the time periods of the effective pulses of the first scan signal scan1 and the second scan signal scan2, thus improving the display effect.

[0059] Optional, such as Figure 1 , Figure 2 and Figure 6 As shown, this embodiment sets the start time of the effective pulse of the first type of clock signal CK-1 (e.g., Figure 6 t3 in the example is later than the start time of the effective pulse of the second type clock signal CK-2 (e.g., t3). Figure 6 In t4), due to the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) (e.g. Figure 6If t1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2, then setting the start time of the effective pulse of the first type of clock signal CK-1 to be later than the start time of the effective pulse of the second type of clock signal CK-2 can make the duration of the effective pulse of the first type of clock signal CK-1 as similar as possible to the duration of the effective pulse of the second type of clock signal CK-2. That is, although the start time and end time of conduction of the transistor receiving the first type of clock signal CK-1 and the transistor receiving the second type of clock signal CK-2 in different first driving circuits 00-1 and second driving circuits 00-2 are staggered, the conduction duration is as consistent as possible, which can effectively improve the stability of the first driving circuit 00-1 and the second driving circuit 00-2.

[0060] In some alternative embodiments, please refer to the references. Figure 1 , Figure 5 and Figure 7 , Figure 7 yes Figure 1 Another connection structure diagram of the pixel circuit. In this embodiment, the pixel circuit 10 includes an amplitude adjustment circuit 10-PAM and a pulse width adjustment circuit 10-PWM that are electrically connected. The amplitude adjustment circuit 10-PAM receives the amplitude data voltage PAM-data and controls the amplitude of the driving current of the pixel circuit 10 driving the light-emitting element 20; the pulse width adjustment circuit 10-PWM receives the pulse width data voltage PWM-data and controls the pulse width of the driving current of the pixel circuit 10 driving the light-emitting element 20; where the pulse width of the driving current is understood as the duration of the driving current, and the amplitude of the driving current is understood as the magnitude of the driving current value.

[0061] The data writing module 101 includes an amplitude data writing module 101-PAM and / or a pulse width data writing module 101-PWM. The amplitude adjustment circuit 10-PAM includes an amplitude data writing module 101-PAM, and the pulse width adjustment circuit 10-PWM includes a pulse width data writing module 101-PWM. The control terminal of the amplitude data writing module 101-PAM is electrically connected to the first sub-scan signal PAM-S2, and the control terminal of the pulse width data writing module 101-PWM is electrically connected to the second sub-scan signal PWM-S2.

[0062] This embodiment explains that in the display panel 000, the pixel circuit 10 includes an amplitude adjustment circuit 10-PAM and a pulse width adjustment circuit 10-PWM electrically connected. That is, the pixel circuit 10 can control the light-emitting element 20 to emit light based on a hybrid method of PWM (Pulse Width Modulation) driving combined with PAM (Pulse Amplitude Modulation) driving. In this embodiment, the data writing module 101 includes an amplitude data writing module 101-PAM and / or a pulse width data writing module 101-PWM. The amplitude adjustment circuit 10-PAM includes the amplitude data writing module 101-PAM. The control terminal of the amplitude data writing module 101-PAM receives a first sub-scan signal PAM-S2. When the first sub-scan signal PAM-S2 controls the amplitude data writing module 101-PAM to be turned on, the amplitude data voltage PAM-data is written into the amplitude data writing module 101-PAM. The amplitude data writing module 101-PAM controls the amplitude of the driving current based on the applied amplitude data voltage PAM-data. The pulse width adjustment circuit 10-PWM includes a pulse width data writing module 101-PWM. The control terminal of the pulse width data writing module 101-PWM receives the second sub-scan signal PWM-S2. When the second sub-scan signal PWM-S2 controls the pulse width data writing module 101-PWM to be turned on, the pulse width data voltage PWM-data is written into the pulse width data writing module 101-PWM. The pulse width data writing module 101-PWM controls the pulse width of the driving current based on the applied pulse width data voltage PWM-data, so that the brightness control of the light-emitting element 20 by the pixel circuit 10 is jointly determined by the amplitude of the driving current and the light emission duration.

[0063] In this embodiment, the pixel circuit 10 employs a hybrid approach combining PWM driving and PAM driving. Under the control of the amplitude adjustment circuit 10-PAM and the pulse width adjustment circuit 10-PWM, the pixel circuit 10 generates a driving current, which is then supplied to the light-emitting element 20. The amplitude adjustment circuit 10-PAM controls the amplitude of the driving current, while the pulse width adjustment circuit 10-PWM adjusts the pulse width of the driving current applied to the light-emitting element 20. Specifically, the pulse width adjustment circuit 10-PWM adjusts the pulse width of the voltage applied to the light-emitting element 20, i.e., it adjusts the actual emission period of the driving current applied to the light-emitting element 20. Simultaneously, it can maintain the driving current applied to the light-emitting element 20 at a constant level to adjust the grayscale or brightness displayed by the light-emitting element 20, rather than adjusting the magnitude of the driving current applied to the light-emitting element 20. Therefore, the amplitude adjustment circuit 10-PAM in this embodiment can provide a certain driving current to the light-emitting element 20 so that the light-emitting element 20 is driven with optimal luminous efficiency. Furthermore, the pulse width adjustment circuit 10-PWM adjusts the emission duty cycle (i.e., the emission period of the light-emitting element 20) of the light-emitting element 20 to adjust the overall grayscale or brightness of the light-emitting element 20. The pixel circuit 10 structure provided in this embodiment, with its amplitude adjustment circuit 10-PAM providing more stable and precise brightness control, can be used to better present details and avoid problems such as uneven brightness or color distortion. The pulse width adjustment circuit 10-PWM can improve the problem of image distortion caused by drastic changes in emission time and driving current when displaying at low grayscale levels. Therefore, the pixel circuit 10 in this embodiment includes a structure with electrically connected amplitude adjustment circuit 10-PAM and pulse width adjustment circuit 10-PWM, which can effectively improve the driving effect of the pixel circuit 10 on the light-emitting element 20 and enhance display quality.

[0064] Optional, such as Figure 7 As shown, in the pixel circuit 10 of this embodiment, the amplitude adjustment circuit 10-PAM may include an amplitude driving module 103-PAM and an amplitude reset module 102-PAM, and the pulse width adjustment circuit 10-PWM may include a pulse width driving module 103-PWM and a pulse width reset module 102-PWM. The driving module 103 of the pixel circuit 10 includes an amplitude driving module 103-PAM and a pulse width driving module 103-PWM. The first module 102 of the pixel circuit 10 may include an amplitude reset module 102-PAM and a pulse width reset module 102-PWM. The control terminal of the amplitude driving module 103-PAM is electrically connected to the amplitude reset module 102-PAM. Under the control of the scanning signal (PAM-S1) received by the control terminal of the amplitude reset module 102-PAM, the amplitude reset module 102-PAM turns on to receive the amplitude reset signal PAM-REF to initialize and reset the control terminal of the amplitude driving module 103-PAM.

[0065] The control terminal of the pulse width drive module 103-PWM is electrically connected to the pulse width reset module 102-PWM. Under the control of the scan signal (PWM-S1) received by the control terminal of the pulse width reset module 102-PWM, the pulse width reset module 102-PWM turns on to receive the pulse width reset signal PWM-REF to initialize and reset the control terminal of the pulse width drive module 103-PWM.

[0066] In some alternative embodiments, the first scan signal scan1 generated by the first driving circuit 00-1 in this embodiment includes a first sub-scan signal PAM-S2 and / or a second sub-scan signal PWM-S2.

[0067] In this embodiment, the control terminal of the amplitude data writing module 101-PAM is electrically connected to the first sub-scan signal PAM-S2, and the control terminal of the pulse width data writing module 101-PWM is electrically connected to the second sub-scan signal PWM-S2. The first sub-scan signal PAM-S2 and the second sub-scan signal PWM-S2 can be understood as scan control signals generated and output by the drive circuit 00, which are used to control the conduction and shutdown of the amplitude data writing module 101-PAM and the pulse width data writing module 101-PWM in the pixel circuit 10.

[0068] Among them, such as Figure 1 , Figure 5 and Figure 8 As shown, Figure 8 yes Figure 1 Another connection structure diagram of the mid-pixel circuit: the first driving circuit 00-1 receives the first type of clock signal CK-1 and generates the first scan signal scan1, which may include the first sub-scan signal PAM-S2.

[0069] This embodiment explains that, in certain modes, the display panel 000 can set the pulse width data voltage PWM-data received by the pulse width data writing module 101-PWM of each pixel circuit 10 to a fixed value. In this case, the amplitude of the driving current is controlled by adjusting the amplitude data voltage PAM-data received by the amplitude adjustment circuit 10-PAM, thereby controlling the brightness of the light-emitting element 20. In the above mode, the last working period before the light-emitting element 20 emits light is when the first sub-scan signal PAM-S2 controls the conduction of the amplitude data writing module 101-PAM, so that the amplitude data voltage PAM-data is written to the pixel circuit 10, thereby adjusting the magnitude of the driving current and realizing the brightness control of the light-emitting element 20. Therefore, in this embodiment, the first drive circuit 00-1 receives the first type of clock signal CK-1 and generates the first scan signal scan1, which may include the first sub-scan signal PAM-S2. If the cutoff time of the effective pulse of the first type of clock signal CK-1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2, that is, the effective pulse time of the first sub-scan signal PAM-S2 generated by the first drive circuit 00-1 after receiving the first type of clock signal CK-1 is later than the second scan signal scan2 generated by the second drive circuit 00-2 after receiving the second type of clock signal CK-2 (at this time, if...) Figure 8 As shown, the data writing module 101 can be understood as including the amplitude data writing module 101-PAM, and the first module 102 can be understood as including the pulse width data writing module 101-PWM, the amplitude reset module 102-PAM, and the pulse width reset module 102-PWM. The second scan signal scan2 can be the second sub-scan signal PWM-S2, or it can be the scan signal received by the control terminal of the amplitude reset module 102-PAM (such as PAM-S1), or it can be the effective pulse moment of the scan signal received by the control terminal of the pulse width reset module 102-PWM (such as PWM-S1). When the PAM-S2 control is turned on, the amplitude data writing module 101-PAM is only controlled by the first sub-scan signal PAM-S2. Other signals, such as the second scan signal scan2, have already ended the control of other modules of the pixel circuit 10, such as the first module 102 or the pulse width data writing module 101-PWM, before the amplitude data voltage PAM-data is transmitted. This can effectively avoid other interference signals from interfering with the process of writing the amplitude data voltage PAM-data to the amplitude data writing module 101-PAM, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0070] Or, such as Figure 1 , Figure 5 and Figure 9 As shown, Figure 9 yes Figure 1Another connection structure diagram of the middle pixel circuit: the first driving circuit 00-1 receives the first type of clock signal CK-1 and generates the first scan signal scan1, which may include the second sub-scan signal PWM-S2.

[0071] This embodiment explains that, in certain modes, the display panel 000 can set the amplitude data voltage PAM-data received by the amplitude data writing module 101-PAM of each pixel circuit 10 to be equal to a fixed value. In this case, the actual emission period applied to the light-emitting element 20 is controlled only by adjusting the pulse width data voltage PWM-data received by the pulse width adjustment circuit 10-PWM, thereby controlling the pulse width of the driving current and adjusting the brightness of the light-emitting element 20. In the above mode, the last working period before the light-emitting element 20 emits light is controlled by the second sub-scan signal PWM-S2, which controls the conduction of the pulse width data writing module 101-PWM, causing the pulse width data voltage PWM-data to be written to the pixel circuit 10, thereby adjusting the pulse width of the driving current and achieving brightness control of the light-emitting element 20. Therefore, in this embodiment, the first scan signal scan1 generated by the first driving circuit 00-1 receiving the first type of clock signal CK-1 may include a second sub-scan signal PWM-S2. If the cutoff time of the effective pulse of the first type of clock signal CK-1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2, that is, the effective pulse time of the second sub-scan signal PWM-S2 generated by the first driving circuit 00-1 after receiving the first type of clock signal CK-1 is later than the second scan signal scan2 generated by the second driving circuit 00-2 after receiving the second type of clock signal CK-2 (at this time, if...) Figure 9As shown, the data writing module 101 can be understood as including the pulse width data writing module 101-PWM, and the first module 102 can be understood as including the amplitude data writing module 101-PAM, the amplitude reset module 102-PAM, and the pulse width reset module 102-PWM. The second scan signal scan2 can be the first sub-scan signal PAM-S2, or it can be the scan signal received by the control terminal of the amplitude reset module 102-PAM (such as PAM-S1), or it can be the effective pulse moment of the scan signal received by the control terminal of the pulse width reset module 102-PWM (such as PWM-S1). Therefore, in the second sub-scan signal... When the PWM-S2 control pulse width data writing module 101-PWM is turned on, it is only controlled by the second sub-scan signal PWM-S2. Other signals, such as the second scan signal scan2, have already ended the control of other modules of the pixel circuit 10, such as the first module 102 or the amplitude data writing module 101-PAM, before the transmission of the pulse width data voltage PWM-data is completed. This can effectively avoid other interference signals from interfering with the process of writing the pulse width data voltage PWM-data to the pulse width data writing module 101-PWM, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0072] Or, such as Figure 1 , Figure 5 and Figure 10 As shown, Figure 10 yes Figure 1 Another connection structure diagram of the middle pixel circuit: the first driving circuit 00-1 receives the first type of clock signal CK-1 and generates the first scan signal scan1, which includes the first sub-scan signal PAM-S2 and the second sub-scan signal PWM-S2.

[0073] This embodiment explains that when the pixel circuit 10 in the display panel 000 includes an amplitude adjustment circuit 10-PAM and a pulse width adjustment circuit 10-PWM, and the drive current is jointly controlled by the amplitude adjustment circuit 10-PAM and the pulse width adjustment circuit 10-PWM, the last working period before the light-emitting element 20 emits light is when the first sub-scan signal PAM-S2 controls the conduction of the amplitude data writing module 101-PAM and the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, so that the amplitude data voltage PAM-data is written into the pixel circuit 10, adjusting the magnitude of the drive current, and the pulse width data voltage PWM-data is written into the pixel circuit 10, adjusting the pulse width of the drive current, thereby realizing the control of the light emission brightness of the light-emitting element 20. Therefore, in this embodiment, the first drive circuit 00-1 receives the first type of clock signal CK-1 and generates the first scan signal scan1, which may include a first sub-scan signal PAM-S2 and a second sub-scan signal PWM-S2. If the cutoff time of the effective pulse of the first type of clock signal CK-1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2, that is, the effective pulse times of the first sub-scan signal PAM-S2 and the second sub-scan signal PWM-S2 generated by the first drive circuit 00-1 after receiving the first type of clock signal CK-1 are both later than the second scan signal scan2 generated by the second drive circuit 00-2 after receiving the second type of clock signal CK-2 (at this time, if...). Figure 10As shown, the data writing module 101 can be understood as including the amplitude data writing module 101-PAM and the pulse width data writing module 101-PWM. The first module 102 can be understood as including the amplitude reset module 102-PAM and the pulse width reset module 102-PWM. The second scan signal scan2 can be a scan signal received by the control terminal of the amplitude reset module 102-PAM (such as PAM-S1) or a scan signal received by the control terminal of the pulse width reset module 102-PWM (such as PWM-S1). At the effective pulse moment, the first sub-scan signal PAM-S2 controls the conduction of the amplitude data writing module 101-PAM, and the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PAM. When the PWM is turned on, it is only controlled by the first sub-scan signal PAM-S2 and the second sub-scan signal PWM-S2, that is, it is only controlled by the first scan signal scan1 generated by the first type of clock signal CK-1. Other signals, such as the second scan signal scan2, have ended their control over other modules of the pixel circuit 10, such as the first module 102, before the transmission of amplitude data voltage PAM-data and pulse width data voltage PWM-data is completed. This can effectively avoid other interference signals from interfering with the process of writing amplitude data voltage PAM-data and pulse width data voltage PWM-data to the data writing module 101, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0074] In some alternative embodiments, please refer to the references. Figure 5 , Figure 9 and Figure 11 , Figure 11 This is a schematic diagram of another planar structure of the display panel provided in this embodiment. In this embodiment, the first driving circuit 00-1 includes multiple cascaded first shift registers SR-1, and the second driving circuit 00-2 includes multiple cascaded second shift registers SR-2. The output of the first shift register SR-1 is electrically connected to the control terminal of the pulse width data writing module 101-PWM, and the output of the second shift register SR-2 is electrically connected to the control terminal of the amplitude data writing module 101-PAM. The second shift register SR-2 receives the first clock signal PAM-S2-CK and outputs the first sub-scan signal PAM-S2; the first shift register SR-1 receives the second clock signal PWM-S2-CK and outputs the second sub-scan signal PWM-S2. The first type of clock signal CK-1 includes the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 includes the first clock signal PAM-S2-CK.

[0075] This embodiment explains that the driving circuit 00 of the display panel 000 includes a first driving circuit 00-1 and a second driving circuit 00-2. That is, the display panel 000 may include at least two sets of driving circuits, which are respectively named the first driving circuit 00-1 and the second driving circuit 00-2. The pixel circuit 10 includes an amplitude adjustment circuit 10-PAM and a pulse width adjustment circuit 10-PWM. The amplitude adjustment circuit 10-PAM includes an amplitude data writing module 101-PAM, and the pulse width adjustment circuit 10-PWM includes a pulse width data writing module 101-PWM. Therefore, the data writing module 101 can be understood as including the pulse width data writing module 101-PWM. The first module 102 can be understood as including at least the amplitude data writing module 101-PAM. The first module 102 may also include other modules of the pixel circuit 10. The first driving circuit 00-1 can be used to generate a scan control signal that controls the pulse width data writing module 101-PWM to turn on or off. That is, the first scan signal scan1 generated by the first driving circuit 00-1 can be the second sub-scan signal PWM-S2. The second driving circuit 00-2 can be used to generate a scan control signal that controls the amplitude data writing module 101-PAM to turn on or off. That is, the second scan signal scan2 generated by the second driving circuit 00-2 can be the first sub-scan signal PAM-S2.

[0076] Optionally, the first driving circuit 00-1 includes multiple cascaded first shift registers SR-1. The output of the first shift register SR-1 can be electrically connected to the control terminal of the pulse width data writing module 101-PWM in the pixel circuit 10 via the first scan line. The first shift register SR-1 receives the second clock signal PWM-S2-CK and outputs the second sub-scan signal PWM-S2. The second driving circuit 00-2 includes multiple cascaded second shift registers SR-2. The output of the second shift register SR-2 can be electrically connected to the control terminal of the amplitude data writing module 101-PAM in the pixel circuit 10 via the second scan line. The second shift register SR-2 receives the first clock signal PAM-S2-CK and outputs the first sub-scan signal PAM-S2. At this time, if the last working period before the light-emitting element 20 emits light is controlled by the second sub-scan signal PWM-S2 to turn on the pulse width data writing module 101-PWM, the pulse width data voltage PWM-data is written into the pixel circuit 10, thereby adjusting the pulse width of the driving current and realizing the brightness control of the light-emitting element 20. Therefore, in this embodiment, the first type of clock signal CK-1 needs to include the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 needs to include the first clock signal PAM-S2-CK. This ensures that the cutoff time of the effective pulse of the first type of clock signal CK-1 (i.e., the second clock signal PWM-S2-CK) is later than the cutoff time of the effective pulse of the second type of clock signal (i.e., the first clock signal PAM-S2-CK). Specifically, the effective pulse time of the second sub-scan signal PWM-S2 generated by the first shift register SR-1 of the first driving circuit 00-1 after receiving the second clock signal PWM-S2-CK is later than the effective pulse time of the second shift register SR-2 of the second driving circuit 00-2 after receiving the first clock signal PWM-S2-CK. When the effective pulse of the first sub-scan signal PAM-S2 generated after signal PAM-S2-CK is activated, the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM. The second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM. Other signals, such as the first sub-scan signal PAM-S2, have already finished controlling the amplitude data writing module 101-PAM before completing the transmission of the pulse width data voltage PWM-data. This effectively avoids interference from other signals in the process of writing the pulse width data voltage PWM-data to the pulse width data writing module 101-PWM, thereby reducing brightness variation, reducing display mura, and improving display performance.

[0077] In some alternative embodiments, please refer to the references. Figure 5 , Figure 9 and Figure 12 , Figure 12This is a schematic diagram of another planar structure of the display panel provided in this embodiment. In this embodiment, the pixel circuit 10 includes an amplitude adjustment circuit 10-PAM and a pulse width adjustment circuit 10-PWM that are electrically connected. The amplitude adjustment circuit 10-PAM receives the amplitude data voltage PAM-data and controls the amplitude of the driving current of the pixel circuit 10 driving the light-emitting element 20; the pulse width adjustment circuit 10-PWM receives the pulse width data voltage PWM-data and controls the pulse width of the driving current of the pixel circuit 10 driving the light-emitting element 20; where the pulse width of the driving current is understood as the duration of the driving current, and the amplitude of the driving current is understood as the magnitude of the driving current value.

[0078] The amplitude adjustment circuit 10-PAM includes an amplitude data writing module 101-PAM, and the control terminal of the amplitude data writing module 101-PAM is electrically connected to the first sub-scan signal PAM-S2. The pulse width adjustment circuit 10-PWM includes a pulse width data writing module 101-PWM, and the control terminal of the pulse width data writing module 101-PWM is electrically connected to the second sub-scan signal PWM-S2.

[0079] The amplitude adjustment circuit 10-PAM also includes an amplitude driving module 103-PAM and an amplitude reset module 102-PAM. The first terminal of the amplitude reset module 102-PAM is electrically connected to the amplitude reset voltage PAM-REF, the second terminal of the amplitude reset module 102-PAM is electrically connected to the control terminal of the amplitude driving module 103-PAM, and the control terminal of the amplitude reset module 102-PAM is electrically connected to the third sub-scan signal PAM-S1. The amplitude reset module 102-PAM is used to receive the amplitude reset voltage PAM-REF during the reset phase to initialize the control terminal of the amplitude driving module 103-PAM. The pulse width modulation circuit 10-PWM also includes a pulse width driving module 103-PWM and a pulse width reset module 102-PWM. The first terminal of the pulse width reset module 102-PWM is electrically connected to the pulse width reset voltage PWM-REF, and the second terminal of the pulse width reset module 102-PWM is electrically connected to the control terminal of the pulse width driving module 103-PWM. The control terminal of the pulse width reset module 102-PWM is electrically connected to the fourth sub-scan signal PWM-S1. The pulse width reset module 102-PWM is used to receive the pulse width reset voltage PWM-REF during the reset phase and initialize the control terminal of the pulse width driving module 103-PWM.

[0080] At this time, the data writing module 101 mentioned in the above embodiment can be understood as including the pulse width data writing module 101-PWM, the first module 102 can be understood as including the amplitude data writing module 101-PAM, the amplitude reset module 102-PAM, and the pulse width reset module 102-PWM. The first scan signal scan1 can include the second sub-scan signal PWM-S2, and the second scan signal scan2 can include the first sub-scan signal PAM-S2 received by the control terminal of the amplitude data writing module 101-PAM, the third sub-scan signal PAM-S1 received by the control terminal of the amplitude reset module 102-PAM, and the fourth sub-scan signal PWM-S1 received by the control terminal of the pulse width reset module 102-PWM.

[0081] Optionally, in the driving circuit 00 included in the display panel 000, the first driving circuit 00-1 includes multiple cascaded first shift registers SR-1, the second driving circuit 00-2 includes a first sub-driving circuit 00-21, a second sub-driving circuit 00-22, and a third sub-driving circuit 00-23, the first sub-driving circuit 00-21 includes multiple cascaded second shift registers SR-2, the second sub-driving circuit 00-22 includes multiple cascaded third shift registers SR-3, and the third sub-driving circuit 00-23 includes multiple cascaded fourth shift registers SR-4; The output of the first shift register SR-1 is electrically connected to the control terminal of the pulse width data writing module 101-PWM; the output of the second shift register SR-2 is electrically connected to the control terminal of the amplitude data writing module 101-PAM; the output of the third shift register SR-3 is electrically connected to the control terminal of the amplitude reset module 102-PAM; and the output of the fourth shift register SR-4 is electrically connected to the control terminal of the pulse width reset module 102-PWM. The second shift register SR-2 receives the first clock signal PAM-S2-CK and outputs the first sub-scan signal PAM-S2; The first shift register SR-1 receives the second clock signal PWM-S2-CK and outputs the second sub-scan signal PWM-S2; The third shift register SR-3 receives the third clock signal PAM-S1-CK and outputs the third sub-scan signal PAM-S1; The fourth shift register SR-4 receives the fourth clock signal PWM-S1-CK and outputs the fourth sub-scan signal PWM-S1; The first type of clock signal CK-1 includes the second clock signal PWM-S2-CK; The second type of clock signal CK-2 includes the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK.

[0082] This embodiment explains that the driving circuit 00 of the display panel 000 includes a first driving circuit 00-1 and a second driving circuit 00-2. The second driving circuit 00-2 includes a first sub-driving circuit 00-21, a second sub-driving circuit 00-22, and a third sub-driving circuit 00-23. That is, the display panel 000 can include at least four sets of driving circuits, which are respectively named the first driving circuit 00-1, the first sub-driving circuit 00-21, the second sub-driving circuit 00-22, and the third sub-driving circuit 00-23. Pixel circuit 10 The system includes an amplitude adjustment circuit 10-PAM and a pulse width adjustment circuit 10-PWM. The amplitude adjustment circuit 10-PAM includes an amplitude data writing module 101-PAM, and the pulse width adjustment circuit 10-PWM includes a pulse width data writing module 101-PWM. Therefore, the data writing module 101 can be understood as including the pulse width data writing module 101-PWM. The first module 102 can be understood as including at least the amplitude data writing module 101-PAM, the amplitude reset module 102-PAM, and the pulse width reset module 102-PWM.

[0083] The first driving circuit 00-1 can be used to generate a scan control signal that controls the pulse width data writing module 101-PWM to turn on or off. That is, the first scan signal scan1 generated by the first driving circuit 00-1 can be the second sub-scan signal PWM-S2. The first sub-driving circuit 00-21 can be used to generate a scanning control signal to control the amplitude data writing module 101-PAM to turn on or off. That is, the second scanning signal scan2 generated by the first sub-driving circuit 00-21 can be the first sub-scan signal PAM-S2. The second sub-driving circuit 00-22 can be used to generate a scanning control signal that controls the amplitude reset module 102-PAM to turn on or off. That is, the second scanning signal scan2 generated by the second sub-driving circuit 00-22 can be the third sub-scan signal PAM-S1. The third sub-drive circuit 00-23 can be used to generate a scan control signal that controls the pulse width reset module 102-PWM to turn on or off. That is, the second scan signal scan2 generated by the third sub-drive circuit 00-23 can be the fourth sub-scan signal PWM-S1. Optional, such as Figure 5 , Figure 9 , Figure 12 and Figure 13 As shown, Figure 13 yes Figure 9 and Figure 12A simplified schematic diagram of the electrical connection between the driving circuit and the pixel circuit. The first driving circuit 00-1 includes multiple cascaded first shift registers SR-1. The output terminal of the first shift register SR-1 can be electrically connected to the control terminal of the pulse width data writing module 101-PWM in the pixel circuit 10 through the first scan line. The first shift register SR-1 receives the second clock signal PWM-S2-CK and outputs the second sub-scan signal PWM-S2. The first sub-driving circuit 00-21 includes multiple cascaded second shift registers SR-2. The output of the second shift register SR-2 can be electrically connected to the control terminal of the amplitude data writing module 101-PAM of the pixel circuit 10 through the second scan line. The second shift register SR-2 receives the first clock signal PAM-S2-CK and outputs the first sub-scan signal PAM-S2. The second sub-driving circuit 00-22 includes multiple cascaded third shift registers SR-3. The output of the third shift register SR-3 can be electrically connected to the control terminal of the amplitude reset module 102-PAM of the pixel circuit 10 through the third scan line. The third shift register SR-3 receives the third clock signal PAM-S1-CK and outputs the third sub-scan signal PAM-S1. The third sub-driving circuit 00-23 includes multiple cascaded fourth shift registers SR-4. The output of the fourth shift register SR-4 can be electrically connected to the control terminal of the pulse width reset module 102-PWM of the pixel circuit 10 through the fourth scan line. The fourth shift register SR-4 receives the fourth clock signal PWM-S1-CK and outputs the fourth sub-scan signal PWM-S1.

[0084] If the last working period before the light-emitting element 20 emits light is the second sub-scan signal PWM-S2 controlling the conduction of the pulse width data writing module 101-PWM, then the pulse width data voltage PWM-data is written into the pixel circuit 10, thereby adjusting the pulse width of the driving current and realizing the control of the light-emitting brightness of the light-emitting element 20. Therefore, in this embodiment, the first type of clock signal CK-1 needs to include the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 needs to include the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK. This ensures that the cutoff time of the effective pulse of the first type of clock signal CK-1 (i.e., the second clock signal PWM-S2-CK) is later than the cutoff time of the effective pulses of all clock signals included in the second type of clock signal CK-2 (i.e., the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK). Specifically, the effective pulse time of the second sub-scan signal PWM-S2 generated by the first shift register SR-1 of the first driving circuit 00-1 after receiving the second clock signal PWM-S2-CK is later than the effective pulse time of the first sub-scan signal PAM-S2 generated by the second shift register SR-2 of the first sub-driving circuit 00-21 after receiving the first clock signal PAM-S2-CK. The effective pulse time of the third sub-scan signal PAM-S1 generated by the third shift register SR-3 of the second sub-drive circuit 00-22 after receiving the third clock signal PAM-S1-CK is later than the effective pulse time of the fourth sub-scan signal PWM-S1 generated by the fourth shift register SR-4 of the third sub-drive circuit 00-23 after receiving the fourth clock signal PWM-S1-CK. Therefore, when the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, it is only controlled by the second sub-scan signal PWM-S2. Other signals such as the first sub-scan signal PAM-S2, the third sub-scan signal PAM-S1, and the fourth sub-scan signal PWM-S1 have finished controlling the various modules of the pixel circuit 10 before completing the transmission of the pulse width data voltage PWM-data. This can effectively avoid other interference signals from interfering with the process of writing the pulse width data voltage PWM-data to the pulse width data writing module 101-PWM, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0085] In some alternative embodiments, please refer to the references. Figure 9 , Figure 12 , Figure 13 and Figure 14 , Figure 15 , Figure 14 yes Figure 12A timing diagram illustrating the first and second type of clock signals received by the driving circuit. Figure 15 yes Figure 12 The driving circuit in the middle adopts Figure 14 The timing diagram of the scan signal generated by the clock signal timing sequence; in this embodiment, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, and the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK.

[0086] This embodiment explains that when the first type of clock signal CK-1 includes the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 includes the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is later than the cutoff time of the effective pulses of all the clock signals included in the second type of clock signal CK-2, the design of each clock signal can be further refined. Specifically, if the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, then the first shift of the first drive circuit 00-1... The effective pulse time of the second sub-scan signal PWM-S2 generated by the bit register SR-1 after receiving the second clock signal PWM-S2-CK is later than the effective pulse time of the fourth sub-scan signal PWM-S1 generated by the fourth shift register SR-4 after receiving the fourth clock signal PWM-S1-CK. This means that the time when the pulse width data voltage PWM-data is written to the pulse width data writing module 101-PWM is later than the time when the pulse width reset voltage PWM-REF is written to the pulse width reset module 102-PWM. When the pulse width adjustment circuit 10-PWM included in the pixel circuit 10 is driving, the reset operation of the control terminal of the pulse width driving module 103-PWM is performed before the pulse width data voltage PWM-data is written.

[0087] The cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK. Therefore, the effective pulse time of the fourth sub-scan signal PWM-S1 generated by the fourth shift register SR-4 of the third sub-drive circuit 00-23 after receiving the fourth clock signal PWM-S1-CK is completely different from the effective pulse time of the first sub-scan signal PAM-S2 generated by the second shift register SR-2 of the first sub-drive circuit 00-21 after receiving the first clock signal PAM-S2-CK. It is understandable that, in the pixel circuit 10, whether the pulse width adjustment circuit 10-PWM or the amplitude adjustment circuit 10-PAM is driving, the reset phase occurs before the data writing phase. Figure 15 The effective pulse time of the first sub-scan signal PAM-S2 is completely different from the effective pulse time of the fourth sub-scan signal PWM-S1. However, the effective pulse time of the fourth sub-scan signal PWM-S1 (when the pulse width reset module 102-PWM writes the pulse width reset signal PWM-REF to perform a reset) is earlier than the effective pulse time of the first sub-scan signal PAM-S2 (when the amplitude data writing module 101-PAM writes the amplitude data voltage PAM-data).

[0088] The cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. Therefore, the effective pulse time of the first sub-scan signal PAM-S2 generated by the second shift register SR-2 of the first sub-driving circuit 00-21 after receiving the first clock signal PAM-S2-CK is later than the effective pulse time of the third sub-scan signal PAM-S1 generated by the third shift register SR-3 of the second sub-driving circuit 00-22 after receiving the third clock signal PAM-S1-CK. As a result, the time when the amplitude data voltage PAM-data is written to the amplitude data writing module 101-PAM is later than the time when the amplitude reset voltage PAM-REF is written to the amplitude reset module 102-PAM. When the amplitude adjustment circuit 10-PAM included in the pixel circuit 10 is driving, the reset operation of the control terminal of the amplitude driving module 103-PAM is performed before the amplitude data voltage PAM-data is written.

[0089] Optional, such as Figure 9 , Figure 12 , Figures 13-15 As shown, in this embodiment, the start time of the effective pulse of the second clock signal PWM-S2-CK coincides with the start time of the effective pulse of the fourth clock signal PWM-S1-CK, and the start time of the effective pulse of the first clock signal PAM-S2-CK coincides with the start time of the effective pulse of the third clock signal PAM-S1-CK. The start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK.

[0090] In this embodiment, the start time of the effective pulse of the second clock signal PWM-S2-CK coincides with the start time of the effective pulse of the fourth clock signal PWM-S1-CK. The start times of the second clock signal PWM-S2-CK and the fourth clock signal PWM-S1-CK also coincide. The start time of the effective pulse of the first clock signal PAM-S2-CK coincides with the start time of the effective pulse of the third clock signal PAM-S1-CK. The start times of the first clock signal PAM-S2-CK and the third clock signal PAM-S1-CK also coincide. Furthermore, the start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK. That is, the second clock signal PWM-S2-CK and the fourth clock signal PWM-S1-CK form a set of coincident start times. These clock signals are used in the first drive circuit 00-1 and the first sub-drive circuit 00-21 to generate the scanning signal used by the pulse width adjustment circuit 10-PWM. The start times of the clock signals can coincide. The first clock signal PAM-S2-CK and the third clock signal PAM-S1-CK form a set of start times that coincide. The start times of the clock signals in the second sub-driving circuit 00-22 and the third sub-driving circuit 00-23, which are used to generate the scanning signal used by the amplitude adjustment circuit 10-PAM, can also coincide. However, the two sets of start times are staggered. This can prevent the transistors in the driving circuit that generates the scanning signal used by the amplitude adjustment circuit 10-PAM and the driving circuit that generates the scanning signal used by the pulse width adjustment circuit 10-PWM from being turned on at the same time. This reduces the signal path coupling of adjacent driving circuits, allowing each driving circuit to work independently and stably. This is beneficial to ensuring the stability of the generated scanning signal waveform. Furthermore, the start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK. This can satisfy the requirement that when the pixel circuit 10 is driving, the data writing stage is executed after the reset stage.

[0091] In some alternative embodiments, please refer to the references. Figure 9 , Figure 12 , Figure 13 , Figure 16 and Figure 17 , Figure 16 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit. Figure 17 yes Figure 12 The driving circuit in the middle adopts Figure 16The timing diagram of the scan signal generated by the clock signal timing sequence; in this embodiment, the start time of the effective pulse of the second clock signal PWM-S2-CK, the start time of the effective pulse of the fourth clock signal PWM-S1-CK, the start time of the effective pulse of the first clock signal PAM-S2-CK, and the start time of the effective pulse of the third clock signal PAM-S1-CK coincide.

[0092] This embodiment explains that when the first type of clock signal CK-1 includes the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 includes the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, such that the cutoff time of the effective pulse of the first type of clock signal CK-1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2, although it can be further refined that the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, and the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK, the amplitude adjustment circuit 10-PAM and pulse width... The start times of the effective pulses of the aforementioned clock signals used by the adjustment circuit 10-PWM coincide. Since, within one row time, there is at least one instance where the cutoff time of the effective pulse of the first type of clock signal CK-1 corresponds to the start time of the effective pulse of the first scan signal scan1, and there is at least one instance where the cutoff time of the effective pulse of the second type of clock signal CK-2 corresponds to the start time of the effective pulse of the second scan signal scan2, that is, when the effective pulse of the clock signal received by the driving circuit cuts off, the scan signal generated by the driving circuit begins. In other words, when the effective pulses of each clock signal received by the driving circuit start does not play a key role in the generation of the scan signal. In order to satisfy that the first scan signal scan1 and the second scan signal scan2 have a certain out-of-order, it is only necessary to satisfy that the cutoff time of the effective pulse of the first type of clock signal CK-1 received by the first driving circuit 00-1 does not coincide with the cutoff time of the effective pulse of the second type of clock signal CK-2 received by the second driving circuit 00-2.

[0093] Therefore, in this embodiment, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, and the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. However, the start times of the effective pulses of the above clock signals coincide, which can ensure the stability of the generated scanning signal waveform and avoid mutual interference. It can also reduce the control complexity of the drive circuit, eliminating the need to design multiple sets of differentiated clock signal start-up timings for different drive circuits. This helps to reduce the difficulty of signal scheduling received by the drive circuit and reduce the risk of timing design errors. Furthermore, the start times of the effective pulses of the clock signals received by different driving circuits coincide, which allows the transistors in the driving circuit to start working synchronously, improving the working consistency of the driving circuit and preventing timing chaos caused by scattered start-up. This helps to further reduce signal coupling interference, ensure the stability of the generated scan signal waveform, and also improve the response efficiency of the driving circuit. The start times of the effective pulses of the clock signals received by different driving circuits coincide, and the transistors controlled by the clock signals can start synchronously, so that the trigger signals of each level of shift register (corresponding to receiving the above four clock signals) are transmitted synchronously, which can reduce the signal distortion caused by the inter-level delay of shift registers and adapt to high-resolution display panels.

[0094] In this embodiment, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, and the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. However, the start times of the effective pulses of the above clock signals coincide, which allows the cutoff times of the effective pulses of all the above clock signals to be completed within one row time. As a result, the scanning signal generated to control the pixel circuit only controls the pixel circuit 10 of the current row and will not affect the control of the pixel circuits of the previous row and the next row.

[0095] Optional, such as Figure 9 , Figure 12 , Figure 13 , Figure 16 and Figure 17As shown, in this embodiment, the effective pulse width of the second clock signal PWM-S2-CK is greater than the effective pulse width of the fourth clock signal PWM-S1-CK, the effective pulse width of the fourth clock signal PWM-S1-CK is greater than the effective pulse width of the first clock signal PAM-S2-CK, and the effective pulse width of the first clock signal PAM-S2-CK is greater than the effective pulse width of the third clock signal PAM-S1-CK.

[0096] The effective pulse duration of the second clock signal PWM-S2-CK covers the effective pulse duration of the fourth clock signal PWM-S1-CK, the effective pulse duration of the fourth clock signal PWM-S1-CK covers the effective pulse duration of the first clock signal PAM-S2-CK, and the effective pulse duration of the first clock signal PAM-S2-CK covers the effective pulse duration of the third clock signal PAM-S1-CK.

[0097] This embodiment explains that in order to set the cutoff time of the effective pulse of the second clock signal PWM-S2-CK to be later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK to be later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, and the cutoff time of the effective pulse of the first clock signal PAM-S2-CK to be later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK, but the start times of the effective pulses of the above clock signals coincide, it is necessary to satisfy that the effective pulse width of the second clock signal PWM-S2-CK is greater than the effective pulse width of the fourth clock signal PWM-S1-CK. The effective pulse width of the second clock signal PWM-S1-CK is greater than the effective pulse width of the first clock signal PAM-S2-CK, and the effective pulse width of the first clock signal PAM-S2-CK is greater than the effective pulse width of the third clock signal PAM-S1-CK. That is, the effective pulse duration of the second clock signal PWM-S2-CK covers the effective pulse duration of the fourth clock signal PWM-S1-CK, the effective pulse duration of the fourth clock signal PWM-S1-CK covers the effective pulse duration of the first clock signal PAM-S2-CK, and the effective pulse duration of the first clock signal PAM-S2-CK covers the effective pulse duration of the third clock signal PAM-S1-CK. Furthermore, in the display panel 000 of this embodiment, the last working period before the light-emitting element 20 emits light is when the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, so that the pulse width data voltage PWM-data is written to the pixel circuit 10, thereby adjusting the pulse width of the driving current and realizing the brightness control of the light-emitting element 20. Therefore, the effective pulse width of the second clock signal PWM-S2-CK is the largest, and the effective pulse duration of the second clock signal PWM-S2-CK is the longest, which can ensure sufficient writing time when the pulse width data voltage PWM-data is written to the pixel circuit 10, thus satisfying the reasonable control of the brightness of the light-emitting element 20.

[0098] In some alternative embodiments, please refer to the references. Figure 9 , Figure 12 , Figure 13 and Figure 18 , Figure 19 , Figure 18 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit. Figure 19 yes Figure 12 The driving circuit in the middle adopts Figure 18The timing diagram of the scan signal generated by the clock signal timing; in this embodiment, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, and the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK.

[0099] This embodiment explains that by setting the first type of clock signal CK-1 to include the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 to include the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is later than the cutoff time of the effective pulses of all the clock signals included in the second type of clock signal CK-2, the design of each clock signal can be further refined. Specifically, If the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, then the effective pulse time of the second sub-scan signal PWM-S2 generated by the first shift register SR-1 of the first drive circuit 00-1 after receiving the second clock signal PWM-S2-CK is later than the effective pulse time of the first sub-scan signal PAM-S2 generated by the second shift register SR-2 of the first sub-drive circuit 00-21 after receiving the first clock signal PAM-S2-CK. This results in the timing of writing the pulse width data voltage PWM-data to the pulse width data writing module 101-PWM being later than the timing of writing the amplitude data voltage PAM-data to the amplitude data writing module 101-PAM (e.g., ...). Figure 19 As shown), when the amplitude adjustment circuit 10-PAM and pulse width adjustment circuit 10-PWM of the pixel circuit 10 are performing data writing, the writing of the pulse width data voltage PWM-data is performed after the writing of the amplitude data voltage PAM-data. That is, the last working period before the light-emitting element 20 emits light is when the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, so that the pulse width data voltage PWM-data is written into the pixel circuit 10, thereby adjusting the pulse width of the driving current and realizing the control of the light emission brightness of the light-emitting element 20.

[0100] The cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK. The effective pulse time of the first sub-scan signal PAM-S2 generated by the second shift register SR-2 of the first sub-drive circuit 00-21 after receiving the first clock signal PAM-S2-CK is later than the effective pulse time of the fourth sub-scan signal PWM-S1 generated by the fourth shift register SR-4 of the third sub-drive circuit 00-23 after receiving the fourth clock signal PWM-S1-CK. Therefore, the effective pulse of the first sub-scan signal PAM-S2 and the effective pulse of the fourth sub-scan signal PAM-S1 are later than the effective pulse time of the fourth sub-scan signal PWM-S1 generated by the fourth shift register SR-4 of the third sub-drive circuit 00-23. The effective pulses of signal PWM-S1 are completely staggered, that is, the operation of writing amplitude data voltage PAM-data into amplitude data writing module 101-PAM is staggered from the operation of pulse width reset module 102-PWM resetting the control terminal of pulse width drive module 103-PWM. After amplitude data voltage PAM-data is written into amplitude data writing module 101-PAM, the operation of resetting the control terminal of pulse width drive module 103-PWM by pulse width reset module 102-PWM is executed, which allows the driving operation of amplitude adjustment circuit 10-PAM to be executed separately from the driving operation of pulse width adjustment circuit 10-PWM.

[0101] The cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. Therefore, the effective pulse time of the fourth sub-scan signal PWM-S1 generated by the fourth shift register SR-4 of the third sub-drive circuit 00-23 after receiving the fourth clock signal PWM-S1-CK is completely different from the effective pulse time of the third sub-scan signal PAM-S1 generated by the third shift register SR-3 of the second sub-drive circuit 00-22 after receiving the third clock signal PAM-S1-CK. Furthermore, the amplitude reset module 102-PAM affects the amplitude drive module 10. After the control terminal of 3-PAM is reset, the control terminal of the pulse width drive module 103-PWM is reset by the pulse width reset module 102-PWM. This satisfies the requirement that the drive of the amplitude adjustment circuit 10-PAM and the drive of the pulse width adjustment circuit 10-PWM be executed separately. At the same time, it also ensures that the last working period before the light-emitting element 20 emits light is controlled by the second sub-scan signal PWM-S2 to turn on the pulse width data writing module 101-PWM, so that the pulse width data voltage PWM-data is written to the pixel circuit 10, thereby adjusting the pulse width of the drive current and realizing the brightness control of the light-emitting element 20.

[0102] Optional, such as Figure 9 , Figure 12 , Figure 13 , Figure 18 and Figure 19As shown, in this embodiment, the start time of the effective pulse of the second clock signal PWM-S2-CK is earlier than the start time of the effective pulse of the first clock signal PAM-S2-CK, the start time of the effective pulse of the first clock signal PAM-S2-CK is earlier than the start time of the effective pulse of the fourth clock signal PWM-S1-CK, and the start time of the effective pulse of the fourth clock signal PWM-S1-CK is earlier than the start time of the effective pulse of the third clock signal PAM-S1-CK. This allows the effective pulse width of the second clock signal PWM-S2-CK to be greater than the effective pulse width of the first clock signal PAM-S2-CK, the effective pulse width of the first clock signal PAM-S2-CK to be greater than the effective pulse width of the fourth clock signal PWM-S1-CK, and the effective pulse width of the fourth clock signal PWM-S1-CK to be greater than the effective pulse width of the third clock signal PAM-S1-CK. Since the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, and the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK, the duration of the effective pulse of the second clock signal PWM-S2-CK covers the duration of the effective pulse of the first clock signal PAM-S2-CK, the duration of the effective pulse of the first clock signal PAM-S2-CK covers the duration of the effective pulse of the fourth clock signal PWM-S1-CK, and the duration of the effective pulse of the fourth clock signal PWM-S1-CK covers the duration of the effective pulse of the third clock signal PAM-S1-CK. Furthermore, in the display panel 000 of this embodiment, the last working period before the light-emitting element 20 emits light is when the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, so that the pulse width data voltage PWM-data is written to the pixel circuit 10, thereby adjusting the pulse width of the driving current and realizing the brightness control of the light-emitting element 20. Therefore, the effective pulse width of the second clock signal PWM-S2-CK is the largest, and the effective pulse duration of the second clock signal PWM-S2-CK is the longest, which can ensure sufficient writing time when the pulse width data voltage PWM-data is written to the pixel circuit 10, thus satisfying the reasonable control of the brightness of the light-emitting element 20.

[0103] In some alternative embodiments, please refer to the references. Figure 9 , Figure 12 , Figure 13 and Figure 20 , Figure 21 , Figure 20 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit. Figure 21 yes Figure 12 The driving circuit in the middle adopts Figure 20 The timing diagram of the scan signal generated by the clock signal timing; in this embodiment, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, and the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. Furthermore, the start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the fourth clock signal PWM-S1-CK, the start time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK, and the start time of the effective pulse of the first clock signal PAM-S2-CK is later than the start time of the effective pulse of the third clock signal PAM-S1-CK.

[0104] In the first clock signal PAM-S2-CK, the second clock signal PWM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, the effective pulse durations of at least some of the clock signals overlap at least partially.

[0105] This embodiment explains that when the first type of clock signal CK-1 includes the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 includes the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is later than the cutoff time of the effective pulses of all clock signals included in the second type of clock signal CK-2, the design of each clock signal can be further refined. Specifically, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, and the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the first clock signal PAM-S2-CK. The cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. This ensures that when the first driving circuit 00-1 receives the second clock signal PWM-S2-CK and generates the second sub-scan signal PWM-S2, and the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, it is only controlled by the second sub-scan signal PWM-S2. Other signals such as the first sub-scan signal PAM-S2, the third sub-scan signal PAM-S1, and the fourth sub-scan signal PWM-S1 have finished controlling the various modules of the pixel circuit 10 before completing the transmission of the pulse width data voltage PWM-data. This effectively avoids interference from other interference signals in the process of writing the pulse width data voltage PWM-data to the pulse width data writing module 101-PWM, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0106] It is understood that the explanation of the design scheme for the effective pulse cutoff time of the clock signal in this embodiment can be found in the above description. Figure 14 and Figure 15 The corresponding embodiments are explained in detail here.

[0107] In this embodiment, the start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the fourth clock signal PWM-S1-CK, the start time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK, and the start time of the effective pulse of the first clock signal PAM-S2-CK is later than the start time of the effective pulse of the third clock signal PAM-S1-CK. That is, if the effective pulse cutoff time of a clock signal is later, the start time of its corresponding effective pulse is also later; if the effective pulse cutoff time of a clock signal is earlier, the start time of its corresponding effective pulse is also earlier. The effective pulse cutoff times of the clock signals received by different driving circuits do not coincide, and the effective pulse start times of the clock signals do not coincide either. However, among the first clock signal PAM-S2-CK, the second clock signal PWM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, the effective pulse duration of at least some clock signals at least partially overlaps (e.g., Figure 20 As shown in the figure, the effective pulse duration of the second clock signal PWM-S2-CK partially overlaps with the effective pulse duration of the fourth clock signal PWM-S1-CK, the effective pulse duration of the fourth clock signal PWM-S1-CK partially overlaps with the effective pulse duration of the first clock signal PAM-S2-CK, and the effective pulse duration of the first clock signal PAM-S2-CK partially overlaps with the effective pulse duration of the third clock signal PAM-S1-CK. This helps to shorten the line time (1H), and the display panel has a shorter frame period under the same number of lines, which can effectively improve the refresh rate and present a smoother dynamic display effect.

[0108] In some alternative embodiments, please refer to the references. Figure 9 , Figure 12 , Figure 13 and Figure 22 , Figure 23 , Figure 22 yes Figure 12 Another timing diagram of the first and second type of clock signals received by the driving circuit. Figure 23 yes Figure 12 The driving circuit in the middle adopts Figure 22The timing diagram of the scan signal generated by the clock signal timing sequence; in this embodiment, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the effective pulse of the first clock signal PAM-S2-CK, the cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK; and the start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the fourth clock signal PWM-S1-CK, the start time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK, and the start time of the effective pulse of the first clock signal PAM-S2-CK is later than the start time of the effective pulse of the third clock signal PAM-S1-CK.

[0109] Among the first clock signal PAM-S2-CK, the second clock signal PWM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, at least some of the clock signals have valid pulse duration periods that do not overlap.

[0110] This embodiment explains that when the first type of clock signal CK-1 includes the second clock signal PWM-S2-CK, and the second type of clock signal CK-2 includes the first clock signal PAM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is later than the cutoff time of the effective pulses of all clock signals included in the second type of clock signal CK-2, the design of each clock signal can be further refined. Specifically, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, the cutoff time of the effective pulse of the second clock signal PWM-S2-CK is later than the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK, and the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the cutoff time of the first clock signal PAM-S2-CK. The cutoff time of the effective pulse of the first clock signal PAM-S2-CK is later than the cutoff time of the effective pulse of the third clock signal PAM-S1-CK. This ensures that when the first driving circuit 00-1 receives the second clock signal PWM-S2-CK and generates the second sub-scan signal PWM-S2, and the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, it is only controlled by the second sub-scan signal PWM-S2. Other signals such as the first sub-scan signal PAM-S2, the third sub-scan signal PAM-S1, and the fourth sub-scan signal PWM-S1 have finished controlling the various modules of the pixel circuit 10 before completing the transmission of the pulse width data voltage PWM-data. This effectively avoids interference from other interference signals in the process of writing the pulse width data voltage PWM-data to the pulse width data writing module 101-PWM, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0111] It is understood that the explanation of the design scheme for the effective pulse cutoff time of the clock signal in this embodiment can be found in the above description. Figure 14 and Figure 15 The corresponding embodiments are explained in detail here.

[0112] In this embodiment, the start time of the effective pulse of the second clock signal PWM-S2-CK is later than the start time of the effective pulse of the fourth clock signal PWM-S1-CK, the start time of the effective pulse of the fourth clock signal PWM-S1-CK is later than the start time of the effective pulse of the first clock signal PAM-S2-CK, and the start time of the effective pulse of the first clock signal PAM-S2-CK is later than the start time of the effective pulse of the third clock signal PAM-S1-CK. That is, if the effective pulse cutoff time of a clock signal is later, the start time of its corresponding effective pulse is also later; if the effective pulse cutoff time of a clock signal is earlier, the start time of its corresponding effective pulse is also earlier. The effective pulse cutoff times of the clock signals received by different driving circuits do not coincide, and the effective pulse start times of the clock signals do not coincide either. However, among the first clock signal PAM-S2-CK, the second clock signal PWM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK, at least some of the clock signals have effective pulse durations that do not overlap (e.g., Figure 22 As shown), preferably, the effective pulse duration of the second clock signal PWM-S2-CK does not overlap with the effective pulse duration of the fourth clock signal PWM-S1-CK, the effective pulse duration of the fourth clock signal PWM-S1-CK does not overlap with the effective pulse duration of the first clock signal PAM-S2-CK, and the effective pulse duration of the first clock signal PAM-S2-CK does not overlap with the effective pulse duration of the third clock signal PAM-S1-CK. This ensures that the time periods for different driving circuits to generate different scanning signals after receiving different clock signals do not coincide, avoiding mutual interference between different scanning signals. This is beneficial to improving the control performance of different modules in the pixel circuit 10 by different scanning signals, thereby improving the display quality.

[0113] Optionally, in this embodiment, as Figure 22 and Figure 23As shown, the effective pulse duration of the second clock signal PWM-S2-CK does not overlap with the effective pulse duration of the fourth clock signal PWM-S1-CK, and the effective pulse duration of the second clock signal PWM-S2-CK is later than the effective pulse duration of the fourth clock signal PWM-S1-CK; the effective pulse duration of the fourth clock signal PWM-S1-CK does not overlap with the effective pulse duration of the first clock signal PAM-S2-CK, and the effective pulse duration of the fourth clock signal PWM-S1-CK is later than the effective pulse duration of the first clock signal PAM-S2-CK; the effective pulse duration of the first clock signal PAM-S2-CK does not overlap with the effective pulse duration of the third clock signal PAM-S1-CK, and the effective pulse duration of the first clock signal PAM-S2-CK is later than the effective pulse duration of the third clock signal PAM-S1-CK.

[0114] In this embodiment, the effective pulse duration of the second clock signal PWM-S2-CK is set to be executed last. This allows the first driving circuit 00-1 to receive the second clock signal PWM-S2-CK and generate the second sub-scan signal PWM-S2. When the second sub-scan signal PWM-S2 controls the conduction of the pulse width data writing module 101-PWM, it is only controlled by the second sub-scan signal PWM-S2. Other signals such as the first sub-scan signal PAM-S2, the third sub-scan signal PAM-S1, and the fourth sub-scan signal PWM-S1 have already ended their control over the various modules of the pixel circuit 10 before completing the transmission of the pulse width data voltage PWM-data. This effectively avoids interference from other interference signals in the process of writing the pulse width data voltage PWM-data into the pulse width data writing module 101-PWM, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0115] Optional, such as Figure 9 , Figure 12 , Figure 13 , Figures 20-23As shown, in this embodiment, since the effective pulse cutoff time of the clock signal received by the driving circuit is later, the start time of its corresponding effective pulse is also later; conversely, the effective pulse cutoff time of the clock signal is earlier, and the start time of its corresponding effective pulse is also earlier. That is, the effective pulse cutoff times of the clock signals received by different driving circuits do not coincide, and the effective pulse start times of the clock signals do not coincide either. Therefore, it can be set that at least some of the clock signals PAM-S2-CK, PWM-S2-CK, PAM-S1-CK, and PWM-S1-CK have equal effective pulse widths. Preferably, the first clock signal PAM-S2-CK has an effective pulse width of equal width. The effective pulse widths of the first clock signal PAM-S2-CK, the second clock signal PWM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK are all equal. That is, the effective pulse durations of the first clock signal PAM-S2-CK, the second clock signal PWM-S2-CK, the third clock signal PAM-S1-CK, and the fourth clock signal PWM-S1-CK are all equal. This can reduce the control complexity of the drive circuit, help reduce the difficulty of signal scheduling received by the drive circuit, and reduce the risk of timing design errors.

[0116] In some alternative embodiments, please refer to the references. Figure 1 , Figure 5 and Figure 24 As shown, Figure 24 yes Figure 1 Another connection structure diagram of the pixel circuit is shown in this embodiment. This example illustrates that in certain modes, the amplitude adjustment circuit 10-PAM and pulse width adjustment circuit 10-PWM of the pixel circuit 10 can be controlled separately. However, the final working period before the light-emitting element 20 emits light is still controlled by the second sub-scan signal PWM-S2 to activate the pulse width data writing module 101-PWM, causing the pulse width data voltage PWM-data to be written into the pixel circuit 10. This adjusts the pulse width of the driving current, thereby controlling the brightness of the light-emitting element 20. Therefore, in this embodiment, the first driving circuit 00-1 can receive the first type of clock signal CK-1 to generate a first scan signal scan1, which includes the second sub-scan signal PWM-S2 and the fourth sub-scan signal PWM-S1. The second driving circuit 00-2 can receive the second type of clock signal CK-2 to generate a second scan signal scan2, which may include the first sub-scan signal PAM-S2 and the third sub-scan signal PAM-S1. The specific implementation scheme is as follows: like Figures 24-27 As shown, Figure 25 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure. Figure 26 yes Figure 24 and Figure 25 A simplified diagram showing the electrical connections between the driver circuit and the pixel circuit. Figure 27 yes Figure 25 A timing diagram of the first type of clock signal and the second type of clock signal received by the driving circuit. In this embodiment, the first driving circuit 00-1 may include a fourth sub-driving circuit 00-11 and a fifth sub-driving circuit 00-21, and the second driving circuit 00-2 may include a sixth sub-driving circuit 00-24 and a seventh sub-driving circuit 00-25. The fourth sub-driving circuit 00-11 includes multiple cascaded fifth shift registers SR-5, the fifth sub-driving circuit 00-21 includes multiple cascaded sixth shift registers SR-6, the sixth sub-driving circuit 00-24 includes multiple cascaded seventh shift registers SR-7, and the seventh sub-driving circuit 00-25 includes multiple cascaded eighth shift registers SR-8. The output of the fifth shift register SR-5 is electrically connected to the control terminal of the pulse width data writing module 101-PWM; the output of the sixth shift register SR-6 is electrically connected to the control terminal of the pulse width reset module 102-PWM; the output of the seventh shift register SR-7 is electrically connected to the control terminal of the amplitude data writing module 101-PAM; and the output of the eighth shift register SR-8 is electrically connected to the control terminal of the amplitude reset module 102-PAM. The fifth shift register SR-5 receives the second clock signal PWM-S2-CK and outputs the second sub-scan signal PWM-S2; The sixth shift register SR-6 receives the fourth clock signal PWM-S1-CK and outputs the fourth sub-scan signal PWM-S1; The seventh shift register SR-7 receives the first clock signal PAM-S2-CK and outputs the first sub-scan signal PAM-S2; The eighth shift register SR-8 receives the third clock signal PAM-S1-CK and outputs the third sub-scan signal PAM-S1; The first type of clock signal CK-1 includes the second clock signal PWM-S2-CK and the fourth clock signal PWM-S1-CK; The second type of clock signal CK-2 includes the first clock signal PAM-S2-CK and the third clock signal PAM-S1-CK.

[0117] In this embodiment, the start time of the effective pulse of the first clock signal PAM-S2-CK coincides with the start time of the effective pulse of the third clock signal PAM-S1-CK, and the end time of the effective pulse of the first clock signal PAM-S2-CK coincides with the end time of the effective pulse of the third clock signal PAM-S1-CK. The start time of the effective pulse of the second clock signal PWM-S2-CK coincides with the start time of the effective pulse of the fourth clock signal PWM-S1-CK, and the cutoff time of the effective pulse of the second clock signal PWM-S2-CK coincides with the cutoff time of the effective pulse of the fourth clock signal PWM-S1-CK. The start time of the effective pulse of the first clock signal PAM-S2-CK is earlier than the start time of the effective pulse of the second clock signal PWM-S2-CK. The cutoff time of the effective pulse of the first clock signal PAM-S2-CK is earlier than the cutoff time of the effective pulse of the second clock signal PWM-S2-CK.

[0118] This embodiment explains that when the first type of clock signal CK-1 includes the second clock signal PWM-S2-CK and the fourth clock signal PWM-S1-CK, and the second type of clock signal CK-2 includes the first clock signal PAM-S2-CK and the third clock signal PAM-S1-CK, the cutoff time of the effective pulse of the first type of clock signal CK-1 (taking a low level as an example) is later than the cutoff time of the effective pulses of all clock signals included in the second type of clock signal CK-2. This allows for further refinement of the design of each clock signal. Specifically, the start time of the effective pulse of the first clock signal PAM-S2-CK is earlier than that of the second clock signal PWM-S1-CK. The start time of the effective pulse of 2-CK; the end time of the effective pulse of the first clock signal PAM-S2-CK is earlier than the end time of the effective pulse of the second clock signal PWM-S2-CK, the start time of the effective pulse of the third clock signal PAM-S1-CK is earlier than the start time of the effective pulse of the fourth clock signal PWM-S1-CK, and the end time of the effective pulse of the third clock signal PAM-S1-CK is earlier than the end time of the effective pulse of the fourth clock signal PWM-S1-CK, thereby satisfying that the end time of the effective pulse of the first type of clock signal CK-1 is later than the end time of the effective pulses of all clock signals included in the second type of clock signal CK-2;However, the start time of the effective pulse of the first clock signal PAM-S2-CK coincides with the start time of the effective pulse of the third clock signal PAM-S1-CK, and the end time of the effective pulse of the first clock signal PAM-S2-CK coincides with the end time of the effective pulse of the third clock signal PAM-S1-CK. Similarly, the start time of the effective pulse of the second clock signal PWM-S2-CK coincides with the start time of the effective pulse of the fourth clock signal PWM-S1-CK, and the end time of the effective pulse of the second clock signal PWM-S2-CK coincides with the end time of the effective pulse of the fourth clock signal PWM-S1-CK. Therefore, the fourth sub-driving circuit 00-11 and the fifth sub-driving circuit 00-21 included in the first driving circuit 00-1 can share the same clock signal line. That is, the second clock signal PWM-S2-CK and the fourth clock signal PWM-S1-CK can be provided to the fourth sub-driving circuit 00-11 respectively by the same clock signal line. The driving circuits 00-11 and the fifth sub-driving circuit 00-21 generate the second sub-scanning signal PWM-S2 and the fourth sub-scanning signal PWM-S1. Similarly, the sixth sub-driving circuit 00-24 and the seventh sub-driving circuit 00-25 included in the second driving circuit 00-2 can share the same clock signal line. That is, the first clock signal PAM-S2-CK and the third clock signal PAM-S1-CK can be provided to the sixth sub-driving circuit 00-24 and the seventh sub-driving circuit 00-25 respectively by the same clock signal line to generate the first sub-scanning signal PAM-S2 and the third sub-scanning signal PAM-S1. This helps to reduce the number of signal traces in the layout space of the display panel 000. Furthermore, by sharing some clock signal lines, the number of pads in the display panel 000 used to connect to the clock signal lines and to the circuit boards such as the driving chip can also be reduced accordingly, which helps to save non-display space in the bonding area, thereby realizing the narrow bezel design of the panel.

[0119] In some alternative embodiments, please refer to the references. Figure 9 , Figures 13-23 and Figure 28 , Figure 28 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present disclosure. In this embodiment, the display panel 000 includes a display area AA, which includes a plurality of pixel circuits 10; the driving circuit 00 is located in the display area AA.

[0120] In this embodiment, the driving circuit 00 of the display panel 000 is located in the display area AA. As mentioned above, the first driving circuit 00-1 and the second driving circuit 00-2 are located in the display area AA of the display panel 000. If they can be interspersed among the pixel circuits 10 within the display area AA, it can avoid occupying too much space when the driving circuit 00 is located in the border area of ​​the display panel 000. This is beneficial to greatly reduce the border space of the display panel 000, thereby reducing the border to achieve an ultra-narrow border or even a borderless display effect.

[0121] In some alternative embodiments, such as Figure 9 , Figures 13-23 and Figure 28 , Figure 29 , Figure 30 , Figure 29 yes Figure 28 A simplified schematic diagram of the clock control signal lines and pixel circuitry in the central display area. Figure 30 yes Figure 28 Another simplified schematic diagram of the clock control signal lines and pixel circuits in the central display area. In this embodiment, the driving circuit 00 is electrically connected to the clock control signal line L-CK. The clock control signal line L-CK includes a first type of clock control signal line L1-CK and a second type of clock signal line L2-CK. The first type of clock control signal line L1-CK is used to provide a first type of clock signal CK-1 to the first driving circuit 00-1, and the second type of clock control signal line L2-CK is used to provide a second type of clock signal CK-2 to the second driving circuit 00-2. The pixel circuit 10 includes a data writing module 101 that is electrically connected to a data line L-data, and the data line L-data is used at least to provide a data voltage to the data writing module 101 of the pixel circuit 10. The clock control signal line L-CK is located in the display area AA, and multiple pixel circuits 10 form a pixel circuit row 10H along the first direction X; The clock control signal line L-CK is located between two adjacent pixel circuits 10 in pixel circuit row 10H; or, The pixel circuit row 10H includes multiple pixel circuit groups 100. Each pixel circuit group 100 includes at least two pixel circuits 10. Each pixel circuit group 100 controls multiple light-emitting elements 20 of different colors to emit light. The clock control signal line L-CK is located between two adjacent pixel circuit groups 100.

[0122] This embodiment explains that after the driving circuit 00 is located in the display area AA, the driving circuit 00 needs to be electrically connected to the clock control signal line L-CK to provide different clock signals to each driving circuit. For example, the clock control signal line L-CK includes a first type clock control signal line L1-CK and a second type clock signal line L2-CK. The first type clock control signal line L1-CK is used to provide the first type clock signal CK-1 in the above embodiment to the first driving circuit 00-1, and the second type clock control signal line L2-CK is used to provide the second type clock signal CK-2 in the above embodiment to the second driving circuit 00-2. The pixel circuit 10 includes... The data writing module 101 requires an electrical connection to the data line L-data. The data line L-data is used at least to provide data voltage to the data writing module 101 of the pixel circuit 10. For example, the data line L-data includes a first type of data line and a second type of data line. The first type of data line provides amplitude data voltage to the amplitude data writing module 101-PAM, and the second type of data line provides pulse width data voltage to the pulse width data writing module 101-PWM. In this case, the clock control signal line L-CK and the pixel circuit 10 can be arranged in the display area AA such that the clock control signal line L-CK is located between any two adjacent pixel circuits 10 in row 10H (e.g., ...). Figure 29 (As shown); or, pixel circuit row 10H includes multiple pixel circuit groups 100, each pixel circuit group 100 including at least two pixel circuits 10, such as pixel circuit group 100 including three pixel circuits 10. The three pixel circuits 10 of pixel circuit group 100 are used to control the light emission of three different colored light-emitting elements 20 (red light-emitting element, green light-emitting element, and blue light-emitting element), and the clock control signal line L-CK is located between two adjacent pixel circuit groups 100 (e.g. Figure 30 (as shown) Figure 29 and Figure 30 In this embodiment, the pixel circuit 10 needs to be electrically connected to the data line L-data. Typically, the data line L-data extends along the second direction Y (the second direction Y and the first direction X are perpendicular to each other in a direction parallel to the plane where the display panel 000 is located). If the driving circuit 00 is located in the display area AA, then when the clock control signal line L-CK extends along the second direction Y, that is, the data line L-data and the clock control signal line L-CK extend in the same direction, and their distance in the display area AA is relatively close. For example, if the clock control signal line L-CK is located between two adjacent pixel circuits 10 in pixel circuit row 10H, and the data line L-data is located between the pixel circuit 10 and the clock control signal line L-CK, the close distance and high coupling between the data line L-data and the clock control signal line L-CK can affect the data line L-data at the moment the signal of the clock control signal line L-CK changes, and the two can easily interfere with each other. To solve the above problem, this embodiment adopts... Figures 13-23The cutoff time of the effective pulse of the first type of clock signal CK-1 does not coincide with the cutoff time of the effective pulse of the second type of clock signal CK-2. Specifically, the cutoff time of the effective pulse of the first type of clock signal CK-1 is later than the cutoff time of the effective pulse of the second type of clock signal CK-2. The effective pulse time of the first scan signal scan1 generated by the first driving circuit 00-1 after receiving the first type of clock signal CK-1 is later than the effective pulse time of the second scan signal scan2 generated by the second driving circuit 00-2 after receiving the second type of clock signal CK-2. Therefore, when the first scan signal scan1 controls the conduction of the data writing module 101 and the data line L-data transmits the data voltage to the pixel circuit 10, it is only controlled by the first scan signal scan1. The second scan signal scan2 has ended the control of other modules in the pixel circuit 10 before the data voltage signal transmission is completed. This can effectively avoid the interference of the signal jump of the clock control signal line L-CK when it is set in the display area AA on the process of writing the data voltage signal to the data writing module 101, thereby helping to reduce brightness variation, reduce display mura, and improve display effect.

[0123] It is understood that in this embodiment, the display panel 000 includes a display area AA, which includes multiple pixel circuits 10. When the driving circuit 00 is also located in the display area AA, it can be as follows: Figure 28 As shown, the first driving circuit 00-1 includes multiple first shift registers SR-1 cascaded sequentially along the second direction Y, and the first driving circuit 00-1 is located between adjacent pixel circuit columns in the first direction X; the first sub-driving circuit 00-21 of the second driving circuit 00-2 includes multiple second shift registers SR-2 cascaded sequentially along the second direction Y, and the first sub-driving circuit 00-21 is located between adjacent pixel circuit columns in the first direction X; the second sub-driving circuit 00-22 of the second driving circuit 00-2 includes multiple third shift registers SR-3 cascaded sequentially along the second direction Y, and the second sub-driving circuit 00-22 is located between adjacent pixel circuit columns in the first direction X; the third sub-driving circuit 00-23 of the second driving circuit 00-2 includes multiple fourth shift registers SR-4 cascaded sequentially along the second direction Y, and the third sub-driving circuit 00-23 is located between adjacent pixel circuit columns in the first direction X.

[0124] Or in some other alternative embodiments, such as Figure 9 , Figures 13-23 and Figure 31 As shown, Figure 31This is a schematic diagram of another planar structure of the display panel provided in this embodiment. When the display panel 000 includes a display area AA, and the display area AA includes multiple pixel circuits 10, and the driving circuit 00 is disposed in the display area AA, a shift register in at least one driving circuit can also be disposed between two adjacent pixel circuit rows 10H in the second direction Y, and the shift register does not overlap with the light-emitting element 20 in the thickness direction of the display panel 000. Specifically, as shown... Figure 31 As shown, taking the layout structure of the first driving circuit 00-1 included in the driving circuit 00 as an example, among the multiple cascaded first shift registers SR-1 included in the first driving circuit 00-1, at least one first shift register SR-1 is disposed between two adjacent pixel circuit rows 10H in the second direction Y, and the first shift register SR-1 does not overlap with the light-emitting element 20 in the thickness direction of the display panel 000, nor does the first shift register SR-1 overlap with the pixel circuit 10 in the thickness direction of the display panel 000; it can also be understood that in the second direction Y, the first shift register SR-1 and the pixel circuit row 10H are arranged alternately, so that at least one driving circuit can be transferred from the non-display area of ​​the display panel to the display area AA of the display panel, thereby reducing the bezel width of the display panel and realizing an ultra-narrow bezel or even a bezel-less design.

[0125] Optionally, in some other alternative embodiments, the first shift register SR-1 may be configured to at least partially overlap with the pixel circuit 10 in the thickness direction of the display panel 000 (not shown in the figure), thereby reducing the overall size of the panel without affecting the display resolution.

[0126] It should be noted that in this embodiment, the shift register included in the driving circuit 00 is set between adjacent pixel circuit rows 10H in the second direction Y. In the figure, the relative size of the shift register and the light-emitting element 20, and the relative size of the shift register and the pixel circuit 10 in the first direction X do not represent the relative size in the actual product. In specific implementation, the size and shape layout of the relevant structures can be designed according to actual needs.

[0127] In some alternative embodiments, please refer to Figure 32 , Figure 32 This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 32This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 000 in the above embodiments; these will not be repeated here.

[0128] Optional, please refer to Figure 33 , Figure 33 This is another planar structural schematic diagram of the display device provided in this embodiment. The display device 111 in this embodiment can also be a splicing display device, which includes multiple display panels 000 spliced ​​together. In this embodiment, the driving circuit 00 of the display panel 000 is located in the display area AA. As in the above embodiment, the first driving circuit 00-1 and the second driving circuit 00-2 are set in the display area AA of the display panel 000, which can achieve an ultra-narrow bezel or even a bezel-less effect for a single display panel 000. Furthermore, after multiple display panels 000 are spliced ​​together to form a splicing display device, the splicing seam at the splicing position is made as narrow as possible, thereby reducing the width of the splicing seam, ensuring the continuity of the image during display, and improving the display effect.

[0129] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0130] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits, each pixel circuit including at least a data writing module and a first module, wherein the control terminal of the data writing module is electrically connected to a first scan signal, and the control terminal of the first module is electrically connected to a second scan signal; It also includes a driving circuit, which comprises a first driving circuit and a second driving circuit; the first driving circuit receives a first type of clock signal and outputs the first scan signal; the second driving circuit receives a second type of clock signal and outputs the second scan signal. The cutoff time of the effective pulse of the first type of clock signal does not coincide with the cutoff time of the effective pulse of the second type of clock signal.

2. The display panel according to claim 1, characterized in that, The cutoff time of the effective pulse of the first type of clock signal is later than the cutoff time of the effective pulse of the second type of clock signal.

3. The display panel according to claim 1, characterized in that, The start time of the effective pulse of the first type of clock signal does not coincide with the start time of the effective pulse of the second type of clock signal.

4. The display panel according to claim 3, characterized in that, The start time of the effective pulse of the first type of clock signal is later than the start time of the effective pulse of the second type of clock signal.

5. The display panel according to claim 1, characterized in that, The pixel circuit includes an amplitude adjustment circuit and a pulse width adjustment circuit that are electrically connected. The amplitude adjustment circuit receives amplitude data voltage and controls the amplitude of the driving current of the pixel circuit driving the light-emitting element. The pulse width adjustment circuit receives pulse width data voltage and controls the pulse width of the drive current; The data writing module includes an amplitude data writing module and / or a pulse width data writing module; the amplitude adjustment circuit includes the amplitude data writing module; and the pulse width adjustment circuit includes the pulse width data writing module. The control terminal of the amplitude data writing module is electrically connected to the first sub-scan signal, and the control terminal of the pulse width data writing module is electrically connected to the second sub-scan signal. The first scan signal includes a first sub-scan signal and / or a second sub-scan signal.

6. The display panel according to claim 5, characterized in that, The first driving circuit includes multiple cascaded first shift registers, and the second driving circuit includes multiple cascaded second shift registers; The output of the first shift register is electrically connected to the control terminal of the pulse width data writing module, and the output of the second shift register is electrically connected to the control terminal of the amplitude data writing module. The second shift register receives the first clock signal and outputs the first sub-scan signal; the first shift register receives the second clock signal and outputs the second sub-scan signal. The first type of clock signal includes the second clock signal, and the second type of clock signal includes the first clock signal.

7. The display panel according to claim 5, characterized in that, The second scan signal includes a third sub-scan signal and a fourth sub-scan signal; The amplitude adjustment circuit further includes an amplitude driving module and an amplitude reset module. The first terminal of the amplitude reset module is electrically connected to the amplitude reset voltage, the second terminal of the amplitude reset module is electrically connected to the amplitude driving module, and the control terminal of the amplitude reset module is electrically connected to the third sub-scan signal. The pulse width adjustment circuit further includes a pulse width driving module and a pulse width reset module. The first terminal of the pulse width reset module is electrically connected to the pulse width reset voltage, the second terminal of the pulse width reset module is electrically connected to the pulse width driving module, and the control terminal of the pulse width reset module is electrically connected to the fourth sub-scan signal. The first driving circuit includes multiple cascaded first shift registers, the second driving circuit includes a first sub-driving circuit, a second sub-driving circuit, and a third sub-driving circuit. The first sub-driving circuit includes multiple cascaded second shift registers, the second sub-driving circuit includes multiple cascaded third shift registers, and the third sub-driving circuit includes multiple cascaded fourth shift registers. The output of the first shift register is electrically connected to the control terminal of the pulse width data writing module, the output of the second shift register is electrically connected to the control terminal of the amplitude data writing module, the output of the third shift register is electrically connected to the control terminal of the amplitude reset module, and the output of the fourth shift register is electrically connected to the control terminal of the pulse width reset module. The second shift register receives the first clock signal and outputs the first sub-scan signal; The first shift register receives the second clock signal and outputs the second sub-scan signal; The third shift register receives the third clock signal and outputs the third sub-scan signal; The fourth shift register receives the fourth clock signal and outputs the fourth sub-scan signal; The first type of clock signal includes the second clock signal, and the second type of clock signal includes the first clock signal, the third clock signal, and the fourth clock signal.

8. The display panel according to claim 7, characterized in that, The cutoff time of the valid pulse of the second clock signal is later than the cutoff time of the valid pulse of the fourth clock signal, the cutoff time of the valid pulse of the fourth clock signal is later than the cutoff time of the valid pulse of the first clock signal, and the cutoff time of the valid pulse of the first clock signal is later than the cutoff time of the valid pulse of the third clock signal.

9. The display panel according to claim 8, characterized in that, The start time of the effective pulse of the second clock signal coincides with the start time of the effective pulse of the fourth clock signal, and the start time of the effective pulse of the first clock signal coincides with the start time of the effective pulse of the third clock signal. The start time of the effective pulse of the second clock signal is later than the start time of the effective pulse of the first clock signal.

10. The display panel according to claim 8, characterized in that, The start times of the effective pulses of the second clock signal, the fourth clock signal, the first clock signal, and the third clock signal coincide.

11. The display panel according to claim 10, characterized in that, The effective pulse duration of the second clock signal covers the effective pulse duration of the fourth clock signal, the effective pulse duration of the fourth clock signal covers the effective pulse duration of the first clock signal, and the effective pulse duration of the first clock signal covers the effective pulse duration of the third clock signal.

12. The display panel according to claim 10, characterized in that, The effective pulse width of the second clock signal is greater than the effective pulse width of the fourth clock signal, the effective pulse width of the fourth clock signal is greater than the effective pulse width of the first clock signal, and the effective pulse width of the first clock signal is greater than the effective pulse width of the third clock signal.

13. The display panel according to claim 7, characterized in that, The cutoff time of the valid pulse of the second clock signal is later than the cutoff time of the valid pulse of the first clock signal, the cutoff time of the valid pulse of the first clock signal is later than the cutoff time of the valid pulse of the fourth clock signal, and the cutoff time of the valid pulse of the fourth clock signal is later than the cutoff time of the valid pulse of the third clock signal.

14. The display panel according to claim 13, characterized in that, The start time of the effective pulse of the second clock signal is earlier than the start time of the effective pulse of the first clock signal, the start time of the effective pulse of the first clock signal is earlier than the start time of the effective pulse of the fourth clock signal, and the start time of the effective pulse of the fourth clock signal is earlier than the start time of the effective pulse of the third clock signal.

15. The display panel according to claim 14, characterized in that, The effective pulse duration of the second clock signal covers the effective pulse duration of the first clock signal, the effective pulse duration of the first clock signal covers the effective pulse duration of the fourth clock signal, and the effective pulse duration of the fourth clock signal covers the effective pulse duration of the third clock signal.

16. The display panel according to claim 14, characterized in that, The effective pulse width of the second clock signal is greater than the effective pulse width of the first clock signal, the effective pulse width of the first clock signal is greater than the effective pulse width of the fourth clock signal, and the effective pulse width of the fourth clock signal is greater than the effective pulse width of the third clock signal.

17. The display panel according to claim 8, characterized in that, The start time of the effective pulse of the second clock signal is later than the start time of the effective pulse of the fourth clock signal, the start time of the effective pulse of the fourth clock signal is later than the start time of the effective pulse of the first clock signal, and the start time of the effective pulse of the first clock signal is later than the start time of the effective pulse of the third clock signal.

18. The display panel according to claim 17, characterized in that, In the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, the effective pulse durations of at least some of the clock signals at least partially overlap.

19. The display panel according to claim 17, characterized in that, Among the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, at least some of the clock signals have valid pulse durations that do not overlap.

20. The display panel according to claim 17, characterized in that, Among the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, at least some of the clock signals have the same effective pulse width.

21. The display panel according to claim 7, characterized in that, The start time of the effective pulse of the first clock signal coincides with the start time of the effective pulse of the third clock signal, and the end time of the effective pulse of the first clock signal coincides with the end time of the effective pulse of the third clock signal. The start time of the effective pulse of the second clock signal coincides with the start time of the effective pulse of the fourth clock signal, and the end time of the effective pulse of the second clock signal coincides with the end time of the effective pulse of the fourth clock signal. The start time of the effective pulse of the first clock signal is earlier than the start time of the effective pulse of the second clock signal; The cutoff time of the effective pulse of the first clock signal is earlier than the cutoff time of the effective pulse of the second clock signal.

22. The display panel according to claim 1, characterized in that, The display panel includes a display area, and the display area includes a plurality of the pixel circuits; The driving circuit is located in the display area.

23. The display panel according to claim 22, characterized in that, The driving circuit is electrically connected to the clock control signal line, which includes a first type of clock control signal line and a second type of clock signal line. The first type of clock control signal line is used to provide the first type of clock signal to the first driving circuit, and the second type of clock control signal line is used to provide the second type of clock signal to the second driving circuit. The clock control signal line is located in the display area, and the plurality of pixel circuits form a pixel circuit row along the first direction; The clock control signal line is located between two adjacent pixel circuits in the pixel circuit row; or, The pixel circuit row includes multiple pixel circuit groups, each pixel circuit group includes at least two pixel circuits, and each pixel circuit group controls multiple light-emitting elements of different colors to emit light. The clock control signal line is located between two adjacent pixel circuit groups.

24. The display panel according to claim 1, characterized in that, Within a line time, the cutoff time of the effective pulse of the first type of clock signal does not coincide with the cutoff time of the effective pulse of the second type of clock signal; wherein, the line time represents the time required for the display panel to drive one line of the pixel circuit during the line-by-line scanning process.

25. A display device, characterized in that, Includes the display panel as described in any one of claims 1-24.

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