Display device and display method

Abstract

The invention provides a display device and a display method.In the display device, a system-on-chip is used for receiving an input information source of a target display mode; the driving unit is used for scaling pixel data in the horizontal direction of an input signal source when the target display mode is a quadruplicated frequency mode, and doubling the refresh rate in the horizontal direction through a data cloning technology; and the time schedule controller is used for simultaneously sending each row of pixel data sent by the driving unit to two rows of pixels corresponding to the display panel through two gate lines in one group of gate lines. Therefore, the horizontal pixel data of the input information source is scaled through the driving unit, the refresh rate in the horizontal direction is doubled through the data cloning technology, and the time schedule controller sends each row of pixel data to two rows of pixels corresponding to the display panel at the same time through two gate lines in one group of gate lines. The quadruplicated frequency mode display is supported under the condition that the total bandwidth of a system-on-chip is not changed.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and display method. Background Technology

[0002] Existing LCD driver systems already support standard and double-frequency modes, using data horizontal scaling and dual-gate timing technology to increase refresh rates and enhance product value. However, when attempting to achieve a quadruple refresh rate, the system faces a critical bottleneck: how to effectively handle the data volume required for a quadruple refresh rate without increasing the total bandwidth of the front-end integrated circuits or upgrading chip specifications. While standard and double-frequency modes can manage bandwidth requirements through data cloning and timing optimization, the exponential increase in data processing volume caused by a quadruple refresh rate significantly exceeds the capabilities of the current architecture. Specifically, the front-end integrated circuits, including the system-on-a-chip (SoC) and timing controller, have a total bandwidth determined by the display panel's resolution and refresh rate. If the bandwidth cannot match the data throughput requirements of a quadruple refresh rate, it will force the system to use higher-cost chips, thereby increasing overall design complexity and manufacturing costs. Summary of the Invention

[0003] This application provides a display device and display method that achieves a four-times refresh rate mode display while maintaining a constant total bandwidth of the system-on-a-chip, thereby reducing system cost and design complexity.

[0004] In a first aspect, the display device provided in the embodiments of this application includes a system-on-a-chip, a timing controller, a driving unit, and a display panel that are electrically connected in sequence.

[0005] The display panel includes multiple data lines, multiple pixels and multiple sets of gate lines. Each data line is electrically connected to two columns of pixels located on both sides of the data line. Each row of pixels is electrically connected to a set of gate lines. Each set of gate lines includes two gate lines. The system-on-a-chip (SoC) is used to receive input signals from a target display mode; wherein the target display mode is one of at least two display modes, and the at least two display modes include a quadruple frequency mode; the total bandwidth of the SoC remains constant under the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution, and refresh rate of the display panel; The driving unit is used to scale the horizontal pixel data of the input signal source when the target display mode is the quadruple refresh rate mode, and double the horizontal refresh rate through data cloning technology, so as to output pixel data that is time-adapted to the timing of the timing controller. The timing controller is used to simultaneously send each row of pixel data sent by the driving unit to the two corresponding rows of pixels on the display panel through two gate lines in the set of gate lines in the quadruple frequency mode, so as to drive the display panel to display data.

[0006] Secondly, the display method provided in the embodiments of this application is applied to a display device, and the method includes: The system-on-a-chip (SoC) receives input signals for a target display mode; wherein the target display mode is one of at least two display modes, including a quadruple refresh rate mode; the total bandwidth of the SoC remains constant under the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution, and refresh rate of the display panel; When the target display mode is the quadruple refresh rate mode, the horizontal pixel data of the input signal source is scaled by the driving unit, and the horizontal refresh rate is doubled by data cloning technology to output pixel data that is time-adapted to the timing of the timing controller. In the quadruple frequency mode, the timing controller sends each row of pixel data sent by the driving unit to the corresponding two rows of pixels on the display panel through two gate lines in a set of gate lines, so as to drive the display panel to display data.

[0007] In summary, the display device and display method provided in this application achieve a four-times refresh rate mode display while maintaining the total bandwidth of the system-on-a-chip (SoC) unchanged. This has the advantages of achieving a four-times refresh rate mode display while keeping the total bandwidth of the SoC constant, and reducing the system cost and design complexity of the display device. Attached Figure Description

[0008] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on the above drawings without any creative effort.

[0009] Figure 1 This is one of the schematic diagrams of a display device provided for an embodiment of this application.

[0010] Figure 2 This is a second schematic diagram of a display device provided for an embodiment of this application.

[0011] Figure 3 This is a third schematic diagram of a display device provided for an embodiment of this application.

[0012] Figure 4 This is a schematic diagram of the link in this embodiment of the application, showing how the input signal source changes from 2K1K to 4K2K on the display panel.

[0013] Figure 5 A timing diagram of the normal mode provided for embodiments of this application.

[0014] Figure 6 A timing diagram of the second harmonic mode provided for an embodiment of this application.

[0015] Figure 7 A timing diagram of the fourth harmonic mode provided for an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0017] In this invention, the terms "first," "second," etc., are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the aforementioned process, method, product, or apparatus.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply that all embodiments are the same, nor are they independent or alternative embodiments mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] This application provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0020] In some embodiments, combined with Figure 1 and Figure 2 As shown, Figure 1One of the schematic diagrams of a display device provided for an embodiment of this application; Figure 2 This is a second schematic diagram of a display device provided as an embodiment of this application. The display device may include a display panel, a timing controller, and a source drive circuit (which can be reused as...). Figure 1 The display panel may include a pixel array, a gate drive circuit (GOA circuit), and a light-emitting controller. The display panel provided in this application embodiment may be, for example, an organic light-emitting diode (OLED) display panel; of course, the display panel may also be a Mini-LED display panel or a Micro-LED display panel. The display panel may also include a substrate, data lines for transmitting data signals DATA, scan lines for transmitting scan signals SCAN, power lines for transmitting the voltage VDD at the positive terminal of the power line or the voltage VSS at the negative terminal of the power line, light-emitting control signal lines for transmitting light-emitting control signals EM, a pixel array, an encapsulation layer, a polarizer, a color filter, etc.

[0021] The substrate can be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of multiple pixel units arranged in rows and columns, forming multiple pixel rows arranged along the row direction and multiple pixel columns arranged along the column direction. Each pixel row and each pixel column includes multiple pixel units, and each pixel unit includes multiple sub-pixels. Each sub-pixel includes a light-emitting device and pixel circuitry. For ease of description, pixel rows and pixel columns may be referred to as "rows" and "columns" thereafter. Taking an OLED display panel as an example, the pixel unit may include an organic light-emitting device and a pixel driving circuit. The pixel driving circuit may include a driving transistor used to control the brightness of the corresponding organic light-emitting device in the display panel. In actual pixel units, the driving transistor may include, but is not limited to, low-temperature polycrystalline silicon (LTPS) and thin-film transistors (TFTs) of metal-oxide-semiconductor semiconductors. The TFT may employ a dual-gate structure, with the organic light-emitting device electrically connected to either the first or second electrode of the TFT. Organic light-emitting devices (OLEDs) can include an emissive layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Different organic materials can emit light of different wavelengths, enabling full-color displays. The encapsulation layer includes a multi-layer structure alternating between organic and inorganic materials. The gate driver on array (GOA) circuit is mainly used for scanning and driving pixel rows. For example, the GOA circuit can include cascaded gate driver units, where each stage of the gate driver unit controls one or more pixel rows, enabling the selection of pixel units. In some embodiments, the GOA can employ single-sided or double-sided driving for multiple pixel rows. Single-sided driving can involve arranging gate driver units on only one side (such as the left or right side) and scanning and driving multiple pixel rows line by line through cascading. Double-sided driving can involve arranging driver units on both the left and right sides of the multiple pixel row, scanning and driving multiple pixel rows line by line through the coordinated operation of both sides. The source driver circuit is used to provide data signals to the pixel units. The timing controller is used to receive externally input image data and synchronization signals, and generate the signals required by the gate driver circuit and the source driver circuit. The power management chip is used to provide the required operating voltage to various parts of the display panel. It should be noted that... Figure 2 This is an illustrative diagram, and the component connections shown are only used to explain the functional logic of the display panel, and are not intended to limit the actual physical structure.

[0022] In one embodiment, such as Figure 1As shown, the display device 100 includes a system-on-chip (SoC) 101, a timing controller (Tcon) 102, a driver unit (Driver) 103, and a display panel (Panel) 104, which are connected in sequence.

[0023] The display panel 104 includes multiple data lines, multiple pixels, and multiple sets of gate lines. Each data line is electrically connected to two columns of pixels located on both sides of the data line, and each row of pixels is electrically connected to a set of gate lines. Each set of gate lines includes two gate lines.

[0024] The system-on-a-chip 101 is used to receive input signals from a target display mode; wherein the target display mode is one of at least two display modes, and the at least two display modes include a quadruple frequency mode; the total bandwidth of the system-on-a-chip 101 remains constant in the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution and refresh rate of the display panel 104.

[0025] The driving unit 103 is used to scale the horizontal pixel data of the input signal source when the target display mode is quadruple frequency mode, and double the horizontal refresh rate through data cloning technology (DCT) to output pixel data that is time-adapted to the timing of the timing controller 102.

[0026] The timing controller 102 is used to simultaneously send each row of pixel data sent by the driving unit 103 to the corresponding two rows of pixels in the display panel 104 through two gate lines in a set of gate lines in the quadruple frequency mode, so as to drive the display panel 104 to display data.

[0027] In this embodiment, the display panel 104 can be implemented based on a dual-line gate (DLG) architecture to facilitate the frequency multiplication function of the display panel 104. As an example, the DLG architecture can specifically involve each row of pixels being connected to two gate lines from a set of gate lines, with adjacent columns of pixels sharing a single data line. For example, a set of gate lines may include a first gate line and a second gate line. The first gate line, one of the two gate lines electrically connected to pixels in the same row, is electrically connected to pixels in odd-numbered columns of that row, and the second gate line is electrically connected to pixels in even-numbered columns of that row. The first and second gate lines are configured to sequentially output gate drive signals to achieve the frequency multiplication function of the display panel 104.

[0028] The system-on-chip 101 can be an integrated circuit chip that integrates most of the functions required by a computer or other electronic system. In this application, its main function is to receive and process input signals and perform preliminary data management according to the target display mode. The system-on-chip 101 is used to receive input signals from the target display mode. The target display mode is one of at least two display modes, including a quadruple frequency mode. The total bandwidth of the system-on-chip 101 remains constant under the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution, and refresh rate of the display panel 104. The system-on-chip 101 can be configured to receive input signals of multiple formats and automatically or manually identify the target display mode according to the characteristics of the signal source (such as resolution and refresh rate).

[0029] The driving unit 103, within the display device, is responsible for further processing and conversion of pixel data to adapt to the specific requirements of the timing controller 102 and the display panel 104. It may include image processing functions such as scaling and cloning. When the target display mode is a quadruple refresh rate mode, the driving unit 103 scales the horizontal pixel data of the input source and doubles the horizontal refresh rate using data cloning technology to output pixel data that is timing-compatible with the timing controller 102. The driving unit 103 may have a built-in image processing engine for scaling the horizontal pixel data of the received input source.

[0030] In quadruple frequency mode, timing controller 102 simultaneously transmits each row of pixel data sent by driving unit 103 to the corresponding two rows of pixels on display panel 104 via two gate lines from a set of gate lines, thereby driving display panel 104 to display data. Timing controller 102 can be designed to have dual gate line driving capability. When receiving pixel data sent by driving unit 103, timing controller 102 can generate corresponding timing signals, causing two gate lines from a set of gate lines to be turned on simultaneously, thereby writing the same row of pixel data in parallel to the two adjacent rows of pixels on display panel 104.

[0031] This application solves the cost and design complexity problems caused by bandwidth limitations and IC upgrade requirements when traditional LCD MNT products implement a four-times refresh rate mode, by using the driving unit 103 to scale and clone the horizontal pixel data while keeping the total bandwidth of the system-on-a-chip 101 unchanged, and by using the timing controller 102 to drive two rows of pixels simultaneously through dual gate lines. This achieves high refresh rate display without increasing the burden on the front-end IC.

[0032] In some embodiments of this application, when the display mode switches between different modes, if the data processing capabilities and bandwidth configuration of the drive unit 103 and the timing controller 102 cannot be flexibly adapted, it may lead to low data transmission efficiency, waste of resources or system instability. Especially in modes that require complex data processing (such as doubling the horizontal refresh rate), ensuring that the components work together and optimizing bandwidth utilization is a challenge.

[0033] Based on this, in one embodiment, when the display mode of the display device switches between at least two display modes, the output bandwidth of the output terminal of the driving unit 103 changes with the switching of the display mode, and the rated bandwidth of the driving unit 103 remains unchanged; the total bandwidth of the timing controller 102 remains unchanged in at least two display modes.

[0034] Specifically, the output bandwidth of the driver unit 103 can be the actual data rate at which the driver unit 103 transmits processed pixel data to the timing controller 102, while the rated bandwidth of the driver unit 103 can be the maximum data processing capability that the driver unit 103 hardware design can support, which is a fixed hardware parameter. By allowing the output bandwidth of the driver unit 103 to be dynamically adjusted according to the actual data processing requirements of the current display mode, the driver unit 103 can flexibly adapt to the data transmission volume in different modes.

[0035] Meanwhile, the total bandwidth of the timing controller 102 remains constant in at least two display modes. The total bandwidth of the timing controller 102 can be its maximum throughput capacity for receiving data from the drive unit 103, performing internal processing, and transmitting data to the display panel 104. By designing the total bandwidth of the timing controller 102 to remain constant in all supported display modes, a stable and predictable data transmission channel can be provided to the display panel 104.

[0036] In this application, when the display device switches between different display modes, the output bandwidth of the drive unit 103 can be dynamically adjusted according to the actual needs of the current mode, while its rated bandwidth remains unchanged. This allows the drive unit 103 to flexibly adapt to the data processing volume in different modes, avoiding resource waste or performance bottlenecks that may be caused by fixed bandwidth. At the same time, the total bandwidth of the timing controller 102 remains unchanged in all display modes, providing a stable and sufficient data transmission channel for the display panel 104, ensuring that display data can be efficiently and accurately transmitted to the display panel 104 regardless of the display mode.

[0037] In some embodiments of this application, there may be a lack of clear definitions and operational details regarding the conversion relationship between the specific input resolution, refresh rate and final display resolution in quadruple frequency mode, as well as how the system-on-a-chip 101, the driver unit 103 and the timing controller 102 work together to accurately achieve the conversion. This may lead to difficulties in ensuring that the display effect is effectively improved in quadruple frequency mode while keeping the total bandwidth of the system-on-a-chip 101 unchanged in practical applications, especially in the specific conversion of resolution and refresh rate, which presents technical challenges.

[0038] Based on this, in one embodiment, the initial resolution of the quadruple frequency mode is M1×N1, and the initial refresh rate is R1; the system-on-a-chip 101 is further configured to transmit the input signal source of the quadruple frequency mode to the driving unit 103 when the target display mode is switched to the quadruple frequency mode; the driving unit 103 is further configured to scale the horizontal pixel data of the input signal source and output a row of 2M1×N1 pixel data; the timing controller 102 is further configured to simultaneously send each row of pixel data in the 2M1×N1 pixel data to the corresponding two rows of pixels in the display panel 104 through two gate lines in a set of gate lines, so as to drive the display panel 104 to display data, so that the resolution of the target data displayed by the display panel 104 is 2M1×2N1 and the refresh rate is R1.

[0039] Specifically, the initial resolution M1×N1 and initial refresh rate R1 of the quadruple refresh mode define the characteristics of the original input signal when entering quadruple refresh mode. Here, M1 represents the number of horizontal pixels in the input signal, N1 represents the number of vertical pixels in the input signal, and R1 represents the frame refresh rate of the input signal. Therefore, The system-on-a-chip 101 can accurately transmit the input signal source with initial resolution M1×N1 and initial refresh rate R1 to the drive unit 103 when it detects that the target display mode has switched to the quadruple refresh rate mode.

[0040] After receiving the input signal from the system-on-a-chip 101, the driving unit 103 performs scaling processing on its horizontal pixel data. This scaling processing aims to expand the original M1 horizontal pixels into 2M1 horizontal pixels, thereby outputting a row of data containing 2M1×N1 pixels. Horizontal pixel data scaling can be implemented using various image processing algorithms.

[0041] After receiving the 2M1×N1 pixel data per row output by the driving unit 103, the timing controller 102 utilizes the specific structure of the display panel 104—that is, each group of gate lines contains two gate lines and can drive two rows of pixels simultaneously—to simultaneously send the pixel data to the corresponding two rows of pixels on the display panel 104. In this way, the timing controller 102 effectively expands the number of pixels in the vertical direction from N1 to 2N1. Ultimately, the resolution of the target data displayed on the display panel 104 reaches 2M1×2N1, while the refresh rate remains at R1. The mechanism of simultaneously driving two rows of pixels is key to doubling the vertical resolution, enabling the display panel 104 to present a higher vertical pixel density without increasing the input signal refresh rate.

[0042] This application clarifies the precise conversion path from the input signal source to the final display effect in quadruple frequency mode. By defining the initial resolution M1×N1 and the refresh rate R1, the driving unit 103 scales the horizontal pixel data to output 2M1×N1 pixel data, and the timing controller 102 uses the dual-gate line structure of the display panel 104 to send each line of data to two lines of pixels simultaneously, thereby enabling the display panel 104 to achieve a target resolution of 2M1×2N1 while maintaining the refresh rate R1. In this way, the display device can effectively convert a lower resolution input signal into a display output with a higher effective resolution while keeping the total bandwidth of the system-on-a-chip 101 unchanged, thus significantly improving the detail and clarity of the displayed content.

[0043] In some embodiments of this application, how to efficiently and accurately control the turn-on timing of the gate lines when actually writing pixel data to the display panel 104, so as to ensure that the data can be stably and completely written to the corresponding two rows of pixels, while avoiding crosstalk or display abnormalities, is a technical problem that needs to be solved.

[0044] Based on this, in one embodiment, the timing controller 102 is further configured to write 2M1×N1 pixel data to two rows of pixels on the display panel 104 by simultaneously turning on two sets of gate lines or by staggering the turn-on times of two adjacent sets of gate lines by a preset frame period; the turn-on time is determined based on N1 and R1.

[0045] When writing 2M1×N1 pixel data to two rows of pixels on the display panel 104, the timing controller 102 can employ one of two strategies. The first strategy is to "simultaneously activate two sets of gate lines." This method allows the timing controller 102 to activate two sets of gate lines at the same time. Since each set of gate lines on the display panel 104 contains two gate lines, activating two sets of gate lines simultaneously means that four gate lines are activated at the same time. This allows the timing controller 102 to write pixel data in parallel to the four rows of pixels controlled by the two sets of gate lines. The timing controller 102 can be designed with multiple independent gate line drive channels, each controlling one set of gate lines. When it is necessary to activate two sets of gate lines simultaneously, the timing controller 102 sends synchronous enable signals to the corresponding two gate line drive channels, activating the two sets of gate lines within the same clock cycle. Parallel writing significantly improves data writing efficiency, especially suitable for scenarios requiring rapid refresh or processing of large amounts of pixel data.

[0046] The second strategy is to "stagger the turn-on times of two adjacent groups of gate lines by a preset frame period". This method can be that the timing controller 102 does not turn on the two groups of gate lines completely synchronously, but instead allows the turn-on times of two adjacent groups of gate lines (e.g., the i-th group and the (i+1)-th group of gate lines) to have a preset time interval, i.e., a preset frame period.

[0047] In this application, the timing controller 102 can flexibly select the gate line activation strategy according to actual needs when writing pixel data in quadruple frequency mode. When two sets of gate lines are activated simultaneously, the parallel writing efficiency of pixel data can be significantly improved, and the overall data writing time can be shortened, thereby better supporting the display requirements of high resolution and high refresh rate. This ensures that the display panel 104 can stably and smoothly display the target data with a resolution of 2M1×2N1 and a refresh rate of R1 in quadruple frequency mode. On the other hand, when the activation time of two adjacent sets of gate lines is staggered by a preset frame period, the instantaneous current load of the gate line driving circuit can be effectively distributed, reducing the risk of power supply noise and signal interference. This improves the signal integrity and display stability of the display panel 104 and avoids display abnormalities or screen flickering caused by instantaneous large current. In addition, the activation time can be accurately determined based on the vertical resolution N1 and refresh rate R1 of the display panel 104, ensuring that the gate line activation pulse width and timing delay are highly matched with the display mode. This optimizes the writing quality of pixel data, ensures that the pixel capacitor can be fully charged, avoids undervoltage or overvoltage writing, and ultimately improves the uniformity and visual effect of the displayed image. The gate line control strategy enables the display device to achieve high resolution and high refresh rate display in a more efficient and stable manner in quadruple frequency mode, effectively solving the balance problem between pixel data writing efficiency and display stability.

[0048] In some embodiments of this application, how to ensure that the system-on-a-chip 101 can perform adaptive processing on the input signal source in double frequency mode, and that the timing controller 102 can efficiently drive the display panel 104 to achieve the desired resolution and refresh rate while keeping the total system bandwidth unchanged, is an issue that needs further consideration.

[0049] Based on this, in one embodiment, at least two display modes also include a double-frequency mode; the initial resolution of the double-frequency mode is M2×N2, and the initial refresh rate is R2; the system-on-a-chip 101 is further configured to scale the horizontal pixel data in the input source of the double-frequency mode when the target display mode is switched to the double-frequency mode, and output a row of 2M2×N2 pixel data; the timing controller 102 is further configured to simultaneously send each row of pixel data in the 2M2×N2 pixel data to the corresponding two rows of pixels in the display panel 104 through two gate lines in a set of gate lines, so as to drive the display panel 104 to display data, so that the resolution of the target data displayed by the display panel 104 is 2M2×2N2 and the refresh rate is R2.

[0050] The double-frequency mode can be a specific operating state supported by the display device. In this mode, the display device processes the input raw video signal to achieve a resolution increase relative to the original signal, typically manifested as doubling the number of pixels in the horizontal and / or vertical directions. Similar to the quadruple-frequency mode, the double-frequency mode aims to optimize the display effect, but may be suitable for different input signal characteristics or user needs, such as when the input source has a low resolution but requires a higher resolution display. "Initial resolution M2×N2" indicates that in the double-frequency mode, the system-on-chip 101 receives M2 horizontal pixels and N2 vertical pixels from the original input source. "Initial refresh rate R2" indicates the refresh frequency of the original input source.

[0051] When the target display mode switches to double-frequency mode, the system-on-chip 101 receives an input signal source with a resolution of M2×N2. To achieve a higher display resolution, the system-on-chip 101 scales the horizontal pixel data of the input signal source. Specifically, the system-on-chip 101 uses interpolation, pixel duplication, or other image processing algorithms to expand each row of M2 pixels into 2M2 pixels, thereby doubling the number of pixels horizontally. After this processing, the pixel data output by the system-on-chip 101 logically represents a data stream with 2M2 horizontal pixels and N2 vertical pixels, preparing for the subsequent timing controller 102 to drive the display panel 104.

[0052] The timing controller 102 receives a row of 2M²×N² pixel data processed by the system-on-a-chip 101. To further improve the vertical resolution of the display panel 104, the timing controller 102 utilizes the special structure of the display panel 104, namely, each group of gate lines contains two gate lines, and can simultaneously drive the corresponding two rows of pixels on the display panel 104. The timing controller 102 writes each row of 2M²×N² pixel data output by the system-on-a-chip 101 into two adjacent physical rows of the display panel 104 by simultaneously activating two gate lines in one group of gate lines. The parallel writing method allows the data of one logical row to fill two physical rows simultaneously, thereby doubling the number of pixels in the vertical direction. After the horizontal scaling processing of the system-on-a-chip 101 (M² becomes 2M²) and the vertical dual-row driving of the timing controller 102 (N² becomes 2N²), the final resolution of the target data displayed by the display panel 104 will reach 2M²×2N².

[0053] In this application, the display device, in addition to supporting the quadruple frequency mode, further expands its support to the double frequency mode. When the target display mode switches to the double frequency mode, the system-on-chip 101 can intelligently scale the horizontal pixel data of the input signal source, increasing the horizontal resolution from M2 to 2M2. Subsequently, the timing controller 102 utilizes the dual-gate line structure of the display panel 104 to simultaneously write each horizontally scaled row of pixel data into two physical rows of the display panel 104, thereby increasing the vertical resolution from N2 to 2N2. Finally, the display panel 104 can display the target data with a resolution of 2M2×2N2 and a refresh rate of R2. This processing method effectively improves the display resolution of the display panel 104 while maintaining the total bandwidth of the system-on-chip 101, providing users with a clearer and more detailed visual experience. It also enhances the compatibility and adaptability of the display device to input signal sources of different resolutions, enabling the display device to flexibly respond to various display needs.

[0054] In some embodiments of this application, the display device may need to be compatible with multiple display modes, including conventional display modes that do not require complex processing, in order to adapt to the needs of different input sources and avoid unnecessary processing overhead or compatibility issues.

[0055] Based on this, in one embodiment, at least two display modes also include a normal mode; the system-on-a-chip 101 is further configured to transmit the input signal source of the normal mode to the driving unit 103 when the target display mode is switched to the normal mode; the timing controller 102 is further configured to write each row of pixel data in the input signal source to each row of pixels of the display panel 104 through a gate line to drive the display panel 104 to display.

[0056] Specifically, the normal mode can be a working mode in which the display device receives and displays data according to the standard display timing and resolution without performing special image processing (such as scaling, data cloning, etc.). This mode corresponds to the original resolution and refresh rate of the display panel 104, or directly matches the resolution and refresh rate of the input signal source, without the need for complex conversion.

[0057] When the target display mode switches to the normal mode, the system-on-a-chip 101, as the core processing unit of the display device, is responsible for receiving external input sources and performing preliminary processing and scheduling according to the current target display mode. At this time, the system-on-a-chip 101 directly transmits the received raw input source data (i.e., the input source in the normal mode) to the driving unit 103 without performing the preprocessing required in the quadruple frequency mode, such as horizontal pixel data scaling or data cloning.

[0058] Based on this, the timing controller 102, as a key component responsible for generating the driving timing signals of the display panel 104, receives pixel data from the driving unit 103 in the normal mode and drives the corresponding single row of pixels to display through a single gate line in the display panel 104 in a standard line-by-line scanning manner.

[0059] As an example, Figure 3 This is a third schematic diagram of a display device provided for an embodiment of this application. Figure 3 As shown, at least two display modes include a quadruple refresh rate mode, a double refresh rate mode, and a normal mode. In the quadruple refresh rate mode, the input source resolution is 2K1K 300Hz; in the driver unit, through Data H-scaling, the output signal becomes 4K1K 300Hz; in the timing controller, by outputting DLG timing, two lines of Gate signals are simultaneously opened, allowing data from one line of pixels to be sent to two lines of pixels simultaneously, achieving a 4K2K 300Hz display on the display panel. By integrating the Data H-scaling function into the final Driver, the total bandwidth of the front-end SOC and Tcon remains unchanged at a 4x refresh rate, with only the bandwidth at the Driver output increasing, without affecting the Driver's own refresh rate. This allows the display device to achieve normal, double refresh rate, and quadruple refresh rate tri-mode display without increasing its refresh rate or cost. For example, in 4x frequency multiplication mode, the Tcon needs to support DLG timing, and the Driver needs to support DCT functionality. Vertical timing processing: The Tcon outputs DLG timing by opening two gate lines or offsetting them by 0.5H to double the refresh rate. Horizontal data processing: The driver unit doubles the refresh rate through horizontal Data H-Scaling. The input signal source changes from 2k1k to a 4K2K link on the display panel, as shown... Figure 4 As shown, Figure 4This is a schematic diagram of the link in this embodiment of the application, showing how the input signal source changes from 2K1K to 4K2K on the display panel.

[0060] In this application, the display device can flexibly adapt to input sources with different performance requirements. When the input source is a standard signal or does not require high refresh rate processing, the system-on-a-chip 101 can directly transmit the original source to the driving unit 103, and the timing controller 102 drives the display panel 104 by writing line by line with a single gate line, thereby avoiding unnecessary complex image processing (such as scaling and data cloning) in the normal mode, and reducing system power consumption and processing latency.

[0061] In some embodiments of this application, if all pixels are simply copied or uniformly interpolated without distinction, unnecessary loss of detail may be introduced in smooth areas of the image, or obvious blockiness and jaggedness may be generated in edge areas, thereby affecting the overall visual quality of the displayed image.

[0062] Based on this, in one embodiment, when the driving unit 103 doubles the horizontal refresh rate through data cloning technology, when the difference in grayscale values ​​between adjacent pixels in the same horizontal row of the input source is less than a preset threshold, a direct pixel data copying method is used to copy the data of the previous pixel in the adjacent pixels to the position of the pixel to be supplemented between the two pixels in the same horizontal row, so as to generate pixel data consistent with the number of pixels in the horizontal direction of the reference resolution of the display panel 104; when the difference in grayscale values ​​between adjacent pixels is greater than or equal to the preset threshold, linear interpolation is used to generate transition pixel data, and based on the grayscale values ​​of two adjacent original pixels in the same horizontal row, the grayscale value of the pixel to be supplemented between the two original pixels is calculated, so as to generate pixel data consistent with the number of pixels in the horizontal direction of the reference resolution.

[0063] Specifically, in quadruple refresh rate mode, the drive unit 103 needs to process the horizontal pixel data of the input source using data cloning technology to generate more pixel data, thereby doubling the horizontal refresh rate without increasing the original data transmission bandwidth. The difference in grayscale values ​​between adjacent pixels in the same horizontal row of the input source can be the difference in grayscale values ​​(e.g., brightness, color components) between any two adjacent pixels in the same horizontal row of the input source. The magnitude of this difference is a key basis for judging the characteristics of local image regions (such as smooth regions or edge regions). The preset threshold is a pre-set value used to compare the grayscale value differences between adjacent pixels. By comparing the actual grayscale value difference with this threshold, it can intelligently determine whether the current region belongs to a region with gradual grayscale changes (difference less than the threshold) or a region with drastic grayscale changes (difference greater than or equal to the threshold), thereby selecting different pixel data generation strategies. When the grayscale value difference between adjacent pixels is small, it indicates that the region belongs to a smooth or uniform region.

[0064] In this application, when the driving unit 103 performs data cloning to double the horizontal refresh rate, it can adaptively select a pixel data generation strategy based on the local characteristics of the image content. For areas with gentle grayscale changes, a direct copying method is used, effectively avoiding unnecessary computational resource consumption and maintaining the smoothness and consistency of the image. For edge areas with drastic grayscale changes, a linear interpolation method is used to generate transition pixel data, thereby effectively smoothing the edges, reducing the blockiness and jaggedness that may be caused by simple copying, and significantly improving the visual quality and detail of the displayed image.

[0065] In some embodiments of this application, the characteristics of the input source (such as resolution and refresh rate) may change dynamically. If there is no effective mechanism to automatically identify the changes and adjust the display mode accordingly, the display device may be unable to work according to the optimal characteristics of the input source, thereby affecting the display effect or requiring manual intervention to switch modes, reducing the user experience and the degree of system automation.

[0066] Based on this, in one embodiment, the display device further includes a mode detection module for identifying the resolution, refresh rate, and data transmission bandwidth of the input signal source, obtaining the identification result, and determining the target display mode based on the identification result. Specifically, when the resolution of the input signal source is half of the reference resolution of the display panel 104 and the refresh rate is four times the reference refresh rate of the display panel 104, the target display mode is switched to the quadruple refresh rate mode; when the resolution of the input signal source is half of the reference resolution and the refresh rate is twice the reference refresh rate, the target display mode is switched to the double refresh rate mode.

[0067] Specifically, the pattern detection module monitors and analyzes various parameters of the input signal source entering the display device in real time. The pattern detection module can be a standalone hardware circuit.

[0068] Specifically, when the resolution of the input signal source is half of the reference resolution of the display panel 104 and the refresh rate is four times the reference refresh rate of the display panel 104, the mode detection module switches the target display mode to the quadruple refresh rate mode; when the resolution of the input signal source is half of the reference resolution and the refresh rate is twice the reference refresh rate, the mode detection module switches the target display mode to the double refresh rate mode.

[0069] The display device described in this application can automatically identify key parameters of the input signal source, such as resolution, refresh rate, and data transmission bandwidth, and intelligently determine and switch to the most suitable target display mode according to preset rules. This automated mode detection and switching mechanism avoids the need for manual intervention and significantly improves the intelligence level of the display device and the user experience.

[0070] In some implementations, if a single, indiscriminate processing method is used when scaling and cloning pixel data, it may lead to a decrease in image quality, such as blurring of edge areas or obvious blockiness due to pixel repetition in smooth transition areas, thereby affecting the user's visual experience.

[0071] Based on this, in one embodiment, the driving unit 103 further includes: an analysis module, a classification module, and an execution module; wherein, the analysis module is used to analyze the difference information between the pixel to be processed and its adjacent pixels; the classification module is used to determine whether there is an edge region in the current area of ​​the target display mode based on the difference information; the execution module is used to process the edge region by adopting a first strategy of preserving edge sharpness during the horizontal pixel data scaling process when there is an edge region in the current area, and to process the transition area in the current area other than the edge region by adopting a second strategy of eliminating the blocky feeling caused by pixel repetition during the horizontal pixel data scaling process, so as to improve the visual quality of the current area.

[0072] Specifically, the analysis module can compare the grayscale values, color components, or brightness values ​​of the currently processed pixel and its neighboring pixels to quantify the degree of similarity or difference between them. For example, if the difference between neighboring pixels exceeds a certain threshold, the region may be identified as an edge region; conversely, it may be identified as a transition region.

[0073] The execution module processes edge regions in the current region using a first strategy to preserve edge sharpness during horizontal pixel data scaling, and processes transition regions (excluding edge regions) in the current region using a second strategy to eliminate blockiness caused by pixel repetition during horizontal pixel data scaling, thereby improving the visual quality of the current region. Based on the classification module's judgment, the execution module employs different processing strategies for different types of regions (edge ​​regions and transition regions). When edge regions exist in the current region, the execution module applies the first strategy aimed at preserving edge sharpness to ensure that image details are not blurred. Simultaneously, for transition regions (excluding edge regions) in the current region, the execution module applies the second strategy aimed at eliminating blockiness caused by pixel repetition to improve overall visual smoothness.

[0074] This application significantly improves the visual quality of the display area by scaling and cloning the horizontal pixel data of the input source to double the horizontal refresh rate. Specifically, through the accurate identification of pixel difference information by the analysis module, the classification module can intelligently distinguish edge regions and transition regions in the image. Based on this, the execution module selectively processes the edge regions using a first strategy to preserve edge sharpness, effectively avoiding edge blurring and ensuring clear presentation of image details. Simultaneously, it processes the transition regions using a second strategy to eliminate the blocky appearance caused by pixel repetition, making the transitions in smooth areas more natural and eliminating blocky artifacts that may result from simple data copying. This segmented and differentiated processing method allows the display device to achieve high refresh rates and resolution while maintaining image detail and overall smoothness, thus providing users with a clearer and more comfortable visual experience.

[0075] In some implementations, if the specific implementation of the first and second strategies is not refined enough, the sharpness of the edge area may not be effectively maintained during the horizontal pixel data scaling process, or a blocky feeling may occur in the transition area due to pixel repetition, thereby affecting the overall display effect.

[0076] Based on this, in one embodiment, the first strategy includes a copy strategy or a weighted strategy; the second strategy includes a fusion strategy; the execution module is further configured to: process pixels in the edge region using the copy strategy or the weighted strategy to maintain edge sharpness; and process pixels in the transition region using the fusion strategy to eliminate blockiness.

[0077] The copying strategy aims to maintain edge sharpness by directly copying pixel data. Specifically, when the execution module identifies an edge region, it can directly copy the data of the edge pixels to their adjacent pixels to be supplemented, ensuring that the clarity and detail of the edge lines are not blurred due to scaling. This method is suitable for scenarios that require a high degree of preservation of the original image details. The weighted strategy performs a weighted average of the pixels in the edge region and their neighboring pixels to achieve a certain degree of smooth transition while maintaining edge sharpness.

[0078] This application, through the driving unit 103, can selectively select and apply different processing strategies based on the characteristics of the image content when scaling the horizontal pixel data of the input signal source. For edge regions in the image, a copying strategy or a weighting strategy can effectively maintain edge sharpness, avoid edge blurring or loss of detail, and thus preserve the image's clarity and structure. For transition regions in the image, a fusion strategy can eliminate the blockiness and unnatural transitions that may be caused by pixel scaling or data cloning, making the color and brightness changes of the image smoother and more continuous.

[0079] In some implementations, ensuring the accuracy and stability of data writing and avoiding display anomalies caused by improper timing control when driving dual gate lines simultaneously are technical challenges that need to be further addressed.

[0080] Based on this, in one embodiment, the timing controller 102 is also used to determine the clock repetition period parameter and drive parameter of the dual-gate timing of the timing control, and send each row of pixel data to the corresponding two rows of pixels on the display panel 104 simultaneously based on the clock repetition period parameter and drive parameter.

[0081] The clock repetition period parameter can be a time parameter used to control the periodicity of the dual-gate drive signal. Its determination requires comprehensive consideration of factors such as the refresh rate, resolution, and data transmission rate of the display panel 104 to ensure the synchronization and efficiency of data writing.

[0082] Based on the determined clock repetition period parameters and drive parameters, the timing controller 102 simultaneously sends each row of pixel data to the corresponding two rows of pixels on the display panel 104. Specifically, the timing controller 102 generates a precise gate line drive clock signal according to the clock repetition period parameters, and generates two synchronous or gate line enable signals with a specific phase relationship according to the drive parameters, controlling two gate lines in a set of gate lines respectively. Simultaneously, the data line drive signal is precisely synchronized with the gate line enable signal, ensuring that within the effective time of gate line enable, the correct pixel data can be written in parallel to the corresponding two rows of pixels on the display panel 104. This guarantees the accuracy and stability of data writing, thereby achieving efficient simultaneous updating of the two rows of pixels.

[0083] As an example, Figure 5 A timing diagram of the normal mode provided for embodiments of this application; as shown. Figure 5 As shown; Figure 6 Timing diagram of the second harmonic mode provided for embodiments of this application; as shown Figure 6 As shown; Figure 7 A timing diagram of the fourth harmonic mode provided for embodiments of this application; as shown below. Figure 7 As shown.

[0084] This application, by precisely determining the clock repetition period parameters and drive parameters of the dual-gate-line timing control, enables the timing controller 102 to generate highly synchronized gate line and data line drive signals that match the characteristics of the display panel 104. This ensures that, in the dual-gate-line simultaneous drive mode, each row of pixel data can be accurately and stably written to the corresponding two rows of pixels on the display panel 104, effectively avoiding problems such as display flickering, ghosting, or incomplete data writing caused by timing mismatch. This timing control not only improves the quality and stability of the displayed image but also optimizes the driving efficiency of the display panel 104, enabling efficient and high-quality image display in quadruple frequency mode.

[0085] This application also proposes a display method using the aforementioned display device. The method includes: receiving an input signal source for a target display mode via a system-on-a-chip (SoC); wherein the target display mode is one of at least two display modes, including a quadruple refresh rate mode; the total bandwidth of the SoC remains constant across the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution, and refresh rate of the display panel; when the target display mode is a quadruple refresh rate mode, scaling the horizontal pixel data of the input signal source is performed by a driving unit, and the horizontal refresh rate is doubled using data cloning technology to output pixel data that is timing-adapted to the timing of the timing controller; in the quadruple refresh rate mode, the timing controller simultaneously sends each row of pixel data sent by the driving unit to the corresponding two rows of pixels on the display panel via two gate lines in a set of gate lines to drive the display panel to display data.

[0086] The details of the display method can be found in the previous description of the display device, and will not be repeated here.

[0087] The display device and display method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. The above modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, characterized in that, It includes a system-on-a-chip, a timing controller, a drive unit, and a display panel that are connected in sequence. The display panel includes multiple data lines, multiple pixels and multiple sets of gate lines. Each data line is electrically connected to two columns of pixels located on both sides of the data line. Each row of pixels is electrically connected to a set of gate lines. Each set of gate lines includes two gate lines. The system-on-a-chip (SoC) is used to receive input signals from a target display mode; wherein the target display mode is one of at least two display modes, and the at least two display modes include a quadruple frequency mode; the total bandwidth of the SoC remains constant under the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution, and refresh rate of the display panel; The driving unit is used to scale the horizontal pixel data of the input signal source when the target display mode is the quadruple refresh rate mode, and to double the horizontal refresh rate through data cloning technology, so as to output pixel data that is time-adapted to the timing of the timing controller. The timing controller is used to simultaneously send each row of pixel data sent by the driving unit to the corresponding two rows of pixels on the display panel through two gate lines in the set of gate lines in the quadruple frequency mode, so as to drive the display panel to display data.

2. The display device according to claim 1, characterized in that, When the display mode of the display device switches between the at least two display modes, the output bandwidth of the output terminal of the driving unit changes with the switching of the display mode, and the rated bandwidth of the driving unit remains unchanged; the total bandwidth of the timing controller remains unchanged in the at least two display modes.

3. The display device according to claim 1, characterized in that, The initial resolution of the quadruple frequency mode is M1×N1, and the initial refresh rate is R1; The system-on-a-chip is also used to transmit the input signal source of the fourth frequency multiplier mode to the driving unit when the target display mode is switched to the fourth frequency multiplier mode; The driving unit is also used to scale the horizontal pixel data of the input signal source and output a row of 2M1×N1 pixel data. The timing controller is further configured to simultaneously send each row of pixel data in the 2M1×N1 pixel data to the corresponding two rows of pixels on the display panel through two gate lines in a set of gate lines, so as to drive the display panel to display data, so that the resolution of the target data displayed by the display panel is 2M1×2N1 and the refresh rate is R1.

4. The display device according to claim 3, characterized in that, The timing controller is further configured to write the 2M1×N1 pixel data to two rows of pixels on the display panel by simultaneously turning on two sets of the gate lines or by staggering the turn-on times of two adjacent sets of the gate lines by a preset frame period; the turn-on time is determined based on N1 and R1.

5. The display device according to claim 1, characterized in that, The at least two display modes also include a double refresh rate mode; the initial resolution of the double refresh rate mode is M2×N2, and the initial refresh rate is R2; The system-on-a-chip is also used to scale the horizontal pixel data in the input source of the double frequency mode when the target display mode is switched to the double frequency mode, and output a row of 2M2×N2 pixel data. The timing controller is further configured to simultaneously send each row of pixel data in the 2M2×N2 pixel data to the corresponding two rows of pixels on the display panel through two gate lines in a set of gate lines, so as to drive the display panel to display data, so that the resolution of the target data displayed by the display panel is 2M2×2N2 and the refresh rate is R2.

6. The display device according to claim 1, characterized in that, The at least two display modes also include a normal mode; the system-on-a-chip is further configured to transmit the input signal source of the normal mode to the driving unit when the target display mode is switched to the normal mode; The timing controller is further configured to write each row of pixel data from the input source to each row of pixels on the display panel through a gate line, thereby driving the display panel to display.

7. The display device according to claim 1, characterized in that, When the driving unit doubles the horizontal refresh rate using data cloning technology, if the difference in grayscale values ​​between adjacent pixels in the same horizontal row of the input source is less than a preset threshold, a direct pixel data copying method is used to copy the data of the previous pixel in the adjacent pixels to the position of the pixel to be supplemented between the two pixels in the same horizontal row, so as to generate pixel data consistent with the number of pixels in the horizontal direction of the reference resolution of the display panel; if the difference in grayscale values ​​between adjacent pixels is greater than or equal to the preset threshold, linear interpolation is used to generate transition pixel data, and the grayscale value of the pixel to be supplemented between the two original pixels is calculated based on the grayscale values ​​of the two original pixels in the same horizontal row, so as to generate pixel data consistent with the number of pixels in the horizontal direction of the reference resolution.

8. The display device according to claim 1, characterized in that, The display device further includes a mode detection module, used to identify the resolution, refresh rate, and data transmission bandwidth of the input signal source, obtain an identification result, and determine the target display mode based on the identification result. Specifically, when the resolution of the input signal source is half of the reference resolution of the display panel and the refresh rate is four times the reference refresh rate of the display panel, the target display mode is switched to the quadruple refresh rate mode; when the resolution of the input signal source is half of the reference resolution and the refresh rate is twice the reference refresh rate, the target display mode is switched to the double refresh rate mode.

9. The display device according to claim 1, characterized in that, The driving unit further includes: an analysis module, a classification module, and an execution module; wherein... The analysis module is used to analyze the difference information between the pixel to be processed and its neighboring pixels; The classification module is used to determine whether there is an edge region in the current area of ​​the target display mode based on the difference information; The execution module is configured to, when the edge region exists in the current region, process the edge region using a first strategy that preserves edge sharpness during horizontal pixel data scaling, and process the transition region in the current region other than the edge region using a second strategy that eliminates blockiness caused by pixel repetition during horizontal pixel data scaling, so as to improve the visual quality of the current region.

10. The display device according to claim 9, characterized in that, The first strategy includes a replication strategy or a weighted strategy; the second strategy includes a fusion strategy; the execution module is further configured to: The pixels in the edge region are processed using the copying strategy or the weighting strategy to maintain the edge sharpness; and the pixels in the transition region are processed using the fusion strategy to eliminate the blocky appearance.

11. The display device according to any one of claims 1-10, characterized in that, The timing controller is further configured to determine the clock repetition period parameter and drive parameter of the dual-gate timing of the timing control, and based on the clock repetition period parameter and the drive parameter, simultaneously send the pixel data of each row to the two rows of pixels corresponding to the display panel.

12. A display method, characterized in that, The method of using the display device according to any one of claims 1-11 includes: The system-on-a-chip (SoC) receives input signals for a target display mode; wherein the target display mode is one of at least two display modes, including a quadruple refresh rate mode; the total bandwidth of the SoC remains constant under the at least two display modes, and the total bandwidth is the product of the horizontal resolution, vertical resolution, and refresh rate of the display panel; When the target display mode is the quadruple refresh rate mode, the horizontal pixel data of the input signal source is scaled by the driving unit, and the horizontal refresh rate is doubled by data cloning technology, so as to output pixel data that is time-adapted to the timing of the timing controller. In the quadruple frequency mode, the timing controller sends each row of pixel data sent by the driving unit to the corresponding two rows of pixels on the display panel through two gate lines in a set of gate lines, so as to drive the display panel to display data.

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