Inductor current-limiting protection circuit and method, DC-DC converter and chip

Abstract

The invention provides an inductor current-limiting protection circuit and method, a DC-DC converter and a chip, and relates to the technical field of DC-DC converters. The inductor current-limiting protection circuit comprises a slope timing circuit which starts timing when a high-side switching tube turn-off signal is detected after the DC-DC converter triggers inductor overcurrent protection, and determines a slope timing voltage based on a target voltage and a preset slope coefficient during the timing period; a reference voltage generating circuit generating a reference voltage according to a power supply voltage and an output voltage of the DC-DC converter; when the slope timing voltage is greater than or equal to the reference voltage, the first comparator determines that the timing time of the slope timing circuit reaches the low-side target conduction time and indicates the low-side switching tube driving control module to control the low-side switching tube of the DC-DC converter to be switched off; the low-side target conduction time is the conduction time of the low-side switching tube in a steady state before the DC-DC converter triggers inductor overcurrent protection. The LS conduction duration can be controlled after the DC-DC converter triggers overcurrent protection, and the method is simple and easy to implement.

Description

Technical Field

[0001] This application relates to the field of DC-DC converter technology, and more particularly to an inductor current limiting protection circuit, method, DC-DC converter, and chip. Background Technology

[0002] A DC-DC converter is a device that converts electrical energy from one voltage value to another in a DC circuit. During operation, if the current flowing through the inductor exceeds its rated value, the inductor will experience magnetic saturation, causing a sharp drop in its inductance value, and may even burn out due to overheating. Therefore, DC-DC converters are typically designed with inductor current overcurrent protection circuits. When the inductor current reaches the protection value, inductor magnetization is stopped, and demagnetization begins. Taking a buck DC-DC converter as an example, during the high-side (HS) switching period (HS period), the inductor current rises. When the inductor current overcurrent protection is triggered, the HS switching transistor is turned off, and the low-side (LS) switching transistor is turned on, causing the inductor current to decrease and the inductor to demagnetize. In this process, the HS phase ends when the inductor overcurrent protection is triggered, while the LS phase ends when the inductor has been demagnetized. Otherwise, the inductor current during the next HS phase will rise above the current limit value due to the inductor current overcurrent protection needing to detect the current, thus failing to achieve the current limiting effect.

[0003] Therefore, controlling the LS conduction time after the DC-DC converter triggers overcurrent protection is particularly important and is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides an inductor current limiting protection circuit, method, DC-DC converter, and chip to control the LS conduction time after the DC-DC converter triggers overcurrent protection.

[0005] In a first aspect, this application provides an inductor current limiting protection circuit for use in a DC-DC converter. The inductor current limiting protection circuit includes a ramp timing circuit, a reference voltage generation circuit, and a first comparator. The ramp timing circuit is used to start timing after the DC-DC converter triggers inductor overcurrent protection and detects a high-side switch turn-off signal. During the timing period, it determines a ramp timing voltage based on the input target voltage and a preset ramp coefficient, and inputs the ramp timing voltage to the non-inverting input of the first comparator. The target voltage is the power supply voltage or output voltage of the DC-DC converter, and is determined based on the architecture of the DC-DC converter. The preset ramp coefficient is determined based on the operating cycle of the DC-DC converter. The reference voltage generation circuit is used to generate a reference voltage based on the power supply voltage and output voltage of the DC-DC converter, and input the reference voltage to the negative input terminal of the first comparator; The output of the first comparator is used to connect to the low-side switch drive control module of the DC-DC converter. The first comparator is used to compare the ramp timing voltage with the reference voltage. When the ramp timing voltage is greater than or equal to the reference voltage, a high-level signal is output to the low-side switch drive control module to instruct the low-side switch drive control module to control the low-side switch of the DC-DC converter to turn off. Wherein, when the ramp timing voltage is greater than or equal to the reference voltage, the timing time of the ramp timing circuit reaches the low-side target conduction time; the low-side target conduction time is the conduction time of the low-side switch in steady state before the DC-DC converter triggers the inductor overcurrent protection.

[0006] In one alternative design, the DC-DC converter is an improved BUCK converter; the improved BUCK converter includes a first switch, a second switch, a third switch, a fourth switch, a switching capacitor, an inductor, and an output capacitor; The drain of the first switching transistor serves as the power supply voltage input terminal of the DC-DC converter for connection to a DC voltage source. The source of the first switching transistor is connected to the drain of the second switching transistor. The second switching transistor is connected to the drain of the third switching transistor through the inductor. The source of the third switching transistor is connected to the drain of the fourth switching transistor. The source of the fourth switching transistor is connected to ground. The conversion capacitor is connected between the drain of the second switch and the drain of the fourth switch, the drain of the third switch is connected to ground through the output capacitor, and the drain of the third switch serves as the voltage output terminal of the DC-DC converter. The first switch, the second switch, and the third switch serve as the high-side switches of the DC-DC converter and are simultaneously turned on during high-side operation; the second switch and the fourth switch serve as the low-side switches of the DC-DC converter and are simultaneously turned on during low-side operation. Wherein, the target voltage is the output voltage output from the voltage output terminal of the DC-DC converter; the low-side target conduction time is the value of the DC-DC converter's operating cycle multiplied by the target voltage difference and divided by the output voltage of the DC-DC converter; and the target voltage difference is the difference between the power supply voltage and the output voltage of the DC-DC converter.

[0007] In an alternative design, the ramp timing circuit includes a second comparator, a first P-type MOSFET, a second P-type MOSFET, a third P-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a sixth N-type MOSFET, a first resistor, and a first capacitor; The non-inverting input of the second comparator serves as the target voltage input of the ramp timing circuit and is connected to the voltage output of the DC-DC converter; the inverting input of the second comparator is connected to the source of the fourth N-type MOSFET and is connected to ground through the first resistor; the output of the second comparator is connected to the gate of the fourth N-type MOSFET, and the drain of the fourth N-type MOSFET is connected to the drain of the first P-type MOSFET. The drain, gate, gate, and gate of the first P-type MOS transistor are connected; the source, source, and source of the third P-type MOS transistor are all connected to the analog power supply voltage; the drain of the second P-type MOS transistor is connected to the drain of the fifth N-type MOS transistor, and the drain of the fifth N-type MOS transistor is connected to the gate of the fifth N-type MOS transistor; the source of the fifth N-type MOS transistor is connected to ground. The drain of the third P-type MOS transistor is connected to ground through the first capacitor, and after being connected to the drain of the sixth N-type MOS transistor, it serves as the output terminal of the ramp timing circuit and is connected to the non-inverting input terminal of the first comparator; the source of the sixth N-type MOS transistor is connected to ground, and the gate of the sixth N-type MOS transistor serves as the detection terminal of the ramp timing circuit for detecting the high-side switch transistor turn-off signal. When the high-side switch transistor is turned off at the detection terminal of the ramp timing circuit, the sixth N-type MOSFET is turned off. When the sixth N-type MOSFET is turned off, the ramp timing circuit starts timing. During the timing period, the ramp timing voltage output by the output terminal of the ramp timing circuit rises at a first target slope until the ramp timing voltage is greater than or equal to the reference voltage, at which point the sixth N-type MOSFET turns on, and the timing ends. The first target slope is the ratio of the output voltage of the DC-DC converter to the preset slope coefficient, and the preset slope coefficient is the product of the resistance value of the first resistor and the capacitance value of the first capacitor.

[0008] In one alternative design, the reference voltage generation circuit includes a second resistor, a third resistor, a fourth resistor, and a seventh N-type MOS transistor; One end of the second resistor serves as the second input terminal of the reference voltage generation circuit and is connected to the power supply voltage input terminal of the DC-DC converter. The other end is connected to ground through the third resistor and to the first end of the fourth resistor. The second end of the fourth resistor is connected to the drain of the seventh N-type MOS transistor and then serves as the output terminal of the reference voltage generation circuit and is connected to the negative phase input terminal of the first comparator. The source of the seventh N-type MOS transistor is connected to ground, and the gate of the seventh N-type MOS transistor is connected to the drain of the fifth N-type MOS transistor. The reference voltage output from the output terminal of the reference voltage generation circuit is the product of the voltage difference between the power supply voltage and the output voltage of the DC-DC converter and the reference voltage coefficient; the reference voltage coefficient is determined based on the resistance values ​​of the second resistor and the third resistor.

[0009] In one alternative design, the resistance of the second resistor is three times that of the third resistor, and the reference voltage coefficient is 1 / 4.

[0010] In one alternative design, the DC-DC converter is a basic architecture-type BUCK converter; the target voltage is the power supply voltage of the DC-DC converter; the low-side target on-time is the value of the DC-DC converter's duty cycle multiplied by the target voltage difference and divided by the DC-DC converter's power supply voltage, and the target voltage difference is the difference between the DC-DC converter's power supply voltage and its output voltage.

[0011] In one optional design, the ramp timing circuit includes a third comparator, an eighth P-type MOSFET, a ninth P-type MOSFET, a tenth N-type MOSFET, an eleventh N-type MOSFET, a second capacitor, and a fifth resistor; the preset slope coefficient is the product of the resistance value of the fifth resistor and the capacitance value of the second capacitor. The non-inverting input of the third comparator serves as the target voltage input of the ramp timing circuit and is connected to the power supply voltage input of the DC-DC converter; the inverting input of the third comparator is connected to the source of the tenth N-type MOSFET and is connected to ground through the fifth resistor; the output of the third comparator is connected to the gate of the tenth N-type MOSFET, and the drains of the tenth N-type MOSFET, the drains of the eighth P-type MOSFET, the gates of the eighth P-type MOSFET, and the gates of the ninth P-type MOSFET are connected; the sources of the eighth P-type MOSFET and the ninth P-type MOSFET are connected to the analog power supply voltage. The drain of the ninth P-type MOS transistor is connected to ground through the second capacitor, and after being connected to the drain of the eleventh N-type MOS transistor, it serves as the output terminal of the ramp timing circuit and is connected to the non-inverting input terminal of the first comparator. The source of the eleventh N-type MOS transistor is connected to ground, and the gate of the eleventh N-type MOS transistor serves as the detection terminal of the ramp timing circuit to detect the high-side switch transistor turn-off signal. When the high-side switch transistor is turned off at the detection terminal of the ramp timing circuit, the eleventh-N type MOSFET is turned off. When the eleventh-N type MOSFET is turned off, the ramp timing circuit starts timing. During the timing period, the ramp timing voltage output by the output terminal of the ramp timing circuit rises with a second target slope until the ramp timing voltage is greater than or equal to the reference voltage, at which point the eleventh-N type MOSFET turns on, and the timing ends. The second target slope is the ratio of the power supply voltage of the DC-DC converter to the preset slope coefficient.

[0012] In one alternative design, the reference voltage generation circuit includes a twelfth P-type MOSFET, a thirteenth P-type MOSFET, a fourteenth N-type MOSFET, a fifteenth N-type MOSFET, a sixteenth N-type MOSFET, a fourth comparator, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; The positive input terminal of the fourth comparator serves as the first input terminal of the reference voltage generation circuit and is connected to the voltage output terminal of the DC-DC converter; the negative input terminal of the fourth comparator is connected to the source of the fourteenth N-type MOSFET and is connected to ground through the ninth resistor; the output terminal of the fourth comparator is connected to the gate of the fourteenth N-type MOSFET; the drain of the fourteenth N-type MOSFET, the drain of the twelfth P-type MOSFET, the gate of the twelfth P-type MOSFET, and the gate of the thirteenth P-type MOSFET are connected; the sources of the twelfth P-type MOSFET and the thirteenth P-type MOSFET are both connected to the analog power supply voltage. The drain of the thirteenth P-type MOS transistor, the drain of the fifteenth N-type MOS transistor, the gate of the fifteenth N-type MOS transistor, and the gate of the sixteenth N-type MOS transistor are connected, and the source of the fifteenth N-type MOS transistor and the source of the sixteenth N-type MOS transistor are both connected to ground. One end of the sixth resistor serves as the second input terminal of the reference voltage generation circuit and is connected to the power supply voltage input terminal of the DC-DC converter. The other end is connected to ground through the seventh resistor and to the first end of the eighth resistor. The second end of the eighth resistor is connected to the drain of the sixteenth N-type MOS transistor and serves as the output terminal of the reference voltage generation circuit, and is connected to the negative phase input terminal of the first comparator. The reference voltage output from the output terminal of the reference voltage generation circuit is the product of the voltage difference between the power supply voltage and the output voltage of the DC-DC converter and the reference voltage coefficient; the product of the reference voltage coefficient and the preset slope coefficient is equal to the operating cycle of the DC-DC converter.

[0013] Secondly, this application provides an inductor current limiting control method applied to a DC-DC converter, the inductor current limiting control method comprising: After the DC-DC converter triggers the inductor overcurrent protection, upon detecting the high-side switch turn-off signal, the low-side switch is controlled to turn on, and a timer is started. When the timing reaches the target conduction time of the low side, the low side switch is turned off. The low-side target conduction time is the conduction time of the low-side switch in steady state before the DC-DC converter triggers inductor overcurrent protection.

[0014] Thirdly, this application provides a DC-DC converter, including an inductor current limiting protection circuit as described in any one of the first aspects above.

[0015] Fourthly, this application provides a chip that includes an inductor current limiting protection circuit as described in any one of the first aspects above, or includes a DC-DC converter as described in the third aspect above.

[0016] Fifthly, this application provides an electronic device, characterized in that it includes an inductor current limiting protection circuit as described in any one of the first aspects above, or includes a DC-DC converter as described in the third aspect above, or includes a chip as described in the fourth aspect above.

[0017] The inductor current limiting protection circuit, method, DC-DC converter, and chip provided in this application control the high-side switch to turn off and the low-side switch to turn on after the DC-DC converter triggers inductor overcurrent protection. Timing begins at this point, and the low-side switch is turned off when the timing reaches the target low-side conduction time. The target low-side conduction time is the steady-state conduction time of the low-side switch before the DC-DC converter triggers inductor overcurrent protection. Thus, by directly setting the conduction time of the low-side switch to the steady-state conduction time before the DC-DC converter triggers inductor overcurrent protection, the conduction duration of the low-side switch after triggering overcurrent protection is controlled. The solution is simple and easy to implement, applicable to various DC-DC converters involving inductor demagnetization, and has a wide range of applications. Attached Figure Description

[0018] Figure 1This is a schematic diagram illustrating the principle of using a valley detection circuit to control the LS switch to turn off in related technologies. Figure 2 This is one of the structural schematic diagrams of the inductor current limiting protection circuit provided in the embodiments of this application; Figure 3 This is a second schematic diagram of the structure of the inductor current limiting protection circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the improved BUCK converter provided in the embodiments of this application; Figure 5 This is the third schematic diagram of the inductor current limiting protection circuit provided in the embodiments of this application; Figure 6 A schematic diagram illustrating the current limiting effect of the inductor current limiting protection circuit provided in the embodiments of this application; Figure 7 This is a flowchart illustrating the inductor current limiting control method provided in an embodiment of this application. Detailed Implementation

[0019] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c. a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] A DC-DC converter is a power electronic device that converts an input DC voltage into different output voltages using high-frequency switching technology. Its core principle is to control the charging and discharging process of an energy storage element by periodically switching the switching device on and off, achieving voltage step-up / step-down conversion by adjusting the duty cycle. Specifically, during the on-phase of the switch, the switching transistor is closed, and the input power supply charges the inductor, converting electrical energy into magnetic energy stored in the inductor, while simultaneously supplying power to the load. During the off-phase of the switch, the switching transistor is open, and the inductor releases the stored energy, supplying power to the load and output capacitor through diodes or synchronous rectifier diodes, maintaining a stable output voltage.

[0023] Inductors, as energy storage components in DC-DC converters, play a crucial role in the circuit. During operation, if the current flowing through the inductor exceeds its rated value, the inductor will experience magnetic saturation, leading to a sharp drop in its inductance value. It may even burn out due to overheating. Therefore, an inductor current overcurrent protection circuit is usually designed to stop magnetizing the inductor and begin demagnetizing it when the inductor current reaches the protection value.

[0024] A BUCK-type DC-DC converter is a converter whose output voltage is lower than its input voltage. It achieves voltage reduction by storing and releasing energy through an inductor and is widely used in power adapters, automotive electronics, and other fields.

[0025] For a BUCK-type DC-DC converter, the current flowing through the inductor rises during the conduction of the high-side switch (HS switch). When the inductor overcurrent protection is triggered, the HS switch turns off and the low-side switch (LS switch) turns on, causing the inductor current to decrease and the inductor to demagnetize. During this process, the turn-off of the HS switch is achieved by triggering the inductor overcurrent protection, while the turn-off of the LS switch requires ensuring that the inductor has completed demagnetization. Otherwise, during the next HS switch conduction cycle, the inductor current will rise above the current-limiting value due to the detection time required by the inductor overcurrent protection, thus failing to achieve the current-limiting effect. Therefore, controlling the LS conduction time after the DC-DC converter triggers the overcurrent protection is particularly important.

[0026] In related technologies, a valley current detection circuit and a comparator need to be designed to turn off the LS switch when the valley current threshold is triggered. For example, Figure 1 This diagram illustrates the principle of controlling the LS switch turn-off using a valley detection circuit in related technologies. In this diagram, ILOAD represents the load current, HS_ON represents the HS switch drive control signal, LS_ON represents the LS switch drive control signal, and IIND represents the inductor current. (Refer to...) Figure 1 As shown, after the DC-DC converter triggers overcurrent protection, the HS switch is turned off and the LS switch is turned on. The inductor begins to demagnetize, and the inductor current decreases. The valley current detection circuit converts the inductor current into a voltage. This voltage, together with the designed reference voltage, is used as the input of the comparator. When the inductor voltage is lower than the reference voltage, the comparator flips, and the LS switch ends its conduction state. This achieves the effect of ending the LS switch's conduction state only after the inductor has finished demagnetizing.

[0027] While this solution can achieve the effect of ending the LS switch's conduction state only after the inductor has been demagnetized, it requires the design of an inductor current detection circuit. This detection circuit needs to accurately reproduce the inductor current, making the circuit design relatively complex, requiring a large area, and resulting in high costs.

[0028] In view of this, this application provides a new LS switch conduction time control scheme. The conduction time of the LS switch after the DC-DC converter triggers inductor overcurrent protection is directly set to the steady-state conduction time of the LS switch before the DC-DC converter triggers inductor overcurrent protection. After the DC-DC converter triggers inductor overcurrent protection, the HS switch is controlled to turn off and the LS switch is turned on, and a timer is started. When the timer reaches the steady-state conduction time of the LS switch before the DC-DC converter triggers inductor overcurrent protection, the LS switch is turned off. This achieves effective protection of the inductor and eliminates the need to design a complex inductor current detection circuit to detect the inductor current. The scheme is simple.

[0029] For example, the LS switch conduction time control scheme provided in the embodiments of this application can be implemented by software, hardware, or a combination of software and hardware.

[0030] In this context, the high-side (HS) switch is the one connected to the positive terminal of the power supply. It is responsible for controlling the current flow from the input source to the load. When turned on, the HS switch transfers the input voltage to the output. The low-side (LS) switch is the one connected to ground or the negative terminal of the power supply. It is responsible for providing a freewheeling path or controlling the current return when turned off.

[0031] The following is combined with Figures 2-6The inductor current limiting protection circuit provided in the embodiments of this application will be described in detail. This inductor current limiting protection circuit can be applied to a DC-DC converter that involves inductor demagnetization, such as a basic BUCK converter, the improved BUCK converter provided in the embodiments of this application (described in detail below), or other architecture DC-DC converters that involve inductor demagnetization.

[0032] Figure 2 An exemplary schematic diagram of one of the inductor current limiting protection circuits provided in this application is shown, with reference to... Figure 2 As shown, the inductor current limiting protection circuit includes a ramp timing circuit 21, a reference voltage generation circuit 22, and a first comparator 23. The detection terminal SE of the ramp timing circuit 21 is used to detect the high-side switch turn-off signal. This detection terminal SE can be connected to the first drive control terminal of the high-side switch drive control module of the DC-DC converter. The high-side switch drive control module can control the on / off state of the high-side switch according to the high-side switch drive control signal input to its first drive control terminal. When the high-side switch drive control signal is a high-side switch turn-off signal (e.g., a low-level signal), the high-side switch is turned off; when the high-side switch drive control signal is a high-side switch turn-on signal (e.g., a high-level signal), the high-side switch is turned on. The target voltage input terminal IN of the ramp timing circuit 21 is used to input the target voltage, and the output terminal of the ramp timing circuit 21 is connected to the non-inverting input terminal of the first comparator 23. The first input terminal of the reference voltage generation circuit 22 can be connected to the voltage output terminal VOUT of the DC-DC converter, or it can be connected to a voltage terminal associated with the voltage output terminal VOUT of the DC-DC converter. Information related to the output voltage of the DC-DC converter can be obtained through this voltage terminal. The second input terminal of the reference voltage generation circuit 22 is connected to the power supply voltage input terminal VIN of the DC-DC converter. The output terminal of the reference voltage generation circuit 22 is connected to the negative inverting input terminal of the first comparator 23. The output terminal LS_TIMEOUT of the first comparator 23 is connected to the low-side switching transistor drive control module of the DC-DC converter.

[0033] The ramp timing circuit 21 is used to start timing after the DC-DC converter triggers inductor overcurrent protection and detects a high-side switch turn-off signal. During timing, the ramp timing voltage is determined based on the target voltage input at the target voltage input terminal IN and a preset ramp coefficient, and then input to the non-inverting input terminal of the first comparator 23. The target voltage input at the target voltage input terminal IN is the power supply voltage or output voltage of the DC-DC converter, and this target voltage is determined based on the architecture of the DC-DC converter. The preset ramp coefficient is determined based on the duty cycle of the DC-DC converter.

[0034] For example, when the DC-DC converter is the improved BUCK converter provided in the embodiments of this application, the target voltage input at the target voltage input terminal IN is the output voltage Vout output at the voltage output terminal of the DC-DC converter; when the DC-DC converter is a basic architecture type BUCK converter, the target voltage input at the target voltage input terminal IN is the power supply voltage Vin of the DC-DC converter.

[0035] The reference voltage generation circuit 22 is used to generate a reference voltage based on the power supply voltage and output voltage of the DC-DC converter, and input the reference voltage to the negative input terminal of the first comparator 23.

[0036] The first comparator 23 is used to compare the ramp timing voltage output by the ramp timing circuit 21 with the reference voltage output by the reference voltage generation circuit 22. When the ramp timing voltage is greater than or equal to the reference voltage, it outputs a high-level signal to the low-side switch drive control module to instruct the low-side switch drive control module to control the low-side switch of the DC-DC converter to turn off.

[0037] When the ramp timing voltage is greater than or equal to the reference voltage, the timing time of the ramp timing circuit 21 reaches the low-side target conduction time, which is the conduction time of the low-side switch in steady state before the DC-DC converter triggers the inductor overcurrent protection.

[0038] Those skilled in the art will understand that before the DC-DC converter triggers inductor overcurrent protection, the conduction times of the low-side and high-side switches of the DC-DC converter are determined by the control loop and eventually reach a steady state under the adjustment of the control loop. In this steady state, the conduction time of the low-side switch is determined, which can be based on the power supply voltage and output voltage of the DC-DC converter. Different DC-DC converters will correspond to different expressions. Therefore, based on the relationship between the conduction time of the low-side switch in steady state and the power supply voltage and output voltage of the DC-DC converter, the timing target of the conduction time of the low-side switch in steady state can be converted into a timing voltage, and related circuits can be designed to perform timing and turn-off control after the low-side switch is turned on.

[0039] The inductor current limiting protection circuit provided in this application includes a ramp timing circuit, a reference voltage generation circuit, and a first comparator. After the DC-DC converter triggers inductor overcurrent protection, the ramp timing circuit starts timing upon detecting a high-side switch turn-off signal. During the timing period, the ramp timing voltage is determined based on the target voltage input at the target voltage input terminal and a preset slope coefficient determined based on the DC-DC converter's operating cycle. The reference voltage generation circuit generates a reference voltage based on the DC-DC converter's power supply voltage and output voltage. The first comparator compares the ramp timing voltage output by the ramp timing circuit with the reference voltage output by the reference voltage generation circuit. If the ramp timing voltage is greater than or equal to the reference voltage, it determines that the timing time of the ramp timing circuit reaches the conduction time of the low-side switch in the steady state before the DC-DC converter triggers inductor overcurrent protection. At this time, the first comparator outputs a high-level signal to the low-side switch drive control module, instructing the low-side switch drive control module to control the low-side switch of the DC-DC converter to turn off. In this way, after the DC-DC converter triggers the inductor overcurrent protection, the conduction time of the low-side switch is directly set to the steady-state conduction time of the low-side switch before the DC-DC converter triggers the inductor overcurrent protection. This achieves control over the conduction time of the low-side switch after triggering the overcurrent protection. It eliminates the need to design a complex inductor current detection circuit to detect the inductor current of the DC-DC converter. The circuit is simple to implement, reduces the footprint and cost, and is applicable to various DC-DC converters involving inductor demagnetization, making it widely applicable.

[0040] In one embodiment of this application, Figure 2 The inductor current-limiting protection circuit provided in the corresponding embodiment can be applied to basic architecture-type BUCK converters, such as synchronous BUCK circuit structures. This synchronous BUCK circuit mainly includes a high-side switch, a low-side switch, an inductor, and an output capacitor. When the high-side switch is on and the low-side switch is off, the inductor stores energy, and the voltage on the side of the inductor connected to the high-side switch is higher than the voltage on the side connected to the output terminal, thus achieving voltage reduction. When the high-side switch is off and the low-side switch is on, the inductor releases energy to supply power to the load. The voltage reduction function can be achieved by controlling the alternating conduction of the high-side and low-side switches.

[0041] Combination Figure 2 When the DC-DC converter is a basic architecture BUCK converter, the target voltage input to the target voltage input terminal IN of the ramp timing circuit 21 is the power supply voltage Vin of the DC-DC converter, and the low-side target on-time CFT can be expressed as the following formula (1): (1) Where Vout is the output voltage of the DC-DC converter, and T is the duty cycle of the DC-DC converter.

[0042] That is, the low-side target on-time CFT is the product of the DC-DC converter's duty cycle T and the target voltage difference, divided by the DC-DC converter's supply voltage Vin. Here, the target voltage difference is the difference between the DC-DC converter's supply voltage Vin and its output voltage Vout.

[0043] According to formula (1), the timing target, which is the low-side target conduction time CFT, can be converted into a timing voltage, and a corresponding ramp timing circuit 21 and reference voltage generation circuit 22 can be designed. For example, a preset slope coefficient Y1 and reference voltage coefficient Y2 can be set according to the working period T of the DC-DC converter, so that the ramp timing voltage output by the ramp timing circuit 21 during the timing period rises with a slope of Vin / Y1, and the reference voltage output by the reference voltage generation circuit 22 is Y2×(Vin-Vout), where T=Y1×Y2, and Y2 is less than 1. When the ramp timing voltage rises to the reference voltage, the following relationship exists as shown in formula (2): (2) At this time, formula (2) is equivalent to formula (1), that is, when the ramp timing voltage rises to the reference voltage, it can be considered that the conduction time of the low-side switch has reached the low-side target conduction time CFT, and at this time the low-side switch of the DC-DC converter is turned off.

[0044] Based on this Figure 3 This is a second schematic diagram of the inductor current limiting protection circuit provided in an embodiment of this application. (Refer to...) Figure 3 As shown, the inductor current limiting protection circuit includes a ramp timing circuit 21, a reference voltage generation circuit 22, and a first comparator 23.

[0045] The ramp timing circuit 21 includes a third comparator A3, an eighth P-type metal-oxide-semiconductor field-effect transistor (MOS transistor) M8, a ninth P-type MOS transistor M9, a tenth N-type MOS transistor M10, an eleventh N-type MOS transistor M11, a second capacitor C2, and a fifth resistor R5.

[0046] The non-inverting input of the third comparator A3 serves as the target voltage input IN of the ramp timing circuit 21 and is connected to the power supply voltage input VIN of the DC-DC converter. The inverting input of the third comparator A3 is connected to the source of the tenth type N MOSFET M10 and is connected to ground GND through the fifth resistor R5. The output of the third comparator A3 is connected to the gate of the tenth type N MOSFET M10, and the drain of the tenth type N MOSFET M10, the drain of the eighth type P MOSFET M8, the gate of the eighth type P MOSFET M8, and the gate of the ninth type P MOSFET M9 are connected. The source of the eighth P-type MOSFET M8 and the source of the ninth P-type MOSFET M9 are connected to the analog power supply voltage AVDD; the drain of the ninth P-type MOSFET M9 is connected to ground GND through the second capacitor C2, and after being connected to the drain of the eleventh N-type MOSFET M11, it serves as the output terminal VRAMP of the ramp timing circuit 21 and is connected to the non-inverting input terminal of the first comparator 23; the source of the eleventh N-type MOSFET M11 is connected to ground GND, and the gate of the eleventh N-type MOSFET M11 serves as the detection terminal SE of the ramp timing circuit 23 to detect the high-side switch turn-off signal.

[0047] The detection terminal SE of the ramp timing circuit 23 can be connected to the first drive control terminal of the high-side switch drive control module of the DC-DC converter. The high-side switch drive control module can control the high-side switch to turn on and off according to the high-side switch drive control signal HS_ON input from its first drive control terminal. When the high-side switch drive control signal HS_ON is a high-side switch off signal (e.g., a low-level signal), the high-side switch is turned off; when the high-side switch drive control signal HS_ON is a high-side switch on signal (e.g., a high-level signal), the high-side switch is turned on.

[0048] according to Figure 3 The inductor current limiting protection circuit shown in the diagram, when the detection terminal SE of the ramp timing circuit 23 detects a high-side switch turn-off signal (e.g., a low-level signal), the eleventh N-type MOSFET M11 is turned off. With the eleventh N-type MOSFET M11 off, the ramp timing circuit 23 starts timing. During timing, the ramp timing voltage Vramp output from the output terminal VRAMP of the ramp timing circuit 23 rises with a second target slope until the ramp timing voltage Vramp is greater than or equal to the reference voltage Vref output from the output terminal VREF of the reference voltage generation circuit 22. At this point, the eleventh N-type MOSFET M11 turns on, and the eleventh N-type MOSFET M11 grounds the output terminal VRAMP of the ramp timing circuit 23, ending the timing. The second target slope is the ratio of the power supply voltage Vin of the DC-DC converter to the preset slope coefficient Y1, where the preset slope coefficient is the product of the resistance value of the fifth resistor R5 and the capacitance value of the second capacitor C2.

[0049] In this way, the ramp timing circuit 23 can realize the timing principle expressed by the above formulas (1) and (2), so that the low-side switch tube is turned off in time when the low-side target conduction time CFT is reached, thereby ensuring that the inductor can be effectively and fully demagnetized and achieve the effect of inductor current limiting.

[0050] Reference Figure 3 As shown, in one embodiment, the reference voltage generation circuit 22 includes a twelfth P-type MOSFET M12, a thirteenth P-type MOSFET M13, a fourteenth N-type MOSFET M14, a fifteenth N-type MOSFET M15, a sixteenth N-type MOSFET M16, a fourth comparator A4, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.

[0051] The positive input terminal of the fourth comparator A4 serves as the first input terminal of the reference voltage generation circuit 22 and is connected to the voltage output terminal VOUT of the DC-DC converter. The negative input terminal of the fourth comparator A4 is connected to the source of the fourteenth N-type MOSFET M14 and is connected to ground through the ninth resistor R9. The output terminal of the fourth comparator A4 is connected to the gate of the fourteenth N-type MOSFET M14. The drain of the fourteenth N-type MOSFET M14, the drain of the twelfth P-type MOSFET M12, the gate of the twelfth P-type MOSFET M12, and the gate of the thirteenth P-type MOSFET M13 are connected. The sources of the twelfth P-type MOSFET M12 and the thirteenth P-type MOSFET M13 are both connected to the analog power supply voltage AVDD. The drain of S-type transistor M13, the drain of the fifteenth N-type MOSFET M15, the gate of the fifteenth N-type MOSFET M15, and the gate of the sixteenth N-type MOSFET M16 are connected. The sources of the fifteenth N-type MOSFET M15 and the sixteenth N-type MOSFET M16 are both connected to ground. One end of the sixth resistor R6 serves as the second input terminal of the reference voltage generation circuit 22 and is connected to the power supply voltage input terminal VIN of the DC-DC converter. The other end is connected to ground GND through the seventh resistor R7 and to the first end of the eighth resistor R8. The second end of the eighth resistor R8 is connected to the drain of the sixteenth N-type MOSFET M16 and serves as the output terminal VREF of the reference voltage generation circuit 22, which is connected to the negative input terminal of the first comparator 23.

[0052] according to Figure 3 The reference voltage Vref output by the output terminal VRAMP of the reference voltage generation circuit 22, as shown in the circuit structure, can be expressed as the following formula (3): (3) Where R6 represents the resistance value of the sixth resistor R6, R7 represents the resistance value of the seventh resistor R7, R8 represents the resistance value of the eighth resistor R8, R9 represents the resistance value of the ninth resistor R9, k1 represents the mirror ratio of the current mirror formed by the fifteenth N-type MOSFET M15 and the sixteenth N-type MOSFET M16, Vin represents the power supply voltage of the DC-DC converter, and Vout represents the output voltage of the DC-DC converter.

[0053] In practical applications, the resistance values ​​of the sixth resistor R6 and the seventh resistor R7 are proportional. This ratio can be determined based on the reference voltage coefficient Y2. For example, if Y2 = 1 / 4, then R6 = 3 × R7. Vref = Y2 × (Vin - Vout) can be achieved by adjusting the resistance values ​​of the seventh resistor R7, the eighth resistor R8, and the mirror ratio k1 of the current mirror formed by the fifteenth N-type MOSFET M15 and the sixteenth N-type MOSFET M16. That is, for the reference voltage generation circuit 22, the reference voltage Vref output at its output terminal VREF is the product of the voltage difference between the DC-DC converter's power supply voltage Vin and its output voltage Vout, and the reference voltage coefficient Y2.

[0054] For example, the resistance value of the ninth resistor R9 can be the same as that of the fifth resistor R5.

[0055] according to Figure 3 The inductor current limiting protection circuit shown in the figure, when the ramp timing voltage Vramp output by the output terminal VRAMP of the ramp timing circuit 21 reaches the reference voltage Vref output by the output terminal VREF of the reference voltage generation circuit 22, the timing time satisfies the following formula (4): (4) Where R5 represents the resistance value of the fifth resistor R5, and C2 represents the capacitance value of the second capacitor C2.

[0056] According to formula (4), the low-side target conduction time CFT can be obtained, which can be expressed as the following formula (5): (5) Wherein, the value of Y2×(R5×C2) is the duty cycle T of the DC-DC converter. Based on the duty cycle T of the DC-DC converter, the low-side target on-time CFT can be determined by setting the resistance value of the fifth resistor R5 and the capacitance value of the second capacitor C2.

[0057] In one embodiment of this application, Figure 2 The inductor current limiting protection circuit provided in the corresponding embodiment can be applied to an improved BUCK converter. Figure 4 A schematic diagram of the improved BUCK converter is shown. (Refer to...) Figure 4As shown, the improved BUCK converter includes a first switching transistor Q1, a second switching transistor Q2, a third switching transistor Q3, a fourth switching transistor Q4, a conversion capacitor CF1, an inductor L1, and an output capacitor Cout.

[0058] The drain of the first switching transistor Q1 serves as the power voltage input terminal VIN of the DC-DC converter for connection to the DC voltage source SV. The source of the first switching transistor Q1 is connected to the drain of the second switching transistor Q2. The second switching transistor Q2 is connected to the drain of the third switching transistor Q3 through the inductor L1. The source of the third switching transistor Q3 is connected to the drain of the fourth switching transistor Q4. The source of the fourth switching transistor Q4 is connected to the ground GND; the conversion capacitor CF1 is connected between the drain of the second switching transistor Q2 and the drain of the fourth switching transistor Q4. The drain of the third switching transistor Q3 is connected to the ground GND through the output capacitor Cout, and the drain of the third switching transistor Q3 serves as the voltage output terminal VOUT of the DC-DC converter. Exemplarily, each switching transistor can be a MOS transistor.

[0059] Specifically, for Figure 4 the shown DC-DC converter, the input voltage Vin input at the power voltage input terminal VIN and the output voltage Vout output at the voltage output terminal VOUT satisfy the relationship Vout < Vin < 2×Vout. The first switching transistor Q1, the second switching transistor Q2, and the third switching transistor Q3 serve as the high-side switching transistors of the DC-DC converter and are simultaneously turned on during the high-side operation period (HS period). The power voltage input terminal VIN charges the voltage output terminal VOUT through the conversion capacitor CF1 and the inductor L1. At this time, the voltage difference across the conversion capacitor CF1 is Vin - Vout, and the current in the inductor L1 rises at a slope of (Vin - Vout) / L1, where L1 is the inductance value of the inductor L1. The second switching transistor Q2 and the fourth switching transistor Q4 serve as the low-side switching transistors of the DC-DC converter and are simultaneously turned on during the low-side operation period (LS period). The current in the inductor L1 is provided by the conversion capacitor CF1, and the current in the inductor L1 drops at a slope of (Vin - 2×Vout) / L1.

[0060] When the DC-DC converter does not trigger inductor overcurrent protection, the duty cycle of the DC-DC converter is (2×Vout - Vin) / Vout. Assuming the operating period of the DC-DC converter is T, the conduction time of the high-side switching transistors of the DC-DC converter is finally stabilized at T×(2×Vout - Vin) / Vout under the regulation of the loop, and the conduction time of the low-side switching transistors is finally stabilized at T×(Vin - Vout) / Vout under the regulation of the loop.

[0061] When the load current gradually increases to the point where the DC-DC converter triggers the inductor overcurrent protection, the loop control fails. Even if the high-side switch is turned off in time by the inductor overcurrent protection, the low-side switch's conduction time becomes very short due to the loop control, and the current in inductor L1 does not complete demagnetization before the next high-side operation begins. Although the high-side switch will be turned off by the inductor overcurrent protection, the detection of the overcurrent protection requires a certain amount of time. During this period, the current in inductor L1 actually increases unrestricted, thus failing to achieve the purpose of current limiting.

[0062] Therefore, the inductor current limiting protection circuit provided in this application embodiment can be used to control the turn-off of the low-side switch. The low-side target on-time CFT of the DC-DC converter is set to T×(Vin-Vout) / Vout in the loop control steady state. After the DC-DC converter triggers the inductor overcurrent protection, the high-side switch (including the first switch Q1, the second switch Q2 and the third switch Q3) is turned off, and the low-side switch (including the second switch Q2 and the fourth switch Q4) is turned on. However, the on-time of the low-side switch is determined by the fixed low-side target on-time CFT. After the low-side target on-time CFT ends, the high-side switch is turned on again.

[0063] Correspondingly, combined Figure 2 The target voltage input at the target voltage input terminal IN of the ramp timing circuit 21 is the output voltage Vout output at the voltage output terminal VOUT of the DC-DC converter; the low-side target conduction time CFT is the value of multiplying the DC-DC converter's operating period T by the target voltage difference and dividing by the DC-DC converter's output voltage Vout, where the target voltage difference is the difference between the DC-DC converter's power supply voltage Vin and its output voltage Vout, i.e., CFT=T×(Vin-Vout) / Vout.

[0064] Based on this, the timing target, the low-side target conduction time (CFT), can be converted into a timing voltage to design the corresponding ramp timing circuit 21 and reference voltage generation circuit 22. For example, a preset slope coefficient Y1 and reference voltage coefficient Y2 can be set according to the working period T of the DC-DC converter, so that the ramp timing voltage output by the ramp timing circuit 21 during the timing period rises with a slope of Vout / Y1, and the reference voltage output by the reference voltage generation circuit 22 is Y2×(Vin-Vout), where T=Y1×Y2, and Y2 is less than 1. When the ramp timing voltage rises to the reference voltage, the following relationship exists: (6) At this time, formula (6) is equivalent to CFT=T×(Vin-Vout) / Vout above, that is, when the ramp timing voltage rises to the reference voltage, it can be considered that the conduction time of the low-side switch has reached the low-side target conduction time CFT, and at this time the low-side switch of the DC-DC converter is turned off.

[0065] Accordingly, based on Figure 4 The improved BUCK converter shown is a DC-DC converter. Figure 5 This is shown as the third schematic diagram of the inductor current limiting protection circuit provided in the embodiment of this application, with reference to... Figure 5 As shown, the inductor current limiting protection circuit includes a ramp timing circuit 21, a reference voltage generation circuit 22, and a first comparator 23.

[0066] The ramp timing circuit 21 includes a second comparator A2, a first P-type MOSFET M1, a second P-type MOSFET M2, a third P-type MOSFET M3, a fourth N-type MOSFET M4, a fifth N-type MOSFET M5, a sixth N-type MOSFET M6, a first resistor R1, and a first capacitor C1. The non-inverting input of the second comparator A2 serves as the target voltage input IN of the ramp timing circuit 21 and is connected to the voltage output VOUT of the DC-DC converter. The inverting input of the second comparator A2 is connected to the source of the fourth N-type MOSFET M4 and is connected to ground GND through the first resistor R1. The output of the second comparator A2 is connected to the gate of the fourth N-type MOSFET M4, and the drain of the fourth N-type MOSFET M4 is connected to the drain of the first P-type MOSFET M1. The drain, gate, gate of the first P-type MOSFET M1, gate of the second P-type MOSFET M2, and gate of the third P-type MOSFET M3 are connected. The source of the first P-type MOSFET M1, the source of the second P-type MOSFET M2, and the gate of the third P-type MOSFET M3 are connected. The source of MOSFET M3 is connected to the analog power supply voltage AVDD; the drain of the second P-type MOSFET M2 is connected to the drain of the fifth N-type MOSFET M5, and the drain of the fifth N-type MOSFET M5 is connected to the gate of the fifth N-type MOSFET M5, and the source of the fifth N-type MOSFET M5 is connected to ground GND; the drain of the third P-type MOSFET M3 is connected to ground GND through the first capacitor C1, and after being connected to the drain of the sixth N-type MOSFET M6, it serves as the output terminal VRAMP of the ramp timing circuit 21 and is connected to the non-inverting input terminal of the first comparator 23; the source of the sixth N-type MOSFET M6 is connected to ground GND, and the gate of the sixth N-type MOSFET M6 serves as the detection terminal SE of the ramp timing circuit 21 to detect the high-side switch turn-off signal.

[0067] The detection terminal SE of the ramp timing circuit 23 can be connected to the first drive control terminal of the high-side switch drive control module of the DC-DC converter. The high-side switch drive control module can control the high-side switch to turn on and off according to the high-side switch drive control signal HS_ON input from its first drive control terminal. When the high-side switch drive control signal HS_ON is a high-side switch off signal (e.g., a low-level signal), the high-side switch is turned off; when the high-side switch drive control signal HS_ON is a high-side switch on signal (e.g., a high-level signal), the high-side switch is turned on.

[0068] according to Figure 5 The inductor current limiting protection circuit shown operates as follows: when the detection terminal SE of the ramp timing circuit 21 detects a high-side switch turn-off signal (e.g., a low-level signal), the sixth N-type MOSFET M6 is turned off. With the sixth N-type MOSFET M6 off, the ramp timing circuit 21 begins timing. During timing, the ramp timing voltage Vramp output from the output terminal VRAMP of the ramp timing circuit 21 rises with a first target slope until the ramp timing voltage Vramp is greater than or equal to the reference voltage Vref. At this point, the sixth N-type MOSFET M6 turns on, grounding the output terminal VRAMP of the ramp timing circuit 23, and the timing ends. The first target slope is the ratio of the DC-DC converter's output voltage Vout to a preset slope coefficient Y1, where Y1 is the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1.

[0069] In this way, the ramp timing circuit 23 can realize the timing principle expressed by the above formula (6), so that the low-side switch tube is turned off in time when the low-side target conduction time CFT is reached, thereby ensuring that the inductor L1 can be effectively and fully demagnetized, and achieving the effect of inductor current limiting.

[0070] based on Figure 4 The improved BUCK converter shown is a DC-DC converter in which, in one embodiment, the reference voltage generation circuit 22 can be employed as follows: Figure 3 The reference voltage generation circuit 22 in the inductor current limiting protection circuit shown takes into account, for example... Figure 3 The reference voltage generation circuit 22 in the inductor current limiting protection circuit shown includes, as well as, the reference voltage generation circuit 22 in the inductor current limiting protection circuit shown. Figure 5 The ramp timing circuit 23 in the present invention has a partially identical structure, which can be reused when designing the reference voltage generation circuit 22 in another embodiment of the present application. Figure 5 Part of the structure of the ramp timing circuit 23.

[0071] Specifically, refer to Figure 5As shown, the reference voltage generation circuit 22 may include a second resistor R2, a third resistor R3, a fourth resistor R4, and a seventh N-type MOSFET M7.

[0072] One end of the second resistor R2 serves as the second input terminal of the reference voltage generation circuit 22, which is connected to the power supply voltage input terminal VIN of the DC-DC converter. The other end is connected to ground GND through the third resistor R3 and to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the drain of the seventh N-type MOSFET M7 and then serves as the output terminal VREF of the reference voltage generation circuit 22, which is connected to the negative phase input terminal of the first comparator 23. The source of the seventh N-type MOSFET M7 is connected to ground GND, and the gate VBN of the seventh N-type MOSFET M7 is connected to the drain of the fifth N-type MOSFET M5.

[0073] In this way, the reference voltage generation circuit 22 can reuse the circuit part composed of the second comparator A2, the first P-type MOSFET M1, the second P-type MOSFET M2, the fourth N-type MOSFET M4, the fifth N-type MOSFET M5 and the first resistor R1 in the ramp timing circuit 21, which simplifies the circuit structure and saves costs while realizing the function of the reference voltage generation circuit 22.

[0074] Understandably, when adopting Figure 5 When the reference voltage generation circuit 22 is shown, the gate VBN of the seventh N-type MOS transistor M7 can be regarded as the first input terminal of the reference voltage generation circuit 22, which can be used to connect with the drain of the fifth N-type MOS transistor M5 in the ramp timing circuit 21. At this time, it is equivalent to the first input terminal of the reference voltage generation circuit 22 receiving a voltage signal related to the output voltage Vout output by the voltage output terminal VOUT of the DC-DC converter.

[0075] according to Figure 5 The reference voltage Vref output by the output terminal VRAMP of the reference voltage generation circuit 22, as shown in the circuit structure, can be expressed as the following formula (7): (7) Where R2 represents the resistance value of the second resistor R2, R3 represents the resistance value of the third resistor R3, R4 represents the resistance value of the fourth resistor R4, R1 represents the resistance value of the first resistor R1, k2 represents the mirror ratio of the current mirror composed of the fifth N-type MOSFET M5 and the seventh N-type MOSFET M7, Vin represents the power supply voltage of the DC-DC converter, and Vout represents the output voltage of the DC-DC converter.

[0076] In practical applications, the resistance values ​​of the second resistor R2 and the third resistor R3 are proportional. This ratio can be determined based on the reference voltage coefficient Y2, where the resistance of the second resistor R2 is (Y2-1) times that of the third resistor R3. For example, in one embodiment, the reference voltage coefficient Y2 = 1 / 4, so the relationship between the resistance values ​​of the second resistor R2 and the third resistor R3 can be set as R2 = 3 × R3. This can be achieved by adjusting the mirror ratio k2 of the current mirror composed of the third resistor R3, the fourth resistor R4, the fifth N-type MOSFET M5, and the seventh N-type MOSFET M7, so that Vref = Y2 × (Vin - Vout). That is, the reference voltage Vref output by the output terminal VREF of the reference voltage generation circuit 22 is the product of the voltage difference between the power supply voltage Vin and the output voltage Vout of the DC-DC converter and the reference voltage coefficient Y2.

[0077] according to Figure 5 The inductor current limiting protection circuit shown in the figure, when the ramp timing voltage Vramp output by the output terminal VRAMP of the ramp timing circuit 21 reaches the reference voltage Vref output by the output terminal VREF of the reference voltage generation circuit 22, the timing time satisfies the following formula (8): (8) Where R5 represents the resistance value of the fifth resistor R5, and C2 represents the capacitance value of the second capacitor C2.

[0078] According to formula (8), the low-side target conduction time CFT can be obtained, which can be expressed as the following formula (9): (9) Wherein, the value of Y2×(R1×C1) is the duty cycle T of the DC-DC converter. Based on the duty cycle T of the DC-DC converter, the low-side target on-time CFT can be determined by setting the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1.

[0079] Based on any of the above embodiments, the inductor current limiting protection circuit Figure 6 A schematic diagram illustrating the current-limiting effect of the inductor current-limiting protection circuit provided in this embodiment is shown. In this diagram, ILOAD represents the load current, HS_ON represents the high-side switch drive control signal, LS_ON represents the low-side switch drive control signal, IIND represents the inductor current, Vramp represents the ramp timing voltage output by the ramp timing circuit 23, and Vref represents the reference voltage output by the reference voltage generation circuit 22. (Refer to...) Figure 6As shown, before the load current ILOAD changes, the on / off state of the high-side and low-side switches of the DC-DC converter is determined by the control loop. When the load current ILOAD changes, the output current of the DC-DC converter is less than the load current ILOAD, and the control loop extends the on-time of the high-side switch until the inductor overcurrent protection is triggered. After the inductor overcurrent protection is triggered, the high-side switch turns off and the low-side switch turns on, and the on-time of the low-side switch is determined by the set low-side target on-time CFT. Since the output current of the DC-DC converter is limited, the high-side and low-side processes will be repeated subsequently, and the inductor will supply power to the load at the current-limited value. The frequency of the DC-DC converter is also determined by the CFT time and will remain consistent with that before the inductor overcurrent protection occurred. In this way, the current limiting effect can be effectively achieved after the inductor overcurrent protection is triggered.

[0080] Based on the same inventive concept, this application also provides an inductor current limiting control method, which is described below in conjunction with... Figure 7 The inductor current limiting control method provided in the embodiments of this application will be described in detail. This inductor current limiting control method can be applied to a DC-DC converter, specifically a DC-DC converter involving inductor demagnetization, such as a basic architecture-type BUCK converter, etc. Figure 4 The improved BUCK converter or other architecture-based DC-DC converter involving inductor demagnetization is shown. This inductor current limiting control method can be implemented in the DC-DC converter via software, or via a combination of software and hardware, or via hardware circuitry, such as the inductor current limiting protection circuit for DC-DC converters provided in any of the above embodiments of this application.

[0081] Figure 7 An exemplary flowchart of the inductor current limiting control method provided in an embodiment of this application is shown below. Figure 7 As shown, the inductor current limiting control method may include the following steps 710 to 720.

[0082] Step 710: After the DC-DC converter triggers the inductor overcurrent protection, and a high-side switch turn-off signal is detected, the low-side switch is turned on and the timing begins.

[0083] After the DC-DC converter triggers overcurrent protection, the HS switch can be turned off by a high-side switch turn-off signal (such as a low-level signal), while the LS switch is turned on simultaneously. When the high-side switch turn-off signal is detected, the timing of the LS switch's on-time is triggered.

[0084] Step 720: When the timing reaches the target conduction time of the low side, control the low side switch to turn off.

[0085] Wherein, the low-side target on-time CFT is the on-time of the low-side switch (LS switch) in steady state before the DC-DC converter triggers inductor overcurrent protection.

[0086] Specifically, before the DC-DC converter triggers the inductor overcurrent protection, the conduction times of the low-side and high-side switches of the DC-DC converter are determined by the control loop and eventually reach a steady state under the adjustment of the control loop. In this steady state, the conduction time of the low-side switch is determined, which can be based on the power supply voltage and output voltage of the DC-DC converter. Different DC-DC converters will have different expressions.

[0087] For example, in the case of a DC-DC converter-based BUCK converter (such as a synchronous BUCK circuit structure), the low-side target on-time CFT can be expressed as the above formula (1). The low-side target on-time CFT can be set to the time determined according to the above formula (1). When the timing reaches the low-side target on-time CFT, the low-side switch is turned off and the HS stage is restarted.

[0088] In DC-DC converters, such as Figure 4 In the case of the improved BUCK converter shown, the low-side target on-time CFT can be expressed as CFT=T×(Vin-Vout) / Vout. The low-side target on-time CFT can be set to the time determined by this formula. When the timing reaches the low-side target on-time CFT, the low-side switch is turned off and the HS stage is restarted.

[0089] The inductor current limiting protection method provided in this application, after the DC-DC converter triggers inductor overcurrent protection, controls the high-side switch to turn off and the low-side switch to turn on. At this time, timing begins, and the low-side switch is turned off when the timing reaches the target low-side conduction time. The target low-side conduction time is the conduction time of the low-side switch in the steady state before the DC-DC converter triggers inductor overcurrent protection. In this way, after the DC-DC converter triggers inductor overcurrent protection, by directly setting the conduction time of the low-side switch to the steady-state conduction time of the low-side switch before the DC-DC converter triggers inductor overcurrent protection, the conduction time of the low-side switch after triggering overcurrent protection is controlled. It does not require the design of a complex inductor current detection circuit to detect the inductor current of the DC-DC converter. The solution is simple and easy to implement, and can be applied to various DC-DC converters involving inductor demagnetization, with a wide range of applications.

[0090] Based on the inductor current limiting control method described in the above embodiments, this application also provides a computer-readable storage medium, such as a non-transitory computer-readable storage medium, which may be a read-only memory (ROM), a random access memory (RAM), a CD-ROM, magnetic tape, a floppy disk, and an optical data storage device, etc. This storage medium stores computer instructions for executing the inductor current limiting control method described in the above embodiments, which will not be elaborated further here.

[0091] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by hardware, or by a program instructing related hardware to implement them. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0092] This application also provides a DC-DC converter, which is a DC-DC converter involving inductor demagnetization, including an inductor current limiting protection circuit as described in any of the above embodiments of this application. After the DC-DC converter triggers inductor overcurrent protection, the ramp timing circuit starts timing upon detecting a high-side switch turn-off signal. During timing, a ramp timing voltage is determined based on the target voltage input at the target voltage input terminal and a preset slope coefficient determined based on the DC-DC converter's operating cycle. A reference voltage generation circuit generates a reference voltage based on the DC-DC converter's power supply voltage and output voltage. A first comparator compares the ramp timing voltage output by the ramp timing circuit with the reference voltage output by the reference voltage generation circuit. If the ramp timing voltage is greater than or equal to the reference voltage, it is determined that the timing time of the ramp timing circuit reaches the on-state conduction time of the low-side switch before the DC-DC converter triggers inductor overcurrent protection. At this time, the first comparator outputs a high-level signal to the low-side switch drive control module, instructing the low-side switch drive control module to control the low-side switch of the DC-DC converter to turn off. In this way, after the DC-DC converter triggers the inductor overcurrent protection, the conduction time of the low-side switch is directly set to the steady-state conduction time of the low-side switch before the DC-DC converter triggers the inductor overcurrent protection. This achieves control over the conduction time of the low-side switch after the overcurrent protection is triggered. There is no need to design a complex inductor current detection circuit to detect the inductor current of the DC-DC converter. The solution is simple and easy to implement, and can be applied to various DC-DC converters involving inductor demagnetization, with a wide range of applications.

[0093] This application also provides a chip that includes an inductor current limiting protection circuit as described in any of the above embodiments, or a DC-DC converter as described above. After the DC-DC converter triggers inductor overcurrent protection, the chip detects a high-side switch turn-off signal via a ramp timing circuit and starts timing upon detection of the high-side switch turn-off signal. During timing, a ramp timing voltage is determined based on the target voltage input at the target voltage input terminal and a preset ramp coefficient determined based on the DC-DC converter's operating cycle. A reference voltage is generated by a reference voltage generation circuit based on the DC-DC converter's power supply voltage and output voltage. A first comparator compares the ramp timing voltage output by the ramp timing circuit with the reference voltage output by the reference voltage generation circuit. If the ramp timing voltage is greater than or equal to the reference voltage, the timing time of the ramp timing circuit is determined to be the conduction time of the low-side switch in its steady state before the DC-DC converter triggers inductor overcurrent protection. At this time, the first comparator outputs a high-level signal to the low-side switch drive control module, instructing the low-side switch drive control module to control the low-side switch of the DC-DC converter to turn off. In this way, after the DC-DC converter triggers inductor overcurrent protection, the conduction time of the low-side switch is directly set to the steady-state conduction time of the low-side switch before the DC-DC converter triggers inductor overcurrent protection. This achieves control over the conduction time of the low-side switch after triggering overcurrent protection, eliminating the need for a complex inductor current detection circuit to detect the inductor current of the DC-DC converter. The solution is simple and easy to implement, applicable to various DC-DC converters involving inductor demagnetization, and has a wide range of applications. Moreover, by making the inductor current limiting protection circuit described in any of the above embodiments or the DC-DC converter described above into a chip, the integration is high and the use is convenient.

[0094] This application also provides an electronic device that includes an inductor current limiting protection circuit as described in any of the above embodiments, or a DC-DC converter as described above, or a chip as described above. This electronic device may include at least one of the following: a mobile phone, wearable device, laptop computer, tablet computer, wireless headset, in-vehicle device, smart home device, virtual reality (VR) terminal device, and augmented reality (AR) terminal device, but is not limited thereto. It can achieve the effects of the inductor current limiting protection circuit as described in any of the above embodiments, or the effects of the DC-DC converter as described above, or the effects of the chip as described above.

[0095] In one embodiment of this application, the electronic device may include a processor, an external memory interface, internal memory, a Universal Serial Bus (USB) interface, a charging management module, a power management module, a battery, an antenna, a mobile communication module, a wireless communication module, an audio module, a speaker, a microphone, a headphone jack, a sensor module, buttons, a motor, an indicator, a camera, a display screen, and a Subscriber Identification Module (SIM) card interface, etc. The sensor module may include motion sensors and gyroscopes, etc.

[0096] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components, or combine some components, or split some components, or have different component arrangements. These components may be implemented in hardware, software, or a combination of software and hardware.

[0097] The processor may include one or more processing units, such as, but not limited to, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors. The controller can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution. The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor may be a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to reuse the instruction or data, it can retrieve it from memory. This avoids repeated accesses, reduces processor waiting time, and thus improves system efficiency.

[0098] The charging management module receives charging signals from the charger. The charger may include a wireless charger or a wired charger. In some wired charging embodiments, the charging management module receives charging input from the wired charger via a USB interface. In some wireless charging embodiments, the charging management module receives wireless charging input via the wireless charging coil of the electronic device. While charging the battery, the charging management module can also supply power to the electronic device via the power management module.

[0099] The power management module connects the battery, the charging management module, and the processor. It receives input from the battery and / or the charging management module to power the processor, internal memory, display screen, camera, and wireless communication module. The power management module can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some embodiments, the power management module may be located within the processor. In other embodiments, the power management module and the charging management module may be located in the same device.

[0100] Wireless communication functionality in electronic devices can be implemented through antennas, mobile communication modules, wireless communication modules, modem processors, and baseband processors. Antennas are used to transmit and receive electromagnetic wave signals. Mobile communication modules can provide solutions for wireless communication applications in electronic devices, including 2G / 3G / 4G / 5G. In some embodiments, at least some functional modules of the mobile communication module can be housed in the same device as at least some modules of the processor.

[0101] Wireless communication modules can provide solutions for at least one of the following wireless communication technologies used in electronic devices: Wireless Local Area Networks (WLANs) (such as Wireless Fidelity (Wi-Fi) networks), Bluetooth (BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), and Infrared (IR), but are not limited to these. A wireless communication module can be one or more devices integrating at least one communication processing module. The wireless communication module receives electromagnetic waves via an antenna, modulates and filters the electromagnetic wave signal, and sends the processed signal to a processor. The wireless communication module can also receive signals to be transmitted from the processor, modulate and amplify them, and then radiate them as electromagnetic waves via the antenna.

[0102] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations thereof that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

Claims

1. An inductive current limiting protection circuit, characterized by, The inductance current limiting protection circuit applied to a DC-DC converter comprises a slope timing circuit, a reference voltage generating circuit and a first comparator; The slope timing circuit is configured to start timing when a high-side switch tube off signal is detected after the DC-DC converter triggers inductance overcurrent protection, determine a slope timing voltage based on an input target voltage and a preset slope coefficient during the timing, and input the slope timing voltage to a positive input terminal of the first comparator; wherein the target voltage is a power supply voltage or an output voltage of the DC-DC converter, and the target voltage is determined based on the architecture of the DC-DC converter; and the preset slope coefficient is determined based on the duty cycle of the DC-DC converter; The reference voltage generating circuit is configured to generate a reference voltage based on the power supply voltage and the output voltage of the DC-DC converter, and input the reference voltage to a negative input terminal of the first comparator; The output terminal of the first comparator is configured to be connected to a low-side switch tube driving control module of the DC-DC converter, and the first comparator is configured to compare the slope timing voltage with the reference voltage, and output a high-level signal to the low-side switch tube driving control module to indicate that the low-side switch tube driving control module controls the low-side switch tube of the DC-DC converter to be off when the slope timing voltage is greater than or equal to the reference voltage. When the slope timing voltage is greater than or equal to the reference voltage, the timing time of the slope timing circuit reaches a low-side target on time; and the low-side target on time is the on time of the low-side switch tube in a steady state before the DC-DC converter triggers inductance overcurrent protection.

2. The inductive current limit protection circuit of claim 1, wherein, The DC-DC converter is an improved BUCK converter; and the improved BUCK converter comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a conversion capacitor, an inductor and an output capacitor; The drain of the first switch tube is connected to a DC voltage source as a power supply voltage input terminal of the DC-DC converter, the source of the first switch tube is connected to the drain of the second switch tube, the second switch tube is connected to the drain of the third switch tube through the inductor, the source of the third switch tube is connected to the drain of the fourth switch tube, and the source of the fourth switch tube is connected to the ground; The conversion capacitor is connected between the drain of the second switch tube and the drain of the fourth switch tube, the drain of the third switch tube is connected to the ground through the output capacitor, and the drain of the third switch tube is connected to a voltage output terminal of the DC-DC converter; The first switch tube, the second switch tube and the third switch tube are high-side switch tubes of the DC-DC converter, and are simultaneously turned on during high-side operation; and the second switch tube and the fourth switch tube are low-side switch tubes of the DC-DC converter, and are simultaneously turned on during low-side operation. The target voltage is an output voltage output by a voltage output end of the DC-DC converter; the low-side target conduction time is a value obtained by multiplying a working cycle of the DC-DC converter by a target pressure difference and then dividing by the output voltage of the DC-DC converter, and the target pressure difference is a difference between a power supply voltage and the output voltage of the DC-DC converter.

3. The inductive current limit protection circuit of claim 2, wherein, The slope timing circuit comprises a second comparator, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, a sixth N-type MOS transistor, a first resistor and a first capacitor; The non-inverting input end of the second comparator is used as a target voltage input end of the slope timing circuit and is connected to the voltage output end of the DC-DC converter; the inverting input end of the second comparator is connected to the source of the fourth N-type MOS transistor and is connected to the ground through the first resistor; the output end of the second comparator is connected to the gate of the fourth N-type MOS transistor, and the drain of the fourth N-type MOS transistor is connected to the drain of the first P-type MOS transistor; The drain of the first P-type MOS transistor, the gate of the first P-type MOS transistor, the gate of the second P-type MOS transistor and the gate of the third P-type MOS transistor are connected; the source of the first P-type MOS transistor, the source of the second P-type MOS transistor and the source of the third P-type MOS transistor are all connected to an analog power supply voltage; the drain of the second P-type MOS transistor is connected to the drain of the fifth N-type MOS transistor, and the drain of the fifth N-type MOS transistor is connected to the gate of the fifth N-type MOS transistor, and the source of the fifth N-type MOS transistor is connected to the ground; The drain of the third P-type MOS transistor is connected to the ground through the first capacitor and is connected to the drain of the sixth N-type MOS transistor, and the drain of the sixth N-type MOS transistor is connected to the output end of the slope timing circuit and is connected to the non-inverting input end of the first comparator; the source of the sixth N-type MOS transistor is connected to the ground, and the gate of the sixth N-type MOS transistor is used as a detection end of the slope timing circuit and is used for detecting the high-side switch tube turn-off signal; In the case that the high-side switch tube turn-off signal is detected at the detection end of the slope timing circuit, the sixth N-type MOS transistor is turned off; in the case that the sixth N-type MOS transistor is turned off, the slope timing circuit starts timing, and during the timing, the slope timing voltage output by the output end of the slope timing circuit rises at a first target slope until the slope timing voltage is greater than or equal to the reference voltage, the sixth N-type MOS transistor is turned on, and the timing ends; wherein the first target slope is a ratio of the output voltage of the DC-DC converter to the preset slope coefficient, and the preset slope coefficient is a product of the resistance value of the first resistor and the capacitance value of the first capacitor.

4. The inductive current limit protection circuit of claim 3, wherein, The reference voltage generation circuit comprises a second resistor, a third resistor, a fourth resistor and a seventh N-type MOS transistor; One end of the second resistor is connected with a power voltage input terminal of the DC-DC converter as a second input terminal of the reference voltage generating circuit, the other end of the second resistor is connected with the ground through the third resistor and connected with a first terminal of the fourth resistor, a second terminal of the fourth resistor is connected with the drain of the seventh N-type MOS tube and connected with the output terminal of the reference voltage generating circuit and the negative phase input terminal of the first comparator; The source of the seventh N-type MOS tube is connected with the ground, and the gate of the seventh N-type MOS tube is connected with the drain of the fifth N-type MOS tube; The reference voltage output by the output terminal of the reference voltage generating circuit is the product of the voltage difference between the power voltage and the output voltage of the DC-DC converter and the reference voltage coefficient; The reference voltage coefficient is determined based on the resistance values of the second resistor and the third resistor.

5. The inductive current limit protection circuit of claim 4, wherein, The resistance value of the second resistor is three times of the resistance value of the third resistor, and the reference voltage coefficient is 1 / 4.

6. The inductive current limit protection circuit of claim 1, wherein, The DC-DC converter is a basic architecture type BUCK converter, the target voltage is the power voltage of the DC-DC converter, the low-side target conduction time is the value obtained by multiplying the working cycle of the DC-DC converter and the target voltage difference and then dividing by the power voltage of the DC-DC converter, and the target voltage difference is the difference between the power voltage and the output voltage of the DC-DC converter.

7. The inductive current limit protection circuit of claim 6, wherein, The slope timing circuit comprises a third comparator, an eighth P-type MOS tube, a ninth P-type MOS tube, a tenth N-type MOS tube, an eleventh N-type MOS tube, a second capacitor and a fifth resistor, and the preset slope coefficient is the product of the resistance value of the fifth resistor and the capacitance value of the second capacitor; The positive phase input terminal of the third comparator is connected with the power voltage input terminal of the DC-DC converter as the target voltage input terminal of the slope timing circuit, the negative phase input terminal of the third comparator is connected with the source of the tenth N-type MOS tube and connected with the ground through the fifth resistor, the output terminal of the third comparator is connected with the gate of the tenth N-type MOS tube, the drain of the tenth N-type MOS tube, the drain of the eighth P-type MOS tube, the gate of the eighth P-type MOS tube and the gate of the ninth P-type MOS tube are connected, and the source of the eighth P-type MOS tube and the source of the ninth P-type MOS tube are connected with an analog power supply voltage; The drain of the ninth P-type MOS tube is connected with the ground through the second capacitor and connected with the drain of the eleventh N-type MOS tube, and the drain of the eleventh N-type MOS tube is connected with the output terminal of the slope timing circuit and the positive phase input terminal of the first comparator as the output terminal of the slope timing circuit; The source of the eleventh N-type MOS tube is connected with the ground, and the gate of the eleventh N-type MOS tube is connected with the detection terminal of the slope timing circuit for detecting the high-side switch tube turn-off signal. In a case where the high-side switch tube is detected to be turned off at the detection end of the slope timing circuit, the eleventh N-type MOS tube is turned off; in a case where the eleventh N-type MOS tube is turned off, the slope timing circuit starts timing, and during the timing, the slope timing voltage output at the output end of the slope timing circuit rises at a second target slope until the eleventh N-type MOS tube is turned on when the slope timing voltage is greater than or equal to the reference voltage, and the timing ends; wherein the second target slope is a ratio of the power supply voltage of the DC-DC converter and the preset slope coefficient.

8. The inductive current limit protection circuit of claim 3 or 6, wherein, The reference voltage generation circuit comprises a twelfth P-type MOS tube, a thirteenth P-type MOS tube, a fourteenth N-type MOS tube, a fifteenth N-type MOS tube, a sixteenth N-type MOS tube, a fourth comparator, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor. The non-inverting input end of the fourth comparator is used as a first input end of the reference voltage generation circuit and is connected with the voltage output end of the DC-DC converter; the inverting input end of the fourth comparator is connected with the source of the fourteenth N-type MOS tube and is connected with the ground through the ninth resistor; the output end of the fourth comparator is connected with the gate of the fourteenth N-type MOS tube; the drain of the fourteenth N-type MOS tube, the drain of the twelfth P-type MOS tube, the gate of the twelfth P-type MOS tube and the gate of the thirteenth P-type MOS tube are connected; the sources of the twelfth P-type MOS tube and the thirteenth P-type MOS tube are connected with an analog power supply voltage; The drain of the thirteenth P-type MOS tube, the drain of the fifteenth N-type MOS tube, the gate of the fifteenth N-type MOS tube and the gate of the sixteenth N-type MOS tube are connected; the sources of the fifteenth N-type MOS tube and the sixteenth N-type MOS tube are connected with the ground; One end of the sixth resistor is used as a second input end of the reference voltage generation circuit and is connected with the power supply voltage input end of the DC-DC converter; the other end of the sixth resistor is connected with the ground through the seventh resistor and is connected with the first end of the eighth resistor; the second end of the eighth resistor is connected with the drain of the sixteenth N-type MOS tube and is used as an output end of the reference voltage generation circuit and is connected with the inverting input end of the first comparator; The reference voltage output at the output end of the reference voltage generation circuit is a product of a voltage difference between the power supply voltage and the output voltage of the DC-DC converter and a reference voltage coefficient; the product of the reference voltage coefficient and the preset slope coefficient is equal to the working period of the DC-DC converter.

9. An inductance current limit control method, characterized by, The inductance current limiting control method is applied to a DC-DC converter and comprises the following steps: In a case where the high-side switch tube is detected to be turned off after the DC-DC converter triggers inductance overcurrent protection, the low-side switch tube is controlled to be turned on and timing is started; In a case where the timing time reaches the low-side target turn-on time, the low-side switch tube is controlled to be turned off. The low-side target on-time is an on-time of the low-side switch in a steady state before the DC-DC converter triggers an inductor over-current protection.

10. A DC-DC converter, characterized by The DC-DC converter comprises the inductor current limiting protection circuit as claimed in any one of claims 1 to 8.

11. A chip, characterized by The DC-DC converter comprises the inductor current limiting protection circuit as claimed in any one of claims 1 to 8, or the DC-DC converter as claimed in claim 10.

12. An electronic device, comprising: The DC-DC converter comprises the inductor current limiting protection circuit as claimed in any one of claims 1 to 8, or the DC-DC converter as claimed in claim 10, or the chip as claimed in claim 11.

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