Anti-single-particle transient reinforcing system for DC-DC converter and reinforcing method of anti-single-particle transient reinforcing system
By introducing a single-event transient hardening system into the DC-DC converter, the effects of SET are detected and counteracted in real time, thus solving the problem of output voltage fluctuation in the DC-DC converter and achieving stable output voltage and compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-10
AI Technical Summary
DC-DC converters are affected by single-event transient (SET) effects in space radiation environments, leading to increased or fluctuating output voltage ripple, which affects system stability and is difficult to effectively harden with existing technologies.
A single-event transient hardening system is adopted, including an error amplifier, transmission gate, load transient detection module, single-event transient detection module, and voltage differential current module. The system counteracts the SET effect by real-time detection and generation of hardening current IRHBD, thereby stabilizing the output of the PWM comparator.
It effectively suppresses output voltage ripple and fluctuations of the DC-DC converter, avoiding the impact on normal dynamic response performance. It has strong compatibility and low implementation cost, and does not require modification of error amplifier parameters.
Smart Images
Figure CN121841101A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radiation hardening technology for analog integrated circuits, specifically a single-event transient hardening system for DC-DC converters, and also relates to a method for hardening this system against single-event transients. Background Technology
[0002] In the space radiation environment, radiation damage to electronic systems is a key cause of spacecraft failure. DC-DC converters, core components in electronic systems responsible for converting motherboard voltage to secondary power supply voltage, are widely used in aerospace systems, and their reliability is crucial to the entire spacecraft. However, with the development of advanced processes, integrated circuits are more susceptible to single-event transients (SETs). For DC-DC converters, SET-induced internal node voltage fluctuations lead to increased overall output voltage ripple, and in severe cases, even large fluctuations in the output voltage. The impact of SET places demands on the reliability of DC-DC converters, as fluctuations in the output voltage of DC-DC converters pose a significant threat to the stability of systems connected to subsequent stages. Therefore, robust design for DC-DC converters to resist single-event transients is essential.
[0003] In current hardening technologies, single-event transient (SET) disturbances (SETs) have a relatively clear impact on digital integrated circuits, and research on hardening digital integrated circuits for SETs is relatively mature. Common methods include redundant switching and the use of dual-interlocked memory structures to accelerate incident point recovery. Compared to digital integrated circuits, the diversity of analog integrated circuit structures and transistor operating modes makes the problems caused by SETs in analog integrated circuits more complex. The propagation of SET disturbances in a circuit is highly dependent on the specific circuit architecture and transistor operating point, making it difficult to formulate a universal hardening solution. Mechanism analysis and customized hardening designs must be performed for specific circuits. Therefore, the impact of SETs on analog integrated circuits is more complex and difficult to estimate. For SET hardening of DC-DC converters, the specific modulation method and control mode of the converter must first be determined to conduct specific SET analysis based on the circuit structure. PWM modulation is widely used due to its stable switching frequency, relatively simple control method and circuit design, low output voltage ripple, and good electromagnetic compatibility. Peak current mode control uses the inductor current signal as the core control quantity, constructing a current inner loop with a response speed far exceeding that of the voltage outer loop, improving the dynamic performance of the system while simplifying system design. Therefore, a SET (Set-Up) hardening design is performed for DC-DC converters using PWM modulation and peak current mode control.
[0004] Essentially, transient current surges (SETs) occur when high-energy particles bombard circuit devices in a space radiation environment. Ionization occurs along the particle's incident path, releasing charge carriers that are collected at the device ports, forming transient currents and causing voltage spikes at sensitive nodes. In analog integrated circuits, high-impedance and large-capacitance nodes are particularly sensitive to SETs. This is because high-impedance and large-capacitance nodes have large RC time constants, making it difficult for radiated charge carriers to dissipate quickly, resulting in easily disturbed and slow-recovering node voltages. In DC-DC converters using PWM peak current mode control, loop compensation is required, necessitating the addition of a frequency compensation section consisting of resistors and capacitors within the loop. This frequency compensation section results in a large capacitance and resistance at the EA output node. Furthermore, to ensure sufficient low-frequency gain in the loop, the EA output impedance is also designed to be large. Therefore, when high-energy particles incident on the EA output node, it will cause... V C Prolonged deviations from normal values affect the output pulse of the PWM comparator, leading to persistent errors in the duty cycle signal and ultimately impacting the output voltage of the DC-DC converter. Summary of the Invention
[0005] The first objective of this invention is to provide a single-event transient hardening system for DC-DC converters, which solves the problem in the prior art where the output pulse error of the PWM comparator is caused by the SET effect at the output node of the error amplifier in the DC-DC converter, resulting in increased output voltage ripple or output voltage fluctuation.
[0006] A second objective of this invention is to provide a method for hardening the single-particle transient hardening system.
[0007] The first technical solution adopted in this invention is a single-event transient hardening system for DC-DC converters, comprising an error amplifier EA, a transmission gate S1, and a two-input AND gate G1, wherein the output node voltage V of the error amplifier EA is... C Resistors R are connected respectively C Voltage limiting module, PWM comparator and voltage sampling output module; It also includes a load transient detection module, a single-event transient detection module, and a voltage differential current conversion module. The single-event transient detection module is connected to the voltage sampling output module. A two-input AND gate G1 is connected to the load transient detection module, the single-event transient detection module, and the transmission gate S1, respectively. The voltage differential current conversion module is connected to the error amplifier EA, the voltage sampling output module, and the single-event transient detection module, respectively. The output signal EN of the two-input AND gate G1 is connected to one end of the transmission gate S1.
[0008] The first technical solution of this invention is also characterized in that, The voltage sampling output module outputs three signals, namely V C1 V CS V C2 And V C1 >V CS >V C2 V C1 With V C2 Connect to the single-particle transient detection module respectively, V CS Connect the voltage differential to current module input terminal.
[0009] The load transient detection module includes comparator OP1 and comparator OP2, which are connected to a DC-DC converter. The positive input terminal of comparator OP1 is connected to a reference voltage V. REF1 The negative input terminal of comparator OP2 is connected to a reference voltage V. REF2 The negative input terminal of comparator OP1 and the positive input terminal of comparator OP2 are both connected to the feedback voltage V of the DC-DC converter. FB The feedback voltage V of the DC-DC converter FB The signal is also input to the positive input terminal of the error amplifier EA. The output signal A of comparator OP1 and the output signal B of comparator OP2 are connected to a two-input AND gate G2. The output of G2 is the load transient signal X, which is connected to the two-input AND gate G1.
[0010] The single-event transient detection module includes comparators OP3 and OP4. The positive input of comparator OP3 is connected to V. C1 The negative input of comparator OP4 is connected to V. C2 The negative input terminal of comparator OP1 and the positive input terminal of comparator OP2 are both connected to V. C The output signal C of comparator OP1 and the output signal D of comparator OP2 are connected to a two-input NAND gate G3. The output of G3 is a single-event transient signal Y, which is connected to a two-input AND gate G1. The output signals C of comparator OP1 and D of comparator OP2 are connected to the input of a voltage-to-current converter module. The input of the voltage-to-current converter module is connected to the output node voltage V of error amplifier EA. C and the V of the voltage sampling output module CS .
[0011] The transmission gate S1 is connected to a sampling resistor R. i Sampling resistor R i One end of the transmission gate S1 is also connected to a DC current I. DC Inductor sampling current I SENSE With slope compensation current I SLOPE Sampling resistor Ri The other end is grounded. Sampling resistor R i The end connected to transmission gate S1 is V SUM Signal generation node, V SUM The signal generation node is connected to the positive input of the PWM comparator, and the PWM comparator outputs a pulse signal V. PWM .
[0012] Compensation resistor R C The other end is connected to a compensation capacitor C C Compensation capacitor C C The other end is grounded.
[0013] The second technical solution adopted in this invention is a single-event transient hardening method, which uses a single-event transient hardening system for DC-DC converters, specifically: S1, collecting feedback voltage V FB and output node voltage V C Generate V C1 V CS V C2 ; S2, compared to V FB The load transient signal X is generated by comparing it with the reference voltage, and then compared with V. C With V C1 V C2 Generate a single-particle transient signal Y and output signals C and D; S3 inputs signals X and Y into the two-input AND gate G1 to obtain EN. EN controls the transmission gate S1 to be turned on only when both X and Y are high, otherwise it is turned off. S4, when transmission gate S1 is turned on, based on V C With V CS The voltage difference and the level states of the output signals C and D generate a reinforcement current I. RHBD ; S5, I RHBD offset V C The SET fluctuation causes V SUM Signal and V C Synchronous signal changes stabilize the PWM comparator output, ensuring that the DC-DC converter output voltage remains stable.
[0014] The second technical solution of the present invention is further characterized in that, S1 specifically refers to: acquiring the feedback voltage V of the DC-DC converter through the load transient detection module. FB and reference voltage V REF1 V REF2 The voltage V at the output node is sampled and output via the voltage sampling output module. C Sampling is performed to generate three reference signals V. C1 VCS V C2 And V C1 >V CS >V C2 Meanwhile, the voltage limiting module limits V C Signal amplitude limiting; S2 specifically refers to: comparing the feedback voltage V through the load transient detection module. FB With reference voltage V REF1 V REF2 The size of V REF1 >V FB >V REF2 Output a high-level load transient signal X when the signal is active, otherwise output a low-level load transient signal X; compare the signal V with the signal V through the single-event transient detection module. C With V C1 V C2 The size of V C >V C1 The system outputs a low-level output signal C, a high-level signal D, and a high-level single-particle transient signal Y. When V... C <V C2 The system outputs a high-level output signal C, a low-level output signal D, and a high-level single-particle transient signal Y. When V C1 >V C >V C2 The system outputs high-level C and D signals and a low-level single-particle transient signal Y. Specifically, S3 inputs the load transient signal X and the single-particle transient signal Y generated by S2 into a two-input AND gate G1 for logical operation and outputs the output signal EN. When X is high and Y is high, EN is high, controlling the transmission gate S1 to be turned on; otherwise, EN is low, and the transmission gate S1 is turned off. Specifically, S4 refers to the voltage differential current module based on the V value of S1 when transmission gate S1 in S3 is turned on. C V CS The output signals C and D of S2 generate a hardening current I to counteract the effects of single-event transient SET. RHBD ; S5 specifically refers to: the activated transmission gate S1 will... RHBD The current collection node transmitted to the sampling resistor Ri, I RHBD With DC current I DC Inductor sampling current I SENSE Slope compensation current I SLOPE The common current flows through the sampling resistor Ri, generating a voltage signal V. SUM ; through I RHBD The compensating effect offsets V C The single-particle transient fluctuation makes V SUM Signal and V CThe signal changes synchronously, thus stabilizing the output period of the PWM comparator. PWM The signal ensures that the output voltage of the DC-DC converter remains stable.
[0015] Strengthening current I in S4 RHBD The voltage differential to current conversion module is based on V C With V CS The compensation current is obtained by converting the voltage difference, and the specific control logic is as follows: When a positive SET occurs, i.e., V C >V C1 At that time, I RHBD = (V C -V CS ) / R i The output signal C is low, I RHBD To V SUM Injected current at the node; When a negative SET occurs, I RHBD = (V CS -V C ) / R i The output signal D is low, I RHBD From V SUM Current is extracted from the node.
[0016] S5 V SUM The signal generation and change logic is divided into three operating conditions: Operating condition one is the positive SET operating condition, specifically: I RHBD To V SUM Node injection current, V SUM =(I DC +I SENSE +I SLOPE +I RHBD )×R i This offsets the positive fluctuations of VC, making V SUM With V C Synchronous increase; Operating condition two is a negative SET operating condition, specifically: I RHBD From V SUM Node current draw, V SUM =(I DC +I SENSE +I SLOPE -I RHBD )×R i This offsets the negative fluctuations of VC, making V SUM With V C Synchronously decrease, and when I RHBD Greater than I DC I SENSE I SLOPE When the superposition value is V, SUM=0; Operating condition three is the no-SET or load transient condition, specifically: transmission gate S1 is open, I RHBD =0, V SUM =(I DC +I SENSE +I SLOPE )×R i Adjust V PWM The signal is used to maintain a stable output.
[0017] The beneficial effects of this invention are: (1) The single-event transient hardening system and its hardening method for DC-DC converters provided by the present invention, by controlling the output node voltage V of EA. C Real-time detection is performed, and when a single-particle transient is detected, a signal is introduced related to V. C Strengthening current I that matches the direction and amplitude of change RHBD Make the positive input signal V of the PWM comparator SUM With negative input signal V C Maintaining synchronized changes fundamentally avoids the influence of V. C The problem of PWM comparator mis-triggering caused by abnormal offset is effectively suppressed, and the abnormal PWM duty cycle caused by SET is significantly reduced, thus significantly reducing the output voltage ripple and fluctuation amplitude of the DC-DC converter.
[0018] (2) The single-event transient (SET) hardening system and its hardening method for DC-DC converters provided by this invention can distinguish between SETs and load transients, thus avoiding impact on the normal dynamic response performance of the DC-DC converter. The system introduces coordinated control between a load transient detection module and a SET detection module, activating the hardening path to generate a hardening current I only when there is no load transient and an SET occurs. RHBD During normal load transient or steady-state operation, the reinforced current path remains closed and does not participate in loop regulation. Therefore, this invention does not weaken the normal dynamic response capability of the DC-DC converter to load changes, and avoids the negative impact of traditional passive reinforcement methods on the transient performance and stability of the DC-DC converter loop.
[0019] (3) The present invention provides a single-event transient hardening system and its hardening method for DC-DC converters, wherein the hardening current I RHBD By V C With reference voltage V CS The voltage difference between them is obtained in real time, and its magnitude depends on the V caused by SET. C The offset magnitude adapts to change. When a positive SET occurs, I... RHBD = (V C -V CS ) / R i To VSUM Node injection current; when a negative SET occurs, I RHBD = (V CS -V C ) / R i From V SUM Node current drawdown. When the SET disturbance is strong, the compensation current increases accordingly; when the SET disturbance weakens and recovers, the compensation current decreases synchronously until it disappears, so that the system smoothly transitions back to normal operating state, thereby avoiding overcompensation or undercompensation problems and improving the reliability of the hardening.
[0020] (4) The single-event transient hardening system and its hardening method for DC-DC converters provided by the present invention directly act on the input side of the PWM comparator. It has strong compatibility and low implementation cost. It does not require modification of the compensation resistor and capacitor parameters of the error amplifier, nor does it require reducing the output impedance of the error amplifier to sacrifice the loop gain. The anti-SET effect can be achieved by introducing a hardening module at the front end of the PWM comparator. It has good circuit portability and is suitable for various DC-DC converter architectures that use PWM modulation and peak current mode control. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the single-event transient hardening system for DC-DC converters according to the present invention; Figure 2 This is a schematic diagram of the key waveforms of the single-event transient hardening method for DC-DC converters in this invention. Detailed Implementation
[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0023] Example 1 This invention provides a single-event transient hardening system for DC-DC converters, such as... Figure 1 As shown, it includes an error amplifier EA, a transmission gate S1, and a two-input AND gate G1. The output node voltage V of the error amplifier EA is... C Resistors R are connected respectively C The system includes a voltage limiting module, a PWM comparator, and a voltage sampling output module; it also includes a load transient detection module, a single-event transient detection module, and a voltage differential current conversion module, with the single-event transient detection module connected to the voltage sampling output module; a two-input AND gate G1 is connected to the load transient detection module, the single-event transient detection module, and the transmission gate S1, respectively; the voltage differential current conversion module is connected to the error amplifier EA, the voltage sampling output module, and the single-event transient detection module, respectively; and the output signal EN of the two-input AND gate G1 is connected to one end of the transmission gate S1.
[0024] Example 2 Based on Example 1, the voltage sampling output module outputs three signals, namely V C1 V CS V C2 And V C1 >V CS >V C2 V C1 With V C2 Connect to the single-particle transient detection module respectively, V CS Connect the voltage differential to current conversion module input terminal. The load transient detection module includes comparator OP1 and comparator OP2, which are connected to a DC-DC converter. The positive input terminal of comparator OP1 is connected to the reference voltage V. REF1 The negative input terminal of comparator OP2 is connected to a reference voltage V. REF2 The negative input terminal of comparator OP1 and the positive input terminal of comparator OP2 are both connected to the feedback voltage V of the DC-DC converter. FB The feedback voltage V of the DC-DC converter FB The signal is also input to the positive input terminal of the error amplifier EA. The output signal A of comparator OP1 and the output signal B of comparator OP2 are connected to a two-input AND gate G2. The output of G2 is the load transient signal X, which is connected to the two-input AND gate G1.
[0025] Example 3 Based on the above embodiments, the single-event transient detection module includes comparators OP3 and OP4, with the positive input terminal of comparator OP3 connected to V. C1 The negative input of comparator OP4 is connected to V. C2 The negative input terminal of comparator OP1 and the positive input terminal of comparator OP2 are both connected to V. C The output signal C of comparator OP1 and the output signal D of comparator OP2 are connected to a two-input NAND gate G3. The output of G3 is a single-event transient signal Y, which is connected to a two-input AND gate G1. The output signals C of comparator OP1 and D of comparator OP2 are connected to the input of a voltage-to-current converter module. The input of the voltage-to-current converter module is connected to the output node voltage V of error amplifier EA. C and the V of the voltage sampling output module CS .
[0026] Example 4 Based on the above embodiment, the transmission gate S1 is connected to a sampling resistor R. i Sampling resistor R i One end of the transmission gate S1 is also connected to a DC current I. DC Inductor sampling current ISENSE With slope compensation current I SLOPE Sampling resistor R i The other end is grounded. Sampling resistor R i The end connected to transmission gate S1 is V SUM Signal generation node, V SUM The signal generation node is connected to the positive input of the PWM comparator, and the PWM comparator outputs a pulse signal V. PWM Compensation resistor R C The other end is connected to a compensation capacitor C C Compensation capacitor C C The other end is grounded.
[0027] Through the EA output node V C When a SET occurs, it is controlled by current compensation. V SUM Signal follows V C The signal changes synchronously to ensure the output signal of the PWM comparator. V PWM A method to keep the output voltage of a DC-DC converter stable by keeping it constant.
[0028] Example 5 This embodiment provides a single-event transient hardening method for DC-DC converters, employing the single-event transient hardening system for DC-DC converters provided in the above embodiment, specifically including the following steps: S1, collecting feedback voltage V FB and output node voltage V C Generate V C1 V CS V C2 ; S2, compared to V FB The load transient signal X is generated by comparing it with the reference voltage, and then compared with V. C With V C1 V C2 Generate a single-particle transient signal Y and output signals C and D; S3 inputs signals X and Y into the two-input AND gate G1 to obtain EN. EN controls the transmission gate S1 to be turned on only when both X and Y are high, otherwise it is turned off. S4, when transmission gate S1 is turned on, based on V C With V CS The voltage difference and the level states of the output signals C and D generate a reinforcement current I. RHBD ; S5, I RHBD offset V C The SET fluctuation causes V SUMSignal and V C Synchronous signal changes stabilize the PWM comparator output, ensuring that the DC-DC converter output voltage remains stable.
[0029] Example 6 Based on Example 5, S1 specifically refers to: acquiring the feedback voltage V of the DC-DC converter through the load transient detection module. FB and reference voltage V REF1 V REF2 The voltage V at the output node is sampled and output via the voltage sampling output module. C Sampling is performed to generate three reference signals V. C1 V CS V C2 And V C1 >V CS >V C2 Meanwhile, the voltage limiting module limits V C Signal amplitude limiting; S2 specifically refers to: comparing the feedback voltage V through the load transient detection module. FB With reference voltage V REF1 V REF2 The size of V REF1 >V FB >V REF2 Output a high-level load transient signal X when the signal is active, otherwise output a low-level load transient signal X; compare the signal V with the signal V through the single-event transient detection module. C With V C1 V C2 The size of V C >V C1 The system outputs a low-level output signal C, a high-level signal D, and a high-level single-particle transient signal Y. When V... C <V C2 The system outputs a high-level output signal C, a low-level output signal D, and a high-level single-particle transient signal Y. When V C1 >V C >V C2 The system outputs high-level C and D signals and a low-level single-particle transient signal Y. Specifically, S3 inputs the load transient signal X and the single-particle transient signal Y generated by S2 into a two-input AND gate G1 for logical operation and outputs the output signal EN. When X is high and Y is high, EN is high, controlling the transmission gate S1 to be turned on; otherwise, EN is low, and the transmission gate S1 is turned off. Specifically, S4 refers to the voltage differential current module based on the V value of S1 when transmission gate S1 in S3 is turned on. C V CSThe output signals C and D of S2 generate a hardening current I to counteract the effects of single-event transient SET. RHBD ; S5 specifically refers to: the activated transmission gate S1 will... RHBD The current collection node transmitted to the sampling resistor Ri, I RHBD With DC current I DC Inductor sampling current I SENSE Slope compensation current I SLOPE The common current flows through the sampling resistor Ri, generating a voltage signal V. SUM ; through I RHBD The compensation effect counteracts the single-particle transient fluctuations of VC, making V SUM Signal and V C The signal changes synchronously, thus stabilizing the output period of the PWM comparator. PWM The signal ensures that the output voltage of the DC-DC converter remains stable.
[0030] Among them, the reinforcement current I in S4 RHBD The voltage differential to current conversion module is based on V C With V CS The compensation current is obtained by converting the voltage difference, and the specific control logic is as follows: When a positive SET occurs, i.e., V C >V C1 At that time, I RHBD = (V C -V CS ) / R i The output signal C is low, I RHBD To V SUM Injected current at the node; When a negative SET occurs, I RHBD = (V CS -V C ) / R i The output signal D is low, I RHBD From V SUM Current is extracted from the node.
[0031] S5 V SUM The signal generation and change logic is divided into three operating conditions: Operating condition one is the positive SET operating condition, specifically: I RHBD To V SUM Node injection current, V SUM =(I DC +I SENSE +I SLOPE +I RHBD )×R i This offsets the positive fluctuations of VC, making V SUM With V CSynchronous increase; Operating condition two is a negative SET operating condition, specifically: I RHBD From V SUM Node current draw, V SUM =(I DC +I SENSE +I SLOPE -I RHBD )×R i This offsets the negative fluctuations of VC, making V SUM With V C Synchronously decrease, and when I RHBD Greater than I DC I SENSE I SLOPE When the superposition value is V, SUM =0; Operating condition three is the no-SET or load transient condition, specifically: transmission gate S1 is open, I RHBD =0, V SUM =(I DC +I SENSE +I SLOPE )×R i Adjust V PWM The signal is used to maintain a stable output.
[0032] Example 7 Based on the single-event transient hardening system for DC-DC converters provided in the above embodiments, the following is given: Figure 2 The diagram shows a key waveform of the anti-single-event transient hardening method applied to a DC-DC converter. Figure 2 In the five waveform graphs, the vertical dashed lines divide the horizontal axis into five time periods, and the waveforms in each graph correspond to each other within the same time period. During the time periods t1, t3, and t5, the entire system is in steady-state operation; neither load transients nor single-event transients have occurred. V C = V C_Normal The voltage sampling output module output remains constant. V C1 > V C = V CS > V C2 In the load transient detection module V REF1 > V FB > V REF2 load transient signal X The value is 1, in the single-event transient detection module. VC1 > V C > V C2 Single-event transient signal Y When the input is 0, the output signal EN of the two-input AND gate G1 is 0, the transmission gate S1 is open, and the voltage difference to current conversion module... I RHBD = ( V C - V CS ) / R i = 0, positive input of PWM comparator V SUM = ( I DC + I SENSE + I SLOPE )* R i ,like Figure 2 As shown, where I DC For a fixed value, ( I SENSE + I SLOPE The waveform is a sawtooth wave, and the negative input of the PWM comparator is... V C The PWM comparator compares the signals at the positive and negative input terminals. V SUM = V C It outputs a pulse signal at regular intervals.
[0033] During time interval t2, the entire system is in positive SET mode. At this time, no load transients occur, and the EA output node experiences a positive SET. V C = V C_+SET The voltage sampling output module outputs an upward fluctuation over time followed by a slow recovery. V C1 > V CS = V C_Normal > V C2 At this time V CS The output voltage of EA is equal to the system's stable operating voltage. V C_Normal In the load transient detection module V REF1 > VFB > V REF2 load transient signal X The value is 1, in the single-event transient detection module. V C = V C_+SET > V C1 > V C2 The comparator OP3 output signal C A value of 0 indicates a positive SET (Single-Effect Transient) signal. Y With the output signal EN of the two-input AND gate G1 set to 1, the transmission gate S1 is turned on, and the voltage-to-current conversion module... I RHBD = ( V C - V CS ) / R i And a positive SET signal C control I RHBD Past V SUM Node injection current, positive input of PWM comparator V SUM = ( I DC + I SENSE + I SLOPE + I RHBD )* R i ,like Figure 2 As shown, I RHBD It is a casual V C A current signal that changes synchronously. The negative input of the PWM comparator is... V C = V C_+SET It can be found that through I RHBD The compensation made V SUM Signal follows V C The signal changes synchronously, and the PWM comparator compares the signals at the positive and negative input terminals. V SUM = V CThe system outputs a pulse signal every hour, with the time difference between each pulse being the same as that during steady-state operation, thus ensuring the output node of the error amplifier EA. V C When a positive SET occurs V PWM It remains unchanged.
[0034] During the time period t4, the entire system is in negative SET mode. At this time, no load transients occur, but the EA output node experiences a negative SET. V C = V C_-SET The voltage fluctuates downwards over time and recovers slowly; the voltage sampling output module outputs... V C1 > V CS = V C_Normal > V C2 At this time V CS The output voltage of EA is equal to the system's stable operating voltage. V C_Normal In the load transient detection module V REF1 > V FB > V REF2 load transient signal X The value is 1, in the single-event transient detection module. V C1 > V C2 > V C = V C_-SET The comparator OP4 output signal D A value of 0 indicates a negative SET, a single-event transient signal. Y With the output signal EN of the two-input AND gate G1 set to 1, the transmission gate S1 is turned on, and the voltage-to-current conversion module... I RHBD = ( V CS - V C ) / R i And negative SET signal D control I RHBD Past V SUM Node current extraction, positive input of PWM comparator V SUM =(I DC + I SENSE + I SLOPE - I RHBD )* R i ,when I RHBD > I DC + I SENSE + I SLOPE hour, V SUM =0. I RHBD It is a casual V C A current signal that changes synchronously. The negative input of the PWM comparator is... V C = V C_-SET It can be found that through I RHBD The compensation made V SUM Signal follows V C The signal changes synchronously. The PWM comparator compares the signals at the positive and negative input terminals, and when... V SUM = V C The system outputs a pulse signal every hour, with the time difference between each pulse being the same as that during steady-state operation, thus ensuring the output node of the error amplifier EA. V C When a negative SET occurs V PWM It remains unchanged.
[0035] The entire system still operates under transient load conditions. This is the normal transient load operating state of a DC-DC converter, therefore it is not... Figure 2 This is shown in the diagram; only the system state is described here. At this point, a load transient occurs. V FB change, V C Follow V FB A change occurred, but SET did not happen. The voltage sampling output module outputs... V C1 > V CS = V C > VC2 The load transient detection module showed V FB > V REF1 > V REF2 or V REF1 > V REF2 > V FB load transient signal X The value is 1, in the single-event transient detection module. V C1 > V C > V C2 Single-event transient signal Y When the input is 0, the output signal EN of the two-input AND gate G1 is 0, the transmission gate S1 is open, and the voltage difference to current conversion module... I RHBD = ( V C - V CS ) / R i = 0, positive input of PWM comparator V SUM = ( I DC + I SENSE + I SLOPE )* R i The negative input of the PWM comparator is V C And with V FB The change occurs. The PWM comparator compares the signals at the positive and negative input terminals; when... V SUM = V C It outputs a pulse signal and adjusts the time interval between pulses.
Claims
1. A single-event transient hardening system for DC-DC converters, characterized in that, It includes an error amplifier EA, a transmission gate S1, and a two-input AND gate G1, wherein the output node voltage V of the error amplifier EA is... C Resistors R are connected respectively C Voltage limiting module, PWM comparator and voltage sampling output module; It also includes a load transient detection module, a single-event transient detection module, and a voltage differential current conversion module. The single-event transient detection module is connected to the voltage sampling output module. The two-input AND gate G1 is connected to the load transient detection module, the single-event transient detection module, and the transmission gate S1, respectively. The voltage differential current conversion module is connected to the error amplifier EA, the voltage sampling output module, and the single-event transient detection module, respectively. The output signal EN of the two-input AND gate G1 is connected to one end of the transmission gate S1.
2. The single-event transient hardening system for a DC-DC converter according to claim 1, characterized in that, The voltage sampling output module outputs three signals, namely V C1 V CS V C2 And V C1 >V CS >V C2 The V C1 With V C2 Connect to the single-event transient detection module and VC respectively. S Connect the voltage differential to current module input terminal.
3. The single-event transient hardening system for a DC-DC converter according to claim 2, characterized in that, The load transient detection module includes comparator OP1 and comparator OP2, and comparator OP1 and comparator OP2 are connected to a DC-DC converter; The positive input terminal of the comparator OP1 is connected to a reference voltage V. REF1 The negative input terminal of the comparator OP2 is connected to a reference voltage V. REF2 The negative input terminal of comparator OP1 and the positive input terminal of comparator OP2 are both connected to the feedback voltage V of the DC-DC converter. FB The feedback voltage V of the DC-DC converter FB The signal is also input to the positive input terminal of the error amplifier EA. The output signal A of the comparator OP1 and the output signal B of the comparator OP2 are connected to a two-input AND gate G2. The output of G2 is the load transient signal X, which is connected to the two-input AND gate G1.
4. The single-event transient hardening system for a DC-DC converter according to claim 3, characterized in that, The single-event transient detection module includes comparators OP3 and OP4, with the positive input of comparator OP3 connected to V. C1 The negative input terminal of the comparator OP4 is connected to V. C2 The negative input terminal of comparator OP1 and the positive input terminal of comparator OP2 are both connected to V. C The output signal C of comparator OP1 and the output signal D of comparator OP2 are connected to a two-input NAND gate G3. The output of G3 is a single-event transient signal Y, which is connected to a two-input AND gate G1. The output signals C of comparator OP1 and D of comparator OP2 are connected to the input of a voltage-to-current converter module. The input of the voltage-to-current converter module is connected to the output node voltage V of error amplifier EA. C and the V of the voltage sampling output module CS .
5. The single-event transient hardening system for a DC-DC converter according to claim 4, characterized in that, The transmission gate S1 is connected to a sampling resistor R. i The sampling resistor R i One end of the transmission gate S1 is also connected to a DC current I. DC Inductor sampling current I SENSE With slope compensation current I SLOPE The sampling resistor R i The other end is grounded; the sampling resistor R i The end connected to transmission gate S1 is V SUM Signal generation node, the V SUM The signal generation node is connected to the positive input terminal of the PWM comparator, which outputs a pulse signal V. PWM .
6. The single-event transient hardening system for a DC-DC converter according to claim 5, characterized in that, The compensation resistor R C The other end is connected to a compensation capacitor C C The compensation capacitor C C The other end is grounded.
7. A method for resisting single-particle transient hardening, characterized in that, The single-event transient hardening system for DC-DC converters as described in claim 6 is specifically as follows: S1, collecting feedback voltage V FB and output node voltage V C Generate V C1 V CS V C2 ; S2, compared to V FB The load transient signal X is generated by comparing it with the reference voltage, and then compared with V. C With V C1 V C2 Generate a single-particle transient signal Y and output signals C and D; S3 inputs signals X and Y into the two-input AND gate G1 to obtain EN. EN controls the transmission gate S1 to be turned on only when both X and Y are high, otherwise it is turned off. S4, when transmission gate S1 is turned on, based on V C With V CS The voltage difference and the level states of the output signals C and D generate a reinforcement current I. RHBD ; S5, I RHBD offset V C The SET fluctuation causes V SUM Signal and V C Synchronous signal changes stabilize the PWM comparator output, ensuring that the DC-DC converter output voltage remains stable.
8. The method for single-event transient hardening of a DC-DC converter according to claim 7, characterized in that, S1 specifically refers to: acquiring the feedback voltage V of the DC-DC converter through the load transient detection module. FB and reference voltage V REF1 V REF2 The voltage V at the output node is sampled and output via the voltage sampling output module. C Sampling is performed to generate three reference signals V. C1 V CS V C2 And V C1 >V CS >V C2 Meanwhile, the voltage limiting module limits V C Signal amplitude limiting; S2 specifically refers to: comparing the feedback voltage V through the load transient detection module. FB With reference voltage V REF1 V REF2 The size of V REF1 >V FB >V REF2 Output a high-level load transient signal X when the signal is active, otherwise output a low-level load transient signal X; compare the signal V with the signal V through the single-event transient detection module. C With V C1 V C2 The size of V C >V C1 The system outputs a low-level output signal C, a high-level signal D, and a high-level single-particle transient signal Y. When V... C <V C2 The system outputs a high-level output signal C, a low-level output signal D, and a high-level single-particle transient signal Y. When V C1 >V C >V C2 The system outputs high-level C and D signals and a low-level single-particle transient signal Y. Specifically, S3 inputs the load transient signal X and the single-particle transient signal Y generated by S2 into a two-input AND gate G1 for logical operation and outputs the output signal EN. When X is high and Y is high, EN is high, controlling the transmission gate S1 to be turned on; otherwise, EN is low, and the transmission gate S1 is turned off. Specifically, S4 refers to the voltage differential current module based on the V value of S1 when transmission gate S1 in S3 is turned on. C V CS The output signals C and D of S2 generate a hardening current I to counteract the effects of single-event transient SET. RHBD ; S5 specifically refers to: the activated transmission gate S1 will... RHBD The current collection node transmitted to the sampling resistor Ri, the I RHBD With DC current I DC Inductor sampling current I SENSE Slope compensation current I SLOPE The common current flows through the sampling resistor Ri, generating a voltage signal V. SUM ; through the I RHBD The compensation effect counteracts the single-particle transient fluctuations of VC, making the V SUM Signal and V C The signal changes synchronously, thus stabilizing the output period of the PWM comparator. PWM The signal ensures that the output voltage of the DC-DC converter remains stable.
9. The method for single-event transient hardening of a DC-DC converter according to claim 8, characterized in that, The reinforcement current I mentioned in S4 RHBD The voltage differential to current conversion module is based on V C With V CS The compensation current is obtained by converting the voltage difference, and the specific control logic is as follows: When a positive SET occurs, i.e., V C >V C1 At that time, I RHBD = (V C -V CS ) / R i The output signal C is low, I RHBD To V SUM Injected current at the node; When a negative SET occurs, I RHBD = (V CS -V C ) / R i The output signal D is low, I RHBD From V SUM Current is extracted from the node.
10. The method for single-event transient hardening of a DC-DC converter according to claim 8, characterized in that, S5 V SUM The signal generation and change logic is divided into three operating conditions: Operating condition one is the positive SET operating condition, specifically: I RHBD To V SUM Node injection current, V SUM =(I DC +I SENSE +I SLOPE +I RHBD )×R i This offsets the positive fluctuations of VC, making V SUM With V C Synchronous increase; Operating condition two is a negative SET operating condition, specifically: I RHBD From V SUM Node current draw, V SUM =(I DC +I SENSE +I SLOPE -I RHBD )×R i This offsets the negative fluctuations of VC, making V SUM With V C Synchronously decrease, and when I RHBD Greater than I DC I SENSE I SLOPE When the superposition value is V, SUM =0; Operating condition three is the no-SET or load transient condition, specifically: transmission gate S1 is open, I RHBD =0, V SUM =(I DC +I SENSE +I SLOPE )×R i Adjust V PWM The signal is used to maintain a stable output.