A wireless optical communication link indication system and method

Abstract

The present application relates to the field of electronic circuit and optical communication technology, provide a kind of wireless optical communication link indication system and method.The system includes transmitting end and receiving end;The transmitting end includes control unit and optical transmitter, the control unit is used to monitor to user data when driving optical transmitter sends effective optical signal, no data is sent to send with low duty ratio burst sequence constitutes idle optical signal;The receiving end includes optical receiver, direct-current blocking impedance network unit, decoding discrimination unit and indication unit;The optical receiver is used to receive free space optical signal and output original electrical signal;The direct-current blocking impedance network unit is used to perform direct current suppression processing to the original electrical signal to obtain alternating current coupling signal, and the present system suppresses background light direct current component by direct-current blocking impedance network unit, and replaces pure amplitude threshold criterion by protocol feature discrimination, reduces the misjudgment caused by background light.

Description

Technical Field

[0001] This invention relates to the fields of electronic circuits and optical communication technology, and in particular to a wireless optical communication link indication system and method. Background Technology

[0002] Wireless optical communication (such as free-space optical communication) uses lasers or light-emitting devices to transmit optical signals in free space, such as air. To facilitate installation, debugging, operation, and maintenance, communication terminals typically need to provide link status indicators, such as whether the link is aligned, whether it is under interference, or whether it is misaligned.

[0003] In existing link indication methods, the common practice is to determine the signal based on the amplitude, average value, or threshold of the output current / voltage of the optical receiver detector. However, in practical applications, the receiver may obtain higher receiving power through large-aperture lenses or optical collection devices, which may also introduce background light (such as sunlight, lamplight, etc.) into the receiving channel, causing the detector to generate a large DC component or low-frequency component.

[0004] Traditional circuit networks lack specific impedance frequency selectivity, leading to saturation or misjudgment by subsequent comparators. Relying solely on amplitude or average values ​​for link indication can result in misinterpretations of link alignment due to background light, impacting debugging efficiency and operational reliability.

[0005] Furthermore, in wireless optical communication links, user service data may be intermittent or bursty. During periods without user data, if the transmitter does not send an identifiable signal, the receiver will have difficulty distinguishing between a misaligned link and an aligned link that is idle, which will further exacerbate the problem of unreliable indication.

[0006] Therefore, a link indication scheme is needed that can still provide identifiable link criteria when there is no user data, and can suppress the influence of background light DC and reduce false positives. Summary of the Invention

[0007] In order to overcome the shortcomings of the prior art, the present invention addresses the technical problem of how to provide a verifiable link alignment / interference / misalignment indication mechanism to reduce misjudgment and improve the reliability of idle link indication when the background light introduces DC bias and there are idle intervals in the service data.

[0008] The wireless optical communication link indication system provided by this invention includes: a transmitter and a receiver;

[0009] The transmitter includes a control unit and an optical transmitter. The control unit is used to drive the optical transmitter to send an effective optical signal when user data is detected, and to send an idle optical signal consisting of a low duty cycle burst sequence when there is no data.

[0010] The receiving end includes an optical receiver, a DC blocking impedance network unit, a decoding and discrimination unit, and an indication unit;

[0011] The optical receiver is used to receive free-space optical signals and output raw electrical signals;

[0012] The DC blocking impedance network unit is used to perform DC suppression processing on the original electrical signal to obtain an AC coupled signal;

[0013] The decoding and discrimination unit is used to perform feature matching on the AC coupling signal based on the protocol to obtain a discrimination result;

[0014] The indicator unit is used to output a link alignment or misalignment indication based on the discrimination result.

[0015] Preferably, the logical constraint of the low duty cycle burst sequence is: it is sent in a preset periodic time window T, and the transmission duration in each periodic window is τ, and τ is less than T and greater than 0.

[0016] Preferably, the control unit sends at least one preset sequence containing high and low level changes within each cycle time window to form an AC burst feature in the signal corresponding to the low duty cycle burst sequence.

[0017] Preferably, the control unit generates a pseudo-random sequence with preset polynomial constraints as the preset sequence through a linear feedback shift register.

[0018] Preferably, the feature matching includes: the decoding discrimination unit performs frame synchronization on the AC coupling signal, and obtains a discrimination result based on the type field as to whether the decoded frame is a valid data frame corresponding to a valid optical signal or an idle data frame corresponding to an idle optical signal.

[0019] Preferably, the decoding discrimination unit performs a verification calculation on the verification field of the decoded frame; in response to the verification calculation passing, the decoded frame is confirmed to be valid, and the discrimination result is generated accordingly.

[0020] Preferably, the DC blocking impedance network unit includes an AC coupling network composed of series capacitors. The AC coupling network utilizes the AC impedance characteristics of the capacitor elements to form a high-pass filter network, performing a preprocessing operation that blocks the DC component and retains the AC modulation component.

[0021] Preferably, the decoding and discrimination unit includes a correlation detection unit, which is used to perform correlation operations on the AC coupling signal to obtain a correlation peak; in response to the correlation peak satisfying a preset threshold, the corresponding time window in the AC coupling signal is locked as a candidate frame, and a protocol field extraction operation is performed on the candidate frame.

[0022] Preferably, the logic switching performed by the indication unit satisfies the following hysteresis condition:

[0023] When the discrimination result indicating link alignment is obtained N times consecutively, the control outputs a link alignment indication;

[0024] When the discrimination result indicating link misalignment is obtained M times consecutively, the control outputs a link misalignment or interference indication, where N and M are positive integers.

[0025] Preferably, a wireless optical communication link indication method, based on the above system, includes:

[0026] S10. Perform data monitoring and send idle optical signals consisting of periodic low duty cycle burst sequences when there is no user data.

[0027] S20. Receive free-space optical signals and convert them into raw electrical signals. Use a DC blocking impedance network to perform DC suppression processing on the raw electrical signals to obtain AC coupling signals.

[0028] S30. Perform feature matching on the AC coupling signal based on the protocol to obtain a discrimination result;

[0029] S40. In response to the determination result indicating link alignment, output a link alignment indication; or in response to the determination result indicating link misalignment, output an interference or misalignment indication.

[0030] Compared with related technologies, the wireless optical communication link indication system provided by the present invention has the following advantages:

[0031] (1) The DC component of the background light is suppressed by the DC blocking impedance network unit, and the false judgment caused by the background light is reduced by replacing the simple amplitude threshold criterion with the protocol feature discrimination;

[0032] (2) When there is no user data, the receiver can still obtain verifiable link criteria and improve the reliability of link indication during idle period.

[0033] (3) By adopting relevant detection, verification and hysteresis decision mechanisms, the ability to resist external light interference and noise is improved, and the indication jitter is avoided. Attached Figure Description

[0034] Figure 1 This is a structural block diagram of the wireless optical communication link indication system of the present invention;

[0035] Figure 2 A timing diagram of the idle optical signal in low duty cycle burst mode;

[0036] Figure 3 This is a schematic circuit topology diagram of a DC blocking impedance network unit;

[0037] Figure 4 Flowchart for decoding discrimination and anti-interference hysteresis indication;

[0038] Figure 5 This is a schematic diagram of the main functional structure of a remote wireless optical communication component system;

[0039] Figure 6 This is a schematic diagram of the circuit principle of the optical transmitter at the transmitting end;

[0040] Figure 7 A schematic diagram of the circuit principle of the optical receiver and front-end processing at the receiving end;

[0041] Figure 8 This is a schematic diagram of the driving and isolation circuit for the indicator unit.

[0042] Reference numerals: 100, transmitter; 110, control unit; 111, data input interface; 112, data status determination unit; 113, sequence generation unit; 114, timing gating unit; 120, transmitter; 121, light source; 200, receiver; 210, optical receiver; 220, DC blocking impedance network unit; 221, AC coupling network; 222, bias network; 230, decoding and discrimination unit; 231, correlation detection unit; 240, indication unit; 241, decision state machine; 242, output drive unit; 243, indicator. Detailed Implementation

[0043] The contents disclosed in this specification allow for the understanding and implementation of other embodiments and technical effects of the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the various technical details in this specification can be adjusted, combined, or replaced according to different application needs, without departing from the spirit and substance of the present invention.

[0044] It should be noted that, without causing technical inconsistencies, the following embodiments and the technical features described therein can be combined with each other. It should also be understood that the terminology used in the embodiments of this invention is only for describing specific implementation schemes and is not intended to limit the scope of protection of this invention.

[0045] For ease of understanding, in this embodiment, the optical signal transmitted when user data is present is called the valid optical signal, and the optical signal transmitted when no user data is present is called the idle optical signal; the data used to form the idle optical signal is called the preset sequence, wherein the preset sequence is a pseudo-random sequence in an optional implementation. Furthermore, the protocol features mentioned herein refer to structured features that the receiving end can verify, and protocol features may include frame synchronization features, type differentiation features, and verification features, etc.

[0046] Please see Figures 1 to 4This invention provides a wireless optical communication link indication system and method based on impedance networks. The system generally includes: a transmitter 100, a receiver 200, and an indication component for outputting link status.

[0047] The core of the system is that when there is no user data, the transmitter still sends an idle optical signal with structural characteristics. The receiver uses the characteristics of the DC blocking impedance network unit to first suppress the DC component introduced by the background light, and then judges the received signal based on the protocol characteristics, thereby outputting a link alignment or interference / misalignment indication.

[0048] Please see Figure 1 The transmitting end 100 includes an optical transmitter 120 and a control unit 110; the receiving end 200 includes an optical receiver 210, a DC blocking impedance network unit 220, a decoding and discrimination unit 230, and an indication unit 240. The control unit 110 can be implemented using a field-programmable gate array, a microcontroller, a digital signal processor, or a combination thereof, and it is provided with a data input interface 111 for connecting user data output from a host computer, service board, or protocol stack.

[0049] The optical transmitter 120 may include a laser device (e.g., a laser diode) and a driving circuit (e.g., a current-driven / modulated drive) to convert the electrical signal output by the control unit 110 into a modulated optical signal that propagates in free space. By separating protocol processing / data generation and photoelectric conversion / emission into two parts, the control unit 110 and the optical transmitter 120, the transmitter structure is clear, facilitating the reuse of control logic under different light source devices or different driving topologies, thereby benefiting system engineering implementation and maintenance / replacement.

[0050] It should be noted that the optical receiver 210 may include a photodetector (such as a photodiode), a transimpedance amplifier, and necessary bias and limiting circuitry to convert the incident light signal into an electrical signal and provide a certain amplitude. The DC blocking impedance network unit 220 is located after the optical receiver 210 to suppress the DC component or slowly changing component caused by background light, outputting an AC component more suitable for protocol discrimination to subsequent stages. By setting the DC blocking impedance network unit 220 in the receiving link, the receiver no longer uses the DC bias level as a basis for link existence, thereby reducing the risk of misjudgment caused by background light under large-aperture light receiving conditions.

[0051] It is worth noting that the decoding and discrimination unit 230 is used to decode and discriminate the DC-blocked signal based on protocol characteristics, and its output discrimination result is given to the indication unit 240. The indication unit 240 may include a general-purpose input / output interface, a relay / drive circuit, and an indicator light (or other visual device) for outputting link alignment or interference / misalignment indications. By adopting a structure of protocol characteristic discrimination + indication output, the link indication is transformed from a simple amplitude threshold judgment to a verifiable judgment, thereby improving the interpretability of the indication conclusion: for example, it can clearly distinguish between receiving a valid signal / idle signal that conforms to the protocol and level changes caused only by background light or other light sources.

[0052] To further illustrate the feasibility of the present invention and its correspondence with engineering implementation, the following section, in conjunction with the system functional structure diagram and circuit schematic provided by the customer, discusses... Figures 1 to 4 The possible implementation methods of each functional unit in the schematic diagram are explained in detail.

[0053] In one specific implementation, the control unit 110 may correspond to a programmable logic device (e.g., a field-programmable gate array FPGA) or a processor module in an engineering platform. For example... Figure 5 As shown, the network interface and its subsequent data interface circuit can be implemented as the hardware implementation of the data input interface 111; the FPGA can be implemented as the specific implementation of the control unit 110.

[0054] Further integration Figure 5 As shown, the internal logic of the FPGA can be divided into a data state determination unit 112, a sequence generation unit 113, and a timing gating unit 114. The data state determination unit 112 monitors whether there is Ethernet data input at the network interface; when no data is determined, the sequence generation unit 113 generates a preset idle sequence; the timing gating unit 114 controls the optical emission drive circuit to operate in a low duty cycle burst mode. This FPGA-based integrated design allows the state switching logic of the present invention (data transmission valid optical signal / no data transmission idle optical signal) to be directly reused and implemented on existing communication link platforms, thus facilitating engineering implementation and platform expansion.

[0055] On the transmitting side, the light emitter 120 and the light source 121 can correspond to the light emission driving circuit + light source device combination in the engineering platform. Figure 6 Taking the schematic diagram of the transmitting circuit shown as an example, it can be used to realize the current driving or modulation driving of the light source device, so that the digital modulation signal output by the control unit 110 is converted into a modulation light signal that propagates in free space.

[0056] Specifically, such as Figure 6As shown, the data output from the FPGA port (including user data and idle data) is amplified, filtered, and then loaded onto the laser to generate an optical signal. In the circuit, U1, R3, R5, and R6 form a non-inverting amplifier circuit, with R5 and R6 controlling the amplification factor, and R3 providing a circuit for the bias current. C3 is a resonant capacitor used to cancel the equivalent inductance of the light-emitting device, while C2, R4, C1, and R2 are used to improve the signal response speed. The laser D1 and R1 form a light-emitting circuit, modulating the AC signal output from the previous circuit into an optical signal for transmission. C4 is responsible for power supply filtering for the light source. By employing a structure where the control unit outputs a modulation signal—a driving circuit drives the light source—this invention achieves electro-optical conversion without limiting the specific driving topology, thus facilitating compatibility with different light source types, driving methods, and power consumption constraints.

[0057] On the receiving side, the optical receiver 210 can correspond to a photodetector + front-end amplification / processing circuit in the engineering platform. Figure 7 Taking the schematic diagram of the receiving circuit shown as an example, a photodetector (e.g., a photodiode) is used to convert the received light into an electrical signal, and a front-end amplifier circuit is used to generate an electrical signal output with a usable amplitude.

[0058] Specifically, such as Figure 7 As shown, C5, C6, and L1 are used for receiver power supply filtering. A reverse voltage is applied to detector PD1 so that the current output by R9 is proportional to the light intensity received by detector PD1. U1 is a current-to-voltage circuit, where R7 serves as a feedback resistor.

[0059] The DC blocking impedance network element 220 can be implemented corresponding to the AC coupling and biasing circuit in an engineering platform. Figure 7 Taking the receiving front-end circuit as an example, the signal output by U1 is sent to the FPGA for processing after passing through the DC blocking filter capacitor C12. C12, as a key impedance element, constitutes a hardware DC blocking network. C12 filters out DC interference signals generated by ambient light, so that the FPGA ultimately receives only AC signals, which include actual user data or idle data. Through the above-described implementation, this invention can disclose a feasible circuit path for DC blocking filtering without exposing specific device parameters, thereby helping to meet the requirement of full disclosure in the specification.

[0060] The decoding and discrimination unit 230 can correspond to the digital processing logic in the engineering platform (such as the internal logic of a field-programmable gate array or processor firmware). It can cooperate with related detection, frame synchronization, type differentiation, and verification protocol discrimination processes to realize link status judgment. Figure 8Taking the anti-interference module and indicator circuit shown as an example, it can be used as one of the hardware implementations of the indicator unit 240 to convert the decoding and discrimination results into different states of the indicator device (e.g., on / off, constantly on / blinking, etc.). Specifically, as shown... Figure 8 As shown, when the FPGA determines that user data or idle data has been received, it outputs an indicator level signal. After amplification (e.g., through transistor Q1 and operational amplifier U6), the relay RL1 is energized. At this time, the indicator light DS1 changes from on to off (or from off to on) when the power is on, thus physically indicating the link status. By applying the path from the protocol's verifiable judgment result to the indicator output to a concrete engineering circuit, the complete closed-loop link of this invention, from signal generation, free space transmission, receiving preprocessing to indicator output, can be clearly understood.

[0061] Please see Figure 2 The control unit 110 can be internally divided into a data status determination unit 112, a sequence generation unit 113, and a timing gating unit 114. Of course, these modules can also be implemented using the same field-programmable gate array logic or firmware flow, and the specific module division method is not limited. The data status determination unit 112 is used to determine whether there is user data to be sent. This can be achieved by detecting whether the transmit first-in-first-out buffer is empty, detecting whether the protocol stack has generated frames to be sent, or detecting the buffer count value, etc.

[0062] By introducing a data status determination unit 112, the transmitter can clearly switch between two states in terms of timing: when there is data, it sends a valid optical signal; when there is no data, it enters an idle transmission mode. This helps to avoid the receiver being unable to determine whether the link is misaligned or aligned but there is no service when the system is completely idle during idle periods.

[0063] More importantly, when the data status determination unit 112 determines that there is no user data, the sequence generation unit 113 generates a preset sequence. The preset sequence can be a fixed sequence, a repeating sequence, or a pseudo-random sequence; in an optional implementation, the preset sequence is a pseudo-random sequence. By using the preset sequence as the idle transmission content, the idle optical signal has reproducible and matchable structural characteristics, which is beneficial for the receiver to perform verification and judgment based on protocol characteristics or related detection, avoiding making alignment conclusions based solely on waveform changes.

[0064] It should be noted that when the preset sequence is a pseudo-random sequence, the sequence generation unit 113 can be implemented using a linear feedback shift register.

[0065] Specifically, the shift register bit width n can be set, and several feedback taps can be selected for XOR feedback to form a preset polynomial; at the same time, an initial seed can be set for power-on initialization or periodic updates. The pseudo-random sequence can be truncated to a certain length as idle data load as needed.

[0066] By setting the generation method of the pseudo-random sequence to configurable parameters such as polynomials / sequence lengths / initial seeds, the implementation details can be made public and reproducible, which is conducive to the specification meeting the requirement of full disclosure and also beneficial for the receiving end to perform matching verification using the same parameters when needed.

[0067] It is worth mentioning that the timing gating unit 114 is used to form a periodic low-duty-cycle burst transmission. It can set the periodic time window T and control the transmission duration τ within each periodic time window, satisfying 0 < τ < T. One implementation method is to use a counter: the counter outputs an enabling transmission gating signal in the interval [0, τ) and a disabling transmission gating signal in the interval [τ, T);

[0068] Another implementation method is to use a periodic trigger pulse + monostable delay, and the gating is opened for a duration of τ after triggering. By introducing the above gating mechanism, the idle optical signals are presented as periodic bursts, which is conducive to retaining obvious AC components after DC blocking filtering and facilitating subsequent-stage detection;

[0069] At the same time, the transmitting end does not continuously output at full duty cycle during the idle period, which is conducive to achieving an engineering balance in terms of power consumption and the ratio of device working time.

[0070] It should be noted that within the τ time when gating enables transmission, the control unit 110 is configured to transmit at least one preset sequence containing high and low level changes within each periodic time window. Here, at least one segment can include: single-segment mode: continuously outputting a segment of sequence bit stream within the τ time;

[0071] multi-segment mode: outputting two or more segments of sequences within the τ time, with short intervals inserted between segments;

[0072] segmented mode: splitting the sequence into several sub-sequences and distributing them within one or more periodic time windows.

[0073] By using the description of at least one segment, the scheme can cover the timing configurations under different link conditions, which is conducive to improving the adaptability of the system and avoiding implementation bypass due to different numbers of transmitted segments.

[0074] Please refer to Figure 3 , the DC blocking impedance network unit 220 includes an AC coupling network 221, and the AC coupling network 221 can include a series coupling capacitor and cooperate with a bias resistor, a feedback network or a subsequent-stage amplifier circuit to form the AC coupling network 221. In free-space optical communication, the receiving end is usually configured with a lens or an optical collection structure to increase the received power. Background light forms a relatively stable light input on the photodetector, which is likely to form a DC bias or a low-frequency slow-changing component at the output of the transimpedance amplifier. When only relying on the level amplitude or average value for link indication, the background light may cause false lighting.

[0075] By identifying the source of the DC component of the background light, targeted DC blocking filtering can be used to remove the DC bias from the link indication criteria, thereby reducing misjudgments caused by background light interference.

[0076] It is important to note that the series capacitor in the AC coupling network 221 is used to block the DC component, causing the signal to vary around the bias level in the subsequent stage. The bias resistor in the bias network provides the operating point required by the input of the subsequent stage, preventing the input of the subsequent comparator or analog-to-digital converter from being floating. If necessary, a feedback network can also be set to match the coupling network with the input impedance of the preceding / following stage, maintaining the amplitude and phase characteristics within the passband.

[0077] By setting up an AC coupling network 221, the high and low level changes brought about by the effective optical signal and the idle optical signal are retained in AC form, while the DC component caused by the background light is attenuated. This makes it easier for the subsequent decoding and discrimination unit 230 to make judgments based on structured features rather than based on the magnitude of the DC level.

[0078] In one implementation, the high-pass cutoff frequency formed by the series coupling capacitor and the equivalent input resistance can be selected as follows: first, determine the minimum effective change frequency to be retained based on the link bit rate, synchronization word length, frame structure and related detection requirements, and then set the high-pass cutoff frequency to be lower than that frequency but higher than the range affected by DC / slow change components.

[0079] By providing the parameter selection logic, DC blocking filtering is no longer a general description, but a circuit design step that can be implemented according to the protocol and link conditions. This is conducive to the full disclosure of the specification and also to the reproduction of the implementation.

[0080] Please see Figure 4 The decoding and discrimination unit 230 is used to determine whether the received signal conforms to the protocol characteristics of a valid optical signal or an idle optical signal.

[0081] Frame synchronization features can be synchronization words, frame header identifiers, or other preset modes. The decoding and discrimination unit 230 can employ sliding window matching: calculating the matching degree by sliding the input bitstream according to the window length, and determining the frame start position after reaching a preset condition. Alternatively, it can first use correlation detection to obtain candidate start points before proceeding to field parsing. By using frame synchronization features, the receiver can locate frame boundaries, which is beneficial for the consistency of subsequent field interpretation and avoids random fluctuations caused by background light or other interference being treated as legitimate frames.

[0082] After synchronization is complete, the decoding discrimination unit 230 reads the type field and distinguishes the decoded frame into a valid data frame or an idle data frame based on the type field. The type field can use a fixed bit width and define at least two values: for example, the first value represents a valid data frame and the second value represents an idle data frame.

[0083] By setting type-distinguishing features, the system can include idle frames sent when there is no user data in the protocol framework, allowing the receiving end to identify them as legitimate signals belonging to its own protocol. This helps to output link alignment indications during idle periods, avoiding misjudging aligned frames without service as misaligned frames.

[0084] It is worth noting that the verification feature can employ cyclic redundancy check (CRC) or other check codes. The decoding and discrimination unit 230 can perform verification calculations on the type field, length field, and payload field, and compare them with the intra-frame verification field. Only when the verification passes is it determined to be a valid optical signal or an idle optical signal. By adding the verification feature, the conditions for being judged as aligned are improved from synchronization + valid type to synchronization + valid type + passed verification, thereby helping to reduce misjudgments caused by external light sources, noise, or signals not conforming to this protocol coincidentally satisfying some fields.

[0085] It should be noted that in this invention, the criterion for link alignment indication is not that a high level indicates alignment, but rather: when the decoding discrimination unit 230 determines that the received signal conforms to the protocol characteristics of a valid optical signal or an idle optical signal, it outputs alignment; when it determines that the signal is invalid and not idle, it outputs interference / misalignment.

[0086] By adopting the above two-choice discrimination rule, the link indication is based on the characteristics of the structured protocol, which helps to exclude the background light DC component, non-protocol modulated light and other situations from the alignment, making the indication result closer to the fact that the local identifiable signal has been received.

[0087] In some implementations, the decoding and discrimination unit 230 includes a correlation detection unit 231. The correlation detection unit 231 performs correlation operations on the received signal with a preset synchronization word or a preset sequence, and triggers protocol field discrimination of candidate frames when the correlation peak value meets a preset threshold condition. The correlation detection can use a synchronization word as a template or a segment of a preset sequence as a template. The template can come from a fixed synchronization word defined by the protocol or from a preset sequence generation rule. The correlation operation can be performed in the bit domain or in the sampling / symbol domain.

[0088] By providing correlated templates, the receiver can still locate possible structured sequences through correlation peaks even in the presence of noise, amplitude fluctuations, or superimposed interference, thereby improving the reliability of synchronization triggering.

[0089] When the correlation peak exceeds a preset threshold, the correlation detection unit 231 outputs the candidate frame start point or candidate window, and then enters the field parsing and verification process. If the field discrimination fails, no alignment conclusion is output. By combining correlation threshold triggering and field verification, the system can both improve the capture capability by utilizing correlation detection and rely on the verification mechanism to avoid treating accidental correlation peaks as legitimate frames, thus helping to maintain the robustness of the indication results in complex lighting environments.

[0090] Please see Figure 1 The indicator unit 240 may include a decision state machine 241 and an output driver unit 242 (e.g., a general purpose input / output interface / relay driver / LED indicator driver). In some embodiments, the indicator unit 240 satisfies a hysteresis decision condition.

[0091] The indicator unit 240 receives the discrimination result output by the decoding and discrimination unit 230. Its decision logic can be set as follows: when the signal is judged as valid or idle N times consecutively, the output link alignment indication is given; when the signal is judged as invalid and not idle M times consecutively, the output link misalignment or interference indication is given, where N and M are positive integers. By employing continuous decision-making (hysteresis), the indicator output does not frequently switch due to single bit errors, transient obstructions, or short-term interference, thereby reducing indicator jitter and improving the consistency of the debugging personnel's judgment of the lamp status meaning.

[0092] The output driver unit 242 can map the judgment result to different light states, such as: constantly lit when aligned, flashing or off when misaligned / interfering; it can also use dual-color LED indicator lights or buzzers. The output driver can directly drive LED indicator lights, or control relays through a universal input / output interface to adapt to high-power indicator lights. By providing multiple light state mapping methods, the system can adapt to different terminal appearances and electrical interfaces, thereby facilitating product deployment and maintenance / replacement.

[0093] It is worth mentioning that, when implementing the above system, a corresponding methodology can be developed:

[0094] Step S10: When user data is detected, the control unit drives the light transmitter to send a valid light signal;

[0095] Step S20: When user data is detected to be missing, the control unit generates a preset sequence and sends idle optical signals in a periodic low duty cycle burst mode;

[0096] Step S30: The receiving end performs DC blocking filtering on the received optical signal to suppress the DC component of the background light;

[0097] Step S40: Decode the filtered signal according to the protocol and determine whether it conforms to the protocol characteristics of a valid or idle optical signal. Output a link alignment or interference / misalignment indication based on the determination result. By expressing the system operation process in a step-by-step manner, software / firmware development and testing can directly set up test cases step by step. For example, test the scenarios of pure background light alignment but no service alignment and external interference light with service, which is beneficial to verify whether the link indication rules are consistent with expectations.

[0098] More importantly, without departing from the spirit and essence of this invention, the following alternative implementations are also possible:

[0099] (1) The preset sequence can also be a fixed sequence or a specific training sequence, as long as the receiver can use it as part of the protocol features for verification and discrimination. By allowing multiple sequence forms, idle transmission can be achieved under different protocol stacks or different chip resource conditions, which is conducive to expanding the adaptation range.

[0100] (2) The number of segments transmitted within a single time window, the length of each segment, and the interval between segments can all be configured according to link conditions. By allowing the configuration of these timing parameters, the product can adjust the balance between acquisition probability and resource usage under different ambient light conditions and different link loss conditions.

[0101] (3) In addition to AC-coupled networks, DC components can also be suppressed by digital high-pass / baseline recovery after sampling by analog-to-digital converters, as long as the purpose of suppressing the DC influence of background light and retaining the recognizable components of the protocol can be achieved. By allowing the combination of analog and digital, different hardware architectures can achieve this effect.

[0102] (4) Type differentiation can be achieved through different frame headers, different synchronization words, or different flag bits; verification can also be performed using different encoding methods. By not limiting field naming and encoding methods, the scheme is more compatible with existing protocols, while still maintaining the core idea of ​​verifiable discrimination.

[0103] The specific embodiments of the present invention have been described in detail above. It should be understood that the above embodiments are merely illustrative examples. Those skilled in the art can adjust, combine, or replace the structure of each unit, signal format, threshold setting, parameter values, and process details without departing from the principle of the present invention, and all such adjustments should fall within the protection scope of the present invention.

Claims

1. A wireless optical communication link indication system, characterized in that, Includes a transmitter (100) and a receiver (200); The transmitter (100) includes a control unit (110) and an optical transmitter (120). The control unit (110) is used to drive the optical transmitter (120) to send an effective optical signal when user data is detected, and to drive the optical transmitter (120) to send an idle optical signal composed of a low duty cycle burst sequence when there is no user data. The control unit (110) is configured to send at least one preset sequence containing high and low level changes within each cycle time window to form an AC burst feature corresponding to the low duty cycle burst sequence in the idle optical signal; The receiving end (200) includes an optical receiver (210), a DC blocking impedance network unit (220), a decoding and discrimination unit (230), and an indication unit (240). The optical receiver (210) is used to receive free-space optical signals and output raw electrical signals; The DC blocking impedance network unit (220) is used to perform DC suppression processing on the original electrical signal to obtain an AC coupling signal; The decoding and discrimination unit (230) includes a correlation detection unit (231), which is used to perform correlation operations on the AC coupling signal to obtain the correlation peak value, and lock the corresponding time window in the AC coupling signal as a candidate frame when the correlation peak value meets a preset threshold. The decoding and discrimination unit (230) is also used to perform frame synchronization and protocol field extraction on the candidate frame, determine whether the candidate frame is a valid data frame corresponding to the valid optical signal or an idle data frame corresponding to the idle optical signal based on the type field, and perform verification calculation on the verification field; In response to the candidate frame being determined as a valid data frame or an idle data frame and the verification calculation passing, the candidate frame is confirmed to be valid, and a discrimination result indicating link alignment is generated accordingly. In response to the candidate frame not being confirmed as a valid data frame or an idle data frame, or the verification calculation failing, a judgment result indicating that the link is misaligned or interfered with is generated; The indicator unit (240) is used to output a link alignment, link misalignment, or interference indication based on the discrimination result, and the logic switching performed by the indicator unit (240) satisfies the following hysteresis condition: when the discrimination result indicating link alignment is obtained N times consecutively, the link alignment indication is controlled to be output; when the discrimination result indicating link misalignment or interference is obtained M times consecutively, the link misalignment or interference indication is controlled to be output, where N and M are positive integers.

2. The wireless optical communication link indication system according to claim 1, characterized in that, The low The logical constraints of the duty cycle burst sequence are: transmission is performed in a preset periodic time window T, and the transmission duration within each periodic time window is τ, satisfying 0 < τ. <T。 3. The wireless optical communication link indication system according to claim 1, characterized in that, The control unit (110) includes a data state determination unit (112), a sequence generation unit (113), and a timing gating unit (114). The data status determination unit (112) is used to determine whether there is user data to be sent; The sequence generation unit (113) is used to generate the preset sequence when there is no user data; The timing gating unit (114) is used to control the preset sequence to be output to the optical transmitter (120) in a low duty cycle burst mode.

4. The wireless optical communication link indication system according to claim 3, characterized in that, The sequence generation unit (113) generates a pseudo-random sequence with preset polynomial constraints through a linear feedback shift register as the preset sequence.

5. The wireless optical communication link indication system according to claim 3, characterized in that, The timing gating unit (114) is configured to output a single preset sequence within a periodic time window, or to output at least two preset sequences within a periodic time window, or to split the preset sequence into several sub-sequences and output them within one or more periodic time windows.

6. The wireless optical communication link indication system according to claim 1, characterized in that, The DC blocking impedance network unit (220) includes an AC coupling network (221) composed of series capacitors. The AC coupling network (221) uses the AC impedance characteristics of the capacitor elements to form a high-pass filter network, which performs a preprocessing operation to block the DC component and retain the AC modulation component.

7. The wireless optical communication link indication system according to claim 6, characterized in that, The DC blocking impedance network unit (220) further includes a bias network (222), which is connected to the input terminal of the AC coupling network (221) and is used to provide a working bias for the input terminal of the decoding and discrimination unit (230).

8. The wireless optical communication link indication system according to claim 1, characterized in that, The correlation detection unit (231) uses a preset synchronization word or at least one segment of the preset sequence as a correlation template to perform correlation operations on the AC coupling signal in the bit domain, sampling domain, or symbol domain.

9. The wireless optical communication link indication system according to claim 1, characterized in that, The indicator unit (240) includes a decision state machine (241), an output drive unit (242), and an indicator (243). The decision state machine (241) is used to generate an indication control signal based on the discrimination results obtained N times or M times in a row; The output drive unit (242) is used to drive the indicator (243) to output a link alignment, link misalignment or interference indication according to the indication control signal.

10. A method for indicating a wireless optical communication link, characterized in that, Execution based on the system according to any one of claims 1 to 9, comprising: S10. Perform data monitoring, send an effective optical signal when user data is detected, send an idle optical signal consisting of a periodic low duty cycle burst sequence when there is no user data, and send at least one preset sequence containing high and low level changes within each periodic time window to form AC burst characteristics in the idle optical signal. S20. Receive free-space optical signals and convert them into raw electrical signals. Use a DC blocking impedance network to perform DC suppression processing on the raw electrical signals to obtain AC coupling signals. S30. Perform correlation operation on the AC coupling signal to obtain the correlation peak value. In response to the correlation peak value satisfying a preset threshold, lock the corresponding time window in the AC coupling signal as a candidate frame. S40. Perform frame synchronization and protocol field extraction on the candidate frame, determine whether the candidate frame is a valid data frame corresponding to the valid optical signal or an idle data frame corresponding to the idle optical signal based on the type field, and perform verification calculation on the verification field. S50. In response to the candidate frame being determined as a valid data frame or an idle data frame and the verification calculation passing, the candidate frame is confirmed to be valid, and a judgment result indicating link alignment is generated accordingly; in response to the candidate frame not being confirmed as a valid data frame or an idle data frame, or the verification calculation failing, a judgment result indicating link misalignment or interference is generated. S60. When the discrimination result indicating link alignment is obtained N times consecutively, a link alignment indication is output; when the discrimination result indicating link misalignment or interference is obtained M times consecutively, a link misalignment or interference indication is output, where N and M are positive integers.

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