Trench MOSFET with periodic P-island shielding

Abstract

The embodiment of the invention relates to a trench MOSFET with periodic P island shielding. A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure also includes a drift layer of the first conductivity type over the semiconductor substrate, a channel layer of the second conductivity type over the drift layer, and a source region of the first conductivity type over the channel layer. The second conductivity type is opposite the first conductivity type. A plurality of trenches penetrate the source region, the channel layer, and a portion of the drift layer. A gate electrode is located within each of the plurality of trenches via a gate insulating film, and a plurality of shielding structures of the second conductivity type are located around the gate electrode. The plurality of shielding structures cover sidewalls and bottoms of the plurality of trenches. The plurality of shielding structures are arranged in an island-like manner.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor devices, and more particularly to trench metal-oxide-semiconductor field-effect transistors (MOSFETs) and their associated shielding techniques. Background Technology

[0002] Trench MOSFETs are widely used in power electronic devices due to their high efficiency and high performance. These devices are designed to handle high voltages and high currents, with reduced on-resistance compared to conventional planar MOSFETs. Trench MOSFETs incorporate a vertical structure in which the gate electrode is placed within a trench etched into the semiconductor substrate, providing a compact and efficient layout.

[0003] Despite their advantages, trench MOSFETs face challenges related to device performance and reliability, especially in high-density integrated circuits. A key issue is the management of parasitic capacitance and electric field, which negatively impact the device's switching performance and overall efficiency. Summary of the Invention

[0004] According to embodiments of this disclosure, a semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes silicon carbide. The semiconductor structure also includes a drift layer of the first conductivity type located above the semiconductor substrate. The semiconductor structure also includes a channel layer of a second conductivity type located above the drift layer. The second conductivity type of the channel layer is opposite to the first conductivity type of the drift layer. The semiconductor structure also includes a source region of the first conductivity type located above the channel layer. The semiconductor structure also includes a plurality of trenches penetrating the source region, the channel layer, and a portion of the drift layer. The semiconductor structure also includes a gate electrode located within each of the plurality of trenches via a gate insulating film. The semiconductor structure also includes a plurality of shielding structures of the second conductivity type located around the gate electrode. The plurality of shielding structures cover the sidewalls and bottom of the plurality of trenches. The plurality of shielding structures are arranged in an island-like manner.

[0005] According to another embodiment of this disclosure, the semiconductor structure includes a plurality of trench structures extending at least partially within a stack of doped semiconductor layers. The plurality of trench structures includes a first trench structure and a second trench structure. A second trench structure is located between two adjacent first trench structures. The semiconductor structure also includes gate structures disposed within the first and second trench structures. The semiconductor structure further includes a plurality of shielding structures at least partially embedded within a stack of doped semiconductor layers surrounding the gate structures within the first trench structures. The plurality of shielding structures are separated by a distance selected based on inducing a three-dimensional pinch-off effect between adjacent shielding structures. The gate structure within the second trench structure is surrounded by the stack of doped semiconductor layers.

[0006] According to another embodiment of this disclosure, the semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes silicon carbide. The semiconductor structure also includes a drift layer of the first conductivity type located above the semiconductor substrate. The semiconductor structure also includes a channel layer of a second conductivity type located above the drift layer. The second conductivity type of the channel layer is opposite to the first conductivity type of the drift layer. The semiconductor structure also includes a source region of the first conductivity type located above the channel layer. The semiconductor structure also includes a plurality of trenches penetrating the source region, the channel layer, and a portion of the drift layer. The semiconductor structure also includes an insulating region lining the plurality of trenches. The insulating region includes a bottom portion, a lower side portion, and a top side portion. The semiconductor structure also includes a gate electrode located within each of the plurality of trenches lining the insulating region. The semiconductor structure also includes a plurality of shielding structures of the second conductivity type located around the gate electrode. The plurality of shielding structures cover the sidewalls and bottom of the plurality of trenches. The plurality of shielding structures are arranged in an island-like manner. Attached Figure Description

[0007] The following detailed description will be better understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the embodiments described herein, in which:

[0008] Figure 1 This is a cross-sectional view of a semiconductor structure after the formation of a stack of doped semiconductor layers, according to an embodiment of the present disclosure;

[0009] Figure 2 This is a cross-sectional view of a semiconductor structure after a heavily doped semiconductor region is formed within a stack of doped semiconductor layers according to an embodiment of the present disclosure;

[0010] Figure 3A This is a top view of a semiconductor structure after a trench structure and a shielding structure have been formed based on a first distribution pattern, according to an embodiment of the present disclosure.

[0011] Figure 3B According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure taken by line A-A' is shown.

[0012] Figure 4A According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure taken by line A-A' shows the alternating pattern of the trench structure formation;

[0013] Figure 4B According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure taken by line A-A' shows the alternating pattern of the formation of heavily doped semiconductor regions;

[0014] Figure 5According to embodiments of this disclosure, as follows Figure 3A The diagram shows a cross-sectional view of the semiconductor structure after an insulating layer has been formed within the trench structure, taken along line A-A'.

[0015] Figure 6A According to embodiments of this disclosure, as follows Figure 3A The diagram shown is a cross-sectional view of the semiconductor structure after the formation of the gate electrode, interlayer dielectric layer, source electrode, and drain electrode, taken along line A-A'.

[0016] Figure 6B According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure taken by line B-B' is shown.

[0017] Figure 6C According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure shown by line A-A' depicts the insulating region with varying thickness.

[0018] Figure 6D According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure taken by line A-A' shows the formation of the shielding region within the source region;

[0019] Figure 6E According to embodiments of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure taken by line A-A' shows the formation of heavily doped semiconductor regions between adjacent shielding regions;

[0020] Figure 6F According to another embodiment of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure shown by line A-A' describes an alternating configuration of shielding structures including shielding regions based on a first distribution pattern;

[0021] Figure 6G According to another embodiment of this disclosure, as follows Figure 3A The cross-sectional view of the semiconductor structure shown by line A-A' depicts an alternating configuration of a shielding structure including a shielding region based on a first distribution pattern and an insulating region with varying thickness.

[0022] Figure 7A This is a top view depicting a semiconductor structure with a trench structure and a shielding structure formed based on a second distribution pattern, according to embodiments of the present disclosure.

[0023] Figure 7B According to embodiments of this disclosure, as follows Figure 7A The cross-sectional view of the semiconductor structure taken by line C-C' is shown.

[0024] Figure 7C According to embodiments of this disclosure, as follows Figure 7A The cross-sectional view of the semiconductor structure taken by line D-D' is shown.

[0025] Figure 7D According to embodiments of this disclosure, as follows Figure 7A The cross-sectional view of the semiconductor structure shown by line C-C' depicts the insulating region with varying thickness.

[0026] Figure 7E According to embodiments of this disclosure, as follows Figure 7A The cross-sectional view of the semiconductor structure shown by line C-C' describes an alternating configuration of shielding structures including shielding regions based on a second distribution pattern;

[0027] Figure 7F According to embodiments of this disclosure, as follows Figure 7A The cross-sectional view of the semiconductor structure shown by line C-C' depicts an alternating configuration of a shielding structure including a shielding region based on a second distribution pattern and an insulating region with varying thickness.

[0028] Figure 8 This is a flowchart depicting the operational steps of manufacturing a semiconductor structure according to embodiments of the present disclosure; and

[0029] Figure 9 This is a flowchart depicting alternating operation steps for manufacturing a semiconductor structure according to embodiments of the present disclosure.

[0030] The accompanying drawings are not necessarily drawn to scale. They are merely schematic representations and are not intended to depict specific parameters of the embodiments of this disclosure. The drawings are intended to depict typical embodiments of this disclosure. In the drawings, similar numbers represent similar elements. Detailed Implementation

[0031] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. The claimed structures and methods may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of various conventional features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0032] For the purposes described below, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives will refer to the disclosed structures and methods, as oriented as shown in the accompanying drawings. Terms such as “above,” “overlying,” “atop,” “on top,” “positioned on,” and “positioned on top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may be present between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0033] To avoid obscuring the presentation of embodiments of this disclosure, some processing steps or operations that may be common in the art may be combined together for presentation and illustration purposes in the following detailed description, and in some cases may not be described in detail. In other cases, some processing steps or operations that may be common in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of the various embodiments of this disclosure.

[0034] In trench MOSFETs, the parasitic capacitance between the gate, source, and drain significantly impacts performance. The electric field distribution within the trench structure can lead to decreased breakdown voltage and increased leakage current, which can compromise both device reliability and efficiency. A key challenge in trench MOSFETs is maintaining oxide reliability, as the electric field tends to concentrate at the bottom corners of the trench when the device is off.

[0035] To mitigate these issues, various shielding techniques have been developed. A common approach involves using a P-type region or "shielding" layer within the trench to manage the electric field distribution and reduce parasitic capacitance. While existing shielding techniques for trench MOSFETs address some parasitic capacitance problems, challenges remain in terms of manufacturing complexity and performance optimization. Traditional P-type shielding regions are typically placed in a fixed configuration, which may not fully optimize electric field management under varying operating conditions and device sizes. For example, although placing a P-type shielding region under the trench can protect the oxide region, it also increases the sheet resistance (Rsp) because the width of the P-type shielding region typically exceeds the width of the trench.

[0036] Embodiments of this disclosure introduce a trench MOSFET design incorporating periodic P-island shielding to address the aforementioned problems. Specifically, embodiments of this disclosure provide P-type shielding regions formed in an island-like manner around a trench. These P-island shielding regions are strategically positioned to protect the oxide electric field in the corners of the trench and in the regions adjacent to these corners. In some embodiments, the P-island shielding regions are arranged in a staggered pattern, while in other embodiments, the P-island shielding regions follow an aligned pattern. The spacing between these P-island regions is chosen to create a three-dimensional (3D) pinch-off effect, which enhances protection for both the corners of the trench and adjacent regions. This approach aims to improve control over the electric field distribution and reduce parasitic effects, thereby improving the performance and reliability of the trench MOSFET without significantly increasing the complexity of the manufacturing process. More particularly, embodiments of this disclosure effectively manage electric fields and parasitic capacitances while maintaining high device density and performance characteristics.

[0037] The following is for reference. Figures 1 to 9 The accompanying drawings describe in detail embodiments of trench MOSFETs with periodic P-island shielding.

[0038] Now for reference Figure 1 According to embodiments of the present disclosure, a cross-sectional view of a semiconductor structure 100 at an intermediate step during a semiconductor manufacturing process is shown. More specifically, Figure 1 The intermediate steps during the formation of a silicon carbide trench MOSFET with periodic p-island shielding are described.

[0039] At this step of the manufacturing process, the semiconductor structure 100 includes alternating layers of semiconductor materials with different dopant concentrations arranged in a stack 10 of doped semiconductor layers. Various types of semiconductor manufacturing operations can be used to form structures such as... Figure 1 The semiconductor structure 100 shown. In particular, various deposition and implantation steps have been performed to form a stack 10 of doped semiconductor layers.

[0040] According to an embodiment, stack 10 includes a first doped semiconductor layer of a first conductivity type made of silicon carbide (SiC) with an added impurity concentration. The first doped semiconductor layer serves as the semiconductor substrate (hereinafter referred to as "substrate") 102 of the semiconductor structure 100. The initial thickness of substrate 102 is approximately 350 μm. During a back-side processing step, substrate 102 can be milled to approximately 100 mm. The impurity concentration in substrate 102 can be approximately 1 × 10⁻⁶. 18 cm -3 Up to approximately 1×10 19 cm -3The conductivity type can vary between P-type and N-type. It should be noted that substrate 102 serves as the drain region for the semiconductor structure 100, providing a path for current. Although the drain region is integrated within substrate 102, in some embodiments, the drain region may be engineered to have different doping characteristics or other modifications to meet specific design requirements, enhance performance, or manage thermal properties.

[0041] Stack 10 also includes a second doped semiconductor layer of a first conductivity type. The second doped semiconductor layer serves as a drift region 104 of the semiconductor structure 100. The drift region 104 is formed above and in contact with the substrate 102. The drift region 104 is made of silicon carbide and has an added impurity concentration lower than that of the substrate 102. Typically, the drift region 104 can be formed by epitaxial growth using the semiconductor substrate 102 as a seed layer. Terms such as “epitaxygrowth and / or deposition” and “epitaxygrowth and / or growth” refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the semiconductor material being grown has the same or substantially similar crystal properties as the semiconductor material on the deposition surface. In some embodiments, the drift region 104 can be formed using chemical vapor deposition (CVD) of a semiconductor material (i.e., SiC). The thickness of the drift region 104 is determined by the device rated voltage. For example, for a 1.2 kV rated device, the thickness of the drift region 104 may be approximately 10 μm. For a 1.2 kV rated device, the impurity concentration in the drift region 104 can be approximately 1 × 10⁻⁶. 16 cm -3 However, the impurity concentration in drift region 104 is not limited to this value and can be around 1 × 10⁻⁶. 14 cm -3 Up to approximately 1×10 17 cm -3 Within this range, it depends on the device's rated voltage.

[0042] Stack 10 also includes a third doped semiconductor layer of a first conductivity type. The third doped semiconductor layer serves as a junction field-effect transistor (JFET) region 108 of the semiconductor structure 100. The JFET region 108 is formed above and in contact with the drift region 104. In some cases, the JFET region 108 can be formed with a higher donor dopant of the first conductivity type, which can be approximately 1 × 10⁻⁶. 15 cm -3 With approximately 1×10 18 cm -3 The thickness varies between these values. The thickness of the JFET region 108 ranges from approximately 0.1 μm to approximately 3.5 μm.

[0043] Stack 10 also includes a fourth doped semiconductor layer of a second conductivity type. The fourth doped semiconductor layer serves as the base region 110 of the semiconductor structure 100. The base region 110 is formed above the JFET region 108. The thickness of the base region 110 is approximately 0.1 μm to approximately 1.0 μm. The impurity concentration of the base region 110 is approximately 1 × 10⁻⁶. 17 cm -3 Or higher. The second conductivity type can be P-type or N-type.

[0044] Stack 10 also includes a fifth doped semiconductor layer of a first conductivity type. The fifth doped semiconductor layer serves as the source region 114 of the semiconductor structure 100. The source region 114 is formed above and in contact with the base region 110. The thickness of the source region 114 is approximately 0.1 μm to approximately 0.5 μm. The source region 114 may include a heavily doped semiconductor layer of a first conductivity type. The dopant concentration of the source region 114 can be, for example, 1 × 10⁻⁶. 19 cm -3 With 1×10 21 cm -3 The changes between them.

[0045] In one or more embodiments, different impurity or dopant concentrations in the stack 10 of doped semiconductor layers can be achieved by ion implantation or diffusion of impurity ions or dopants. For example, in an embodiment where the first conductivity type is N-type and the second conductivity type is P-type, an N-type dopant such as phosphorus (P) or arsenic (As) can be implanted into one or more semiconductor layers of the stack 10 to form an N-type doped semiconductor layer, while a P-type dopant such as boron (B), aluminum (Al), or gallium (Ga) can be implanted into one or more semiconductor layers of the stack 10 to form a P-type doped semiconductor layer.

[0046] Now for reference Figure 2 According to an embodiment of the present disclosure, a cross-sectional view of a semiconductor structure 100 after a heavily doped semiconductor region 206 is formed within a stack 10 is shown.

[0047] In this embodiment, an ion implantation process is performed on the semiconductor structure 100 to form heavily doped semiconductor regions 206 within a stack 10 of doped semiconductor layers. Each heavily doped semiconductor region 206 embedded within the stack 10 extends from the top surface of the source region 114 through a predetermined depth within the drift region 104. The predetermined depth of the heavily doped semiconductor region 206 within the drift region 104 can be from approximately 0.8 μm to approximately 3.5 μm.

[0048] Therefore, various types of ion implantation processes can be used to form the heavily doped semiconductor region 206, achieving this depth. For example, in one embodiment, a random ion implantation process can be used to form the heavily doped semiconductor region 206. In another embodiment, a channelized ion implantation process can be used to form the heavily doped semiconductor region 206. Depending on the dopant concentration of the drift region 104, the heavily doped semiconductor region 206 can be formed to a depth of approximately 1 × 10⁻⁶. 15 cm -3 With approximately 1×10 19 cm -3 The impurity concentration of the second conductivity type varies between these regions. More specifically, the impurity concentration in the heavily doped semiconductor region 206 is at least 10 times greater than the impurity concentration in the drift region 104.

[0049] For illustrative purposes only, and not for limitation, two heavily doped semiconductor regions 206 are shown in the figure. It will be understood that any number of heavily doped semiconductor regions 206 can be formed in the semiconductor structure 100 to meet design requirements.

[0050] Now refer to Figures 3A to 3B According to embodiments of the present disclosure, different views of a semiconductor structure 100 are shown after a plurality of trench structures 310 and shielding structures 306 have been formed based on a first distribution pattern. In this embodiment, Figure 3A This is a top view of semiconductor structure 100; and Figure 3B Is it like this? Figure 3A The cross-sectional view of the semiconductor structure 100 depicted in the figure is taken along line A-A'.

[0051] In this embodiment, the plurality of trenches (hereinafter referred to as "trenches") 310 include those formed in the heavily doped semiconductor region 206 ( Figure 2 The first plurality of trenches (hereinafter referred to as "first trenches") 310a are formed within the stack 10 of doped semiconductor layers, and the second plurality of trenches (hereinafter referred to as "second trenches") 310b are formed within the stack 10 of doped semiconductor layers. The process of forming trenches 310 may include exposing a pattern on a photoresist layer, transferring the pattern to a hard mask layer (not shown) using photolithography and reactive ion etching (RIE) processes, and then transferring the pattern to include the heavily doped semiconductor region 206. Figure 2 ) stacked 10.

[0052] Figure 3B The first trench 310a formed within each heavily doped semiconductor region 206 is shown. As shown, the heavily doped semiconductor regions 206 retained in the semiconductor structure 100 ( Figure 2A shielding structure (or shielding area) 306 is formed around the first trench 310a. More specifically, each shielding structure 306 is disposed along the opposing sidewalls 312 and bottom surface 314 of the first trench 310. In other words, the shielding structure 306 covers the perimeter of the first trench 310a defined by the opposing sidewalls 312 and bottom surface 314. Figure 3B As shown, the upper part of the shielding structure 306 is adjacent to the JFET region 108, the base region 110 and the source region 114, while the bottom part of the shielding structure 306 is surrounded by the drift region 104.

[0053] The second trench 310b exposes the opposite sidewalls of the source region 114, the base region 110, the JFET region 108, the upper sidewall of the drift region 104, and the upper surface of the drift region 104.

[0054] In one or more embodiments, the depth of the first trench 310a and the second trench 310b into the stack 10 (as measured in the -y direction) can vary between approximately 0.8 μm and approximately 3.0 μm. The width of the first trench 310a and the second trench 310b (as measured in the x direction) can vary between approximately 0.3 mm and approximately 2.0 mm.

[0055] After the first trench 310a and the second trench 310b are formed, the thickness of the remaining heavily doped semiconductor material forming the shielding structure 306 can vary between approximately 0.1 mm and approximately 1.0 mm.

[0056] According to an embodiment, after forming a first trench 310a and a second trench 310b in the semiconductor structure 100, a channel region 320 is defined within the base region 110. The channel region 320 is configured to be adjacent to the first trench 310a and the second trench 310b and to contact the JFET region 108 and the source region 114. Therefore, the size of the fourth doped semiconductor layer of the stack 10 providing the base region 110 can be within the range that provides a short-channel effect.

[0057] For simplicity, the first trench 310a and the second trench 310b will be collectively referred to as "trench 310" in the following text.

[0058] Continue to refer to Figure 3A The shielding structure 306, formed in an island-like manner, is arranged around the trench 310 according to a first distribution pattern. In this embodiment, the first distribution pattern includes an interleaved distribution pattern. Specifically, as... Figure 3A As shown, the shielding structure 306 is formed in an interlaced or checkerboard pattern of isolated clusters or segments, where each cluster resembles an "island". The island-like shielding structures 306 are located in non-adjacent areas within the trench 310, with each shielding structure 306 spaced apart or at intervals. L pSeparated, such as Figure 3A As shown.

[0059] distance L p The distance between the shielding structures 306 can be a predetermined value selected based on creating a three-dimensional (3D) pinch-off effect between the shielding structures 306, which enhances protection for the two corners and adjacent areas of the trench 310. In an embodiment, the distance between the shielding structures 306... L p The distance can vary between 0.1 mm and 2.0 mm. Preferably, the distance between the shielding structures 306 is... L p The gap can be at least 0.1 mm to achieve a 3D pinch-off effect. This method aims to improve the control of the electric field distribution and reduce parasitic effects in the semiconductor structure 100.

[0060] Now for reference Figures 4A to 4B According to another embodiment of this disclosure, a cross-sectional view of the semiconductor structure 100 depicts an alternating pattern of trench 310 and shielding structure 306. In this embodiment, Figure 4A and Figure 4B Is along as Figure 3A The cross-sectional view of the semiconductor structure 100 is shown by line A-A'.

[0061] Alternatively, in some embodiments, trenches 310 may be formed within the stack 10 of doped semiconductor layers prior to the formation of the shielding structure 306, such as Figure 4A As shown. In this case, the injection process used to form the shielding structure 306 can be performed on the sidewalls of the stack 10 exposed by the selected trench 310, as shown. Figure 4B As shown.

[0062] The implantation process can be either random ion implantation or channelized ion implantation. The implantation process can be performed until the impurity concentration and thickness of the aforementioned shielding structure 306 are achieved. Based on design requirements, certain regions of the stack 10, including some trenches 310, are masked during the implantation process to prevent the formation of the shielding structure 306 within these regions. In other words, some trenches 310 remain unimplanted, thereby allowing the island-like shielding structure 306 to remain intact. Figure 3A The pattern shown is an alternating distribution.

[0063] Now for reference Figure 5 According to an embodiment of this disclosure, a cross-sectional view of a semiconductor structure 100 after an insulating layer 502 has been formed within the trench 310 is shown. In this embodiment, Figure 5 Is along as Figure 3A The cross-sectional view of the semiconductor structure 100 taken by line A-A' is shown.

[0064] After the shielding structure 306 is formed, the manufacturing process continues by forming an insulating layer 502 within the trench 310 using various types of deposition processes. The insulating layer 502 electrically isolates the subsequently formed gate electrode from the active region of the semiconductor structure 100. The insulating layer 502 substantially covers the relatively vertical sidewalls and the top surface of the shielding structure 306. The insulating layer 502 also covers areas within the un-implanted trench 310, particularly those areas in the trench 310 not protected by the shielding structure 306. More specifically, the insulating layer 502 is deposited along the sidewalls of the source region 114, the base region 110, the JFET region 108, and the drift region 104, and is deposited above the top surface of the drift region 104 exposed by the un-implanted trench 310.

[0065] In one or more embodiments, the insulating layer 502 can be formed by conformal deposition of a gate insulating film. Non-limiting examples of the gate insulating film used to form the insulating layer 502 may include silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), lanthanum oxide (La2O3), zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), etc. In exemplary embodiments, the thickness of the insulating layer 502 can vary between approximately 10 nm and approximately 100 nm.

[0066] Now for reference Figures 6A to 6C According to an embodiment of this disclosure, a cross-sectional view of a semiconductor structure 100 after the formation of a gate electrode 602, an interlayer dielectric layer 630, a top metal layer 650, and a bottom metal layer 662 is shown. In this embodiment, Figure 6A Is along as Figure 3A The cross-sectional view of the semiconductor structure 100 taken by line A-A' shown is shown. Figure 6B Is along as Figure 3A The cross-sectional view of the semiconductor structure 100 taken by line B-B' as described above, and Figure 6C Is along as Figure 3A The cross-sectional view of the semiconductor structure 100 taken by line A-A' is shown.

[0067] The process for forming the gate electrode 602 can be typical and common in the art. The process typically involves depositing a conductive material, such as polysilicon, within a trench 310 lined with an insulating layer 502. The gate electrode 602 and the insulating layer 502 provide a gate structure for the semiconductor structure 100. After forming the gate electrode 602, an interlayer dielectric layer 630 may be formed to fill voids and electrically isolate active regions within the semiconductor structure 100. The interlayer dielectric layer 630 is disposed above the upper surface of the stack 10 of doped semiconductor layers. More specifically, as Figure 6AAs shown, the interlayer dielectric layer 630 covers the upper surface of the shielding structure 306 and partially covers the upper portion of the source region 114. In one or more embodiments, the interlayer dielectric layer 630 may be formed using conformal deposition (e.g., CVD) of a dielectric material such as silicon oxide, silicon nitride, etc. In one or more embodiments, a patterning process may be performed on the interlayer dielectric layer 630 to achieve the shape shown in the figure.

[0068] In the depicted embodiment, a top metal layer 650 is deposited over the interlayer dielectric layer 630 and the exposed portion of the source region 114. The top metal layer 650 provides electrical contact for the source terminals or source electrodes of the source region 114. In some embodiments, similar to the island shield structure 306, heavily doped source contacts of a second conductivity type (e.g., P+ source contacts) may be arranged periodically. This arrangement eliminates the need for additional space for the source contacts, thereby enabling a more aggressive reduction in cell pitch within the semiconductor structure 100.

[0069] A bottom metal layer 662 may be formed on the bottom surface of the substrate 102. The bottom metal layer 662 serves as a drain terminal or drain electrode that provides electrical (ohmic) contact with the substrate 102.

[0070] Now for reference Figure 6C In some embodiments, an insulating region with varying thickness can be created within the trench 310, instead of as... Figures 6A to 6B A conformal layer of insulating material is applied as shown in insulating layer 502. Figure 6C As shown, the alternative configuration of the semiconductor structure 100 is characterized in that the insulating region 610 is formed by a two-step oxidation process in the trench 310 (e.g., Figure 5 The gate oxide material (e.g., silicon oxide SiOx) formed within the region (shown) is composed of this material. This two-step process allows for precise control of the thickness of the bottom portion of the insulating region 610.

[0071] Specifically, a thinner layer of insulating material (e.g., gate oxide) can provide relatively more effective control over the channel, while a thicker layer of insulating material can prevent gate oxide breakdown. The threshold voltage of semiconductor structure 100 can also be controlled using the thickness of the insulating material forming insulating region 610. If the electric field in drift region 104 is too high, the insulating material will degrade over time, negatively impacting the overall lifetime and reliability of semiconductor structure 100. Degradation of the oxide can cause a shift in the threshold voltage. For trench MOSFETs, trenches tend to have a relatively deep profile (e.g., along the y-axis) compared to their width (e.g., the x-axis). Therefore, electric field lines tend to concentrate at the bottom of the trench, resulting in a higher electric field below the trench (e.g., in the -y direction) than in other regions, such as near the sidewalls of the trench.

[0072] like Figure 6C As shown, the insulating region 610 may include an upper portion 604, a lower portion 606, and a bottom portion 608. The thickness of the upper portion 604 is denoted as V. The thickness of the lower portion 606 is denoted as U. The thickness of the bottom portion 608 is denoted as T. Thicknesses U and T may be greater than thickness V. Thicknesses U and T may be the same or different.

[0073] The bottom portion 608 can contact the shielding structure 306. The bottom portion 608 and the shielding structure 306 can help reduce the trench 310 (…). Figure 5 The upper portion 604 may contact at least one of the source region 114, the base region 110, and the JFET region 108. The lower portion 606 may contact at least the JFET region 108 and the drift region 104. The lower portion 606 may help to further reduce the electric field in the trench 310 ( Figure 5 The electric field of the drift region 104 near the side wall and corner of the )

[0074] In the embodiment, the thickness V of the upper portion 604 can vary between approximately 1 nm and 20 nm, the thickness T of the bottom portion 608 can vary between approximately 1 nm and 500 nm, and the thickness U of the lower portion 606 can vary within the range of approximately 1 nm to 500 nm.

[0075] Now for reference Figures 6D to 6G According to embodiments of this disclosure, it is shown that along such Figure 3A The cross-sectional view of the semiconductor structure 100 taken by line A-A' shows the alternating pattern of the shielding structure 306.

[0076] In this embodiment, Figure 6D The diagram illustrates the formation of shielding region 640 within a specific region of source region 114. Shielding region 640 can be formed using various ion implantation processes, wherein the impurity concentration of the second conductivity type ranges from approximately 1 × 10⁻⁶. 19 cm -3 Up to approximately 1×10 21 cm -3 The placement of each shielding region 640 within the source region 114 can be customized to meet specific design requirements. In some embodiments, the shielding region 640 may be formed similarly to the heavily doped semiconductor region 206, having a comparable impurity concentration.

[0077] Figure 6E The diagram illustrates the formation of a heavily doped semiconductor region 206 in the region of stack 10 located between two adjacent shielding regions 640. (See above for reference.) Figure 2The process for forming the heavily doped region 206 is described in detail. This alternative manufacturing process allows the shielding layer to be placed on either side of the heavily doped semiconductor region 206, adjacent to the source region 114. In an embodiment, the shielding region 640 serves as a lateral extension of a second conductivity type, positioned adjacent to the source region 114 and along the upper part of the shielding structure 306. This arrangement also enhances electric field management.

[0078] Figure 6F A semiconductor structure 100 including a shielding region 640 is depicted after the formation of a gate electrode 602, an interlayer dielectric layer 630, a top metal layer 650, and a bottom metal layer 662. In this embodiment, the shielding effect of the shielding structure 306 is further enhanced by including a shielding region 640 on the opposite top side of each shielding structure 306. Figure 6G In the diagram, semiconductor structure 100 is shown with a shielding region 640 located on the opposite top side of shielding structure 306 and having the above reference. Figure 6C The insulating region 610 of varying thicknesses is characterized by the aforementioned regions.

[0079] Now for reference Figures 7A to 7D According to embodiments of the present disclosure, different views of a semiconductor structure 200 are shown after trenches 310 and shielding structures 306 are formed using a second distribution pattern. In this embodiment, Figure 7A This is a top view of semiconductor structure 200. Figure 7B Is along as Figure 7A The diagram shows a cross-sectional view of the semiconductor structure 200 taken along line C-C'. Figure 7C Is along as Figure 7A The cross-sectional view of semiconductor structure 200 taken by line D-D' is shown, and Figure 7D Is along as Figure 7A The cross-sectional view of the semiconductor structure 200 taken by the C-C' line is shown.

[0080] In this embodiment, a shielding structure 306 is formed according to a second distribution pattern. The second distribution pattern comprises an alignment pattern of isolated clusters or segments, where each cluster resembles an "island." The island-like shielding structures 306 are located in consecutive equidistant areas within the trench 310, wherein adjacent shielding structures 306 are spaced apart. L q Separated, such as Figure 7A As shown. As mentioned above, distance L q It can be a predetermined value that can create a 3D pinch-off effect between the shielding structures 306, which enhances the protection of the two corners and adjacent areas of the trench 310. L q The distance can be compared with Figure 3A The distance shown L pSame, or may be different L p In an embodiment, the distance between the shielding structures 306 arranged in an aligned pattern is... L q The distance can vary between 0.1 mm and 2.0 mm. Preferably, the distance between the shielding structures 306 is... L q It can be at least 0.1 mm to achieve a 3D pinch-off effect.

[0081] Figure 7D The illustration depicts a scenario where a semiconductor structure 200 is formed using an aligned distribution pattern. However, instead of a conformal insulating layer 502, this structure incorporates an insulating region 610, characterized by regions of varying thickness, as previously discussed. Figure 6C As stated above.

[0082] Now for reference Figures 7E to 7F According to embodiments of this disclosure, it is shown that along such Figure 7A The diagram shown is a cross-sectional view of the semiconductor structure 200 taken by line C-C', depicting the shielding region 640.

[0083] Figure 7E A semiconductor structure 200 including a shielding region 640 is depicted after the formation of a gate electrode 602, an interlayer dielectric layer 630, a top metal layer 650, and a bottom metal layer 662. As described above, the shielding effect of the shielding structure 306 is further enhanced by including a shielding region 640 on the opposite top side of each shielding structure 306. In this embodiment, the shielding structure 306 is configured according to... Figure 7A The alignment or second distribution pattern shown is positioned. Figure 7E In the diagram, semiconductor structure 200 is shown with a shielding region 640 located on the opposite top side of shielding structure 306 and having the above reference. Figure 6C The insulating region 610 of varying thicknesses is characterized by the aforementioned regions.

[0084] Now for reference Figure 8 According to an embodiment of the present disclosure, a flowchart 800 describing the operational steps for manufacturing a semiconductor structure is shown.

[0085] The process for forming the semiconductor structure begins at step 802: forming a plurality of doped semiconductor layers vertically stacked on a semiconductor substrate of a first conductivity type. The semiconductor substrate is made of silicon carbide. In an embodiment, forming the plurality of doped semiconductor layers vertically stacked on the semiconductor substrate further includes: forming a drift region of the first conductivity type above the semiconductor substrate; forming a JFET region of the first conductivity type above the drift region; forming a base region of the second conductivity type above the JFET region, the base region including a channel region positioned along the sides of the first plurality of trench structures and the second plurality of trench structures; and forming a source region of the first conductivity type above the base region.

[0086] The process continues at step 804: Multiple shielding semiconductor regions of a second conductivity type are formed within the multiple doped semiconductor layers. The second conductivity type is the opposite of the first conductivity type. In an embodiment, forming the multiple shielding semiconductor regions of the second conductivity type further includes selectively implanting regions of the multiple doped semiconductor layers such that each resulting shielding structure includes a heavily doped semiconductor region having an impurity concentration at least 10 times greater than the impurity concentration in the drift region. In an embodiment, selectively implanting regions of the multiple doped semiconductor layers includes at least one of a random ion implantation process or a channelized ion implantation process.

[0087] The process continues at step 806: a first plurality of trench structures are formed within each of the plurality of shielding semiconductor regions to form a plurality of shielding structures. Each shielding structure is formed along the bottom portion and opposite sidewall of the respective trench structure. According to an embodiment, the plurality of shielding structures are configured in an island-like manner following a first distribution pattern and are separated by a distance selected based on creating a 3D pinch-off effect between adjacent shielding structures. For example, the distance separating the plurality of shielding structures is at least 0.1 mm. In one embodiment, the first distribution pattern includes an interleaved distribution pattern. In another embodiment, the first distribution pattern includes an aligned distribution pattern.

[0088] The process continues at step 808: a second plurality of trench structures are formed in the regions of the plurality of doped semiconductor layers located between adjacent shielding structures. It should be noted that the first plurality of trench structures and the second plurality of trench structures are simultaneously formed within the plurality of shielding semiconductor regions and in the regions of the plurality of doped semiconductor layers located between adjacent shielding structures.

[0089] Finally, in step 810, a gate structure is formed within the first plurality of trench structures and the second plurality of trench structures. In an embodiment, forming the gate structure further includes: conformally depositing an insulating layer within the first trench structure and the second trench structure; and depositing a gate electrode within the first trench structure and the second trench structure lined with the insulating layer. In one or more embodiments, the process further includes forming an interlayer dielectric layer over the gate structure, the interlayer dielectric layer extending partially above the upper surface of the plurality of doped semiconductor layers; forming a source terminal electrically connected to a source region; and forming a drain terminal electrically connected to a semiconductor substrate.

[0090] Figure 9 This is a flowchart depicting alternative operation steps for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0091] The alternative process begins at step 902: forming a plurality of doped semiconductor layers vertically stacked on a semiconductor substrate of a first conductivity type. In an embodiment, the semiconductor substrate is made of silicon carbide. In one or more embodiments, forming the plurality of doped semiconductor layers vertically stacked on the semiconductor substrate further includes: forming a drift region of the first conductivity type over the semiconductor substrate; forming a JFET region of the first conductivity type over the drift region; forming a base region of the second conductivity type over the JFET region, the base region including a channel region positioned along the sides of the first plurality of trench structures and the second plurality of trench structures; and forming a source region of the first conductivity type over the base region.

[0092] The process continues at step 904: forming a plurality of trench structures that extend at least partially within a plurality of doped semiconductor layers. The plurality of trench structures includes a first trench structure and a second trench structure. The second trench structure is located between two first trench structures.

[0093] The process continues in step 906: mask second trench structure.

[0094] The process continues at step 908: portions of the multiple doped semiconductor layers exposed by the first trench structure are implanted to form multiple shielding structures, each shielding structure covering the bottom portion and opposite sidewalls of a corresponding first trench structure. According to an embodiment, the multiple shielding structures are configured in an island-like manner following a first distribution pattern and are separated by a distance chosen based on creating a 3D pinch-off effect between adjacent shielding structures. For example, the distance separating the multiple shielding structures is at least 0.1 mm. In one embodiment, the first distribution pattern includes an interleaved distribution pattern. In another embodiment, the first distribution pattern includes an aligned distribution pattern.

[0095] Implanting portions of multiple doped semiconductor layers exposed by a first trench structure to form multiple shielding structures includes implanting the exposed portions of the multiple doped semiconductor layers until each resulting shielding structure includes a heavily doped semiconductor region having an impurity concentration at least 10 times greater than the impurity concentration in the drift region. In an embodiment, implanting portions of the multiple doped semiconductor layers exposed by the first trench structure to form multiple shielding structures includes performing at least one of a random ion implantation process or a channelized ion implantation process.

[0096] Finally, in step 910, a gate structure is formed within a first trench structure and a second trench structure of the plurality of trench structures. In an embodiment, forming the gate structure further includes: removing a mask from the second trench structure; conformally depositing an insulating layer within the first trench structure and the second trench structure; and depositing a gate electrode within the first trench structure and the second trench structure lined with the insulating layer. In one or more embodiments, the process further includes forming an interlayer dielectric layer over the gate structure, the interlayer dielectric layer extending partially above the upper surface of the plurality of doped semiconductor layers; forming a source terminal electrically connected to a source region; and forming a drain terminal electrically connected to a semiconductor substrate.

[0098] Example

[0099] Example 1: A method for forming a semiconductor structure, comprising:

[0100] Multiple doped semiconductor layers are formed and vertically stacked on a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is made of silicon carbide;

[0101] Multiple shielding semiconductor regions of a second conductivity type are formed within multiple doped semiconductor layers; the second conductivity type is opposite to the first conductivity type.

[0102] In each of the multiple shielding semiconductor regions, a first plurality of trench structures are formed to form a plurality of shielding structures, each shielding structure covering the bottom portion and the opposite sidewall of the corresponding trench structure. The plurality of shielding structures are configured in an island-like manner following a first distribution pattern and are separated by a distance selected based on creating a 3D pinch-off effect between adjacent shielding structures.

[0103] A second plurality of trench structures are formed in a region of multiple doped semiconductor layers located between adjacent shielding structures; and

[0104] A gate structure is formed within a first plurality of trench structures and a second plurality of trench structures.

[0105] Example 2: According to the method of Example 1, forming the gate structure further includes:

[0106] An insulating layer is conformally deposited within the first trench structure and the second trench structure; and

[0107] Gate electrodes are deposited within a first trench structure and a second trench structure lined with an insulating layer.

[0108] Example 3: According to the method of either Example 1 or 2, wherein forming a plurality of doped semiconductor layers vertically stacked on a semiconductor substrate further includes:

[0109] A drift region of the first conductivity type is formed above the semiconductor substrate;

[0110] A JFET region of the first conductivity type is formed above the drift region;

[0111] A base region of a second conductivity type is formed above the JFET region, the base region including a channel region positioned along the sides of the first plurality of trench structures and the second plurality of trench structures; and

[0112] A source region of the first conductivity type is formed above the base region.

[0113] Example 4: According to the method of any one of Examples 1 to 3, wherein the first distribution pattern includes an alternating distribution pattern.

[0114] Example 5: According to any of Examples 1 to 4, wherein the first distribution pattern includes an aligned distribution pattern.

[0115] Example 6: According to any one of Examples 1 to 5, wherein the plurality of shielding semiconductor regions forming the second conductivity type further includes:

[0116] Selective regions of multiple doped semiconductor layers are implanted such that each resulting shielding structure includes a heavily doped semiconductor region having an impurity concentration at least 10 times that of the impurity concentration in the drift region.

[0117] Example 7: The method according to any one of Examples 1 to 6, wherein selective implantation of a plurality of doped semiconductor layers includes:

[0118] Perform at least one of random ion implantation process or channelized ion implantation process.

[0119] Example 8: According to the method of any one of Examples 1 to 7, the distance between the multiple shielding structures is at least 0.1 mm.

[0120] Example 9: Based on any one of Examples 1 through 8, the method also includes:

[0121] An interlayer dielectric layer is formed above the gate structure, extending partially above the upper surface of multiple doped semiconductor layers.

[0122] Example 10: The method based on any one of Examples 1 through 9 also includes:

[0123] Forming source terminals electrically connected to the source region; and

[0124] A drain terminal is formed that is electrically connected to the semiconductor substrate.

[0125] Example 11: A method for forming a semiconductor structure, comprising:

[0126] Multiple doped semiconductor layers are formed and vertically stacked on a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is made of silicon carbide;

[0127] Multiple trench structures are formed that extend at least partially within multiple doped semiconductor layers, the multiple trench structures including a first trench structure and a second trench structure, wherein the second trench structure is located between two first trench structures;

[0128] Mask the second trench structure;

[0129] A portion of the multiple doped semiconductor layers exposed by the first trench structure is implanted to form multiple shielding structures, each shielding structure covering the bottom portion and opposite sidewall of a corresponding first trench structure. The multiple shielding structures are arranged in an island-like manner following a first distribution pattern and are separated by a distance chosen based on creating a 3D pinch-off effect between adjacent shielding structures; and

[0130] A gate structure is formed within the first trench structure and the second trench structure in a plurality of trench structures.

[0131] Example 12: According to the method of Example 11, forming the gate structure further includes:

[0132] Remove the mask from the second trench structure;

[0133] An insulating layer is conformally deposited within the first trench structure and the second trench structure; and

[0134] Gate electrodes are deposited within a first trench structure and a second trench structure lined with an insulating layer.

[0135] Example 13: According to the method of any one of Examples 11 and 12, forming a plurality of doped semiconductor layers vertically stacked on a semiconductor substrate further includes:

[0136] A drift region of the first conductivity type is formed above the semiconductor substrate;

[0137] A JFET region of the first conductivity type is formed above the drift region;

[0138] A base region of a second conductivity type is formed above the JFET region, the base region including a channel region positioned along the sides of a first plurality of trench structures and a second plurality of trench structures; and

[0139] A source region of the first conductivity type is formed above the base region.

[0140] Example 14: According to the method of any one of Examples 11 to 13, wherein the first distribution pattern includes an interleaved distribution pattern.

[0141] Example 15: According to any one of Examples 11 to 14, wherein the first distribution pattern includes an aligned distribution pattern.

[0142] Example 16: According to any one of Examples 11 to 15, implanting portions of the plurality of doped semiconductor layers exposed by the first trench structure to form a plurality of shielding structures includes:

[0143] The exposed portions of multiple doped semiconductor layers are implanted until each resulting shielding structure includes a heavily doped semiconductor region having an impurity concentration at least 10 times that in the time-drift region.

[0144] Example 17: According to any one of Examples 11 to 16, implanting portions of the plurality of doped semiconductor layers exposed by the first trench structure to form a plurality of shielding structures includes:

[0145] Perform at least one of random ion implantation process or channelized ion implantation process.

[0146] Example 18: According to the method of any one of Examples 11 to 17, the distance between the multiple shielding structures is at least 0.1 mm.

[0147] Example 19: According to any one of Examples 11 to 18, the method also includes:

[0148] An interlayer dielectric layer is formed above the gate structure, which extends partially above the upper surface of multiple doped semiconductor layers.

[0149] Example 20: The method according to any one of Examples 11 to 19 also includes:

[0150] Forming source terminals electrically connected to the source region; and

[0151] A drain terminal is formed that is electrically connected to the semiconductor substrate.

[0152] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” are intended to include the plural forms as well. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, they specify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that the events or conditions described below may or may not occur, and the description includes both cases where the event occurs and cases where it does not occur.

[0153] For ease of description, spatial relative terms such as “inside,” “outside,” “below,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” etc., are used herein to describe the relationship of an element or feature to another element(s) or feature(s) shown in the figures. In addition to the orientation shown in the figures, spatial relative terms may be intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “below” other elements or features would be oriented “above” other elements or features. Thus, the example term “below” can cover both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein shall be interpreted accordingly.

[0154] As used herein and throughout the specification and claims, approximate language may be used to modify any quantitative expression that allows for variation without altering its underlying function. Therefore, values ​​modified by one or more terms, such as “about,” “approximately,” and “substantially,” are not limited to specified precise values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Herein and throughout the specification and claims, range limitations may be combined and / or interchanged, and unless otherwise indicated by context or language, such ranges are identified and include all subranges contained herein. For example, “about” used for a specific value within a range may be used for two values, and unless otherwise determined by the precision of the instrument used to measure the value, may indicate + / - 10% of the specified value(s).

[0155] Various embodiments of this disclosure have been described for illustrative purposes, but these descriptions are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate comprising silicon carbide; The first type of conductivity drift layer is located above the semiconductor substrate; A second conductivity type channel layer is located above the drift layer, and the second conductivity type of the channel layer is opposite to the first conductivity type of the drift layer; The source region of the first conductivity type is located above the channel layer; Multiple trenches penetrate the source region, the channel layer, and a portion of the drift layer; A gate electrode is located within each of the plurality of trenches via a gate insulating film; as well as The second conductivity type has a plurality of shielding structures located around the gate electrode, wherein the plurality of shielding structures cover the sidewalls and bottom of the plurality of trenches and are arranged in an island-like manner.

2. The semiconductor structure according to claim 1, wherein the plurality of shielding structures are arranged in an interlaced pattern.

3. The semiconductor structure of claim 1, wherein the plurality of shielding structures are arranged in an alignment pattern.

4. The semiconductor structure of claim 1, wherein the plurality of shielding structures are separated by a predetermined interval in a first direction, and the predetermined interval is greater than 0.1 mm and less than 2.0 mm.

5. The semiconductor structure of claim 1, wherein the plurality of shielding structures comprises an impurity concentration of at least 10 times that of the impurity concentration in the drift layer.

6. A semiconductor structure, comprising: Multiple trench structures extend at least partially within a stack of doped semiconductor layers, the multiple trench structures including a first trench structure and a second trench structure, wherein the second trench structure is located between two adjacent first trench structures; A gate structure is disposed within the first trench structure and the second trench structure; as well as Multiple shielding structures, at least partially embedded within the stack of doped semiconductor layers surrounding the gate structure within the first trench structure, are separated at a distance chosen based on inducing a three-dimensional pinch-off effect between adjacent shielding structures. The gate structure within the second trench structure is surrounded by the stack of doped semiconductor layers.

7. The semiconductor structure according to claim 6, wherein the gate structure further comprises: An insulating layer is applied to the first trench structure and the second trench structure; as well as The gate electrode is disposed above the insulating layer.

8. The semiconductor structure of claim 6, wherein the plurality of shielding structures are configured in an island-like manner.

9. The semiconductor structure of claim 6, wherein the plurality of shielding structures are distributed in an alternating pattern.

10. The semiconductor structure of claim 6, wherein the plurality of shielding structures are distributed in an alignment pattern.

11. The semiconductor structure of claim 6, wherein the stacking of the doped semiconductor layers comprises: A semiconductor substrate of a first conductivity type, said semiconductor substrate being made of silicon carbide; The drift region of the first conductivity type is located above the semiconductor substrate; The JFET region of the first conductivity type is located above the drift region; A base region of a second conductivity type is disposed above the JFET region, the second conductivity type being opposite to the first conductivity type, the base region including a channel region positioned along the plurality of trench structures; and The source region of the first conductivity type is located above the base region.

12. The semiconductor structure according to claim 11, further comprising: The source terminal is electrically connected to the source region; as well as The drain terminal is electrically connected to the semiconductor substrate.

13. The semiconductor structure of claim 6, wherein the distance separating the plurality of shielding structures is at least 0.1 mm.

14. A semiconductor structure comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate comprising silicon carbide; The first type of conductivity drift layer is located above the semiconductor substrate; A second conductivity type channel layer is located above the drift layer, and the second conductivity type of the channel layer is opposite to the first conductivity type of the drift layer; The source region of the first conductivity type is located above the channel layer; Multiple trenches penetrate the source region, the channel layer, and a portion of the drift layer; An insulating region is lined on the plurality of trenches, wherein the insulating region includes a bottom portion, a lower side portion and an upper side portion; A gate electrode is located in each of the plurality of trenches lined with the insulating region; as well as The second conductivity type has a plurality of shielding structures located around the gate electrode, wherein the plurality of shielding structures cover the sidewalls and bottom of the plurality of trenches and are arranged in an island-like manner.

15. The semiconductor structure of claim 14, wherein the thickness of the bottom portion of the insulating region is greater than the thickness of the upper portion of the insulating region.

16. The semiconductor structure of claim 14, wherein the thickness of the lower portion of the insulating region is greater than the thickness of the upper portion.

17. The semiconductor structure of claim 14, wherein the plurality of shielding structures are arranged in an interlaced pattern.

18. The semiconductor structure of claim 14, wherein the plurality of shielding structures are arranged in an alignment pattern.

19. The semiconductor structure of claim 14, wherein the plurality of shielding structures are separated by a predetermined interval in a first direction, and the predetermined interval is greater than 0.1 μm and less than 2.0 μm.

20. The semiconductor structure of claim 14, wherein the plurality of shielding structures comprises an impurity concentration of at least 10 times the impurity concentration in the drift layer.

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